CN116884358A - Mini LED driving chip capable of realizing single-sided wiring and backlight system - Google Patents

Abstract

The invention discloses a mini LED driving chip capable of realizing single-sided wiring and a backlight system, and mainly solves the problems of more signal pins and complex system and high cost of the existing PM driving chip. The LED driving chip comprises a buffer U2, a buffer U3, a buffer U25, a buffer U6, a shift register, an instruction decoding module, a clock module, a forwarding processing module, a latch and register, an SRAM unit, a Pulse Width Modulation (PWM) unit, a digital control circuit, a current control circuit and a power supply generating circuit. The LED driving chip provided by the invention has the advantages that the signal ports of the chip are greatly simplified, the total pin number of the chip is reduced while the number of the LED driving ports is kept more, and the matrix LED backlight function can be realized without peripheral devices, so that the LED backlight system can greatly reduce the use number of the LED driving chips.

Description

Mini LED driving chip capable of realizing single-sided wiring and backlight system

Technical Field

The invention belongs to the field of integrated circuits, and particularly relates to a mini LED driving chip capable of realizing single-sided wiring and a backlight system.

Background

mini LEDs (sub-millimeter light emitting diodes) are increasingly being used for matrix backlight driving of liquid crystal displays. Currently, miniLED backlights are divided into two modes, AM (active matrix) driving and PM (passive matrix) driving. The AM (active matrix) driver mostly adopts a wiring mode of a single-sided circuit board, that is, a driver chip and a lamp bead are placed on a circuit board and interconnected through a single-layer wiring. The cost of the circuit board of the AM (active matrix) driving mode is low, but the total cost of the system is still high because the number of LED driving chips is very large because the number of LED driving ports is small. PM (active matrix) driving is characterized in that a mode of adding a multilayer circuit board for wiring is mostly adopted for wiring, a driving chip is separated from the lamp beads, and an LED driving system is connected to the circuit board of the lamp beads through a flat cable after the wiring of the multilayer circuit board is adopted for interconnection with the lamp beads. The number of driving chips is greatly reduced if the scan mode is adopted, but the number of chips is also reduced by times, and additional multi-layer circuit boards are required to be added, so that the complexity and cost of the system are increased greatly, and the cost benefit of reducing the number of chips is covered by the cost of the circuit boards. Patent 202111424817.8 proposes a solution for wiring a single-sided circuit board, which can be seen that the number of LED lamp areas controlled by a single driving chip is limited, each chip controls 3 lamp areas, the number of pins of each chip is less, the control is simpler, and the wiring of the single-sided circuit board is easier to realize. However, the LED backlight system realized by the patent requires more LED driving chips and has higher cost. Fig. 1 is a schematic circuit diagram of a PM (active matrix) driving mini LED backlight system. It can be seen that the function of the LED driving chip is much more complex than that of the LED driving chip shown in patent 202111424817.8, and the LED lamp driven by a single driving chip is also much more complex than that shown in patent 202111424817.8. The LED driving chip shown in fig. 1 has a chip enable terminal EN, a vertical synchronization signal Vsync, an LED power supply voltage adjustment pin FBO, and the like. The LED driving ports are more, and the driving chip is generally arranged in the middle of the LED lamp group when the circuit board is wired, and the driving chip is connected with the LED lamp group to the periphery, so that the wiring pressure of the circuit board can be reduced. It can be seen that the enable EN, the vertical sync Vsync, the clock SCLK, and the chip enable CS signals of each chip are all connected to the controller, and these traces are blocked by the driving lines of the LEDs if the single-sided wiring is performed. It can be seen in the illustration that the wires need to be jumped through the connection of the driver chip to the LED light string. Therefore, the PM (active matrix) driving chip needs to adopt a multi-layer circuit board wiring mode, and most of circuit boards of the LED backlight group are circuit boards with single-sided wiring, which needs to separate the driving chip from the LED lamps. A circuit board of a driving chip is required to be added, and an LED driving output of the driving chip is connected to the circuit board of the LED through a flat cable to be connected to the LED. Therefore, the circuit board needs to be added, the flat cable is added, the number of the driving chips can be greatly reduced due to the fact that the number of the driving ports of the LEDs of the driving chips is large, the cost of the driving chips is reduced, but the total system cost is not reduced, and even can be increased.

Disclosure of Invention

The invention aims to provide a mini LED driving chip capable of realizing single-sided wiring and a backlight system, which mainly solve the problems of more signal pins and complex system and high cost of the existing PM driving chip.

In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:

a mini LED driving chip capable of realizing single-sided wiring comprises a buffer U2 with an input end serving as a signal input SDI port, a buffer U3 with an input end serving as a clock input DCLK port, a buffer U25 with an output end serving as a signal output SDO port, a buffer U6 with an output end serving as a clock output DCLKO port, a shift register U8, an instruction decoding module U12, a clock module U11, a forwarding processing module U10, a latch and register U9, an SRAM unit U13, a pulse width modulation PWM unit U14, a digital control circuit U17, a current control circuit U16 and a power supply generating circuit U15;

the signal input SDI is buffered by the buffer U2 and then is connected to the instruction decoding module U12 and the forwarding processing module U10, and the clock input DCLK is buffered by the buffer U3 and then is connected to the inputs of the clock module U11, the instruction decoding module U2 and the buffer U6; the output of the buffer U6 is a clock output pin DCLKO of the LED driving chip; the clock module U11 receives the buffer input of the clock signal DCLK and generates an internal clock signal clk related to the DCLK clock, and the internal clock signal clk is output to the instruction decoding module U12 and the digital control circuit U17;

the instruction decoding module U12 also receives buffer inputs of the SDI and the DCLK, when the clock inputs the high level of the DCLK, the internal clock signal clk is utilized to time the high level of the DCLK, after the set delay is reached, an instruction area marking signal is output, the counting of pulses with rising edges of the SDI is started, and meanwhile, the signals are output to the forwarding processing module U10; the instruction decoding module outputs an instruction corresponding to the SDI pulse number at the falling edge of the DCLK;

the forwarding processing module U10 outputs the signal to the input of the buffer U25, and the output of the buffer U25 is a signal output pin SDO of the LED driving chip;

when data is transmitted, the forwarding processing module U10 outputs the output of the shift register U8 to the buffer U25, enters an instruction area working mode when the high level time of the clock DCLK is longer, and the forwarding processing module U10 forwards the pulse with the rising edge information of the SDI and forcedly outputs the high level without the rising edge information to the low level;

the latch and the register U9 temporarily stores the data of the shift register U8 when the latch signal group is valid, and then the data is transferred to the flash memory SRAM unit U13; the latch and the register U9 are used for controlling the output mode of the Pulse Width Modulation (PWM) unit U14 and the output current, and the output of the latch and the register U9 is connected to the digital control circuit U17 and the current control circuit U16;

the digital control circuit U17 is responsible for controlling the read-write of the SRAM unit U13, the pulse output form of the Pulse Width Modulation (PWM) unit U14 and the output current of the current control circuit U16;

the current control circuit U16 is responsible for generating high-precision constant current value output to the Pulse Width Modulation (PWM) unit U14 for driving the LEDs, and is also responsible for generating IFB current feedback according to the voltage information of the constant current output provided by the PWM unit U14 so as to adjust the voltage of the LED power supply;

the power generation circuit U15 generates a plurality of chip internal use power sources according to the input VIN power supply voltage.

A mini LED driving chip capable of realizing single-sided wiring comprises a tri-state buffer U1, a buffer U2 with an input end serving as a signal input SDI port, a buffer U3 with an input end serving as a clock input DCLK port, a buffer U4, a buffer U5 with an output end serving as a signal output SDO port, a buffer U6 with an output end serving as a clock output DCLKO port, a data back transmission module U7, a shift register U8, an instruction decoding module U12, a clock module U11, a forwarding processing module U10, a latch and register U9, an SRAM unit U13, a pulse width modulation PWM unit U14, a digital control circuit U17, a current control circuit U16 and a power supply generating circuit U15;

the signal input SDI is buffered by the buffer U2 and then is connected to the instruction decoding module U12 and the forwarding processing module U10, and the clock input DCLK is buffered by the buffer U3 and then is connected to the inputs of the clock module U11, the instruction decoding module U2 and the buffer U6; the output of the buffer U6 is a clock output pin DCLKO of the LED driving chip; the clock module U11 receives the buffer input of the clock signal DCLK and generates an internal clock signal clk related to the DCLK clock, and the internal clock signal clk is output to the instruction decoding module U12 and the digital control circuit U17;

the instruction decoding module U12 also receives buffer inputs of the SDI and the DCLK, when the clock inputs the high level of the DCLK, the internal clock signal clk is utilized to time the high level of the DCLK, after the set delay is reached, an instruction area marking signal is output, the counting of pulses with rising edges of the SDI is started, and meanwhile, the signals are output to the forwarding processing module U10; the instruction decoding module outputs an instruction corresponding to the SDI pulse number at the falling edge of the DCLK;

the forwarding processing module U10 outputs the signal to the input of the tri-state buffer U5, and the output of the tri-state buffer U5 is the signal output pin SDO of the LED driving chip;

when data is transmitted, the forwarding processing module U10 outputs the output of the shift register U8 to the tri-state buffer U5, enters an instruction area working mode when the high level time of the clock DCLK is longer, and the forwarding processing module U10 forwards the pulse with the rising edge information of the SDI and forcedly outputs the high level without the rising edge information to the low level;

the data return module U7 controls the data direction by the command SBen, SBen is invalid when data is normally issued, at the moment, the SDI signal buffered by the buffer U2 is output to the data return module U7, and the data return module U7 outputs the SDI signal to the shift register U8; when the data is returned to the working state, SBen is effective, the tri-state buffer U1 is enabled, and the tri-state buffer U5 is closed to enable the output high-resistance state; the signal of the signal output SDO pin is output to a data return module U7 through a U4 buffer, the data return module U7 outputs the signal to a shift register U8, and meanwhile, the data return module U7 sends the output of the shift register U8 to the input end of a tri-state buffer U1, and the tri-state buffer U1 outputs the signal to the input end of a signal input pin SDI;

the latch and the register U9 temporarily stores the data of the shift register U8 when the latch signal group is valid, and then the data is transferred to the flash memory SRAM unit U13; the latch and the register U9 are used for controlling the output mode of the Pulse Width Modulation (PWM) unit U14 and the output current, and the output of the latch and the register U9 is connected to the digital control circuit U17 and the current control circuit U16;

the digital control circuit U17 is responsible for controlling the read-write of the SRAM unit U13, the pulse output form of the Pulse Width Modulation (PWM) unit U14 and the output current of the current control circuit U16;

the current control circuit U16 is responsible for generating high-precision constant current value output to the Pulse Width Modulation (PWM) unit U14 for driving the LEDs, and is also responsible for generating IFB current feedback according to the voltage information of the constant current output provided by the PWM unit U14 so as to adjust the voltage of the LED power supply;

the power generation circuit U15 generates a plurality of chip internal use power sources according to the input VIN power supply voltage.

A mini LED matrix type backlight system adopts the LED driving chip; the LED driving circuit comprises a controller, a switching power supply, a voltage dividing resistor R1, a voltage dividing resistor R2, a jumper resistor R0, a plurality of LED driving chips and a plurality of LED lamp groups; wherein, a plurality of LED driving chips are sequentially connected; one LED driving chip is correspondingly connected with two LED lamp groups;

the controller is connected to the LED driving chip through the SDI port and the DCLK port, the SDI port and the DCLK port of the LED driving chip at the rear stage are correspondingly connected to the SDO port and the DCLKO port of the LED driving chip at the front stage, the LED driving chip is also connected to the FB pin of the switching power supply through the IFB pin, the output LED power supply voltage VIN of the switching power supply is connected to the power supply ends of all LED lamp groups, the divider resistors R1 and R2 are connected between the power supply voltage VIN and the ground, the middle divider point is connected to the FB pin of the switching power supply, and the jumper resistor R0 is connected between the IFB pin of the first LED driving chip and the FB pin of the switching power supply.

A mini LED matrix type backlight system adopts the LED driving chip; the LED driving circuit comprises a controller, a switching power supply, a voltage dividing resistor R1, a voltage dividing resistor R2, a plurality of LED driving chips and a plurality of LED lamp groups; wherein, a plurality of LED driving chips are sequentially connected; one LED driving chip is correspondingly connected with two LED lamp groups;

the controller is connected to the LED driving chip through an SDI port and a DCLK port, the SDI port and the DCLK port of the LED driving chip of the rear stage are correspondingly connected to the SDO port and the DCLKO port of the LED driving chip of the front stage, the switching power supply outputs LED power supply voltage VIN to the power supply ends of all LED lamp groups, the voltage dividing resistors R1 and R2 are connected between the power supply voltage VIN and the ground, and the middle voltage dividing point is connected to the FB pin of the switching power supply; the controller is provided with a control line connected with the switching power supply.

Compared with the prior art, the invention has the following beneficial effects:

(1) The LED driving chip provided by the invention has the advantages that the signal ports of the chip are greatly simplified, the total pin number of the chip is reduced while the number of the LED driving ports is kept more, and the matrix LED backlight function can be realized without peripheral devices, so that the LED backlight system can greatly reduce the use number of the LED driving chips.

(2) The LED driving chip can simplify wiring of the circuit board of the LED backlight system, has rich functions and can realize wiring of the single-sided circuit board of the LED backlight driving system. The LED backlight system realized by adopting the LED driving chip provided by the invention has the advantages of rich functions, simple system and low cost.

Drawings

Fig. 1 is a schematic diagram of a prior art LED matrix backlight system of a PM driving technology.

Fig. 2 is a diagram showing an internal structure of an LED driving chip in embodiment 1 of the present invention.

Fig. 3 is a diagram showing an internal structure of an LED driving chip in embodiment 2 of the present invention.

Fig. 4-mini LED matrix backlight system in embodiment 3 of the present invention.

Fig. 5-mini LED matrix backlight system in embodiment 4 of the present invention.

Fig. 6 is a diagram of package pins of the mini LED driver chip of the present invention-embodiment 2.

Detailed Description

The invention will be further illustrated by the following description and examples, which include but are not limited to the following examples.

Example 1

As shown in fig. 2, the mini LED driving chip capable of realizing single-sided wiring disclosed by the present invention includes a buffer U2 with an input terminal as a signal input SDI port, a buffer U3 with an input terminal as a clock input DCLK port, a buffer U25 with an output terminal as a signal output SDO port, a buffer U6 with an output terminal as a clock output DCLKO port, a shift register U8, an instruction decoding module U12, a clock module U11, a forwarding processing module U10, a latch and register U9, an SRAM unit U13, a pulse width modulation PWM unit U14, a digital control circuit U17, a current control circuit U16, and a power supply generating circuit U15.

The signal input SDI is buffered by the buffer U2 and then is connected to the instruction decoding module U12 and the forwarding processing module U10, and the clock input DCLK is buffered by the buffer U3 and then is connected to the inputs of the clock module U11, the instruction decoding module U2 and the buffer U6; the output of the buffer U6 is a clock output pin DCLKO of the LED driving chip; the clock module U11 receives the buffered input of the clock signal DCLK and generates an internal clock signal clk related to the DCLK clock, which is output to the command decoder U12 and the digital control circuit U17.

The instruction decoding module U12 also receives buffer inputs of the SDI and the DCLK, when the clock inputs the high level of the DCLK, the internal clock signal clk is utilized to time the high level of the DCLK, after the set delay is reached, an instruction area marking signal is output, the counting of pulses with rising edges of the SDI is started, and meanwhile, the signals are output to the forwarding processing module U10; the instruction decoding module outputs an instruction corresponding to the SDI pulse number at a falling edge of DCLK.

The forwarding processing module U10 outputs to the input of the buffer U25, and the output of the buffer U25 is the signal output pin SDO of the LED driving chip. When data is transmitted, the forwarding processing module U10 outputs the output of the shift register U8 to the buffer U25, enters the instruction area working mode when the high level time of the clock DCLK is longer, and the forwarding processing module U10 forwards the pulse with the rising edge information of the SDI and forcedly outputs the high level without the rising edge information to the low level.

The latch and the register U9 temporarily stores the data of the shift register U8 when the latch signal group is valid, and then the data is transferred to the flash memory SRAM unit U13; the latch and the register in the register U9 store various status configuration information of the LED driving chip, which is used to control the output mode and the output current of the PWM unit U14, and the output of the latch and the register U9 is connected to the digital control circuit U17 and the current control circuit U16.

The digital control circuit U17 is responsible for controlling the read/write of the SRAM cell U13, the form of the pulse output of the pulse width modulation PWM unit U14, and the output current magnitude of the current control circuit U16. The current control circuit U16 is responsible for generating a high-precision constant current value output to the Pulse Width Modulation (PWM) unit U14 for driving the LEDs, and is also responsible for generating IFB current feedback according to voltage information of the constant current output provided by the PWM unit U14 so as to adjust the voltage of the LED power supply.

The power generation circuit U15 generates a plurality of chip internal use power sources according to the input VIN power supply voltage. Such as the digital circuit using a low voltage power supply Vldo, the port circuit using a VDD power supply, etc.

When the image data is normally sent, the clock input DCLK is buffered and output to the shift register U8 through the U3, the data is input through the SDI signal pin and then output to the instruction decoding module U12 through the buffer U2, the data in each DCLK period shift register U8 is synchronously output to the forwarding processing module U10, and the forwarding processing module U10 outputs the data to the buffer U25 and then buffers and outputs the data to the SDO pin. After the data is shifted into the shift register, DCLK sends a data latch instruction, the high level is continuously maintained, and SDI sends 2 high level pulses after a certain time delay. The instruction decoding module U12 decodes the data latch instruction after receiving the instruction, outputs a high-level pulse data latch signal LAn at the falling edge of DCLK, sends the high-level pulse data latch signal LAn to the latch and register U9, and uniformly latches the data in the shift register U8 into the latch. The instruction decoding module outputs an instruction area marking signal and controls the forwarding processing module U10 to output the buffer U2 to the buffer U25. The SDI signal is buffered out to the SDO pin by U25 for 2 high pulses during the DCLK high. Thus, one transmission of image data is realized.

Example 2

As shown in fig. 3, the difference between the present embodiment and embodiment 1 is that the LED driving chip in the present embodiment has a data feedback function, and compared with embodiment 1 of fig. 2, the tri-state buffer U1, the data feedback module U7, the buffer U4 and the IFB pin output are added in fig. 3. While buffer U25 is tuned to tri-state buffer U5.

In this embodiment, the signal input SDI is buffered by the buffer U2 and then is received by the instruction decoding module U12 and the forwarding processing module U10, and the clock input DCLK is buffered by the buffer U3 and then is received by the inputs of the clock module U11, the instruction decoding module U2 and the buffer U6; the output of the buffer U6 is a clock output pin DCLKO of the LED driving chip; the clock module U11 receives the buffered input of the clock signal DCLK and generates an internal clock signal clk related to the DCLK clock, which is output to the command decoder U12 and the digital control circuit U17.

The instruction decoding module U12 also receives buffer inputs of the SDI and the DCLK, when the clock inputs the high level of the DCLK, the internal clock signal clk is utilized to time the high level of the DCLK, after the set delay is reached, an instruction area marking signal is output, the counting of pulses with rising edges of the SDI is started, and meanwhile, the signals are output to the forwarding processing module U10; the instruction decoding module outputs an instruction corresponding to the SDI pulse number at the falling edge of the DCLK; a latch signal group LAn, a backhaul control enable SBen, and a forwarding instruction received to the forwarding processing module, etc. as shown in fig. 3.

The forwarding processing module U10 outputs the signal to the input of the tri-state buffer U5, and the output of the tri-state buffer U5 is the signal output pin SDO of the LED driving chip;

when data is transmitted, the forwarding processing module outputs the output of the shift register U8 to the tri-state buffer U5, enters the working mode of the instruction area when the high level time of the clock DCLK is longer, and forwards the pulse with rising edge information of the SDI, and forcibly outputs the high level without rising edge information to the low level.

The data feedback module U7 controls the data direction by the command SBen, SBen is invalid when data is normally issued, at the moment, the SDI signal buffered by the U2 is output to the data feedback module, and the data feedback module outputs the SDI signal to the shift register U8. In the data return operation state, SBen is active, the tri-state buffer U1 is enabled, and the tri-state buffer U5 is turned off to enable the output high-impedance state. The signal of the signal output SDO pin is output to the data return module U7 through the U4 buffer, the data return module outputs the signal to the shift register U8, and meanwhile, the data return module sends the output of the shift register U8 to the input end of the tri-state buffer U1, and the tri-state buffer U1 outputs the signal to the signal input pin SDI end.

The latch and the register U9 have two functions, when the latch signal group LAn is effective, the latch temporarily stores the data of the shift register, and then the data is transferred to the flash memory SRAM U13, and various state configuration information of the driving chip is stored in the register and used for controlling the PWM output mode and the output current of the OUTn, so that the output of the U9 can be connected to the digital control circuit U17 and the current control circuit U16. The digital control circuit U17 is responsible for controlling the read-write of the SRAM, the form of PWM pulse output and the output current of the current control circuit. The current control circuit U16 is responsible for generating a high-precision constant current value to be output to the PWM unit for driving the LEDs, and is also responsible for generating IFB current feedback according to the voltage information of the constant current output OUTn provided by the PWM unit so as to adjust the voltage of the LED power supply. The power supply generating circuit U15 generates a plurality of chip internal use power supplies, such as a power supply Vldo for a digital circuit, a VDD power supply for a port circuit, and the like, based on the input VIN power supply voltage.

When the image data is normally transmitted, the SBen signal is disabled, the tri-state buffer U1 is disabled to output a high-impedance state, and the tri-state buffer U5 is enabled to buffer output. The clock input DCLK is buffered and output to the shift register U8 through the U3, the data is input through the SDI signal pin and then output to the data return module U7 through the buffer U2, the data return module outputs the data to the shift register U8, and the data is moved into the shift register U8 bit by bit in cooperation with the buffer output clock of the DCLK. The data in each DCLK period shift register U8 is output to the forwarding processing module U10, and the forwarding processing module U10 outputs the data to the tri-state buffer U5, and then buffers the data to the SDO pin. After the data is shifted into the shift register, DCLK sends a data latch instruction, the high level is continuously maintained, and SDI sends 2 high level pulses after a certain time delay. The instruction decoding module decodes the data latch instruction after receiving the instruction, outputs a high-level pulse data latch signal LAn at the falling edge of DCLK, sends the high-level pulse data latch signal LAn to the latch and register U9, and uniformly latches the data in the shift register U8 into the latch. The simultaneous instruction decoding module outputs an instruction area marking signal and controls the forwarding processing module U10 to output the output of the buffer U2 to the tri-state buffer U5. The SDI signal is buffered out to the SDO pin by U5 for 2 high pulses during the DCLK high. Thus, one transmission of image data is realized.

When data backhaul is required. The data return instruction and the state configuration data are sent first, and the difference is that the number of high-level pulses of SDI in the instruction area is different, such as 6 pulses, as the flow of sending image data is the same. The SDI cooperates with DCLK to send state configuration data bit by bit, after the sending is completed, DCLK continuously maintains high level, after a certain time delay, the SDI sends 6 high level pulses, and then DCLK becomes low. The instruction decoding module outputs data feedback instructions on the falling edge of DCLK after receiving 6 pulses in the instruction area, SBen instruction is enabled, the tri-state buffer U1 is enabled to buffer output to the input, and the tri-state buffer U5 is disabled to output high resistance state. At this time, DCLK continues to send clock signals, SDO signals are buffered by the buffer U4 and output to the data backhaul module U7, the data backhaul module outputs the data backhaul signals to the shift register U8, the data backhaul signals are matched with the clock signals of DCLK, the data backhaul signals of the SDO are transferred into the shift register U8 bit by bit, meanwhile, the data of the shift register U8 of the chip is output to the data backhaul module U7, and the data backhaul module outputs the data backhaul signals to the tri-state buffer U1 to be buffered and output to the SDI port. When the DCLK clock signal is continuously transmitted, the data of the chip shift register U8 is completely shifted out and output from the SDI pin, and then the data received from the SDO port is continuously shifted out to the SDI pin. Thereby implementing the return of SDO data to the SDI output. After the data return is finished, a data return instruction is sent, for example, DCLK continuously maintains high level, and SDI sends 7 high level pulses after a period of time delay. The instruction decode module turns off the SBen signal after 7 pulses are received at the falling edge of DCLK. Thus, a data return function is realized. Fig. 6 is a chip pin package diagram of the present embodiment.

Through the design, the LED driving chip in the embodiment has the advantages of being capable of realizing the wiring of the single-sided circuit board of the LED backlight driving system while having the rich functions of LED power supply voltage feedback adjustment, signal vertical synchronization, data feedback, chip enabling and the like.

Example 3

A mini LED matrix type backlight system employing the LED driving chip as described in example 1 or 2; the LED driving circuit comprises a controller, a switching power supply, a voltage dividing resistor R1, a voltage dividing resistor R2, a jumper resistor R0, a plurality of LED driving chips and a plurality of LED lamp groups; wherein, a plurality of LED driving chips are sequentially connected; one LED driving chip is correspondingly connected with two LED lamp groups. In this embodiment, two LED driving chips and 4 LED lamp groups are taken as an example, where the two LED driving chips are respectively denoted as an LED driving chip 1 and an LED driving chip 2. The 4 LED lamp groups are respectively marked as an LED lamp group 1, an LED lamp group 2, an LED lamp group 3 and an LED lamp group 4.

In this embodiment, the controller is connected to the LED driving chip 1 through the SDI port and the DCLK port, the SDO port and the DCLKO port of the LED driving chip 1 are connected to the LED driving chip 2, the LED driving chip 1 is further connected to the LED lamp group 1 and the LED lamp group 2, the LED driving chip 1 is further connected to the FB pin of the switching power supply through the IFB pin, the LED driving chip 2 is connected to the LED lamp group 3 and the LED lamp group 4, the switching power supply outputs the LED power supply voltage VIN to the power supply terminals of all the LED lamp groups, the voltage dividing resistors R1 and R2 are connected between the power supply voltage VIN and the ground, the intermediate voltage dividing point is connected to the FB pin of the switching power supply, and the jumper resistor R0 is connected between the IFB pin of the LED driving chip 1 and the FB pin of the switching power supply.

As shown in fig. 4, the controller only needs to connect two control lines to the LED driving chip 1, such as the data and command pulse signal SDI and the clock signal DCLKO shown in fig. 4. And there are only two signal interconnection lines between the LED driving chip 1 and the LED driving chip 2, and the data and command pulse output signal SDO and the clock output signal DCLKO. Compared with the 6 signal interconnection of the prior art scheme of fig. 1, the invention greatly simplifies the interconnection lines of the driving chip and the controller and the interconnection lines between the driving chip and the driving chip. As shown in fig. 4, neither the signal line SDI, DCLK, SDO nor the DCLKO will cross the connection line between the driver chip and the LED lamp set, and only a small amount of jumper wires are needed to implement single-sided wiring of the circuit board.

Example 4

As shown in fig. 5, a mini LED matrix type backlight system adopts a driving chip as in embodiment 2, and includes a controller, a switching power supply, a voltage dividing resistor R1, a voltage dividing resistor R2, a plurality of LED driving chips and a plurality of LED lamp groups; wherein, a plurality of LED driving chips are sequentially connected; one LED driving chip is correspondingly connected with two LED lamp groups. In this embodiment, two LED driving chips and 4 LED lamp groups are taken as an example, where the two LED driving chips are respectively denoted as an LED driving chip 1 and an LED driving chip 2. The 4 LED lamp groups are respectively marked as an LED lamp group 1, an LED lamp group 2, an LED lamp group 3 and an LED lamp group 4.

The present embodiment is different from embodiment 3 in that the present embodiment adopts the LED driving chip having the data return function, so that the LED driving port information of both the LED driving chip 1 and the LED driving chip 2 can be returned to the controller through the signal lines SDI and DCLK. The controller can control the output voltage VIN of the switching power supply according to the returned LED driving port information by adding a control line connected with the switching power supply. Therefore, the connection line from the IFB port of the LED driving chip 1 to the FB port of the switching power supply can be omitted, so that the connection line between the LED driving chip 1 and the controller is simpler.

That is, in this embodiment, the controller is connected to the LED driving chip 1 through the SDI port and the DCLK port, the SDO port and the DCLKO port of the LED driving chip 1 are connected to the LED driving chip 2, the LED driving chip 1 is further connected to the first LED lamp group 1 and the LED lamp group 2, the LED driving chip 2 is connected to the LED lamp group 3 and the fourth LED lamp group 3, the switching power supply outputs the LED power supply voltage VIN to the power supply terminals of all the LED lamp groups, the voltage dividing resistors R1 and R2 are connected between the power supply voltage VIN and the ground, and the intermediate voltage dividing point is connected to the FB pin of the switching power supply; the controller is provided with a control line connected with the switching power supply.

Through the design, the backlight system of the embodiment simplifies wiring of the circuit board of the LED backlight system, so that the circuit board has rich functions, and meanwhile, the wiring of the single-sided circuit board of the LED backlight driving system can be realized, and the circuit board has the advantages of rich functions, simplicity in system and low cost. Thus, the present invention provides a significant and substantial improvement over the prior art.

The above embodiment is only one of the preferred embodiments of the present invention, and should not be used to limit the scope of the present invention, but all the insubstantial modifications or color changes made in the main design concept and spirit of the present invention are still consistent with the present invention, and all the technical problems to be solved are included in the scope of the present invention.

Claims (4)

1. The mini LED driving chip capable of realizing single-sided wiring is characterized by comprising a buffer U2 with an input end serving as a signal input SDI port, a buffer U3 with an input end serving as a clock input DCLK port, a buffer U25 with an output end serving as a signal output SDO port, a buffer U6 with an output end serving as a clock output DCLKO port, a shift register U8, an instruction decoding module U12, a clock module U11, a forwarding processing module U10, a latch and register U9, an SRAM unit U13, a pulse width modulation PWM unit U14, a digital control circuit U17, a current control circuit U16 and a power supply generating circuit U15;

the signal input SDI is buffered by the buffer U2 and then is connected to the instruction decoding module U12 and the forwarding processing module U10, and the clock input DCLK is buffered by the buffer U3 and then is connected to the inputs of the clock module U11, the instruction decoding module U2 and the buffer U6; the output of the buffer U6 is a clock output pin DCLKO of the LED driving chip; the clock module U11 receives the buffer input of the clock signal DCLK and generates an internal clock signal clk related to the DCLK clock, and the internal clock signal clk is output to the instruction decoding module U12 and the digital control circuit U17;

the instruction decoding module U12 also receives buffer inputs of the SDI and the DCLK, when the clock inputs the high level of the DCLK, the internal clock signal clk is utilized to time the high level of the DCLK, after the set delay is reached, an instruction area marking signal is output, the counting of pulses with rising edges of the SDI is started, and meanwhile, the signals are output to the forwarding processing module U10; the instruction decoding module outputs an instruction corresponding to the SDI pulse number at the falling edge of the DCLK;

the forwarding processing module U10 outputs the signal to the input of the buffer U25, and the output of the buffer U25 is a signal output pin SDO of the LED driving chip;

when data is transmitted, the forwarding processing module U10 outputs the output of the shift register U8 to the buffer U25, enters an instruction area working mode when the high level time of the clock DCLK is longer, and the forwarding processing module U10 forwards the pulse with the rising edge information of the SDI and forcedly outputs the high level without the rising edge information to the low level;

the latch and the register U9 temporarily stores the data of the shift register U8 when the latch signal group is valid, and then the data is transferred to the flash memory SRAM unit U13; the latch and the register U9 are used for controlling the output mode of the Pulse Width Modulation (PWM) unit U14 and the output current, and the output of the latch and the register U9 is connected to the digital control circuit U17 and the current control circuit U16;

the digital control circuit U17 is responsible for controlling the read-write of the SRAM unit U13, the pulse output form of the Pulse Width Modulation (PWM) unit U14 and the output current of the current control circuit U16;

the current control circuit U16 is responsible for generating high-precision constant current value output to the Pulse Width Modulation (PWM) unit U14 for driving the LEDs, and is also responsible for generating IFB current feedback according to the voltage information of the constant current output provided by the PWM unit U14 so as to adjust the voltage of the LED power supply;

the power generation circuit U15 generates a plurality of chip internal use power sources according to the input VIN power supply voltage.

2. The mini LED driving chip capable of realizing single-sided wiring is characterized by comprising a tri-state buffer U1, a buffer U2 with an input end serving as a signal input SDI port, a buffer U3 with an input end serving as a clock input DCLK port, a buffer U4, a buffer U5 with an output end serving as a signal output SDO port, a buffer U6 with an output end serving as a clock output DCLKO port, a data back transmission module U7, a shift register U8, an instruction decoding module U12, a clock module U11, a forwarding processing module U10, a latch and register U9, an SRAM unit U13, a pulse width modulation PWM unit U14, a digital control circuit U17, a current control circuit U16 and a power supply generating circuit U15;

the signal input SDI is buffered by the buffer U2 and then is connected to the instruction decoding module U12 and the forwarding processing module U10, and the clock input DCLK is buffered by the buffer U3 and then is connected to the inputs of the clock module U11, the instruction decoding module U2 and the buffer U6; the output of the buffer U6 is a clock output pin DCLKO of the LED driving chip; the clock module U11 receives the buffer input of the clock signal DCLK and generates an internal clock signal clk related to the DCLK clock, and the internal clock signal clk is output to the instruction decoding module U12 and the digital control circuit U17;

the instruction decoding module U12 also receives buffer inputs of the SDI and the DCLK, when the clock inputs the high level of the DCLK, the internal clock signal clk is utilized to time the high level of the DCLK, after the set delay is reached, an instruction area marking signal is output, the counting of pulses with rising edges of the SDI is started, and meanwhile, the signals are output to the forwarding processing module U10; the instruction decoding module outputs an instruction corresponding to the SDI pulse number at the falling edge of the DCLK;

the forwarding processing module U10 outputs the signal to the input of the tri-state buffer U5, and the output of the tri-state buffer U5 is the signal output pin SDO of the LED driving chip;

when data is transmitted, the forwarding processing module U10 outputs the output of the shift register U8 to the tri-state buffer U5, enters an instruction area working mode when the high level time of the clock DCLK is longer, and the forwarding processing module U10 forwards the pulse with the rising edge information of the SDI and forcedly outputs the high level without the rising edge information to the low level;

the data return module U7 controls the data direction by the command SBen, SBen is invalid when data is normally issued, at the moment, the SDI signal buffered by the buffer U2 is output to the data return module U7, and the data return module U7 outputs the SDI signal to the shift register U8; when the data is returned to the working state, SBen is effective, the tri-state buffer U1 is enabled, and the tri-state buffer U5 is closed to enable the output high-resistance state; the signal of the signal output SDO pin is output to a data return module U7 through a U4 buffer, the data return module U7 outputs the signal to a shift register U8, and meanwhile, the data return module U7 sends the output of the shift register U8 to the input end of a tri-state buffer U1, and the tri-state buffer U1 outputs the signal to the input end of a signal input pin SDI;

the latch and the register U9 temporarily stores the data of the shift register U8 when the latch signal group is valid, and then the data is transferred to the flash memory SRAM unit U13; the latch and the register U9 are used for controlling the output mode of the Pulse Width Modulation (PWM) unit U14 and the output current, and the output of the latch and the register U9 is connected to the digital control circuit U17 and the current control circuit U16;

the digital control circuit U17 is responsible for controlling the read-write of the SRAM unit U13, the pulse output form of the Pulse Width Modulation (PWM) unit U14 and the output current of the current control circuit U16;

the current control circuit U16 is responsible for generating high-precision constant current value output to the Pulse Width Modulation (PWM) unit U14 for driving the LEDs, and is also responsible for generating IFB current feedback according to the voltage information of the constant current output provided by the PWM unit U14 so as to adjust the voltage of the LED power supply;

the power generation circuit U15 generates a plurality of chip internal use power sources according to the input VIN power supply voltage.

3. A mini LED matrix type backlight system, characterized in that the LED driving chip as claimed in claim 1 or 2 is used; the LED driving circuit comprises a controller, a switching power supply, a voltage dividing resistor R1, a voltage dividing resistor R2, a jumper resistor R0, a plurality of LED driving chips and a plurality of LED lamp groups; wherein, a plurality of LED driving chips are sequentially connected; one LED driving chip is correspondingly connected with two LED lamp groups;

the controller is connected to the LED driving chip through the SDI port and the DCLK port, the SDI port and the DCLK port of the LED driving chip at the rear stage are correspondingly connected to the SDO port and the DCLKO port of the LED driving chip at the front stage, the LED driving chip is also connected to the FB pin of the switching power supply through the IFB pin, the output LED power supply voltage VIN of the switching power supply is connected to the power supply ends of all LED lamp groups, the divider resistors R1 and R2 are connected between the power supply voltage VIN and the ground, the middle divider point is connected to the FB pin of the switching power supply, and the jumper resistor R0 is connected between the IFB pin of the first LED driving chip and the FB pin of the switching power supply.

4. A mini LED matrix backlight system, wherein the LED driving chip of claim 2 is used; the LED driving circuit comprises a controller, a switching power supply, a voltage dividing resistor R1, a voltage dividing resistor R2, a plurality of LED driving chips and a plurality of LED lamp groups; wherein, a plurality of LED driving chips are sequentially connected; one LED driving chip is correspondingly connected with two LED lamp groups;

the controller is connected to the LED driving chip through an SDI port and a DCLK port, the SDI port and the DCLK port of the LED driving chip of the rear stage are correspondingly connected to the SDO port and the DCLKO port of the LED driving chip of the front stage, the switching power supply outputs LED power supply voltage VIN to the power supply ends of all LED lamp groups, the voltage dividing resistors R1 and R2 are connected between the power supply voltage VIN and the ground, and the middle voltage dividing point is connected to the FB pin of the switching power supply; the controller is provided with a control line connected with the switching power supply.