CN116868355A

CN116868355A - Beam shaping secondary optic for micro light emitting diode

Info

Publication number: CN116868355A
Application number: CN202180093298.3A
Authority: CN
Inventors: 萨米尔·梅祖阿里; 安德里亚·皮诺斯
Original assignee: Meta Platforms Technologies LLC
Current assignee: Meta Platforms Technologies LLC
Priority date: 2020-12-21
Filing date: 2021-10-27
Publication date: 2023-10-10

Abstract

The present invention relates to the use of semiconductor-based waveguides as secondary optics to reduce the beam divergence of light produced by an LED. A light source includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes an LED. The second semiconductor die is bonded to the first semiconductor device and includes a crystal waveguide having a first waveguide surface, a second waveguide surface, and a waveguide body. The first waveguide surface receives light from the LED. The waveguide body is composed of a crystalline material that transmits light received from the first waveguide surface to the second waveguide surface. The second waveguide surface emits a receiving portion of light at a second beam divergence that is substantially less than the first beam divergence.

Description

Beam shaping secondary optic for micro light emitting diode

Technical Field

The present disclosure relates generally to micro light emitting diodes (micro light emitting diode, micro-LEDs). More particularly, the present disclosure relates to the fabrication and use of a crystal waveguide as a secondary optical element of a micro LED to collimate and/or reduce the beam divergence of light emitted by the LED.

Background

Light emitting diodes (light emitting diode, LEDs) convert electrical energy to light energy and have many benefits over other light sources, such as reduced size, improved durability, and improved efficiency. LEDs may be used as light sources in many display systems (e.g., televisions, computer monitors, laptop computers, tablet computers, smartphones, projection systems, and wearable electronics). Micro LEDs (Micro-LEDs, "μleds") based on group III nitride semiconductors (e.g., alN, gaN, inN, alGaInP, and other alloys of quaternary phosphide compositions, etc.) have begun to be developed for various display applications due to their small size (e.g., linear dimensions less than 100 μm, less than 50 μm, less than 10 μm, or less than 5 μm), high packing density (and thus higher resolution), and high brightness. For example, individual micro-LEDs that emit light of different colors (e.g., red, green, and blue) may be used to form a sub-pixel of a display system (e.g., a television or near-eye display system).

Disclosure of Invention

The present disclosure relates generally to micro light emitting diodes (micro light emitting diode, micro-LEDs). More particularly, the present disclosure relates to the fabrication and use of a crystal waveguide as a secondary optical element of a micro LED to collimate and/or reduce the beam divergence of light emitted by the LED. The waveguide and LED may be used in combination for the light source. According to some embodiments, a light source may include a first semiconductor die and a second semiconductor die. The first semiconductor die may include a first Light Emitting Device (LED). The first LED may include a first light emitting surface (light emitting surface, LES) that emits light (generated within the first LED) out of the first LED with a first beam divergence. The second semiconductor die may be bonded to the first semiconductor device and may include a first crystal waveguide. The first waveguide may include a first waveguide surface, a second waveguide surface, and a waveguide body. The first waveguide surface may be configured to receive at least a portion of light generated within the first LED from the first LES of the first LED. The second waveguide surface may be configured as a second LES. The waveguide body may be composed of a transparent crystalline material that transmits light received by the first waveguide surface to the second waveguide surface. The first waveguide surface, the second waveguide surface, and the waveguide body may be configured such that the second waveguide surface emits a received portion of light generated within the first LED out of the first waveguide with a second beam divergence. The second beam divergence may be substantially less than the first beam divergence. Thus, according to some embodiments, there may be provided a light source comprising: a first semiconductor die including a Light Emitting Device (LED) having a Light Emitting Surface (LES) that emits light out of the LED with a first beam divergence; and a second semiconductor die bonded to the first semiconductor die, the second semiconductor die including a waveguide comprising: a first waveguide surface configured to receive light emitted by the LES of the LED at a first beam divergence; a second waveguide surface; and a waveguide body comprising a transparent crystalline material that transmits light received by the first waveguide surface to the second waveguide surface, wherein the second waveguide surface and the waveguide body are configured such that the second waveguide surface emits light received by the first waveguide surface out of the waveguide with a second beam divergence that is less than the first beam divergence.

In some embodiments, the light source is included in a wearable device that generates a virtual reality environment for a user wearing the wearable device. In other embodiments, the light source is included in a wearable device that generates an augmented reality environment for a user wearing the wearable device. The first LED may be a micro light emitting diode. The spatial dimension of the first LES of the first LED may be LESs than 10 microns. In some embodiments, each of the first and second waveguide surfaces may have a spatial dimension of less than 5 microns. The first waveguide surface may be smaller than the second waveguide surface. In some embodiments, the optical coupling efficiency between the LED and the waveguide is at least 0.70.

The transparent crystalline material may be gallium nitride (GaN) grown on a semiconductor substrate. Each spatial dimension of each defect in the optical surface finish (optical surface finish) of the first waveguide may be less than 5 nanometers (nm). The first semiconductor die may include an LED array including first LEDs. The second semiconductor die may include a waveguide array including a first waveguide. There may be a one-to-one correspondence between each LED of the LED array and each waveguide of the waveguide array. The first LED may uniquely correspond to the first waveguide.

In some embodiments, the waveguide array may be formed on a continuous layer of transparent crystalline material. The waveguide body of each waveguide of the waveguide array may protrude from a continuous layer of transparent crystalline material. The proximal surface of each waveguide of the waveguide array may comprise a portion of a continuous layer of transparent crystalline material. The distal surface of each waveguide of the waveguide array may be displaced from a continuous layer of transparent crystalline material.

In other embodiments, the waveguide array may be formed on a discontinuous layer of transparent crystalline material. The discontinuous layer of transparent crystalline material may include an array of separate dielectric layer portions (array of separate dielectric layer portions) formed via an etching process. There may be a one-to-one correspondence between each dielectric layer portion of the array of separate dielectric layer portions and each waveguide of the array of waveguides.

The waveguide body may have a tapered shape characterized by a taper angle associated with a growth process of transparent crystalline material on a semiconductor substrate. The first surface area of the first waveguide surface may be smaller than the second surface area of the second waveguide surface due to the crystal growth process and/or the tapered shape. The waveguide body may have a mesa shape formed at least in part by removing a portion of the transparent crystalline material from the second semiconductor die via an etching process.

The first waveguide may further include a reflective layer encapsulating a portion of the waveguide body. The waveguide body may be configured to reduce transmission losses associated with the waveguide body and reduce beam divergence of a receiving portion of light generated within the first LED. The second semiconductor die may further include a first dielectric layer encapsulating at least a portion of the waveguide body. The first dielectric layer may cover the first waveguide surface. The second semiconductor die may further include a second dielectric layer and a transparent crystalline material layer. The second dielectric layer may cover the second waveguide surface. A transparent crystalline material layer may be interposed between the first dielectric layer and the second dielectric layer.

The second semiconductor die may also include an opaque spacer structure. The spacer structure may be positioned around at least a portion of a perimeter of the second waveguide surface and extend beyond a plane of the second semiconductor die. The positioning of the spacer structure may define a columnar volume extending beyond the plane of the second semiconductor die. The spacer structure may be configured to limit transmission of light emitted by the second waveguide surface and exiting the second semiconductor die within a columnar volume extending beyond a plane of the second semiconductor die.

In some embodiments, the second waveguide surface may have a curved shape formed at least in part by removing a portion of the transparent crystalline material from the second semiconductor die via an etching process such that the curved shape of the second waveguide surface is configured to reduce beam divergence of light emitted by the second waveguide surface and exiting the second semiconductor die.

In at least one embodiment, the shape of the second waveguide surface is a planar surface. The second semiconductor die may include a convex dielectric lens, for example, a convex lens composed of and/or fabricated from a dielectric material. In some embodiments, the dielectric material may include silicon dioxide or any other dielectric material that includes sufficient light refraction characteristics. The convex dielectric lens may cover a second waveguide surface that receives a portion of light generated within the first LED and emitted by the second waveguide surface at a second beam divergence. The convex dielectric lens may emit the receiving portion of the light with a third beam divergence that is less than the second beam divergence. The light source may further include a transparent glass substrate bonded to the second semiconductor die and covering the second waveguide surface. The second semiconductor die may be interposed between the first semiconductor die and the glass substrate.

In some embodiments, a method of manufacturing a light source may include: an array of crystalline waveguides is grown on a layer of crystalline material located on a first semiconductor wafer. A metallization layer may be deposited and/or formed over at least a portion of the crystalline material. The metallization layer may provide optical isolation of each waveguide in the array of crystalline waveguides from each other waveguide in the array of waveguides. The crystal waveguide array may be physically removed from the first semiconductor wafer. The waveguide array may be coupled to an array of Light Emitting Devices (LEDs). There may be a one-to-one correspondence between each waveguide of the crystal waveguide array and each LED of the LED array. Each waveguide of the crystal waveguide array may be configured to reduce beam divergence of light emitted from the respective LED.

In some embodiments, a method of manufacturing a light source is provided, the method comprising: fabricating a first semiconductor die including a Light Emitting Device (LED) having a Light Emitting Surface (LES) that emits light out of the LED with a first beam divergence; fabricating a second semiconductor die, the second semiconductor die comprising a waveguide having a first waveguide surface, a second waveguide surface, and a waveguide body, the waveguide body comprising a transparent crystalline material; and bonding the second semiconductor die to the first semiconductor die such that the first waveguide surface is configured to receive light emitted by the LES of the LED at a first beam divergence, wherein the waveguide body is configured to transmit light received by the first waveguide surface to the second waveguide surface, and the second waveguide surface is configured to emit light received by the first waveguide surface out of the waveguide at a second beam divergence that is LESs than the first beam divergence.

In some embodiments, there is provided an apparatus comprising: a first semiconductor die including a Light Emitting Device (LED) having a Light Emitting Surface (LES) that emits light out of the LED with a first beam divergence; and a second semiconductor die bonded to the first semiconductor die, the second semiconductor die including a waveguide comprising: a first waveguide surface configured to receive light emitted by the LES of the LED at a first beam divergence; a second waveguide surface; and a waveguide body comprising a transparent crystalline material that transmits light received by the first waveguide surface to the second waveguide surface, wherein the second waveguide surface and the waveguide body are configured such that the second waveguide surface emits light received by the first waveguide surface out of the waveguide with a second beam divergence that is less than the first beam divergence.

Another method for fabricating a light source includes growing a three-dimensional (3D) array of crystalline structures on a layer of crystalline material. A layer of crystalline material may be located on the first semiconductor wafer. The 3D crystal structure array may be used to fabricate an embossing and/or embossing tool. The embossing tool may have a shape complementary to the shape of the 3D crystal structure array. In some embodiments, the embossing tool is a soft embossing and/or embossing tool. In other embodiments, the embossing tool is a hard embossing and/or embossing tool. An embossing tool may be used to form the waveguide array. The waveguide array may be coupled to an array of Light Emitting Devices (LEDs) to form a light source. The waveguide array may be configured to reduce beam divergence of light emitted from the LED array.

The embodiments disclosed herein are merely examples and the scope of the disclosure is not limited to these embodiments. A particular embodiment may include all, some, or none of the components, elements, features, functions, operations, or steps of the embodiments disclosed herein. Embodiments according to the invention are specifically disclosed in the appended claims directed to a light source, a method and an apparatus, wherein any feature mentioned in one claim category (e.g. light source) may also be claimed in another claim category (e.g. method or apparatus). The dependencies or references in the appended claims are chosen for formal reasons only. However, any subject matter resulting from the intentional reference to any preceding claim (particularly the multiple dependent claims) may also be claimed such that any combination of claims and their features is disclosed and claimed regardless of the dependency chosen in the appended claims. The subject matter which may be claimed includes not only the combination of features set forth in the attached claims, but also any other combination of features in the claims, wherein each feature mentioned in the claims may be combined with any other feature, or combination of other features, in the claims. Furthermore, any of the embodiments and features described or depicted herein may be claimed in separate claims and/or may be claimed in any combination with any of the embodiments or features described or depicted herein or with any of the features of the appended claims.

This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used in isolation to determine the scope of the claimed subject matter. The subject matter should be understood with reference to appropriate portions of the entire specification of this disclosure, any or all of the accompanying drawings, and each claim. The foregoing and other features and examples will be described in more detail in the following specification, claims and accompanying drawings.

Drawings

Illustrative embodiments are described in detail below with reference to the following drawings.

Fig. 1 is a simplified block diagram of an example of an artificial reality system environment including a near-eye display, according to some embodiments.

Fig. 2 is a perspective view of an example of a near-eye display in the form of a head-mounted display (HMD) device for implementing some of the examples disclosed herein.

Fig. 3 is a perspective view of an example of a near-eye display in the form of a pair of glasses for implementing some of the examples disclosed herein.

Fig. 4 illustrates an example of an optical perspective augmented reality system including a waveguide display, in accordance with certain embodiments.

Fig. 5A illustrates an example of a near-eye display device including a waveguide display, in accordance with some embodiments.

Fig. 5B illustrates an example of a near-eye display device including a waveguide display, in accordance with some embodiments.

Fig. 6 illustrates an example of an image source component in an augmented reality system according to some embodiments.

Fig. 7A illustrates an example of a Light Emitting Diode (LED) with a vertical mesa structure in accordance with certain embodiments.

Fig. 7B is a cross-sectional view of an example of an LED having a parabolic mesa structure in accordance with certain embodiments.

Fig. 8A illustrates an example of a method for die-to-wafer bonding of an LED array, in accordance with certain embodiments.

Fig. 8B illustrates an example of a method for wafer-to-wafer bonding of an LED array according to some embodiments.

Fig. 9A-9D illustrate examples of methods for hybrid bonding of LED arrays according to some embodiments.

Fig. 10 illustrates an example of an LED array having secondary optic fabricated thereon, in accordance with certain embodiments.

Fig. 11A illustrates an example angular distribution of light emitted by a Lambertian light emitting device (Lambertian-like light emitting device) in accordance with certain embodiments.

Fig. 11B illustrates a cross-sectional view of a light source including an array of waveguides as beam collimating secondary optics for an array of light emitting devices, according to some embodiments.

Fig. 11C illustrates an example angular distribution of light emitted by a lambertian light emitting device employing a waveguide as a secondary optic, in accordance with certain embodiments.

Fig. 12A illustrates a semiconductor process for fabricating the waveguide array of fig. 11B, in accordance with certain embodiments.

Fig. 12B illustrates a method for manufacturing the light source of fig. 11B, in accordance with certain embodiments.

Fig. 13 illustrates an embodiment for a high fill factor waveguide array.

Fig. 14A illustrates a semiconductor process for fabricating the high fill factor waveguide array of fig. 13, in accordance with certain embodiments.

Fig. 14B illustrates a method for fabricating the high fill factor waveguide array of fig. 13, in accordance with certain embodiments.

Fig. 15 shows an embodiment for an array of crystal-partitioned waveguides (crystalline baffled waveguide).

Fig. 16A illustrates a semiconductor process for fabricating the array of partitioned waveguides of fig. 15, in accordance with certain embodiments.

Fig. 16B illustrates a method for fabricating the array of partitioned waveguides of fig. 15, in accordance with certain embodiments.

Fig. 17A illustrates a semiconductor process for manufacturing a soft embossing tool for embossing an array of waveguides in an amorphous material, in accordance with certain embodiments.

FIG. 17B illustrates a method for manufacturing the soft imprint tool of FIG. 17A, in accordance with certain embodiments.

Fig. 18A illustrates a semiconductor process for manufacturing a hard embossing tool 1800 for embossing an array of waveguides in an amorphous material, in accordance with certain embodiments.

FIG. 18B illustrates a method for manufacturing the hard imprint tool of FIG. 18A, in accordance with certain embodiments.

Fig. 19 is a simplified block diagram of an electronic system of an example of a near-eye display, according to some embodiments.

The figures depict embodiments of the present disclosure for purposes of illustration only. Those skilled in the art will readily recognize from the following description that alternative embodiments of the illustrated structures and methods may be employed without departing from the principles of the present disclosure or the benefits of the disclosure.

In the drawings, similar components and/or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished by following the reference label by a dash and a second reference label that distinguishes among the similar components. If only the first reference number is used in the specification, the description may be applied to any one of a plurality of similar components having the same first reference number, irrespective of the second reference number.

Detailed Description

The present disclosure relates generally to Light Emitting Diodes (LEDs). More particularly, and not by way of limitation, disclosed herein are techniques for fabricating and employing semiconductor-based optical waveguides as secondary optical components for Light Emitting Diodes (LEDs) and/or micro-LEDs (μleds).

Because of the small size and mass of the μled and the low power requirements, the μled is a good candidate for a light source in a variety of devices, such as, but not limited to, mobile devices with pixel-based displays and wearable devices with head-mounted and/or near-eye displays. However, the light produced by the μled may not be directly used as a light source for certain applications and/or devices. At least because the angular distribution of the light produced by the μled is relatively broad and/or diffuse, the light produced by the μled may be too diffuse to be directly used as a light source for the following devices and/or applications: these devices and/or applications require light with relatively small and/or well-defined beam spots. That is, the light beam generated and emitted by the μled may be relatively divergent and/or non-collimated such that the divergent light beam cannot be used as a light source for a display in a device and/or application. For example, a typical μled may emit a beam with a beam profile that approximates Lambert's cosine law. The angular distribution of the intensity of a Lambertian-like beam may be approximately proportional to cos θ, where θ is measured from a light emitting surface (light) normal to a Light Emitting Diode (LED) The LES) vector measured angle. The angular distribution (or beam divergence) of the light beam emitted by such lambertian LEDs is characterized by a full width at half maximum (full width at half maximum, FWHM) of about 120 ° (i.e.,). For an example of lambertian beam divergence, see the angular distribution 1108 of fig. 11A.

For many applications (e.g., applications employing a μled as the light source for one or more pixels in a display), the lambertian distribution of light may be too diffuse. For example, some applications may require that a substantial portion of the LED light output (e.g., 80% of the beam intensity or power) fall within an emission cone having a relatively small opening angle and/or emission angle (e.g., 20 °). Accordingly, the skilled person has considered to employ conventional beam shaping techniques to collimate (or reduce the beam divergence of) the beam profile of the μled.

Such conventional beam shaping (e.g., beam collimation) techniques for the light produced by the μled include the use of lenses (e.g., microlenses) as secondary optics for reducing the beam divergence. However, conventional microlenses may not sufficiently reduce the divergence of the light beam. Thus, with respect to various applications employing a μled as a light source, a significant portion of the light beam of the μled may be distributed outside of the desired emission cone, even after passing through a conventional microlens. Microlenses have traditionally been manufactured by embossing and/or embossing processes (e.g., nanoimprint lithography processes) on amorphous (or amorphous) materials (e.g., fused silica). Conventional nanoimprint lithography may require the use of expensive "hard" embossing tools. In addition to the significant cost of the tool, surface finishing (surface finish) of conventionally manufactured hard embossing tools may not have sufficient quality to emboss the micro-lenses of the size required to reduce the beam divergence of the μled. Due to the small surface area of the emitting surface of the μled, the surface area of the micro lens required to collimate the light beam may be on the order of a few square micrometers. It is difficult and expensive to reliably manufacture hard imprint tools having features on the order of several microns in physical size. Sufficient collimation of the beam and/or reduction of the beam divergence of such microlenses may require that any defects on the lens surface finish be less than about 5 nanometers. Conventional methods of manufacturing hard tools may not reliably produce such small feature sizes and/or sufficiently smooth surface finishes. If the feature size of the microlenses is not small enough, or if relatively large (e.g., >5 nm) defects are present in the surface finish of the embossing tool, the microlenses may not sufficiently reduce the beam divergence. For many applications, microlenses manufactured by hard embossing tools or other conventional methods may not be sufficient to reduce the beam divergence of the light emitted by the μled.

Accordingly, various embodiments herein relate to fabricating and employing semiconductor-based waveguides as secondary optical components to reduce beam divergence of light generated by LEDs and μleds, as compared to conventional microlens-based approaches. For example, beam shaping secondary optics (e.g., any of the waveguides discussed herein) may be used to shape the beam profile of the light produced by the μled (e.g., reduce the divergence of the beam). Thus, beam shaping optics may be utilized to employ μleds in applications requiring well-collimated light and/or less diffuse optical intensity and/or power distribution.

More specifically, in various embodiments, non-conventional and novel semiconductor-based waveguide structures (e.g., enhanced waveguides fabricated from crystalline semiconductor materials) are employed as secondary optical components for the μled. The semiconductor-based waveguide is used to collimate light generated by the LED and/or the μled and/or to reduce beam divergence of light generated by the LED and/or the μled. Reducing the beam divergence can sufficiently increase the optical power density of the beam of the LED to employ the LED in a variety of applications requiring highly collimated light and/or a tightly controlled beam profile (e.g., a beam with relatively small divergence and/or well-defined beam spot). Various inventive embodiments are described herein that relate to the fabrication and use of semiconductor-based waveguides as secondary optical components for LEDs. Various embodiments include devices, systems, methods, materials, embossing/embossing tools, and the like.

In some embodiments, the μled may emit a beam characterized by a first beam divergence (e.g., see fig. 11A, which shows a lambertian-like beam with a FWHM of about 120 °). When an enhanced waveguide is employed as the secondary optic of the LED, the beam (after passing through the waveguide) can be characterized by a second beam divergence that is substantially less than the first beam divergence. For example, the second beam divergence may be such that about 80% of the beam power or intensity is confined within an emission cone of about 20 °. Without the use of an enhanced waveguide, approximately only 11% of the first beam divergence falls within such an emission cone. For an example of reducing beam divergence by a waveguide as a secondary optic, see the angular distribution 1160 of fig. 11C. A significant reduction in beam divergence is demonstrated by a visual comparison between a first beam divergence (e.g., angle distribution 1108 of fig. 11A) and a second beam divergence (e.g., angle distribution 1160 of fig. 11C). With an optical coupling efficiency (between the μled and the waveguide) of about 70%, the use of the waveguide may result in a transmission gain that exceeds the transmission gain of at least 5 times with a μled without the waveguide. For example, as described above, in the absence of a waveguide, approximately 11% of the light is confined within the 20 ° emission cone, while in the presence of a waveguide, the overall efficiency (within the desired emission cone) is approximately 0.7x0.8≡0.56.

In various embodiments, the waveguide structure may be made of a semiconductor material such as, but not limited to, gallium nitride (GaN). To fabricate the waveguide, a layer of semiconductor material may be deposited on a semiconductor substrate (e.g., a semiconductor wafer) formed of a separate semiconductor material. The semiconductor material of the waveguide structure may be a material of a grown crystal structure. By crystal growth, a crystal structure can be grown on a deposited layer of semiconductor material. In crystalline form, the semiconductor material may be relatively transparent to the frequency of the light emitted by the μled. Due to the optical properties of the crystalline material (e.g., its refractive index relative to the refractive index outside the crystalline material), the crystalline structure may sufficiently confine and transmit the received light and act as a waveguide for the frequency characteristics of the μled.

That is, due to the optical properties and shape of the waveguide, the sidewall surfaces of the waveguide (e.g., the surfaces of the waveguide body that are generally aligned with the direction of beam propagation) may provide significant internal reflection of light within the waveguide. Furthermore, due to the nature of the crystal structure grown on the semiconductor substrate, the waveguide structure may include a tapered shape. The waveguide structure may reduce the beam divergence of the received light and increase the internal reflection of the sidewalls of the waveguide, at least due to the tapered shape that occurs during the growth of the crystal structure. Thus, the waveguide structure may act as a focusing and/or collimating waveguide that shapes the received light beam. Furthermore, at least one shape of the exit surface of the waveguide (e.g., the waveguide surface that emits the light beam after the light passes through the waveguide body) may be formed (e.g., by an etching process) to include a lens (or beam shaping) effect that further increases the focusing and/or collimating capabilities of the waveguide. For example, the exit surface of the waveguide may be etched and/or polished to a shape similar to the surface of a spherical lens and/or a convex lens.

In some embodiments, one or more μleds (e.g., a one-dimensional (1D) array or a two-dimensional (2D) array of μleds) or an array of another such light emitting device may be fabricated on and/or bonded to the first semiconductor die. One or more waveguides (corresponding 1D waveguide array or 2D waveguide array) may be fabricated on the second semiconductor die. The first semiconductor die and the second semiconductor die may be bonded such that each μled is aligned with a corresponding waveguide (e.g., there is a one-to-one correspondence between each μled and the waveguide of the corresponding semiconductor die). The LEDs of the LED array may include a light emitting surface (light emitting surface, LES) that emits at least a portion of the light generated within the active area of the LEDs. The light emitted by the LES of the LED may have a first beam divergence as measured by the angular distribution of the beam. For example, the first beam divergence may be lambertian-like and characterized as having a FWHM of about 120 °.

When the first semiconductor die and the second semiconductor die are bonded, the dies may be aligned such that each LED of the LED array is aligned with a corresponding waveguide of the waveguide array that corresponds to that LED. The waveguide may include a first waveguide surface, a second waveguide surface, a waveguide body, and sidewalls of the body. The first waveguide surface may be closely aligned with the LES of the LED such that the first waveguide surface receives light emitted by the LES of the LED, e.g., the light of the LED is incident on the first waveguide surface and enters the volume of space defined by the waveguide body. In some embodiments, the first waveguide surface is a generally planar surface. The beam propagation direction may be generally orthogonal to the plane of the first waveguide surface. Thus, the first waveguide surface may be configured as a light receiving surface that serves as an entrance (into the volume of space defined by the waveguide body) for the light of the LED, or other light incident on the first waveguide surface. The volume of space defined by the waveguide body may be filled with a crystalline material. Due to the significant internal reflection of the waveguide, the crystalline material (and thus the waveguide body) may transmit at least a substantial portion of the received light from the first waveguide surface to the second waveguide surface, e.g., the waveguide body has little absorption or leakage of light.

The second waveguide surface may be configured to emit light (e.g., light transmitted from the first waveguide surface to the second waveguide surface via the waveguide body) out of the waveguide body and into the surrounding environment of the waveguide. That is, the second waveguide surface may be configured as a light exit surface and/or a light emitting surface of the waveguide. The shape of the waveguide body and/or the shape of the second waveguide surface may be used to substantially collimate the light beam and/or to substantially reduce the divergence of the light beam. Furthermore, due to the optical transmission efficiency of the waveguide (e.g., the optical transparency of the waveguide) and its pronounced optical internal reflection characteristics, the optical power loss experienced by the light beam is small when the angular divergence of the light beam is reduced through the waveguide via its passage.

As described above, the light beam may enter the waveguide via the first waveguide surface with a first beam divergence. The light beam may exit the waveguide via the second waveguide surface with a second beam divergence that is substantially less than the first beam divergence. For example, the first beam divergence may be characterized by a FWHM of about 120 °. The second beam divergence may be characterized such that about 80% of the beam is contained within an emission cone having an opening angle of about 20 °. Thus, the waveguide may act as a secondary optic that collimates the LED light, or at least significantly reduces the beam divergence of the LED light.

Some embodiments may be "high fill factor" embodiments in which the aspect ratio of the waveguide body is increased. The increased aspect ratio may increase the collimation capability and/or divergence reduction capability of the waveguide. Various embodiments may include a "spacer" structure that optically isolates adjacent waveguides and still provides the waveguides with greater collimation and/or divergence reduction capabilities. Still other embodiments may additionally and/or alternatively include dielectric "lens" structures that act as the secondary optic of the waveguide (or the tertiary optic of the LED). Such dielectric lens structures may provide greater collimation and/or divergence reduction capabilities for the waveguide. Some embodiments include fabricating "soft" or "hard" embossing or coining tools in waveguide arrays using a crystal waveguide growth process. Such an embossing tool may be used to fabricate similarly shaped waveguide structures in other materials. Thus, the waveguides discussed herein may be fabricated by other methods (e.g., embossing or coining) and/or other waveguide materials.

The use of a waveguide as a secondary optic to reduce the beam divergence of the light emitted by the LED has several advantages over the use of conventional microlenses to focus the light from the LED. For many applications where conventional microlenses may not be sufficient to reduce beam divergence, the beam shaping characteristics of the enhanced waveguide may significantly reduce beam divergence and can be used in such applications. Thus, when the waveguides discussed herein are used as secondary optics for a μled, these waveguides may enable the μled to be used in applications where a microlens as a beam collimator may be defective. That is, after passing through the waveguide, the divergence of the beam of the μled may be small enough for various applications in which conventional microlens-based approaches do not sufficiently reduce the divergence of the beam. Thus, the combination of a μled and an enhanced waveguide can be used as a light source in many applications requiring a relatively low beam divergence.

As noted above, the fabrication of conventional microlenses may require the use of relatively expensive "hard" embossing or embossing tools. In contrast to embossing-based fabrication, the waveguides discussed herein are formed by a semiconductor fabrication process. Such processes include, but are not limited to, growing a crystal structure of a waveguide on a wafer; depositing an oxide and/or metallization layer on portions of the wafer (e.g., by a photolithographic process); and etching (e.g., by an etching process) a surface of the wafer and/or a surface of the waveguide. Such a semiconductor process does not require expensive stamping tools. As described above, the surface of a conventional embossing tool may not be smooth enough to accurately and uniformly emboss microlenses having feature sizes on the order of several microns. For example, defects on the stamping surface of the stamping tool may be greater than 5nm, and the resulting microlenses may be insufficient to collimate light for certain applications. That is, surface imperfections in conventional embossing tools may cause the microlenses to significantly scatter and/or disperse the light beam to be collimated. Accordingly, the various waveguide embodiments discussed herein may provide significantly more collimation and/or reduction in beam divergence than employing microlenses.

Rather than using an embossing tool that is expensive and/or not sufficiently "smooth" (e.g., free of surface defects greater than the feature size threshold), the fabrication of the waveguides discussed herein involves growing a crystalline structure that includes crystals of the waveguide. The crystal growth process may make the crystal structure grown on a wafer (e.g., a semiconductor substrate) extremely uniform across the wafer (in shape and crystal form structure). As described above, the waveguide body may include a tapered shape (e.g., truncated cone (truncated pyramid) and/or mesa structure), wherein the tapered shape of the waveguide is extremely uniform across the wafer as a result of the crystal growth process. The precise shape and uniformity of the waveguide can result in precise and uniform optical characteristics such that the beam divergence across the wafer-fabricated waveguide is significantly and uniformly reduced. Embodiments employing waveguides as secondary optics may significantly reduce the divergence of the light beam when compared to collimating the light beam of an LED using conventional microlenses, and may be significantly cheaper to manufacture.

The micro LEDs and waveguides described herein may be used in conjunction with a variety of technologies (e.g., artificial reality systems). Artificial reality systems, such as head-mounted display (HMD) systems or head-up display (HUD) systems, typically include a display configured to present an artificial image depicting an object in a virtual environment. The display may present or combine images of real objects with virtual objects, as in a Virtual Reality (VR) application, an augmented reality (augmented reality, AR) application, or a Mixed Reality (MR) application. For example, in AR systems, a user may view both a display image (e.g., a computer-generated image (CGI)) of a virtual object and the surrounding environment, for example, through see-through transparent display glasses or lenses (commonly referred to as optical see-through) or viewing a display image of the surrounding environment captured by a camera (commonly referred to as video see-through). In some AR systems, an artificial image may be presented to a user using an LED-based display subsystem.

As used herein, the term "Light Emitting Diode (LED)" refers to a light source including at least an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting region (i.e., an active region) between the n-type semiconductor layer and the p-type semiconductor layer. The light emitting region may include one or more semiconductor layers forming one or more heterostructures (e.g., quantum wells). In some embodiments, the light emitting region may include a plurality of semiconductor layers forming one or more multiple-quantum-wells (MQWs), each including a plurality of (e.g., about 2 to 6) quantum wells.

As used herein, the term "micro LED" or "μled" refers to an LED having a chip with a linear dimension of less than about 200 μm, such as less than 100 μm, less than 50 μm, less than 20 μm, less than 10 μm, or less. For example, the linear dimensions of the micro-LEDs may be as small as 6 μm, 5 μm, 4 μm, 2 μm or less. Some micro LEDs may have a linear dimension (e.g., length or diameter) comparable to the minority carrier diffusion length. However, the disclosure herein is not limited to micro LEDs, and may also be applied to mini-LEDs (mini-LEDs) and large LEDs.

As used herein, the term "bond" may refer to various methods of physically and/or electrically connecting two or more devices and/or wafers, such as adhesive bonding, metal-to-metal bonding, metal oxide bonding, wafer-to-wafer bonding, die-to-wafer bonding, hybrid bonding, soldering, and under bump metallization (under-bump metallization), and the like. For example, adhesive bonding may use a curable adhesive (e.g., epoxy) to physically bond two or more devices and/or wafers by adhesion. The metal-to-metal bond may include, for example, wire bonding or flip chip bonding using a solder interface (e.g., a pad or ball), a conductive adhesive, or a solder joint between metals. Metal oxide bonding may form a metal and oxide pattern on each surface, bonding the oxide segments together, and then bonding the metal segments together to form a conductive path. Wafer-to-wafer bonding may bond two wafers (e.g., silicon wafers or other semiconductor wafers) without any intervening layers and is based on chemical bonds between the surfaces of the two wafers. Wafer-to-wafer bonding may include wafer cleaning and other pre-treatments, alignment and pre-bonding at room temperature, and annealing at elevated temperatures (e.g., about 250 ℃ or higher). Die-to-wafer bonding may use bumps on one wafer to align the features of the preformed chip with the driver of the wafer. Hybrid bonding may include, for example, wafer cleaning, high precision alignment of contacts of one wafer with contacts of another wafer, dielectric bonding of dielectric materials within the wafer at room temperature, and metal bonding of the contacts by annealing, for example, at a temperature of 250 ℃ to 300 ℃ or higher. As used herein, the term "bump" may generally refer to a metal interconnect that is used or formed during bonding.

In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the examples of the present disclosure. It will be apparent, however, that various examples may be practiced without these specific details. For example, devices, systems, structures, components, methods, and other means may be shown as block diagram form in order to avoid obscuring the examples in unnecessary detail. In other instances, well-known devices, processes, systems, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring the examples. These drawings and descriptions are not intended to be limiting. The terms and expressions which have been employed in the present disclosure are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding any equivalents of the features shown and described or portions of the features shown. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

micro-LED used as light source

Fig. 1 is a simplified block diagram of an example of an artificial reality system environment 100 including a near-eye display 120, according to some embodiments. The artificial reality system environment 100 shown in fig. 1 may include a near-eye display 120, an optional external imaging device 150, and an optional input/output interface 140, each of which may be coupled to an optional console 110. Although fig. 1 illustrates an example of an artificial reality system environment 100 including a near-eye display 120, an external imaging device 150, and an input/output interface 140, any number of these components may be included in the artificial reality system environment 100, or any of these components may be omitted. For example, there may be a plurality of near-eye displays 120 monitored by one or more external imaging devices 150 in communication with the console 110. In some configurations, the artificial reality system environment 100 may not include an external imaging device 150, an optional input/output interface 140, and an optional console 110. In alternative configurations, the artificial reality system environment 100 may include different components or additional components.

Near-eye display 120 may be a head-mounted display that presents content to a user. Examples of content presented by near-eye display 120 include one or more of the following: image, video, audio, or any combination thereof. In some embodiments, the audio may be presented via an external device (e.g., speaker and/or headphones) that receives audio information from the near-eye display 120, the console 110, or both, and presents audio data based on the audio information. Near-eye display 120 may include one or more rigid bodies, which may be rigidly or non-rigidly coupled to each other. The rigid coupling between rigid bodies may be such that the rigid bodies being coupled act as a single rigid entity. The non-rigid coupling between the rigid bodies may allow the rigid bodies to move relative to one another. In various embodiments, the near-eye display 120 may be implemented in any suitable form factor, including a pair of glasses. Some embodiments of near-eye display 120 are further described below with respect to fig. 2 and 3. Further, in various embodiments, the functionality described herein may be used in a head-mounted device (head set) that combines images of the environment external to the near-eye display 120 with artificial reality content (e.g., computer generated images). Accordingly, the near-eye display 120 may augment images of a physical real-world environment external to the near-eye display 120 with generated content (e.g., images, video, sound, etc.) to present augmented reality to the user.

In various embodiments, near-eye display 120 may include one or more of display electronics 122, display optics 124, and eye tracking unit 130. In some embodiments, the near-eye display 120 may also include one or more positioners 126, one or more position sensors 128, and an inertial measurement unit (inertial measurement unit, IMU) 132. The near-eye display 120 may omit any of the eye tracking unit 130, the positioner 126, the position sensor 128, and the IMU132, or the near-eye display may include additional elements in various embodiments. Further, in some embodiments, near-eye display 120 may include the following elements: the elements combine the functions of the various elements described in connection with fig. 1.

Display electronics 122 may display images to a user or facilitate display of images based on data received, for example, from console 110. In various embodiments, display electronics 122 may include one or more display panels, such as a liquid crystal display (liquid crystal display, LCD), an organic light emitting diode (organic light emitting diode, OLED) display, an inorganic light emitting diode (inorganic light emitting diode, ILED) display, a micro light emitting diode (micro light emitting diode, μled) display, an active-matrix OLED (AMOLED) display, a Transparent OLED (TOLED) display, or some other display. For example, in one embodiment of the near-eye display 120, the display electronics 122 may include a front TOLED panel, a rear display panel, and an optical component (e.g., an attenuator, polarizer, or diffraction film or spectral film) located between the front display panel and the rear display panel. The display electronics 122 may include a plurality of pixels that emit light of a dominant color, such as red, green, blue, white, or yellow. In some implementations, the display electronics 122 may display three-Dimensional (3D) images through stereoscopic effects produced by the two-Dimensional panel to create a subjective perception of image depth. For example, display electronics 122 may include a left display positioned in front of the left eye of the user and a right display positioned in front of the right eye. The left and right displays may present multiple copies of the image that are horizontally displaced relative to each other to create a stereoscopic effect (i.e., a perception of image depth when the user views the image).

In some embodiments, display optics 124 may optically display image content (e.g., using an optical waveguide and an optical coupler), or may amplify image light received from display electronics 122, correct optical errors associated with the image light, and present the corrected image light to a user of near-eye display 120. In various embodiments, for example, display optics 124 may include one or more optical elements, such as a substrate, an optical waveguide, an aperture, a fresnel lens, a convex lens, a concave lens, an optical filter, an input coupler/output coupler, or any other suitable optical element that may affect image light emitted from display electronics 122. Display optics 124 may include a combination of different optical elements and mechanical couplings to maintain the relative spacing and orientation of the optical elements in the combination. One or more optical elements in display optics 124 may have an optical coating, such as an anti-reflective coating, a filter coating, or a combination of different optical coatings.

The magnification of the image light by the display optics 124 may allow the display electronics 122 to be physically smaller, lighter in weight, and consume less power than larger displays. Additionally, zooming in may increase the field of view of the displayed content. The amount of magnification of the image light by the display optics 124 may be varied by adjusting the optics, adding optics, or removing optics from the display optics 124. In some embodiments, display optics 124 may project the display image to one or more image planes that may be farther from the user's eye than near-eye display 120.

The display optics 124 may also be designed to correct one or more types of optical errors, such as two-dimensional optical errors, three-dimensional optical errors, or any combination thereof. The two-dimensional error may include optical aberrations that occur in two dimensions. Example types of two-dimensional errors may include barrel distortion, pincushion distortion, longitudinal chromatic aberration, and lateral chromatic aberration. The three-dimensional error may include an optical error that occurs in three dimensions. Example types of three-dimensional errors may include spherical aberration, coma, curvature of field, and astigmatism.

The locators 126 may be objects located at specific locations on the near-eye display 120 relative to each other and relative to a reference point on the near-eye display 120. In some implementations, the console 110 can identify the locator 126 in the image acquired by the external imaging device 150 to determine the location, orientation, or both of the artificial reality headset. The locator 126 may be an LED, a corner cube reflector, a reflective marker, a type of light source that contrasts with the environment in which the near-eye display 120 operates, or any combination thereof. In embodiments where the locator 126 is an active component (e.g., an LED or other type of light emitting device), the locator 126 may emit light in the visible light band (e.g., about 380nm to 750 nm), in the Infrared (IR) band (e.g., about 750nm to 1 mm), in the ultraviolet band (e.g., about 10nm to about 380 nm), in another portion of the electromagnetic spectrum, or in any combination of portions of the electromagnetic spectrum.

The external imaging device 150 may include one or more cameras, one or more video cameras, any other device capable of capturing images including one or more of the plurality of locators 126, or any combination thereof. Further, the external imaging device 150 may include one or more optical filters (e.g., to improve signal-to-noise ratio). The external imaging device 150 may be configured to detect light emitted or reflected from the locator 126 that is in the field of view of the external imaging device 150. In embodiments where the positioners 126 comprise passive elements (e.g., retroreflectors), the external imaging device 150 may comprise a light source that illuminates some or all of the plurality of positioners 126, which positioners 126 may retroreflect light to the light source in the external imaging device 150. Slow calibration data may be transmitted from the external imaging device 150 to the console 110, and the external imaging device 150 may receive one or more calibration parameters from the console 110 to adjust one or more imaging parameters (e.g., focal length, focus, frame rate, sensor temperature, shutter speed, aperture, etc.).

The position sensor 128 may generate one or more measurement signals in response to movement of the near-eye display 120. Examples of the position sensor 128 may include an accelerometer, a gyroscope, a magnetometer, other motion detection sensors or error correction sensors, or any combination thereof. For example, in some embodiments, the position sensor 128 may include a plurality of accelerometers that measure translational motion (e.g., forward/backward, up/down, or left/right) and a plurality of gyroscopes that measure rotational motion (e.g., pitch, yaw, or roll). In some embodiments, the position sensors may be oriented orthogonal to each other.

IMU 132 may be an electronic device such as: the electronic device generates fast calibration data based on received measurement signals from one or more of the plurality of position sensors 128. The position sensor 128 may be located external to the IMU 132, internal to the IMU 132, or any combination thereof. Based on one or more measurement signals from the one or more position sensors 128, the IMU 132 may generate fast calibration data indicative of an estimated position of the near-eye display 120 relative to an initial position of the near-eye display 120. For example, IMU 132 may integrate measurement signals received from accelerometers over time to estimate a velocity vector and integrate the velocity vector over time to determine an estimated location of a reference point on near-eye display 120. Alternatively, the IMU 132 may provide sampled measurement signals to the console 110, which may determine the fast calibration data. While the reference point may be defined generically as a point in space, in various embodiments the reference point may also be defined as a point within the near-eye display 120 (e.g., the center of the IMU 132).

The eye tracking unit 130 may comprise one or more eye tracking systems. Eye tracking may refer to determining the positioning of the eye relative to the near-eye display 120, including the orientation and position of the eye relative to the near-eye display 120. The eye tracking system may comprise an imaging system for imaging one or more eyes, and the eye tracking system may optionally comprise a light emitter that may generate light directed to the eyes such that light reflected by the eyes may be collected by the imaging system. For example, the eye tracking unit 130 may include an incoherent or coherent light source (e.g., a laser diode) that emits light in the visible or infrared spectrum, and a camera that collects light reflected by the user's eye. As another example, the eye tracking unit 130 may collect reflective radio waves emitted by the micro radar unit. The eye tracking unit 130 may use low power light emitters that emit light at a frequency and intensity that does not harm the eye or cause physical discomfort. The eye tracking unit 130 may be arranged to increase the contrast in the image of the eye acquired by the eye tracking unit 130 and to reduce the total power consumed by the eye tracking unit 130 (e.g. to reduce the power consumed by the light emitters and imaging systems comprised in the eye tracking unit 130). For example, in some embodiments, the eye tracking unit 130 may consume less than 100 milliwatts of power.

The near-eye display 120 may use the orientation of the eyes to, for example, determine the inter-pupillary distance (inter-pupillary distance, IPD) of the user, determine gaze direction, introduce depth cues (e.g., blurred images outside of the user's main line of sight), collect heuristics about user interactions in VR media (e.g., time spent on any particular subject, object, or frame as a function of the stimulus suffered), based in part on some other function of the orientation of at least one of the user's eyes, or any combination thereof. Because the orientation of the user's eyes can be determined, the eye tracking unit 130 is able to determine the location at which the user is looking. For example, determining the direction of the user's gaze may include determining a convergence point based on the determined orientations of the left and right eyes of the user. The convergence point may be the point at which the foveal axes (foveal axises) of the user's eyes intersect. The direction of the user's gaze may be the direction of a line passing through the convergence point and the midpoint between the pupils of the user's eyes.

The input/output interface 140 may be a device that allows a user to send an action request to the console 110. An action request may be a request to perform a particular action. For example, the action request may be to start or end an application, or to perform a particular action within an application. Input/output interface 140 may include one or more input devices. Example input devices may include a keyboard, mouse, game controller, glove, button, touch screen, or any other suitable device for receiving action requests and transmitting the received action requests to console 110. The action request received by the input/output interface 140 may be transmitted to the console 110, and the console 110 may perform an action corresponding to the requested action. In some embodiments, the input/output interface 140 may provide haptic feedback to the user in accordance with instructions received from the console 110. For example, the input/output interface 140 may provide haptic feedback when an action request is received, or when the console 110 has performed a requested action and transmitted instructions to the input/output interface 140. In some embodiments, the external imaging device 150 may be used to track the input/output interface 140, such as a tracking controller (which may include, for example, an IR light source) or the position or location of the user's hand, to determine the user's motion. In some embodiments, the near-eye display 120 may include one or more imaging devices to track the input/output interface 140, such as tracking the position or location of a controller or a user's hand to determine the user's motion.

The console 110 may provide content to the near-eye display 120 for presentation to a user based on information received from one or more of the external imaging device 150, the near-eye display 120, and the input/output interface 140. In the example shown in fig. 1, the console 110 may include an application library 112, a head mounted device tracking module 114, an artificial reality engine 116, and an eye tracking module 118. Some embodiments of console 110 may include different modules or additional modules than those described in connection with fig. 1. The functions described further below may be distributed among the components of console 110 in a different manner than described herein.

In some embodiments, the console 110 may include a processor and a non-transitory computer readable storage medium storing instructions executable by the processor. A processor may include multiple processing units that execute instructions in parallel. The non-transitory computer readable storage medium may be any memory, such as a hard disk drive, removable memory, or solid state drive (e.g., flash memory or dynamic random access memory (dynamic random access memory, DRAM)). In various embodiments, the modules of console 110 described in connection with fig. 1 may be encoded as instructions in a non-transitory computer-readable storage medium that, when executed by a processor, cause the processor to perform the functions described further below.

The application library 112 may store one or more applications executed by the console 110. The application may include a set of instructions that when executed by the processor generate content for presentation to a user. The content generated by the application may be responsive to input from a user received via activity of the user's eyes, or may be responsive to input received from the input/output interface 140. Examples of applications may include gaming applications, conferencing applications, video playback applications, or other suitable applications.

The head mounted device tracking module 114 may use slow calibration information from the external imaging device 150 to track the movement of the near-eye display 120. For example, the head mounted device tracking module 114 may use the observed locator from the slow calibration information and a model of the near-eye display 120 to determine the location of the reference point of the near-eye display 120. The head mounted device tracking module 114 may also use location information from the quick calibration information to determine the location of the reference point of the near-eye display 120. Additionally, in some embodiments, the head mounted device tracking module 114 may use portions of the fast calibration information, the slow calibration information, or any combination thereof to predict the future position of the near-eye display 120. The head mounted device tracking module 114 may provide the estimated future position or the predicted future position of the near-eye display 120 to the artificial reality engine 116.

The artificial reality engine 116 may execute an application within the artificial reality system environment 100 and receive position information of the near-eye display 120, acceleration information of the near-eye display 120, velocity information of the near-eye display 120, a predicted future position of the near-eye display 120, or any combination thereof from the head mounted device tracking module 114. The artificial reality engine 116 may also receive estimated eye position and orientation information from the eye tracking module 118. Based on the received information, the artificial reality engine 116 may determine what is provided to the near-eye display 120 to present to the user. For example, if the received information indicates that the user has seen to the left, the artificial reality engine 116 may generate content for the near-eye display 120 that reflects the activity of the user's eyes in the virtual environment. In addition, the artificial reality engine 116 may perform an action within an application executing on the console 110 in response to a received action request from the input/output interface 140 and provide feedback to the user to indicate that the action has been performed. The feedback may be visual feedback or audible feedback via the near-eye display 120, or tactile feedback via the input/output interface 140.

The eye tracking module 118 may receive eye tracking data from the eye tracking unit 130 and determine a position of the user's eye based on the eye tracking data. The position of the eye may include the orientation, position, or both of the eye relative to the near-eye display 120 or any element thereof. Because the axis of rotation of the eye changes as the position of the eye in its orbit changes, determining the position of the eye in its orbit may allow the eye tracking module 118 to more accurately determine the orientation of the eye.

Fig. 2 is a perspective view of an example of a near-eye display in the form of an HMD device 200 for implementing some of the examples disclosed herein. The HMD device 200 may be part of, for example, a VR system, an AR system, an MR system, or any combination thereof. HMD device 200 may include a body 220 and a headband 230. Fig. 2 shows the bottom side 223, front side 225, and left side 227 of the body 220 in perspective view. Headband 230 may have an adjustable or extendable length. There may be sufficient space between the body 220 and the headband 230 of the HMD device 200 to allow a user to secure the HMD device 200 to their head. In various embodiments, HMD device 200 may include additional, fewer, or different components. For example, in some embodiments, HMD device 200 may include eyeglass temples and foot covers, as shown, for example, in fig. 3 below, without headband 230.

The HMD device 200 may present media to a user, including virtual and/or enhanced views of a physical, real-world environment, the views having computer-generated elements. Examples of media presented by the HMD device 200 may include images (e.g., two-dimensional (2D) images or three-dimensional (3D) images), video (e.g., 2D video or 3D video), audio, or any combinations thereof. The images and video may be presented to each eye of the user by one or more display components (not shown in fig. 2) housed in the body 220 of the HMD device 200. In various embodiments, the one or more display components may include a single electronic display panel or multiple electronic display panels (e.g., one display panel for each eye of a user). Examples of one or more electronic display panels may include, for example, an LCD display, an OLED display, an ILED display, a μled display, an AMOLED display, a TOLED display, some other display, or any combination thereof. The HMD device 200 may include two eyebox (eye box) areas.

In some implementations, the HMD device 200 may include various sensors (not shown), such as a depth sensor, a motion sensor, a position sensor, and an eye tracking sensor. Some of these sensors may use a structured light pattern for sensing. In some implementations, the HMD device 200 may include an input/output interface for communicating with a console. In some implementations, the HMD device 200 may include a virtual reality engine (not shown) that may execute applications within the HMD device 200 and receive depth information, position information, acceleration information, velocity information, predicted future positions, or any combinations thereof, of the HMD device 200 from various sensors. In some implementations, information received by the virtual reality engine can be used to generate signals (e.g., display instructions) that are provided to one or more display components. In some implementations, the HMD device 200 may include locators (not shown, such as the locator 126) that are located at multiple fixed positions on the body 220 relative to each other and relative to a reference point. Each of these positioners may emit light that is detectable by an external imaging device.

Fig. 3 is a perspective view of an example of a near-eye display 300 in the form of a pair of glasses for implementing some of the examples disclosed herein. Near-eye display 300 may be a particular implementation of near-eye display 120 of fig. 1 and may be configured to operate as a virtual reality display, an augmented reality display, and/or a mixed reality display. Near-eye display 300 may include a frame 305 and a display 310. The display 310 may be configured to present content to a user. In some embodiments, display 310 may include display electronics and/or display optics. For example, as described above with respect to near-eye display 120 of fig. 1, display 310 may include an LCD display panel, an LED display panel, or an optical display panel (e.g., a waveguide display assembly).

The near-eye display 300 may also include various sensors 350a, 350b, 350c, 350d, and 350e located on the frame 305 or within the frame 305. In some embodiments, the sensors 350 a-350 e may include one or more depth sensors, motion sensors, position sensors, inertial sensors, or ambient light sensors. In some embodiments, the sensors 350 a-350 e may include one or more image sensors configured to generate image data representing different fields of view in different directions. In some embodiments, the sensors 350 a-350 e may be used as input devices to control or affect the display content of the near-eye display 300, and/or to provide an interactive VR/AR/MR experience to a user of the near-eye display 300. In some embodiments, sensors 350 a-350 e may also be used for stereoscopic imaging.

In some embodiments, the near-eye display 300 may also include one or more illuminators 330 for projecting light into the physical environment. The projected light may be associated with different frequency bands (e.g., visible light, infrared light, ultraviolet light, etc.), and the projected light may be used for various purposes. For example, one or more of the illuminators 330 may project light in a dark environment (or in an environment with low intensity infrared light, ultraviolet light, etc.) to assist the sensors 350 a-350 e in capturing images of different objects in a dark environment. In some embodiments, one or more illuminators 330 may be used to project a particular light pattern onto an object within the environment. In some embodiments, one or more luminaires 330 may be used as locators, such as the locators 126 described above with respect to fig. 1.

In some embodiments, the near-eye display 300 may also include a high resolution camera 340. The camera 340 may acquire images of the physical environment in the field of view. The acquired images may be processed, for example, by a virtual reality engine (e.g., artificial reality engine 116 of fig. 1) to add virtual objects to the acquired images or to modify physical objects in the acquired images, and the processed images may be displayed to a user via display 310 for an AR application or an MR application.

Fig. 4 illustrates an example of an optical see-through augmented reality system 400 including a waveguide display, according to some embodiments. The augmented reality system 400 may include a projector 410 and a combiner 415. Projector 410 may include a light source or image source 412 and projector optics 414. In some embodiments, the light source or image source 412 may include one or more micro LED devices as described above. In some embodiments, the image source 412 may include a plurality of pixels, such as an LCD display panel or an LED display panel, that display the virtual object. In some embodiments, the image source 412 may include a light source that produces coherent or partially coherent light. For example, the image source 412 may include a laser diode, a vertical cavity surface emitting laser, an LED, and/or micro LEDs as described above. In some embodiments, the image source 412 may include a plurality of light sources (e.g., micro LED arrays as described above), each emitting monochromatic image light corresponding to a primary color (e.g., red, green, or blue). In some embodiments, the image source 412 may include three two-dimensional micro LED arrays, where each two-dimensional micro LED array may include a plurality of micro LEDs configured to emit primary (e.g., red, green, or blue) light. In some embodiments, the image source 412 may include an optical pattern generator, such as a spatial light modulator. Projector optics 414 may include one or more optical components that may condition light from image source 412, such as to spread light from image source 412, to collimate light from image source 412, to scan light from image source 412, or to project light from image source 412 to combiner 415. The one or more optical components may include, for example, one or more lenses, liquid lenses, mirrors, apertures, and/or gratings. For example, in some embodiments, the image source 412 may include one or more one-dimensional micro LED arrays or elongated two-dimensional micro LED arrays, and the projector optics 414 may include one or more one-dimensional scanners (e.g., micro mirrors or prisms) configured to scan the one-dimensional micro LED arrays or elongated two-dimensional micro LED arrays to generate the image frames. In some embodiments, projector optics 414 may include a liquid lens (e.g., a liquid crystal lens) with a plurality of electrodes that allows scanning of light from image source 412.

Combiner 415 may include an input coupler 430 for coupling light from projector 410 into substrate 420 of combiner 415. Combiner 415 may transmit at least 50% of the light in the first wavelength range and reflect at least 25% of the light in the second wavelength range. For example, the first wavelength range may be visible light from about 400nm to about 650nm, and the second wavelength range may be infrared band from about 800nm to about 1000nm, for example. The input coupler 430 may include a volume holographic grating, a diffractive optical element (diffractive optical element, DOE) (e.g., a surface relief grating), an angled surface of the substrate 420, or a refractive coupler (e.g., a wedge or prism). For example, the input coupler 430 may include a reflector bragg grating or a transmissive bragg grating. The input coupler 430 may have a coupling efficiency for visible light of greater than 30%, 50%, 75%, 90% or more. Light coupled into the substrate 420 may propagate within the substrate 420 by, for example, total internal reflection (total internal reflection, TIR). The substrate 420 may be in the form of a lens of a pair of eyeglasses. The substrate 420 may have a flat surface or a curved surface and may include one or more types of dielectric materials, such as glass, quartz, plastic, polymer, polymethyl methacrylate (PMMA), crystal, or ceramic. The thickness of the substrate may range, for example, from less than about 1mm to about 10mm or more. The substrate 420 may be transparent to visible light.

The substrate 420 may include a plurality of output couplers 440 or may be coupled to a plurality of output couplers 440, each output coupler configured to extract at least a portion of the light guided by the substrate 420 and propagating within the substrate 420 from the substrate 420 and direct the extracted light 460 toward an eyebox 495 where an eye 490 of a user of the augmented reality system 400 may be located when the augmented reality system 400 is in use. The plurality of output couplers 440 may replicate the exit pupil to increase the size of the eyebox 495 so that the displayed image is visible in a larger area. Like input coupler 430, output coupler 440 may include a grating coupler (e.g., a volume hologram grating or a surface relief grating), other diffractive optical elements (diffraction optical element, DOE), prisms, and the like. For example, the output coupler 440 may include a reflector bragg grating or a transmissive bragg grating. The output coupler 440 may have different coupling (e.g., diffraction) efficiencies at different locations. The substrate 420 may also allow light 450 from the environment in front of the combiner 415 to pass through with little or no loss. The output coupler 440 may also allow light 450 to pass through with little loss. For example, in some embodiments, the output coupler 440 may have a very low diffraction efficiency for the light 450, such that the light 450 may refract or otherwise pass through the output coupler 440 with little loss, and thus may have a higher intensity than the extracted light 460. In some implementations, the output coupler 440 may have a high diffraction efficiency for the light 450 and may diffract the light 450 with little loss in certain desired directions (i.e., diffraction angles). As a result, the user can view a combined image of the environment in front of the combiner 415 and the image of the virtual object projected by the projector 410.

Fig. 5A illustrates an example of a near-eye display (NED) device 500 including a waveguide display 530, in accordance with some embodiments. NED device 500 may be an example of a near-eye display 120, an augmented reality system 400, or another type of display device. NED device 500 may include a light source 510, projection optics 520, and a waveguide display 530. The light source 510 may include a panel for multiple light emitters of different colors, such as a panel of red light emitters 512, a panel of green light emitters 514, and a panel of blue light emitters 516. A plurality of red light emitters 512 are organized into an array; a plurality of green emitters 514 are organized into an array; and a plurality of blue emitters 516 are organized in an array. The size and spacing of the light emitters in the light source 510 may be small. For example, each light emitter may have a diameter of less than 2 μm (e.g., about 1.2 μm) and the pitch may be less than 2 μm (e.g., about 1.5 μm). Accordingly, the number of light emitters in each of the plurality of red light emitters 512, the plurality of green light emitters 514, and the plurality of blue light emitters 516 may be equal to or greater than the number of pixels in the display image (e.g., 960 x 720, 1280 x 720, 1440 x 1080, 1920 x 1080, 2160 x 1080, or 2560 x 1080 pixels). Accordingly, the display images may be simultaneously generated by the light sources 510. No scanning element may be used in NED device 500.

The light emitted by the light source 510 may be conditioned by projection optics 520 before reaching the waveguide display 530, and the projection optics 520 may include a lens array. Projection optics 520 may collimate light emitted by light source 510 or focus light emitted by light source 510 into waveguide display 530, which may include a coupler 532 for coupling light emitted by light source 510 into waveguide display 530. Light coupled into waveguide display 530 may propagate within waveguide display 530 by total internal reflection as described above with respect to fig. 4. Coupler 532 may also couple a portion of the light propagating within waveguide display 530 out of waveguide display 530 and toward user's eye 590.

Fig. 5B illustrates an example of a near-eye display (NED) device 550 including a waveguide display 580, in accordance with some embodiments. In some embodiments, NED device 550 may use scan mirror 570 to project light from light source 540 to an image field where user's eye 590 may be. NED device 550 may be an example of a near-eye display 120, an augmented reality system 400, or another type of display device. The light sources 540 may include one or more rows or columns of light emitters of different colors, such as a plurality of rows of red light emitters 542, a plurality of rows of green light emitters 544, and a plurality of rows of blue light emitters 546. For example, the plurality of red light emitters 542, the plurality of green light emitters 544, and the plurality of blue light emitters 546 may each include N rows, each row including, for example, 2560 light emitters (pixels). A plurality of red light emitters 542 are organized into an array; a plurality of green emitters 544 are organized into an array; and a plurality of blue emitters 546 are organized into an array. In some embodiments, the light source 540 may include a single row of light emitters for each color. In some embodiments, the light source 540 may include multiple columns of light emitters for each of the colors red, green, and blue, where each column may include, for example, 1080 light emitters. In some embodiments, the size and/or spacing of the light emitters in the light source 540 may be relatively large (e.g., about 3 μm to 5 μm), so the light source 540 may not include enough light emitters for simultaneously generating full display images. For example, the number of light emitters of a single color may be less than the number of pixels in the display image (e.g., 2560×1080 pixels). The light emitted by the light source 540 may be a set of collimated or diverging light beams.

The light emitted by the light source 540 may be conditioned by various optics (e.g., a collimating lens or free form optical element 560) before reaching the scanning mirror 570. The free-form optical element 560 may include, for example, a multi-faceted prism (multi-faceted prism) or another light folding element for directing light emitted by the light source 540 toward the scanning mirror 570, thereby, for example, changing the propagation direction of the light emitted by the light source 540, such as by about 90 ° or more. In some embodiments, the free-form optical element 560 may be rotatable to scan light. The scanning mirror 570 and/or the free-form optical element 560 may reflect and project light emitted by the light source 540 to the waveguide display 580, which may include a coupler 582 for coupling light emitted by the light source 540 into the waveguide display 580. Light coupled into waveguide display 580 may propagate within waveguide display 580 by total internal reflection as described above with respect to fig. 4. The coupler 582 may also couple a portion of the light propagating within the waveguide display 580 out of the waveguide display 580 and toward the user's eye 590.

The scanning mirror 570 may comprise a microelectromechanical system (microelectromechanical system, MEMS) mirror or any other suitable mirror. The scan mirror 570 can be rotated to scan in one or two dimensions. As the scan mirror 570 rotates, light emitted by the light source 540 may be directed toward different areas of the waveguide display 580 such that a full display image may be projected onto the waveguide display 580 and directed by the waveguide display 580 toward the user's eye 590 during each scan cycle. For example, in embodiments where light source 540 includes light emitters for all pixels in one or more rows, or one or more columns, scan mirror 570 may be rotated in a column or row direction (e.g., x-direction or y-direction) to scan an image. In embodiments where light source 540 includes light emitters for some, but not all, of the pixels in one or more rows, or columns, scan mirror 570 may be rotated in both the row and column directions (e.g., x-direction and y-direction) to project a display image (e.g., using a raster scan pattern).

NED device 550 may operate within a predetermined display period. The display period (e.g., display period) may refer to the duration of scanning or projecting a full image. For example, the display period may be the inverse of the desired frame rate. In the NED device 550 including the scan mirror 570, the display period may also be referred to as a scan period or scan cycle. The light generated by the light source 540 may be rotationally synchronized with the scanning mirror 570. For example, each scanning cycle may include a plurality of scanning steps, wherein the light source 540 may generate a different light pattern in each respective scanning step.

During each scan cycle, a display image may be projected onto waveguide display 580 and user's eye 590 as scan mirror 570 rotates. The actual color value and light intensity (e.g., brightness) of a given pixel location of a display image may be the average of the light beams of the three colors (e.g., red, green, and blue) illuminating that pixel location during the scan period. After the completion of the scanning period, the scanning mirror 570 may be restored to the initial position to project the light of the first few lines of the next display image, or may be rotated in the opposite direction, or the pattern may be scanned to project the light of the next display image, wherein a new set of driving signals may be fed to the light source 540. The same process may be repeated as the scan mirror 570 rotates during each scan cycle. In this way, different images may be projected to the user's eye 590 at different scan periods.

Fig. 6 illustrates an example of an image source component 610 in a near-eye display system 600 according to some embodiments. The image source component 610 may include, for example, a display panel 640 that may generate a display image to be projected toward the eyes of a user and a projector 650 that may project the display image generated by the display panel 640 as described above with respect to the waveguide display of fig. 4-5B. The display panel 640 may include a light source 642 and a driving circuit 644 for the light source 642. Light source 642 may comprise, for example, light source 510 or 540. Projector 650 may include, for example, free form optics 560, scanning mirror 570, and/or projection optics 520 as described above. The near-eye display system 600 may also include a controller 620 that synchronously controls the light source 642 and the projector 650 (e.g., the scanning mirror 570). Image source component 610 may generate and output image light to a waveguide display (not shown in fig. 6), such as waveguide display 530 or 580. As described above, the waveguide display may receive image light at one or more input coupling elements and direct the received image light to one or more output coupling elements. The input coupling element and the output coupling element may comprise, for example, diffraction gratings, holographic gratings, prisms, or any combination thereof. The input coupling element may be selected such that total internal reflection occurs within the waveguide display. The output coupling element may couple out portions of the totally internally reflected image light from the waveguide display.

As described above, the light source 642 may include a plurality of light emitters arranged in an array or matrix. Each light emitter may emit monochromatic light, such as red, blue, green, and infrared light, etc. Although RGB colors are often discussed in this disclosure, the embodiments described herein are not limited to using red, green, and blue as primary colors. Other colors may also be used as primary colors for the near-eye display system 600. In some embodiments, the display panel according to an embodiment may use more than three primary colors. Each pixel in the light source 642 may include three sub-pixels including red micro LEDs, green micro LEDs, and blue micro LEDs. Semiconductor LEDs typically include an active light emitting layer within a multilayer of semiconductor materials. The multiple layers of semiconductor material may comprise different compound materials, or the same substrate with different dopants and/or different doping densities. For example, the multi-layer semiconductor material may include an n-type material layer, an active region, which may include a heterostructure (e.g., one or more quantum wells), and a p-type material layer. Multiple layers of semiconductor material may be grown on a surface of a substrate having a particular orientation. In some embodiments, to increase light extraction efficiency, mesas comprising at least some of the layers of semiconductor material may be formed.

The controller 620 may control image rendering operations of the image source component 610, such as operation of the light sources 642 and/or operation of the projector 650. For example, the controller 620 may determine instructions for the image source component 610 to render one or more display images. These instructions may include display instructions and scan instructions. In some embodiments, the display instructions may include an image file (e.g., a bitmap file). The display instructions may be received, for example, from a console (e.g., console 110 described above with respect to fig. 1). The image source component 610 can use the scan instructions to generate image light. The scan instructions may specify, for example, the type of source of image light (e.g., monochromatic or polychromatic), the scan rate, the orientation of the scanning device, one or more illumination parameters, or any combination thereof. The controller 620 may include a combination of hardware, software, and/or firmware, which is not shown here to avoid obscuring other aspects of the disclosure.

In some embodiments, the controller 620 may be a graphics processing unit (graphics processing unit, GPU) of the display device. In other embodiments, the controller 620 may be other kinds of processors. Operations performed by the controller 620 may include: content for display is acquired and divided into discrete portions. The controller 620 may provide scan instructions to the light sources 642 including addresses corresponding to individual source elements of the light sources 642 and/or electrical bias applied to the individual source elements. The controller 620 may instruct the light sources 642 to sequentially present discrete portions using light emitters corresponding to one or more rows of pixels in an image that is ultimately displayed to a user. The controller 620 may also instruct the projector 650 to make various adjustments to the light. For example, the controller 620 may control the projector 650 to scan these discrete portions to different regions of the coupling element of the waveguide display (e.g., waveguide display 580) described above with respect to fig. 5B. In this way, at the exit pupil of the waveguide display, the individual discrete portions are presented at respective different positions. Although the individual discrete portions are presented at respective different times, the presentation and scanning of the discrete portions occurs fast enough that the user's eyes can integrate the different portions into a single image or a series of images.

The image processor 630 may be a general purpose processor and/or one or more special purpose circuits dedicated to performing the features described herein. In one embodiment, a general purpose processor may be coupled to a memory to execute software instructions that cause the processor to perform certain processes described herein. In another embodiment, image processor 630 may be one or more circuits dedicated to performing certain features. Although the image processor 630 in fig. 6 is shown as a separate unit from the controller 620 and the driving circuit 644, in other embodiments, the image processor 630 may be a subunit of the controller 620 or a subunit of the driving circuit 644. In other words, in these embodiments, the controller 620 or the driving circuit 644 may perform various image processing functions of the image processor 630. The image processor 630 may also be referred to as an image processing circuit.

In the example shown in fig. 6, the light source 642 may be driven by a driving circuit 644 based on data or instructions (e.g., display instructions and scan instructions) transmitted from the controller 620 or the image processor 630. In one embodiment, the drive circuit 644 may include a circuit board that is connected to and mechanically holds the light emitters of the light sources 642. The light source 642 may emit light according to one or more illumination parameters that are set by the controller 620 and possibly adjusted by the image processor 630 and the drive circuit 644. The light source 642 may use illumination parameters to generate light. The illumination parameters may include, for example, source wavelength, pulse rate, pulse amplitude, beam type (continuous or pulsed), one or more other parameters that may affect the emitted light, or any combination thereof. In some embodiments, the source light generated by light source 642 may include multiple beams of red, green, and blue light, or any combination thereof.

Projector 650 may perform a set of optical functions such as focusing image light generated by light source 642, combining image light generated by light source 642, adjusting image light generated by light source 642, or scanning image light generated by light source 642. In some embodiments, projector 650 may include a combination assembly, a light conditioning assembly, or a scanning mirror assembly. Projector 650 may include one or more optical components that optically condition light from light source 642 and possibly redirect light from light source 642. One example of adjusting the light may include adjusting the light, such as expanding, collimating, correcting one or more optical errors (e.g., field curvature, chromatic aberration, etc.), some other adjustment of the light, or any combination thereof. The optical components of projector 650 may include, for example, lenses, mirrors, apertures, gratings, or any combination thereof.

Projector 650 may redirect image light via one or more reflective and/or refractive portions thereof such that the image light is projected toward the waveguide display in certain orientations. The location at which the image light is redirected toward the waveguide display may depend on the particular orientation of the one or more reflective and/or refractive portions. In some embodiments, projector 650 includes a single scanning mirror that scans in at least two dimensions. In other embodiments, projector 650 may include multiple scan mirrors, each scanning in directions orthogonal to each other. Projector 650 may perform a raster scan (horizontally or vertically), a bi-stable resonance scan (bi-resonant scan), or any combination thereof. In some embodiments, projector 650 may perform controlled vibrations in the horizontal and/or vertical directions at a particular oscillation frequency to scan in two dimensions and generate a two-dimensional projected image of the media presented to the user's eyes. In other embodiments, projector 650 may include a lens or prism that may function similar to or the same as one or more scanning mirrors. In some embodiments, image source assembly 610 may not include a projector, where light emitted by light source 642 may be directly incident on a waveguide display.

In semiconductor LEDs, photons are typically generated by recombination of electrons and holes within an active region (e.g., one or more semiconductor layers) with an internal quantum efficiency, where internal quantum efficiency is the proportion of radiative electron-hole recombination in the active region that emits photons. The generated light may then be extracted from the LED in a particular direction or within a particular solid angle. The ratio of the number of emitted photons extracted from an LED to the number of electrons passing through the LED is known as the external quantum efficiency, which describes how efficiently an LED converts injected electrons into photons extracted from the device.

The external quantum efficiency may be proportional to injection efficiency, internal quantum efficiency, and extraction efficiency. Injection efficiency refers to the proportion of electrons injected into the active region through the device. Extraction efficiency is the proportion of photons generated in the active region that escape the device. For LEDs, especially for miniature LEDs of reduced physical size, it can be challenging to increase internal and external quantum efficiency, and/or to control the emission spectrum. In some embodiments, to increase light extraction efficiency, mesas comprising at least some of the layers of semiconductor material may be formed.

Fig. 7A shows an example of an LED 700 with a vertical mesa structure. LED 700 may be a light emitter in light source 510, 540, or 642. The LED 700 may be a micro LED made of an inorganic material (e.g., a multi-layered semiconductor material). The layered semiconductor light emitting device may include a plurality of layers of III-V semiconductor materials. The group III-V semiconductor material may include one or more group III elements (e.g., aluminum (Al), gallium (Ga), or indium (In)) In combination with a group V element (e.g., nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb)). When the group V element of the group III-V semiconductor material includes nitrogen, the group III-V semiconductor material is referred to as a group III nitride material. Layered semiconductor light emitting devices may be fabricated by growing multiple epitaxial layers on a substrate using techniques such as Vapor Phase Epitaxy (VPE), liquid Phase Epitaxy (LPE), molecular beam epitaxy (molecular beam epitaxy, MBE), or metal organic chemical vapor deposition (metalorganic chemical vapor deposition, MOCVD). For example, multiple layers of semiconductor material may be formed with a particular lattice orientation (e.gSuch as polar oriented, nonpolar oriented, or semipolar oriented) substrates, such as GaN, gaAs, or GaP substrates, or substrates including but not limited to sapphire, silicon carbide, silicon, zinc oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride, lithium gallate, partially substituted spinels, or shared beta-LiAlO ₂ A substrate of a quaternary tetragonal oxide of a structure, wherein the substrate may be cut in a specific direction to expose a specific plane as a growth surface.

In the example shown in fig. 7A, LED 700 may include a substrate 710, which may include, for example, a sapphire substrate or a GaN substrate. Semiconductor layer 720 may be grown on substrate 710. The semiconductor layer 720 may include a group III-V material (e.g., gaN) and may Be p-type doped (e.g., doped with Mg, ca, zn, or Be) or n-type doped (e.g., doped with Si or Ge). One or more active layers 730 may be grown on the semiconductor layer 720 to form an active region. The active layer 730 may include a group III-V material (e.g., one or more InGaN layers, one or more AlInGaP layers, and/or one or more GaN layers) that may form one or more heterostructures (e.g., one or more quantum wells or MQWs). The semiconductor layer 740 may be grown on the active layer 730. The semiconductor layer 740 may include a group III-V material, (e.g., gaN), and may Be p-type doped (e.g., doped with Mg, ca, zn, or Be) or n-type doped (e.g., doped with Si or Ge). One of the semiconductor layer 720 and the semiconductor layer 740 may be a p-type layer, and the other may be an n-type layer. The semiconductor layer 720 and the semiconductor layer 740 sandwich the active layer 730 to form a light emitting region. For example, the LED 700 may include an InGaN layer between a p-type GaN layer doped with magnesium and an n-type GaN layer doped with silicon or oxygen. In some embodiments, the LED 700 may include an AlInGaP layer between a p-type AlInGaP layer doped with zinc or magnesium and an n-type AlInGaP layer doped with selenium, silicon, or tellurium.

In some embodiments, an electron-blocking layer (EBL) (not shown in fig. 7A) may be grown to form a gap between the active layer 730 and at least one of the semiconductor layer 720 or the semiconductor layer 740Layering. The EBL can reduce electron leakage current and improve LED efficiency. In some embodiments, heavily doped semiconductor layer 750 (e.g., P ⁺ Semiconductor layer or P ⁺⁺ A semiconductor layer) may be formed on the semiconductor layer 740 and act as a contact layer that forms ohmic contacts and reduces the contact resistance of the device. In some embodiments, conductive layer 760 may be formed on heavily doped semiconductor layer 750. The conductive layer 760 may include, for example, indium Tin Oxide (ITO) or an Al/Ni/Au film. In one example, conductive layer 760 may include a transparent ITO layer.

In order to contact the semiconductor layer 720 (e.g., n-GaN layer) and more efficiently extract light emitted by the active layer 730 from the LED 700, the semiconductor material layers (including the heavily doped semiconductor layer 750, the semiconductor layer 740, the active layer 730, and the semiconductor layer 720) may be etched to expose the semiconductor layer 720 and form a mesa structure including the layers 720 to 760. The mesa structure may confine carriers within the device. Etching the mesa structure may result in formation of mesa sidewalls 732, which may be orthogonal to the growth plane. A passivation layer 770 may be formed on the sidewalls 732 of the mesa structure. The passivation layer 770 may include an oxide layer (e.g., siO ₂ A layer) and may act as a reflector to reflect the emitted light out of LED 700. The contact layer 780 may include a metal layer (e.g., al, au, ni, ti or any combination thereof), and may be formed on the semiconductor layer 720 and may serve as an electrode of the LED 700. Further, another contact layer 790 (e.g., an Al/Ni/Au metal layer) may be formed on the conductive layer 760 and may serve as another electrode of the LED 700.

When a voltage signal is applied to the contact layers 780 and 790, electrons and holes may recombine in the active layer 730, wherein the recombination of electrons and holes may cause photon emission. The wavelength and energy of the emitted photons may depend on the band gap between the valence and conduction bands in the active layer 730. For example, the InGaN active layer may emit green light or blue light, the AlGaN active layer may emit blue to ultraviolet light, and the AlInGaP active layer may emit red, orange, yellow, or green light. The emitted photons may be reflected by the passivation layer 770 and may exit the LED 700 from the top (e.g., conductive layer 760 and contact layer 790) or the bottom (e.g., substrate 710).

In some embodiments, the LED 700 may include one or more other components (e.g., lenses) located on the light emitting surface (e.g., substrate 710) to focus or collimate the emitted light or couple the emitted light into a waveguide. In some embodiments, the LED may include a mesa of another shape (e.g., planar, conical, semi-parabolic, or parabolic), and the base region of the mesa may be circular, rectangular, hexagonal, or triangular. For example, the LEDs may include mesas of curved shape (e.g., parabolic shape) and/or non-curved shape (e.g., conical shape). The mesa may be truncated or non-truncated.

Fig. 7B is a cross-sectional view of an example of an LED 705 having a parabolic mesa structure. Similar to LED 700, LED 705 may include multiple layers of semiconductor material, such as multiple layers of group III-V semiconductor material. The layer of semiconductor material may be epitaxially grown on a substrate 715 (e.g., a GaN substrate or a sapphire substrate). For example, semiconductor layer 725 may be grown on substrate 715. Semiconductor layer 725 may comprise a group III-V material (e.g., gaN) and may Be p-type doped (e.g., doped with Mg, ca, zn, or Be) or n-type doped (e.g., doped with Si or Ge). One or more active layers 735 may be grown on semiconductor layer 725. The active layer 735 may include a group III-V material (e.g., one or more InGaN layers, one or more AlInGaP layers, and/or one or more GaN layers), which may form one or more heterostructures (e.g., one or more quantum wells). Semiconductor layer 745 may be grown on active layer 735. Semiconductor layer 745 may comprise a group III-V material (e.g., gaN) and may Be p-type doped (e.g., doped with Mg, ca, zn, or Be) or n-type doped (e.g., doped with Si or Ge). One of semiconductor layer 725 and semiconductor layer 745 may be a p-type layer, while the other may be an n-type layer.

In order to contact the semiconductor layer 725 (e.g., an n-type GaN layer) and more efficiently extract light emitted by the active layer 735 from the LED 705, the semiconductor layer may be etched to expose the semiconductor layer 725 and form a mesa structure including the layers 725 to 745. The mesa structure may confine carriers within the injection region of the device. Etching the mesa structure may result in formation of mesa sidewalls (also referred to herein as facets) that may be non-parallel to, or in some cases orthogonal to, the growth plane associated with the crystal growth of layer 725 through layer 745.

As shown in fig. 7B, LED 705 may have a mesa structure that includes a flat top. Dielectric layer 775 (e.g., siO ₂ Or SiN _X ) May be formed on facets of the mesa structure. In some embodiments, the dielectric layer 775 may comprise multiple layers of dielectric material. In some embodiments, a metal layer 795 may be formed on the dielectric layer 775. The metal layer 795 may include one or more metals or metal alloy materials, such as aluminum (Al), silver (Ag), gold (Au), platinum (Pt), titanium (Ti), copper (Cu), or any combination thereof. The dielectric layer 775 and the metal layer 795 may form a mesa reflector that may reflect light emitted by the active layer 735 toward the substrate 715. In some embodiments, the mesa reflector may be parabolic to act as a parabolic reflector that may at least partially collimate the emitted light.

Electrical contacts 765 and 785 may be formed on semiconductor layer 745 and semiconductor layer 725, respectively, to act as electrodes. The electrical contacts 765 and 785 may each comprise an electrically conductive material, such as Al, au, pt, ag, ni, ti, cu or any combination thereof (e.g., ag/Pt/Au or Al/Ni/Au), and may serve as electrodes for the LED 705. In the example shown in fig. 7B, electrical contact 785 may be an n-contact and electrical contact 765 may be a p-contact. The electrical contact 765 and the semiconductor layer 745 (e.g., p-type semiconductor layer) may form a back reflector for reflecting light emitted by the active layer 735 back to the substrate 715. In some embodiments, the electrical contact 765 and the metal layer 795 comprise one or more of the same materials and may be formed using the same process. In some embodiments, an additional conductive layer (not shown) may be included as an intermediate conductive layer between the electrical contacts 765 and 785 and the semiconductor layer.

When a voltage signal is applied across contacts 765 and 785, electrons and holes may recombine in the active layer 735. The recombination of electrons and holes may cause photon emission, thereby generating light. The wavelength and energy of the emitted photons may depend on the band gap between the valence and conduction bands in the active layer 735. For example, the InGaN active layer may emit green light or blue light, and the AlInGaP active layer may emit red light, orange light, yellow light, or green light. The emitted photons may propagate in many different directions and may be reflected by the mesa reflector and/or the back reflector, and may exit the LED 705, for example, from the bottom side (e.g., substrate 715) shown in fig. 7B. One or more other secondary optical components (e.g., lenses or gratings) may be formed on the light emitting surface (e.g., substrate 715) to focus or collimate the emitted light and/or couple the emitted light into the waveguide.

One or two-dimensional arrays of the above-described LEDs may be fabricated on a wafer to form a light source (e.g., light source 642). The drive circuitry (e.g., drive circuitry 644) may be fabricated on a silicon wafer, for example, using a CMOS process. The LEDs and the drive circuitry on the wafer may be diced and then bonded together; or may be bonded on a wafer level and then diced. Various bonding techniques may be used to bond the LEDs and the driving circuitry, such as adhesive bonding, metal-to-metal bonding, metal oxide bonding, wafer-to-wafer bonding, die-to-wafer bonding, hybrid bonding, and the like.

Fig. 8A illustrates an example of a method for die-to-wafer bonding of an LED array, in accordance with certain embodiments. In the example shown in fig. 8A, LED array 801 may include a plurality of LEDs 807 on a carrier substrate 805. Carrier substrate 805 may comprise various materials, such as GaAs, inP, gaN, alN, sapphire, siC, si, or the like. The LED 807 may be fabricated, for example, by growing various epitaxial layers, forming mesa structures, and forming electrical contacts or electrodes prior to performing bonding. The epitaxial layers may include various materials such as GaN, inGaN, (AlGaIn) P, (AlGaIn) AsP, (AlGaIn) AsN, (AlGaIn) Pas, (Eu: inGa) N, or (AlGaIn) N, etc., and may include an N-type layer, a P-type layer, and an active layer including one or more heterostructures (e.g., one or more quantum wells or MQWs). The electrical contacts may comprise various electrically conductive materials, such as metals or metal alloys.

Wafer 803 may include a base layer 809 having passive or active integrated circuits (e.g., driver circuits 811) fabricated thereon. The base layer 809 may comprise, for example, a silicon wafer. A drive circuit 811 may be used to control the operation of the LED 807. For example, the driving circuit for each LED 807 may include a 2T1C pixel structure having two transistors and one capacitor. Wafer 803 may also include a bonding layer 813. The bonding layer 813 may include various materials such as metal, oxide, dielectric, cuSn, auTi, and the like. In some embodiments, a patterned layer 815 may be formed on a surface of the bonding layer 813, wherein the patterned layer 815 may include a metal mesh made of a conductive material (e.g., cu, ag, au, al, or the like).

LED array 801 may be bonded to wafer 803 by bonding layer 813 or patterning layer 815. For example, patterned layer 815 may include metal pads or bumps made of various materials (e.g., cuSn, auSn, or nanoporous Au) that may be used to align LEDs 807 of LED array 801 with corresponding drive circuitry 811 on wafer 803. In one example, the LED array 801 may be brought toward the wafer 803 until the LEDs 807 come into contact with corresponding metal pads or bumps corresponding to the driver circuitry 811. Some or all of the LEDs 807 may be aligned with the drive circuitry 811 and then bonded to the wafer 803 via the patterned layer 815 by various bonding techniques (e.g., metal-to-metal bonding). After bonding the LEDs 807 to the wafer 803, the carrier substrate 805 may be removed from the LEDs 807.

Fig. 8B illustrates an example of a method for wafer-to-wafer bonding of an LED array according to some embodiments. As shown in fig. 8B, the first wafer 802 may include a substrate 804, a first semiconductor layer 806, an active layer 808, and a second semiconductor layer 810. The substrate 804 may comprise various materials, such as GaAs, inP, gaN, alN, sapphire, siC, si, or the like. The first semiconductor layer 806, the active layer 808, and the second semiconductor layer 810 may include various semiconductor materials, such as GaN, inGaN, (AlGaIn) P, (AlGaIn) AsP, (AlGaIn) AsN, (AlGaIn) Pas, (Eu: inGa) N, or (AlGaIn) N. In some embodiments, the first semiconductor layer 806 may be an n-type layer and the second semiconductor layer 810 may be a p-type layer. For example, the first semiconductor layer 806 may Be an n-type doped GaN layer (e.g., doped with Si or Ge), and the second semiconductor layer 810 may Be a p-type doped GaN layer (e.g., doped with Mg, ca, zn, or Be). The active layer 808 may include, for example, one or more GaN layers, one or more InGaN layers, and one or more AlInGaP layers, etc., which may form one or more heterostructures (e.g., one or more quantum wells or MQWs).

In some embodiments, the first wafer 802 may also include a bonding layer. The bonding layer 812 may include various materials such as metals, oxides, dielectrics, cuSn or AuTi, etc. In one example, the bonding layer 812 may include p-contacts and/or n-contacts (not shown). In some embodiments, other layers may also be included on the first wafer 802, such as a buffer layer between the substrate 804 and the first semiconductor layer 806. The buffer layer may include various materials, such as polycrystalline GaN or AlN. In some embodiments, a contact layer may be located between the second semiconductor layer 810 and the bonding layer 812. The contact layer may comprise any suitable material for providing electrical contact to the second semiconductor layer 810 and/or the first semiconductor layer 806.

The first wafer 802 may be bonded to the wafer 803 through bonding layer 813 and/or bonding layer 812, the wafer 803 including the driving circuit 811 and bonding layer 813 as described above. Bonding layer 812 and bonding layer 813 may be made of the same material or different materials. Bonding layer 813 and bonding layer 812 can be substantially planar. The first wafer 802 may be bonded to the wafer 803 by various methods (e.g., metal-to-metal bonding, eutectic bonding, metal oxide bonding, anodic bonding, thermocompression bonding, ultraviolet (UV) bonding, and/or fusion bonding).

As shown in fig. 8B, a first wafer 802 may be bonded to wafer 803 with the p-side of the first wafer 802 (e.g., second semiconductor layer 810) facing downward (i.e., toward wafer 803). After bonding, the substrate 804 may be removed from the first wafer 802, and the first wafer 802 may then be processed from the n-side. The process may include, for example, forming a particular mesa shape for each LED, and forming optical components corresponding to each LED.

Fig. 9A-9D illustrate examples of methods for hybrid bonding of LED arrays according to some embodiments. Hybrid bonding may generally include wafer cleaning and activation, high precision alignment of contacts of one wafer with contacts of another wafer, dielectric bonding of dielectric material at the surface of the wafer at room temperature, and metal bonding of these contacts by annealing at elevated temperatures. Fig. 9A shows a substrate 910 on which passive or active circuitry 920 is fabricated. As discussed above with reference to fig. 8A-8B, the substrate 910 may comprise, for example, a silicon wafer. The circuit 920 may include a drive circuit for an LED array. The bonding layer may include dielectric regions 940 and contact pads 930 connected to circuitry 920 through electrical interconnects 922. The contact pads 930 may include, for example, cu, ag, au, al, W, mo, ni, ti, pt or Pd, etc. The dielectric material in dielectric region 940 may include SiCN, siO ₂ 、SiN、Al ₂ O ₃ 、HfO ₂ 、ZrO ₂ Or Ta ₂ O ₅ Etc. The bonding layer may be planarized and polished using, for example, chemical mechanical polishing, wherein the planarization or polishing may cause dishing (bowl-like profile) in the contact pads. The surface of the bonding layer may be cleaned and activated by, for example, an ion (e.g., plasma) or fast atom (e.g., ar) beam 905. The activated surfaces may be atomically clean and may react to form a direct bond between the wafers when the wafers are contacted, for example, at room temperature.

Fig. 9B shows a wafer 950 that includes an array of micro LEDs 970 fabricated thereon as described above with respect to, for example, fig. 7A-8B. Wafer 950 may be a carrier wafer and may include, for example, gaAs, inP, gaN, alN, sapphire, siC, si, or the like. Micro LED 970 may include an n-type layer, an active region, and a p-type layer epitaxially grown on wafer 950. The epitaxial layer may comprise the various III-V semiconductor materials described above, and may be processed from the p-type layer side to etch mesa structures (e.g., generally vertical structures, parabolic structures, tapered structures, etc.) in the epitaxial layer. Can be used forTo form passivation and/or reflective layers on the sidewalls of the mesa structure. The p-contact 980 and the n-contact 982 may be formed in a layer 960 of dielectric material deposited over the mesa structure, and the p-contact 980 and the n-contact 982 may be in electrical contact with the p-type layer and the n-type layer, respectively. The dielectric material in dielectric material layer 960 may include, for example, siCN, siO ₂ 、SiN、Al ₂ O ₃ 、HfO ₂ 、ZrO ₂ Or Ta ₂ O ₅ Etc. The p-contact 980 and the n-contact 982 may comprise, for example, cu, ag, au, al, W, mo, ni, ti, pt or Pd, etc. The top surface of the p-contact 980, the top surface of the n-contact 982, and the top surface of the dielectric material layer 960 may form a bonding layer. The bonding layer may be planarized and polished using, for example, chemical mechanical polishing, wherein polishing may cause dishing in the p-contact 980 and n-contact 982. The bonding layer may then be cleaned and activated by, for example, ion (e.g., plasma) or fast atom (e.g., ar) beam 915. The activated surfaces may be atomically clean and may react to form a direct bond between the wafers when the wafers are contacted, for example, at room temperature.

Fig. 9C illustrates a room temperature bonding process for bonding dielectric materials in each bonding layer. For example, after the bonding layer including dielectric region 940 and contact pad 930, and the bonding layer including p-contact 980, n-contact 982, and dielectric material layer 960 are surface activated, wafer 950 and micro-LEDs 970 may be inverted and wafer 950 and micro-LEDs 970 may be brought into contact with substrate 910 and circuitry formed thereon. In some embodiments, compressive pressure 925 may be applied to substrate 910 and wafer 950 such that the bonding layers press against each other. Due to surface activation and depressions in the contacts, dielectric region 940 and dielectric material layer 960 may be in direct contact due to surface attraction forces, and a reaction may occur between dielectric region 940 and dielectric material layer 960 and form chemical bonds, as surface atoms may have dangling bonds and may be in an unstable energy state after activation. Thus, the dielectric material in dielectric region 940 and the dielectric material in dielectric material layer 960 may be bonded together with or without heat treatment or pressure.

Fig. 9D illustrates an annealing process for bonding contacts in the bonding layers after bonding the dielectric materials in the bonding layers. For example, the contact pad 930 and the p-contact 980 or n-contact 982 may be bonded together by annealing at a temperature of, for example, about 200 ℃ to 400 ℃ or higher. During the annealing process, the heat 935 may expand the contacts more than the dielectric material (because of the different coefficients of thermal expansion), and thus may close the recessed gaps between these contacts, so that the contact pads 930 may contact the p-contacts 980 or the n-contacts 982, and may form a direct metal bond at the activated surfaces.

In some embodiments where the materials of the two bonded wafers have different coefficients of thermal expansion (coefficient of thermal expansion, CTE), bonding the dielectric material at room temperature may help reduce or prevent misalignment of the contact pads caused by the different thermal expansion. In some embodiments, to further reduce or avoid misalignment of the contact pads at high temperatures during annealing, trenches may be formed between micro LEDs, between groups of micro LEDs, or through a portion or all of the substrate, etc., prior to bonding.

After the micro LED is bonded to the driving circuit, the substrate on which the micro LED is fabricated may be thinned or removed, and various secondary optical components may be fabricated on the light emitting surface of the micro LED, for example, to extract light emitted from the active region of the micro LED, collimate light emitted from the active region of the micro LED, and redirect light emitted from the active region of the micro LED. In one example, microlenses may be formed over the micro-LEDs, where each microlens may correspond to a respective micro-LED and may help improve light extraction efficiency and collimate light emitted by the micro-LED. In some embodiments, the secondary optic may be fabricated in the substrate or n-type layer of the micro LED. In some embodiments, the secondary optic may be fabricated in a dielectric layer deposited on the n-type side of the micro LED. Examples of secondary optical components may include lenses, gratings, anti-reflection (AR) coatings, prisms, photonic crystals, or the like.

Fig. 10 illustrates an example of an LED array 1000 with secondary optics fabricated thereon, according to some embodiments. The LED array 1000 may be fabricated by bonding LED chips or wafers to a silicon wafer on which electronic circuitry is fabricated using any suitable bonding technique described above with respect to, for example, fig. 8A-9D. In the example shown in fig. 10, the LED array 1000 may be bonded using a wafer-to-wafer hybrid bonding technique as described above with respect to fig. 9A-9D. The LED array 1000 may include a substrate 1010, which may be, for example, a silicon wafer. Integrated circuit 1020 (e.g., LED driver circuit) may be fabricated on substrate 1010. The integrated circuit 1020 may be connected to the p-contact 1074 and the n-contact 1072 of the micro LED 1070 by interconnects 1022 and contact pads 1030, wherein each contact pad 1030 may form a metal bond with the p-contact 1074 and the n-contact 1072. The dielectric layer 1040 on the substrate 1010 may be bonded to the dielectric layer 1060 by fusion bonding.

The substrate (not shown) of the LED chip or wafer may be thinned or removed to expose the n-type layer 1050 of the micro LED 1070. Various secondary optical components (e.g., spherical microlenses 1082, gratings 1084, microlenses 1086, and anti-reflective layer 1088, etc.) may be formed in the n-type layer 1050 or on top of the n-type layer 1050. For example, a spherical microlens array may be etched in the semiconductor material of the micro LED 1070 using a gray scale mask and a photoresist having a linear response to exposure, or using an etch mask formed by thermal reflow of a patterned photoresist layer. Similar photolithographic techniques or other techniques may also be used to etch the secondary optic in the dielectric layer deposited over n-type layer 1050. For example, a microlens array may be formed in a polymer layer by thermally reflowing the polymer layer patterned using a binary mask. The microlens array in the polymer layer may be used as a secondary optic or may be used as an etch mask to transfer the contours of the microlens array into a dielectric or semiconductor layer. The dielectric layer may comprise SiCN, siO, for example ₂ 、SiN、Al ₂ O ₃ 、HfO ₂ 、ZrO ₂ Or Ta ₂ O ₅ Etc. In some cases In an embodiment, the micro LED 1070 may have a plurality of corresponding secondary optical components such as micro lenses and anti-reflective coatings, micro lenses etched in semiconductor material and micro lenses etched in dielectric material layers, micro lenses and gratings, spherical lenses and aspherical lenses, etc. Three different secondary optic components are shown in fig. 10 to illustrate some examples of secondary optic components that may be formed on micro LEDs 1070, which does not necessarily mean that different secondary optic components are used simultaneously for each LED array.

Crystal waveguide for reducing beam divergence of light generated by an LED

In addition to and/or as an alternative to the secondary optical components discussed in connection with fig. 10, semiconductor-based waveguides may be used as the secondary optical components in some embodiments. As described above, the light beam emitted by the LED may be too divergent and/or diffuse to be used in many applications (e.g., as a light source in a head-mounted display, a near-eye display, a heads-up display, etc.). For example, LEDs that emit light beams having lambertian angular distributions may not be used directly without some secondary optics that collimate the light beam and/or reduce the divergence of the light beam. The waveguides discussed herein may be used as secondary optics to shape the beam of an LED (e.g., to collimate the beam and/or to reduce the divergence of the beam). When the waveguide is used as a secondary optic, such lambertian LEDs can be used in the following applications: the application requires a relatively collimated light source and/or a light beam with a narrow beam profile (e.g., a light beam with a small beam divergence).

Fig. 11A illustrates an example angular distribution 1108 of light 1106 emitted by the lambertian light emitting device 1102, according to some embodiments. The light emitting device 1102 may be an LED, such as any of the LEDs discussed herein, including but not limited to the LED 700 of fig. 7A, the LED 705 of fig. 7B, and/or the LED 1070 of fig. 10. LED 1102 may be a micro light emitting diode (μled). As such, LED 1102 may include a Light Emitting Surface (LES) 1126 that emits light having a first beam divergence (as indicated by arrow 1106). The linear dimension of LES1126 may be LESs than 10 microns. The first beam divergence may be characterized by a lambertian-like angular distribution 1108, e.g., I oc cos θ, where I is the intensity of the beam and θ is the angle measured from a vector orthogonal to LES 1126. In the graph of the lambertian angular distribution 1108, the y-axis represents the beam intensity (I) and the x-axis represents the angle (θ) of the angular distribution. Because the intensity and/or power of the large amount of light 1106 falls outside of a narrow angular range (e.g., |θ|+.20), the angular distribution 1108 may be too diffuse and/or dispersed to directly use the LED 1102 as the light source 1102 in many applications.

Fig. 11B illustrates a cross-sectional view of a light source 1110 including a waveguide array 1114 as a beam collimating secondary optic for a light emitting device array 1112, according to some embodiments. In contrast to the light emitting device 1102 shown in fig. 11A, which does not employ any secondary optics, the light source 1100 of fig. 11B may be used in a variety of applications as follows: the application requires a relatively collimated beam with reduced beam divergence. The waveguide array 1114 may include a first waveguide 1140. The light emitting device array may include a first light emitting device (e.g., light emitting device 1102 of fig. 11A). As shown in the lambertian angular distribution 1108 of fig. 11A, the Light Emitting Surface (LES) 1126 of the light emitting device 1102 may emit a light beam having a first light beam divergence. Each other light emitting device of the array 1112 of light emitting devices may be another example of a light emitting device 1102. Thus, each light emitting device of array 1112 may emit a relatively non-collimated light beam having a lambertian angular distribution 1008 (e.g., a first beam divergence). See bottom of fig. 12A for a projection view of an exemplary (but non-limiting) embodiment of a three-dimensional (3D) structure of waveguide array 1114. In fig. 12A, waveguide array 1114 is a two-dimensional (2D) waveguide array. In other embodiments, waveguide array 1114 may be a one-dimensional (1D) waveguide array.

The light emitting device array 1112 may be similar to at least one of the LED array 801 of fig. 8A, the LED array 970 of fig. 9B-9D, and/or the LED array 1000 of fig. 10. Thus, although not shown in fig. 11B, the LED array 1114 may be included in a semiconductor wafer (or a portion of a semiconductor wafer, such as a semiconductor die) such as, but not limited to, the first wafer 802 of fig. 8B or the wafer 950 of fig. 9B-9D. In some embodiments, the LED array 1114 may be included or embedded within a first semiconductor die (e.g., a portion of a wafer that has been removed or separated from other portions of the wafer), which is not shown in fig. 11B.

Similarly, a waveguide array 1114 can be included in the second semiconductor die 1120. The second semiconductor die 1120 may be bonded to a first semiconductor die comprising the LED array 1112. The first semiconductor die (not shown in fig. 11B) and the second semiconductor die 1120 may be aligned such that there is a one-to-one correspondence between each LED in the LED array 1112 and each waveguide of the waveguide array 1114. For example, the first LEDs 1102 of the LED array 1112 uniquely correspond to the first waveguides 1140 of the waveguide array 1114.

Each of these waveguides (including the first waveguide 1140) of the waveguide array 1114 may be composed of a semiconductor material. In some embodiments, the semiconductor material may include a crystalline structure, i.e., the semiconductor material may be a crystalline material. In some non-limiting embodiments, the semiconductor material of the waveguide may be gallium nitride (GaN). The semiconductor material of the waveguide may be an optically transparent material (e.g., optically transparent to at least a majority of the frequency of light generated by the plurality of LEDs of the LED array 1112). The optically transparent crystalline semiconductor material is shown in fig. 11B by the cross-hatching pattern shown in the first waveguide 1140, as well as in each of the other waveguides of the waveguide array 1114.

The first waveguide 1140 may include a first waveguide surface 1142, a second waveguide surface 1144, and a waveguide body 1146. As shown by the cross-hatching pattern shown in the waveguides of the waveguide array 1114 (including but not limited to the first waveguide 1140), the volume of space defined by the waveguide body 1146 may be filled with crystalline semiconductor material. As discussed further in connection with at least fig. 12, the waveguides may be fabricated by one or more semiconductor processes. Semiconductor processing can achieve fine surface modification on waveguides. For example, the spatial dimension of any defects of the first waveguide surface 1142 and/or the second waveguide surface 1144 may be less than 5 nanometers (nm).

The first semiconductor die (not shown in fig. 11B) and the second semiconductor die 1120 may be aligned such that the first LED 1102 corresponds to the first waveguide 1140. Accordingly, the first waveguide surface 1142 may be configured and/or arranged to receive at least a portion of the light generated within the first LED 1102 from the LES1126 of the first LED 1102. According to some embodiments, the received light may have a first beam divergence of the light 1106 emitted by the lambertian light source 1102 (e.g., the first beam divergence is characterized by the angular distribution 1108). When a light beam enters the first waveguide 1140, the waveguide body 1146 may transmit the light beam to the second waveguide surface 1144. The second waveguide surface 1144 may be configured to emit light (e.g., light transmitted from the first waveguide surface 1142 to the second waveguide surface 1144 via the waveguide body 1146) out of the waveguide body 1146 and into the surrounding environment of the first waveguide. That is, the second waveguide surface 1144 may be configured as a light-emitting surface and/or a light-emitting surface of the waveguide. Light exiting the second waveguide surface 1144 may have a second beam divergence that is substantially less than the first beam divergence of the light entering the first waveguide surface 1142 (e.g., the second beam divergence is less than the first beam divergence).

The shape of the waveguide body 1146, as well as the shape of the first waveguide surface 1142 and/or the second waveguide surface 1144, may be used to substantially collimate the light beam and/or substantially reduce the divergence of the light beam as the light beam is transmitted through the first waveguide 1140. Furthermore, due to the optical transmission efficiency of the first waveguide 1140 (e.g., optical transparency of the crystalline semiconductor material) and its pronounced optical internal reflection characteristics, the light beam experiences insignificant loss of focused power (optical power) as the angular divergence of the light beam decreases through the waveguide by its passage.

As shown in fig. 11B, the shape of the waveguide body 1146 may be a tapered shape, wherein a surface area including an end of the first waveguide surface 1142 may be smaller than a surface area including an end of the second waveguide surface 1144. The tapered shape may be characterized by a taper angle (e.g., the angle formed by the intersection of the first waveguide surface 1142 with the sidewalls of the waveguide body 1146). The taper angle may be characteristic of the crystal growth process of the waveguide on the semiconductor substrate. The tapered shape of the waveguide body 1146 may be used to increase internal reflection of the first waveguide 1140 (e.g., reduce transmission losses associated with the waveguide body 1146) and enhance beam divergence reduction from a first beam divergence to a second beam divergence.

To further increase internal reflection associated with the waveguide, and to further enhance beam divergence reduction from the first beam divergence to the second beam divergence, an optically reflective layer 1152 may be included in the second semiconductor die 1120. The reflective layer 1152 may encapsulate at least a portion of the waveguide body 1146 (e.g., a sidewall of the waveguide body 1146). The reflective layer 1152 may be a metallization layer (e.g., an aluminum layer and/or a gold layer) that prevents light leakage from the sidewalls of the waveguide body 1146.

The second waveguide surface 1144 may be shaped to further reduce the beam divergence of the light emitted by the first waveguide 1140. As shown in fig. 11B, the second waveguide surface may be shaped like a sphere and/or a convex lens. That is, the shape of the second waveguide surface may be a curved shape. Such curved shapes may further collimate and/or focus the light beam.

Fig. 11C illustrates an example angular distribution 1160 of light emitted by a lambertian light emitting device 1102 that employs a waveguide 1140 as a secondary optic, according to some embodiments. As described above, the light emitted by the waveguide 1140 may have a second beam divergence that is substantially less than the first beam divergence of the light emitted by the LED 1102. The second beam divergence can be characterized by the angular distribution 1160 of fig. 11C, where I is the intensity of the beam and θ is the angle measured from a vector orthogonal to LES1126 of the first LED 1102. In the graph of the angular distribution 1108 of light emitted by the first waveguide 1140, the y-axis represents the beam intensity (I) and the x-axis represents the angle (θ) of the angular distribution. Comparison of the angular distribution 1160 with the angular distribution 1108 of fig. 11A clearly shows that the second beam divergence is significantly less than the first beam divergence. The second beam divergence may be such that about 80% of the beam power or intensity is confined within an emission cone of about 20 °. Thus, when the first waveguide 1140 is employed as a secondary optic of the first LED 1102, the first waveguide may act as a beam collimating waveguide that significantly reduces the beam divergence of the light beam emitted by the first LED 1102. Each of these waveguides of the waveguide array 1114 may be similar to the first waveguide 1140. Accordingly, each of these waveguides of the waveguide array 1114 may act as a beam collimating waveguide that significantly reduces the beam divergence of the light beam for the respective LEDs of the LED array 1112.

Returning to fig. 11B, the longitudinal dimension or direction of the waveguide (e.g., first waveguide 1140) may refer to the direction in which a light beam propagates or propagates within the waveguide. Thus, the longitudinal direction of the first waveguide 1140 may be substantially aligned with a vector direction (e.g., the vertical direction of fig. 11B) orthogonal to the first waveguide surface 1142. The length of the first waveguide 1140 (or waveguide body 1146) may refer to the spatial distance between the first waveguide surface 1142 and the second waveguide surface 1144. The lateral direction and/or dimension of the waveguide may refer to a direction and/or dimension that is substantially orthogonal to the longitudinal direction and/or dimension. In some embodiments, the spatial distance corresponding to the length of the first waveguide may be measured from the first waveguide surface 1142 (a planar surface in the embodiment shown in fig. 11B) to the "apex" of the curvature of the second waveguide surface 1144 (e.g., the point on the curvature of the second waveguide surface 1144 furthest from the plane of the first waveguide surface 1142). The lateral (or lateral) dimension or direction of the waveguide (e.g., the first waveguide 1140) may refer to a direction orthogonal to the longitudinal dimension of the waveguide. Thus, the lateral (or lateral) dimension of the first waveguide 1140 may be aligned with a vector (e.g., the horizontal direction of fig. 11B) that lies substantially within the "plane" of the first waveguide surface 1142. The width of the first waveguide 1140 (or waveguide body 1146) may refer to the spatial distance between opposing points on each sidewall of the waveguide body 1146. The width varies along the longitudinal dimension due to the tapered shape of the waveguide body 1146. Thus, the width of the first waveguide 1140 may refer to the "average" width of the waveguide body 1146 (e.g., the average width is determined via integration along the longitudinal direction of the waveguide body 1146). The aspect ratio of a waveguide may refer to the ratio of the length of the waveguide to the width (or average width) of the waveguide.

The second semiconductor die 1120 may include a first dielectric layer 1122 and a second dielectric layer that encapsulate the waveguide array 1114Layer 1124. At least one of the dielectric layers 1122/1124 may be composed of an oxide material such as, but not limited to, silicon dioxide (SiO) ₂ ). Thus, the at least one dielectric layer may be an oxide layer (e.g., a silicon dioxide layer). In other embodiments, at least one of the dielectric layers 1122/1124 may be composed of a nitride material, such as, but not limited to, silicon nitride. Thus, the at least one dielectric layer may be a nitride layer (e.g., a silicon nitride layer). The first dielectric layer 1122 may encapsulate at least a portion of the waveguide body 1146. The first dielectric layer 1122 may cover at least a portion of the first waveguide surface 1142. The second dielectric layer 1124 may cover at least a portion of the second waveguide surface 1144. The second semiconductor die 1120 may additionally include a layer of crystalline material 1150 interposed between the first semiconductor die and the second semiconductor die 1120. The first dielectric layer 1122 and/or the second dielectric layer 1124 may act as passivation layers for the semiconductor layer 1150 and each of the plurality of waveguides (e.g., the first waveguide 1140).

As discussed further in connection with at least fig. 12, waveguide array 1114 may be grown and/or formed over a continuous layer of crystalline material 1150. The waveguide body of each waveguide may protrude vertically from the continuous layer of crystalline material 1150 and/or beyond the continuous layer of crystalline material 1150. The proximal (or near) surface of each waveguide of the waveguide array (e.g., the first waveguide surface 1142 of the first waveguide 1140) relative to the corresponding LED may comprise a portion of a continuous transparent layer of crystalline material 1150. The distal surface of each waveguide of the waveguide array (e.g., the second waveguide surface 1144 of the first waveguide 1140) relative to the respective LED may be vertically displaced from the continuous transparent layer of crystalline material 1150. The curved shape of the second waveguide surface 1144 may be formed on the crystalline material layer 1150 via an etching process. As used herein, the terms "distal" and "proximal" may refer to generally opposite directions or portions of a waveguide. The proximal (or proximal) portion of the waveguide may refer to the following portion of the waveguide: the portion is closer to the LED that will illuminate the waveguide, such as the portion of waveguide 1140 that includes the first waveguide surface 1142. The distal portion or end of the waveguide 1140 is a portion that includes a second waveguide surface 1144.

The light source 1110 may optionally include a transparent substrate layer 1130. The transparent substrate layer 1130 may be a transparent glass layer bonded to the second semiconductor die 1120 such that the second semiconductor die 1120 is interposed between the first semiconductor die and the transparent substrate layer 1130. In some embodiments, a transparent substrate layer 1130 may be bonded to the second dielectric layer 1124 to cover the exit surface of the waveguide (e.g., the second waveguide surface 1144). The second dielectric layer 1124 (and/or the first dielectric layer 1122) may be formed of SiO ₂ The composition is formed. Thus, the second dielectric layer 1124 can act as a passivation layer for the light emitting surface of the waveguide (e.g., second waveguide surface 1144) and/or the semiconductor material layer 1150. Light emitted by the second waveguide surface 1144 (and any other light emitting surfaces of the waveguides) may be transmitted through the passivated second dielectric layer 1124 and/or the transparent substrate layer 1130 without significant power loss/absorption and/or dissipation.

Because of the reduced beam divergence (e.g., characterized by the angular distribution 1160 of fig. 11C), the light source 1110 (or any other light source discussed herein) may be used as and/or included as a light source in a wearable device. For example, the light source 1100 may be included in a wearable device (e.g., the head-mounted display device 200 of fig. 2) as follows: the wearable device generates a virtual reality environment for a user wearing the wearable device. As another example, the light source 1100 may be included in a wearable device (e.g., the near-eye display 300 of fig. 3) as follows: the wearable device generates an augmented reality environment for a user wearing the wearable device.

Fig. 12A illustrates a semiconductor process 1200 for fabricating the waveguide array 1114 of fig. 11B, in accordance with certain embodiments. Part of the discussion regarding the semiconductor process 1200 will be made with reference to the light source 1100 of fig. 11B. Semiconductor process 1200 can begin at step 1202, where a crystalline material layer 1150 is formed on a semiconductor substrate 1104. In some embodiments, the semiconductor substrate 1104 may be a crystal growth substrate wafer composed of a growth material such as, but not limited to, si/AlO ₃ . Crystalline material of crystalline material layer 1150The material may include, but is not limited to, gaN. An array of crystal structures is grown on a crystal growth substrate 1104. The crystal structure array includes at least a first crystal structure (the first crystal structure corresponds to the first waveguide 1140, and thus the first waveguide 1140 and the first crystal structure 1140 are interchangeable throughout).

Through the steps of process 1200, each of the plurality of crystal structures of the array of crystal structures forms a waveguide of waveguide array 1114 (or fig. 11B). The crystal structure array corresponds to the waveguide array 1114, and a first crystal structure 1140 (or first waveguide 1140) of the crystal structure array corresponds to the first waveguide 1140 of the waveguide array 1114. Thus, the terms "crystal structure" and "waveguide" are used interchangeably herein. Each of the plurality of crystal structures (or waveguides) of the crystal (or waveguide) array including the first waveguide 1140 extends beyond the layer of crystal material 1150 once grown. The shape and structure of the crystal structure is very uniform throughout the crystal structure array due to the crystal growth process. Accordingly, the following discussion of the first crystal structure (or waveguide) 1140 applies to each crystal structure (or waveguide).

The first crystalline structure 1140 extends beyond the crystalline material layer 1150 and/or protrudes from the crystalline material layer 1150. The first crystal structure 1140 includes a waveguide body 1146, a sidewall 1148 of the body 1146, and a first surface 1142. The first surface 1142 is a distal surface with respect to the layer of crystalline material 1150. The sidewalls 1148 taper angle with the normal vector of the surface of the layer of crystalline material 1150 due to the crystal growth process. The taper angle is an inward facing angle such that the sidewalls 1148 are closer together near the first surface 1142 than they are near the surface of the crystalline material layer 1150. Thus, the orientation, taper angle, and first surface 1142 of the side wall 1148 characterize the tapered shape of the waveguide body 1146. Although not shown in the cross-sectional view of the steps of process 1200 in fig. 12A, first crystal structure 1140 (or first waveguide 1140) is a symmetrical three-dimensional (3D) structure. Due to the tapered shape of the 3D waveguide body 1146, the 3D waveguide body may be a tapered crystal body 1146. The first surface 1142 may form a truncated cone-shaped waveguide body 1146. In some embodiments, the crystal growth process results in the tapered waveguide body 1146 having a hexagonal pyramid shape truncated via the first surface 1142.

The bottom of fig. 12A shows a perspective view of an exemplary (but non-limiting) embodiment of a three-dimensional (3D) structure of waveguide array 1114, which is formed by an array of crystal structures through the steps of process 1200. As shown at the bottom of fig. 12A, the waveguide array 1114 is a two-dimensional (2D) waveguide array. In other embodiments, waveguide array 1114 may be a one-dimensional (1D) waveguide array. Note that: included in the waveguide array 1114 is the truncated hexagonal pyramid shape of the waveguides. In a perspective view of the waveguide array 1114, the light receiving surface (e.g., the first waveguide surface 1142 of the first waveguide 1140) is shown facing upward, while the light emitting surface (e.g., the second waveguide surface 1144 of the first waveguide 1140) is not visible from this perspective. Note that the vertical orientation of the waveguide array 1114 (relative to the plane of the page) shown in fig. 12A is opposite to the vertical orientation of the waveguide array shown in fig. 11B. For example, the "lower" plane shown in the projected view may represent either the second dielectric layer 1124 or the transparent substrate layer 1130. Note that the vertical orientation of the waveguide array 1114 (relative to the plane of the page) shown in fig. 12A is opposite to the vertical orientation of the waveguide array shown in fig. 11B. Note also that the illustrated vertical orientation of steps 1202-1208 of process 1200 shown in fig. 12A is opposite to the vertical orientation of waveguide array 1114 shown in fig. 11B. The vertical illustrations of steps 1210 through 1218 of process 1200 shown in fig. 12A are the same as the vertical orientation of waveguide 1114 shown in fig. 11B.

Process 1200 may next proceed to step 1204, where an optically reflective layer 1152 may be formed on the array of crystal structures. Reflective layer 1152 may be formed on the "upper" surface of crystalline material layer 1150. The reflective layer 1152 may cover the sidewalls 1148 of the first crystal structure 1140 but not the first surface 1142, as shown in step 1204. Also as shown in step 1204, a reflective layer 1152 may cover at least a portion of the upper surface of the crystalline material layer 1150, wherein the covered portion is located between adjacent crystalline structures of the array of crystalline structures. The reflective layer 1152 may encapsulate at least a portion of the waveguide body 1146. The reflective layer 1152 may be a metallization layer (e.g., an aluminum layer) that prevents light leakage from the sidewalls 1148 of the waveguide body 1146.

Also at step 1204, a first dielectric layer 1122 can be formed over the array of crystal structures such that each of the plurality of crystal structures (including the first crystal structure 1140) is interposed between the first dielectric layer 1122 and the crystal growth substrate 1104. The first dielectric layer 1122 may be silicon dioxide (SiO ₂ ) Or another optically transparent dioxide layer of dioxide. In other embodiments, the first dielectric layer 1122 may be a nitride layer, such as a silicon nitride layer. The first dielectric layer 1122 may encapsulate at least a portion of the waveguide body 1146. The first dielectric layer 1122 can cover at least a portion of the first surface 1142. A reflective layer 1152 may be interposed between the crystalline material layer 1150 and the first dielectric layer 1122, as shown in step 1204.

At step 1206, a transfer wafer 1154 may be bonded to the first dielectric layer 1122 such that each of the crystalline material layer 1150, the reflective layer 1152, and the first dielectric layer 1122 is interposed between the crystal growth substrate 1104 and the transfer wafer 1154. Process 1200 may proceed to step 1208, where crystal growth substrate 1104 may be removed from crystalline material layer 1150 in step 1208. It is also noted that, at least for purposes of illustration, the transfer wafer 1154, first dielectric layer 1122, and crystalline material layer 1150 being bonded have been rotated 180 degrees (in the plane of the page) such that their respective vertical orientations are flipped.

At step 1210, a semiconductor etching process may be employed to remove a portion of crystalline material layer 1150. An etching process may be used to form a second surface on each of the crystal structures. Step 1210 shows: the first waveguide structure 1140 includes a second waveguide surface 1144 in addition to the first waveguide surface 1142. The semiconductor etching process may include forming the second waveguide surface 1144 with a spherical, convex, or any other lenticular shape. In step 1212, a second dielectric layer 1124 may be formed over the waveguide array 1114. The second dielectric layer 1124 may cover a second waveguide surface of the waveguide, including but not limited to a second waveguide surface 1144 of the first waveguide 1140. Thus, a waveguide may be interposed between the first dielectric layer 1122 and the second dielectric layer 1124. The structure comprising the waveguide array 1114 interposed between the first and second dielectric layers 1122, 1124 may be a semiconductor die (or whole wafer), such as the second semiconductor die 1120.

Process 1200 may proceed to step 1214, at step 1214, transparent substrate layer 1130 may be bonded to second dielectric layer 1124 such that second dielectric layer 1124 is interposed between waveguide array 1114 and second dielectric layer 1124. At step 1216, the transfer wafer 1154 may be removed from the second semiconductor die 1120. In step 1218, the second semiconductor die 1120 can be bonded to a first semiconductor die including the array of light emitting devices 1112. The first semiconductor die may be bonded to a first dielectric layer 1122 of a second semiconductor die 1120. By bonding a second semiconductor die 1120 including a waveguide array 1114 to a first semiconductor die including an LED array 1112, the light source 1110 of fig. 11B is formed.

Fig. 12B illustrates a method 1220 for manufacturing the light source 1110 of fig. 11B, according to some embodiments. Method 1220 may include at least a portion of one or more steps of semiconductor process 1200 of fig. 12A. Method 1220 begins at block 1222 where an array of crystal structures is grown on a layer of crystal material deposited on a semiconductor substrate at block 1222. For example, as in step 1202 of process 1200, the crystalline structure forming waveguide array 1114 may be a grown crystalline material layer 1150. A layer of crystalline material may be deposited and/or formed on at least a portion of a semiconductor wafer (e.g., crystal growth substrate 1104). At block 1224, a reflective layer (e.g., metallization layer 1252) may be formed and/or deposited over portions of the crystal structure array (e.g., waveguide array 1114) as shown in the illustration for step 1204 of process 1200. Similar to step 1204 of process 1200, a first dielectric layer (e.g., first dielectric layer 1122) may be formed and/or deposited over the reflective layer, and/or portions of the waveguide array.

At block 1226, the transfer wafer may be bonded to the first dielectric layer (see, e.g., step 1206 of process 1200). At block 1228, the semiconductor substrate (e.g., crystal growth substrate 1104) may be physically separated from the crystal structure array and/or the layer of crystal material (see step 1208 of process 1200). At block 1230, portions of the crystalline material are then removed (e.g., via an etching process) to form a light emitting surface (e.g., second waveguide surface 1144) of each of the waveguides (e.g., see step 1210 of process 1200).

At block 1232, a second dielectric layer (e.g., second dielectric layer 1124) is formed and/or deposited over the layer of crystalline material (e.g., see step 1212 of process 1200). At block 1334, a transparent substrate layer (e.g., transparent substrate layer 1130) may be bonded to the second dielectric layer (e.g., see step 1214 of process 1200). At block 1236, the transfer wafer may be physically separated from the first dielectric layer (e.g., see step 1216 of process 1200). At block 1238, a first semiconductor die including an array of light emitting devices is bonded to a second semiconductor die (e.g., second semiconductor die 1120) including an array of waveguides (see, e.g., step 1218 of process 1200).

In some embodiments of process 1200 and method 1220, as well as other processes and methods discussed herein, a first semiconductor die (or another die) including an array of LEDs is formed on a first semiconductor wafer. A second semiconductor die (or another die) including a waveguide array may be formed on the second semiconductor die. A first semiconductor wafer (e.g., a wafer comprising an array of LEDs) may be sawed (or diced) to form a first plurality of semiconductor die comprising first semiconductor die. That is, the first semiconductor die may be included in a first portion of the first semiconductor wafer. A first portion of the first semiconductor wafer may be removed (e.g., sawed and/or cut) from the first semiconductor wafer to form a first semiconductor die. Similarly, a second semiconductor wafer (e.g., a wafer including an array of waveguides) may be sawed (or diced) to form a second plurality of semiconductor die including a second semiconductor die. That is, the second semiconductor die may be included in the first portion of the second semiconductor wafer. The first portion of the second semiconductor wafer may be removed (e.g., sawed and/or cut) from the second semiconductor wafer to form a second semiconductor die.

In some embodiments, a die (e.g., a first semiconductor die) comprising an array of LEDs may be bonded to a die (e.g., a second semiconductor die) comprising an array of waveguides after the die are formed by sawing or dicing the respective wafers. That is, each of the first semiconductor wafer and the second semiconductor wafer may be diced prior to step 1238. For example, the second semiconductor wafer may be diced between step 1236 and step 1238 to form second semiconductor dies. After the LED array is fabricated on the first wafer, the first semiconductor wafer may be diced (to form first dies). Thus, in step 1238, the first semiconductor die and the second semiconductor die may be aligned and bonded. Such an embodiment may be referred to as a die-level embodiment because the individual dies are bonded to each other after sawing the dies from the respective wafer. In other embodiments, the first semiconductor die and the second semiconductor die may be bonded first, followed by dicing of the wafer. For example, the first and second semiconductor dies may be bonded before they are diced from the first and second semiconductor wafers, while the first and second dies remain part of their respective wafers. These embodiments may be referred to as wafer level embodiments.

High fill factor crystal waveguide

Fig. 13 illustrates an embodiment for a high fill factor waveguide array. The waveguide embodiment shown in fig. 13 may be referred to as a "high fill factor" embodiment. These high fill factor embodiments include waveguide array 1314. The term "fill factor" of a waveguide array (or embodiment) may refer to the ratio of the surface area (or linear dimension) of the light emitting surface of a waveguide (e.g., the second waveguide surface of a waveguide) to the waveguide pitch (e.g., the spatial distance or linear distance between adjacent waveguides of the waveguide array). Thus, the ratio for the high fill factor embodiment may be greater than for the embodiment discussed in connection with fig. 11A-12B.

As used herein, the term "pitch" may refer to or otherwise represent the spatial distance between adjacent elements of an array (e.g., a waveguide array or an LED array). In various embodiments, each LED/waveguide pair of an LED array coupled to a waveguide array may serve as a light source for a pixel in a display (e.g., a pixel in a near-eye display). Thus, the pitch of the LED/waveguide array may match or at least be similar to the pitch of the light receiving surface of the pixel array of the display. For such embodiments, it may be advantageous for the waveguide/LED pairs to fully and/or uniformly illuminate the light receiving surface of the corresponding pixel. This is also advantageous to reduce and/or minimize any illuminated "dark spots" between adjacent light receiving surfaces of the pixels. By increasing the fill factor (e.g., the ratio of the area of the light-emitting surface of the waveguide to the pitch of the light-emitting surface of the waveguide), the high fill factor embodiments achieve greater uniformity of pixel illumination, and a reduction and/or attenuation of illuminated "dark spots" between adjacent light-receiving surfaces of the pixel. Various high fill factor embodiments may increase the fill factor ratio by increasing the surface area of the waveguide illumination surface.

In high fill factor embodiments, the light emitting surface of the waveguide (e.g., the second waveguide surface of the waveguide included in waveguide array 1314) may have a larger surface area, e.g., a larger fill factor, than the light emitting waveguide surface of the waveguide of the embodiments discussed in connection with fig. 11A-12B. The larger surface area of the second waveguide surface of the waveguide, the corresponding LED of which serves as a light source, may provide more uniform and/or complete illumination for the pixel. The waveguide can uniformly illuminate the pixel with its larger light emitting surface. Thus, with the high fill factor embodiments discussed herein, the "dark spots" between adjacent pixels (e.g., areas that receive little or no illumination from the waveguide) are attenuated, reduced, and/or minimized. The high fill factor waveguides included in waveguide array 1314 may additionally provide a greater beam divergence reduction for light passing through the waveguides as compared to waveguide array 1114 shown in fig. 11B-12B and/or discussed in connection with fig. 11B-12B.

Fig. 13 shows three views of a high fill factor waveguide array 1314: a perspective view 1302, a top view 1304, and a cross-section view 1306. The high-fill factor waveguide array 1314 may include a first high-fill factor waveguide 1340. As shown in fig. 13, waveguide array 1314 is a 2D waveguide array. However, similar to the non-high fill factor waveguide array 1114 of fig. 11B, the high fill factor waveguide array 1314 may be fabricated as a 1D high fill factor waveguide array. The high fill factor waveguide (e.g., the first waveguide 1340) may include a light emitting structure (e.g., light emitting structure 1358) as part of its waveguide body. The light emitting structure may be composed of the same material (e.g., gaN) as the waveguide body. The light emitting structure may be located on a portion of the tapered waveguide body that is wider than another portion of the waveguide body. That is, the light emitting structure of the waveguide may be located at the distal end of the waveguide instead of the proximal end of the waveguide. The light emitting structure may further "widen" the light emitting surface of the waveguide, which increases the surface area of the light emitting surface. Thus, the light emitting structure may increase the fill factor of the array. The light emitting surface of the waveguide (e.g., second waveguide surface 1344) is located on the "underside" of the light emitting structure (e.g., light emitting structure 1358) of the perspective view 1302.

During the fabrication of the high fill factor embodiments, an etching process may be employed to alter and/or enhance the shape of the sidewalls and waveguide body of the waveguide from a "default" shape of the sidewalls and waveguide body (e.g., to a default shape resulting from a crystal growth process). The enhanced shape may include the formation of the light emitting structure (e.g., light emitting structure 1358) described above. The light emitting structure formed on the distal end of the waveguide body may be formed by the etching process. For a non-limiting example of one such variation of the default shape of the waveguide body, see the high fill factor embodiment discussed in connection with fig. 13-14B. The enhanced shape may increase the fill factor, and the beam collimation and/or divergence reducing effect of the waveguide. The enhanced shape may include varying the taper (e.g., taper angle) of the waveguide body along the longitudinal dimension of the waveguide. In addition to "shaping" the waveguide via an etching process, the aspect ratio of the waveguide may also be increased. The increased aspect ratio may further enhance the collimation characteristics and/or beam divergence reduction characteristics of the waveguide.

Similar to the first waveguide 1140 of the waveguide array 1114, the first waveguide 1340 of the waveguide array 1314 includes a first waveguide surface 1342, a second waveguide surface 1344, and a waveguide body 1346. Note that: the second waveguide surface 1344 is located on the light emitting structure 1358. The first waveguide surface 1342 receives light generated by the LED and the second waveguide surface 1344 transmits the received light out of the waveguide body 1346. The distal end of the waveguide body 1346 (e.g., the portion of the waveguide body 1346 furthest from the light receiving waveguide surface (e.g., the first waveguide surface 1344)) includes a light emitting structure 1358. In perspective view 1302, second waveguide surface 1344 is located on the "underside" of light emitting structure 1358. The light emitting structure 1358 is a bulk structure and is formed of a crystalline material (e.g., gaN) that constitutes the waveguide body 1346. The light emitting structure 1358 may be a block structure. In some embodiments, the shape of the block-like structure 1358 may be a tapered shape. One or more lateral (or transverse) dimensions of the light emitting structure 1358 (e.g., a spatial dimension that is substantially orthogonal to a dimension along a direction of light through the waveguide body 1346) may be greater than a lateral dimension of the remainder of the waveguide body 1346.

As shown in side view 1306, and similar to waveguide array 1114, waveguide array 1314 may be bonded to transparent substrate layer 1330. Referring again to fig. 11B-12A, the first waveguide 1140 (and each of the other waveguides of the waveguide array 1114) may have a first aspect ratio. Here, the aspect ratio may refer to a ratio of an approximate longitudinal dimension of the waveguide body to an approximate lateral or lateral dimension of the waveguide body. The first high-fill-factor waveguide 1340 (and each of the other waveguides of the high-fill-factor waveguide array 1314) has a second aspect ratio. Visual comparison between the cross-sectional view 1306 and the cross-sectional view of the light source 1110 of fig. 11B shows that the second aspect ratio (of the first waveguide 1340) is greater than the first aspect ratio (of the first waveguide 1140). The "height" of the light emitting structure 1358 may help to increase the aspect ratio. Note that: the "width" of the light emitting structure 1358 helps to increase the fill factor of the waveguide 1340. The greater aspect ratio and fill factor of the high fill factor waveguide can be achieved by etching the waveguide to change the shape of the waveguide body. The larger aspect ratio and fill factor of the high fill factor waveguides of the high fill factor waveguide array 1314 may provide greater beam collimation and/or greater beam divergence reduction than the smaller aspect ratio of the waveguide array 1114. The fabrication of such high fill factor waveguides is discussed in connection with fig. 14A-14B. However, as shown in perspective 1302 and cross-section 1306, the waveguide body 1346 is shaped to approximate a hexagonal mesa. An etching process may form trenches 1356 between adjacent waveguides. The grooves 1356 may reduce the average width of the waveguide, which increases the aspect ratio of the waveguide.

The shape of the trench 1356 (formed via an etching process) may form a "progressive" tapered shape of the waveguide body 1346, wherein the progressive tapered shape enhances beam collimation and/or beam divergence reduction. The etching process may vary the taper angle along the longitudinal dimension of the waveguide body 1346. The shape of the waveguide body 1346 may be characterized by two (or more) taper angles. The cross-sectional view 1306 shows that the taper angle near the second waveguide surface 1346 is smaller than the taper angle near the first waveguide surface 1342. That is, the cone angle of the light beam near the exit of the first waveguide 1340 (via the second waveguide surface 1344) may be smaller than the cone angle of the light beam near the entrance in the first waveguide 1340 (via the first waveguide surface 1342). A decrease in cone angle (as the beam is transmitted through the waveguide body 1346) may result in greater beam collimation and/or a decrease in beam divergence. A larger taper angle near the first waveguide surface 1342 (as compared to a smaller taper angle near the second waveguide surface 1342) may result in a larger distance and/or spacing between adjacent light entering the waveguide surface (e.g., first waveguide surface 1342). In some embodiments, the taper angle may vary continuously along the longitudinal dimension of the waveguide body 1346.

These views also show that the light emitting structure (e.g., light emitting structure 1358) is formed via a discontinuous layer of crystalline material. These discontinuities of the GaN of the light emitting structure may at least partially optically isolate the waveguides of the waveguide array 1314. Such optical isolation may result in less "light leakage" between physically adjacent waveguides in waveguide array 1314. Such discontinuities may cause the array of crystalline material structures acting as light emitting structures to increase the fill factor of the waveguide array. The light emitting structure may be formed and/or fabricated via an etching process of the crystalline material.

Fig. 14A illustrates a semiconductor process 1400 for fabricating the high fill factor waveguide array 1314 of fig. 13, in accordance with certain embodiments. Part of the discussion regarding semiconductor process 1400 will refer to high fill factor waveguide array 1314 of fig. 13, and process 1200 of fig. 12A. The semiconductor process 1400 may begin at step 1402 by forming a layer 1350 of crystalline material on a semiconductor substrate 1304 at step 1402. Similar to step 1202, an array of crystal structures may be grown on a layer 1350 of crystal material deposited on the semiconductor substrate 1304. Thus, the semiconductor material of the substrate 1304 may be a crystal growth substrate. The array of crystal structures forms a high fill factor waveguide array 1314 via the step of etching the layer of crystal material of process 1400. The waveguide array 1314 includes a first high fill-factor waveguide 1340. The first waveguide 1340 includes a first waveguide surface 1342 and a sidewall 1348.

Comparison of the illustrations of step 1402 and step 1202 shows that for a high fill factor embodiment, the initial thickness of the crystalline material layer (e.g., crystalline material layer 1350) may be greater than the thickness of the corresponding crystalline material layer (e.g., the thickness of crystalline material layer 1150) for a non-high fill factor embodiment. An increase in the thickness of the crystalline material layer 1350 may increase the fill factor of the first waveguide layer 1340. For example, etching away portions of the crystalline material layer 1350 (increased thickness) enables shaping of the first waveguide 1340, as shown in step 1403, to provide a greater beam divergence reduction as the beam passes through the first waveguide 1340. In some embodiments, the increased thickness increases the aspect ratio of the high fill factor embodiment.

In step 1403, a semiconductor etch process is performed on the crystalline material layer 1350. As shown in the illustration of step 1403, an etching process may selectively remove the increased thickness portion of the layer of crystalline material to increase the fill factor of the first waveguide 1340. In some embodiments, the etching shapes the first waveguide 1340, and shapes each of the other waveguides to form a hexagonal mesa-shaped waveguide body with a block-shaped light emitting structure on a distal portion of the waveguide body. The etching alters the shape of the waveguide sidewalls 1348 to form a progressive taper shape of the waveguide body 1346. The etching process may create trenches 1356 between adjacent waveguides, as well as create light emitting structures 1358. The shapes of the waveguide body 1346, the light emitting structure 1358, and the trench 1356 may be changed by changing the etching process.

In some embodiments, the semiconductor substrate 1304 may be a crystal growth substrate wafer composed of a growth material such as, but not limited to, si/AlO ₃ . The crystalline material of crystalline material layer 1350 may include, but is not limited to, gaN. An array of crystal structures is grown on a crystal growth substrate 1304. The array of crystal structures includes at least a first crystal structure 1340.

Process 1400 may next proceed to step 1404 where, at step 1404, an optically reflective layer 1352 may be formed on the array of crystal structures. Similar to step 1204, a reflective layer 1352 may be formed on the "upper" surface of the crystalline material layer 1350 at step 1404. Also similar to step 1204, at step 1404, a first dielectric layer 1322 can be formed over the array of crystal structures such that each of the plurality of crystal structures (including the first crystal structure 1340) is interposed between the first dielectric layer 1322 and the crystal growth substrate 1304.

Similar to step 1206, at step 1406, a transfer wafer 1354 may be bonded to the first dielectric layer 1322 such that each of the crystalline material layer 1350, the reflective layer 1352, and the first dielectric layer 1322 is interposed between the crystal growth substrate 1304 and the transfer wafer 1354. Process 1400 may proceed to step 1408. Step 1408 may be similar to step 1208, and the crystal growth substrate 1304 may be removed from the crystal material layer 1350. Also similar to step 1208, in step 1408, the bonded transfer wafer 1354, first dielectric layer 1322, and crystalline material layer 1350 have been rotated 180 ° (in the plane of the page) so that their respective vertical orientations are flipped.

Similar to step 1210, at step 1410, a semiconductor etching process may be employed to remove a portion of crystalline material layer 1350. An etching process may be used to form a second surface on each of the crystal structures. Note that: the etching process performed at step 1410 is performed on the following surfaces of the crystalline material layer 1350: which is opposite to the surface of crystalline material layer 1350 on which the etching process of step 1403 was performed. Step 1410 shows: the first waveguide structure 1340 includes a second waveguide surface 1344 in addition to the first waveguide surface 1342. The semiconductor etching process may include forming the second waveguide surface 1344 with a spherical, convex, or any other lenticular shape. Similar to step 1212, a second dielectric layer 1324 may be formed on the waveguide array 1314 at step 1412. The second dielectric layer 1324 may cover a second waveguide surface of each waveguide, including but not limited to the second waveguide surface 1344 of the first waveguide 1340. Thus, a waveguide may be interposed between the first dielectric layer 1322 and the second dielectric layer 1324. The structure comprising waveguide array 1314 interposed between first dielectric layer 1322 and second dielectric layer 1324 may be a semiconductor die (or an entire wafer), such as second semiconductor die 1320.

Process 1400 may proceed to step 1414, similar to step 1214, at step 1414, transparent substrate layer 1330 may be bonded to second dielectric layer 1324 such that second dielectric layer 1324 is interposed between waveguide array 1314 and second dielectric layer 1324. At step 1416, the transfer wafer 1354 may be removed from the second semiconductor die 1320.

Fig. 14B illustrates a method 1420 for fabricating the high fill factor waveguide array 1314 of fig. 13, in accordance with some embodiments. Method 1420 may include at least a portion of one or more steps of semiconductor process 1400 of fig. 14A. The method 1420 begins at block 1422 by growing an array of crystal structures on a layer of crystal material deposited on a semiconductor substrate at block 1422. For example, as in step 1402 of process 1400, the crystal structure forming waveguide array 1314 may be a grown crystalline material layer 1350. A layer of crystalline material may be deposited and/or formed on at least a portion of a semiconductor wafer (e.g., crystal growth substrate 1304).

At block 1423, portions of the layer of crystalline material are removed to shape the waveguide body from the crystalline structure. Portions of the crystalline material may be removed via a semiconductor etching process, as discussed in connection with step 1403 of process 1400. At block 1424, a reflective layer (e.g., metallization layer 1352) may be formed and/or deposited over portions of the array of crystal structures (e.g., waveguide array 1314), as shown for the illustration of step 1404 of process 1400. Similar to step 1404 of process 1400, a first dielectric layer (e.g., first dielectric layer 1322) may be formed and/or deposited over the reflective layer, and/or portions of the waveguide array. At block 1426, a transfer wafer may be bonded to the first dielectric layer (see, e.g., step 1406 of process 1400). At block 1428, the semiconductor substrate (e.g., crystal growth substrate 1304) may be physically separated from the crystal structure array and/or the layer of crystal material (see step 1408 of process 1400). At block 1430, portions of the crystalline material are then removed (e.g., via an etching process) to form a light emitting surface (e.g., second waveguide surface 1344) of each of the waveguides (see, e.g., step 1410 of process 1400). Note that: the etching process performed at step 1430 is performed on the following surfaces of the crystalline material layer 1350: which is opposite the surface of crystalline material layer 1350 on which the etching process of step 1423 was performed.

At block 1432, a second dielectric layer (e.g., second dielectric layer 1324) is formed and/or deposited over the crystalline material layer (e.g., see step 1412 of process 1400). At block 1434, a transparent substrate layer (e.g., transparent substrate layer 1330) may be bonded to the second dielectric layer (e.g., see step 1414 of process 1400). At block 1436, the transfer wafer may be physically separated from the first dielectric layer (see, e.g., step 1416 of process 1400). At block 1338, a first semiconductor die including an array of light emitting devices is bonded to a second semiconductor die (e.g., second semiconductor die 1120) including an array of waveguides (see, e.g., step 1218 of process 1200).

Waveguide with partition plate

Fig. 15 shows an embodiment of a crystal-partitioned waveguide array 1514. The waveguide embodiment shown in fig. 15 may be referred to as a "baffled" embodiment because the non-transparent baffle structure optically isolating each waveguide from adjacent waveguides enhances the collimation and/or divergence reduction of the light beam passing through the waveguides. The optical isolation of the spacer structures also reduces "light leakage" between adjacent waveguides. These waveguides may additionally and/or alternatively include an oxide "lens" structure that acts as a secondary or tertiary optic that provides further collimation and/or divergence reduction of the light beam passing through the waveguide. In the various embodiments discussed throughout, either or both of the semiconductor spacer structures and/or dielectric lens structures discussed in connection with at least fig. 15-16B may be adapted and additionally deployed in any of the embodiments discussed in connection with fig. 11B-14B.

As shown in fig. 15, the crystal waveguide 1514 includes a first waveguide 1540. Similar to the other waveguides discussed throughout, the first waveguide 1540 includes a first waveguide surface 1542 for light of the LED to enter the waveguide body 1546 of the first waveguide 1540. The waveguide body 1546 transmits light from the first surface 1542 to the second waveguide surface 1544 (which is a planar surface in fig. 15). Similar to other embodiments discussed throughout, second waveguide surface 1542 may emit a light beam (with reduced beam divergence) from waveguide body 1546. As discussed further below, the emitted light beam may enter a dielectric lens structure 1560 for further beam shaping (e.g., collimation and/or divergence reduction).

Dielectric lens structure 1560 may be composed of a transparent dioxide material such as, but not limited to, siO ₂ . Thus, dielectric lens structure 1560 may be a dioxide lens structure. In other embodiments, the dielectric material used to fabricate dielectric lens structure 1560 may be silicon nitride. Due to the difference between the refractive index of the semiconductor material of the waveguide body 1546 and the refractive index of the dielectric material of the dielectric lens structure 1560 (e.g., silicon dioxide or silicon nitride), light may be refracted and/or lens treated via the lens structure 1560. As shown in fig. 15, at least one surface of the dielectric lens structure 1560 (e.g., the second lens surface 1562 that serves as a light emitting surface of the lens 1560) may have a shape similar to a sphere and/or a convex lens. The other surface of the dielectric lens structure 1560 (e.g., the first lens surface 1562 that serves as the light entrance surface of the lens) may be a planar surface that mates with the light emitting surface of the first waveguide 1540 (e.g., the second waveguide surface 1544). Light emitted by the second waveguide surface 1544 may be received by the first lens surface 1562, passed through the lens structure 1560, and emitted by the second lens surface 1564. Thus, the lens structure 1560 may further shape the profile of the light beam emitted by the first waveguide 1540, e.g., the lens structure 1560 may further shape the light of the LED The beam is collimated and/or the divergence of the beam of the LED is reduced. Note that: the dielectric lens structure 1560 may serve as a passivation layer for the first waveguide 1540. One or more spacer structures (e.g., first spacer structure 1582 and second spacer structure 1584) may extend and/or protrude from semiconductor material layer 1550 (or secondary dielectric layer, such as, but not limited to, second dielectric layer 1124 of fig. 11B and/or second dielectric layer 1324 of fig. 14A). As described below, the baffle structure may be used to further optically isolate and/or further shape the beam profile (e.g., to enhance collimation and/or reduce beam divergence). Although the first 1582 and second 1584 are shown in fig. 15 as two separate baffle structures, the first 1582 and second 1584 baffle structures may be a single 3D baffle structure extending into and out of the page.

The spacer structures (first spacer structure 1582 and second spacer structure 1584) may be composed of an opaque semiconductor material, such as, but not limited to, silicon (Si). The opaque semiconductor material may be an optically absorptive material, at least for the frequencies emitted by the LED. The baffle structure of the waveguide may be used to effectively absorb portions of the light beam (emitted by the waveguide) that may "interfere" with the light beam emitted by an adjacent waveguide. That is, the baffle structure further collimates the light beam emitted by the waveguide by removing portions of the light beam emitted by the waveguide near the edges of the beam profile that still fall outside of the emission cone desired for various applications using LEDs as light sources.

As described above, the waveguide may additionally and/or alternatively include a dielectric lens structure (e.g., dielectric lens structure 1560) aligned with the light emitting surface of the waveguide (second waveguide surface 1544 of first waveguide 1540). The dielectric lens structure may be composed of an optically transparent semiconductor material (e.g., a dielectric material) that refracts incident light such that the beam divergence of the incident light beam decreases as it passes through the lens structure. The dielectric material may be a dioxide, such as, but not limited to, silicon dioxide (SiO ₂ ). Thus, the dielectric lens may be an oxide lens. The alignment of the dielectric lens structures with their respective waveguides is such that the lens structures receive the light beams emitted from the light emitting surfaces of the waveguides. As discussed throughout, the angular divergence of the light emitted by the emitting surface of the waveguide has been significantly reduced as it passes through the waveguide body. The light beam emitted by the waveguide is transmitted through (and refracted by) the dielectric lens structure for further collimation and/or divergence reduction. The dielectric lens structure may act as a spherical and/or convex lens for further collimating the light beam and/or reducing the divergence of the light beam. That is, the dielectric lens structure may be used as a collimating secondary optic (or as a tertiary optic for an LED) for a combination of an LED and a semiconductor waveguide.

Fig. 16A illustrates a semiconductor process 1600 for fabricating the array 1514 of the partitioned waveguide of fig. 15, in accordance with certain embodiments. Portions of the discussion regarding semiconductor process 1600 will refer to the array 1514 of waveguides with baffles of fig. 15, as well as process 1200 of fig. 12A and/or process 1400 of fig. 14A. For example, the process 1200 and/or the process 1400 may be adapted to include semiconductor spacer structures (first spacer structure 1582 and second spacer structure 1584) and/or dielectric lens structures (dielectric lens structures 1560) for waveguides of a corresponding waveguide array.

The semiconductor process 1600 may begin at step 1602 with forming a layer 1550 of crystalline material on a semiconductor substrate 1504 at step 1602. Similar to step 1202 of process 1200, an array of crystal structures can be grown on a layer of crystal material 1550 deposited on a semiconductor substrate 1504. Thus, the semiconductor material of the substrate 1504 can be a crystal growth substrate. The semiconductor substrate 1504 may be a semiconductor wafer. The semiconductor material of the substrate 1504 may be an optically opaque and/or optically absorptive material such as, but not limited to, silicon (Si). The semiconductor substrate 1504 may be a silicon wafer. Through the steps of process 1600, an array of crystalline structures is formed into an array of partitioned waveguides 1514. The waveguide array 1514 includes a first slab waveguide 1540. The first waveguide 1540 includes a first waveguide surface 1542, a waveguide body 1546, and a sidewall 1548 surrounding the waveguide body 1546.

At step 1604 (and similar to step 1204 of process 1200), an optically reflective layer 1552 can be formed on the array of crystalline structures. The reflective layer 1552 formed at step 1604 may be formed on the "upper" surface of the crystalline material layer 1550. Also similar to step 1204, at step 1604, a first dielectric layer 1522 may be formed over the array of crystal structures such that the body of each crystal structure (including waveguide body 1546 of first crystal structure 1540) is interposed between first dielectric layer 1522 and semiconductor substrate 1504. Note that: for the first waveguide 1140 of the waveguide array 1114 (see, e.g., fig. 12A), a thin portion of the first dielectric layer covers the planar first waveguide surface 1142 of the first waveguide 1140. In contrast, the first dielectric layer 1522 (see, e.g., fig. 15) of the array of septum waveguides 1514 does not cover the planar first waveguide surface 1542 of the first waveguide 1540. These embodiments may vary, and in some embodiments (e.g., first waveguide 1140, first waveguide 1340, and first waveguide body 1540), the optically transparent first dielectric layer (e.g., first dielectric layer 1122, first dielectric layer 1322, and first dielectric layer 1522) may completely cover the first waveguide surface (e.g., first waveguide surface 1142, first waveguide surface 1342, and first waveguide surface 1142) of the incoming light. In other embodiments, the first dielectric layer may only partially cover the first waveguide surface of the waveguide or not cover it at all.

The process 1600 proceeds to step 1606 where, in step 1606, an etching process is performed on the semiconductor substrate 1504. As shown in the illustration for step 1606, the semiconductor etch process selectively removes portions of the semiconductor substrate 1504 from the semiconductor material layer 1550. The etching process exposes the light emitting surface of each waveguide. For example, the second waveguide surface 1544 is exposed to the first waveguide 1540. The second waveguide surface 1544 will be the light emitting surface of the first waveguide 1540. In this embodiment, each of the first waveguide surface 1542 and the second waveguide surface 1544 of the first waveguide 1540 is a planar surface. In contrast, as shown in fig. 12A, for the first waveguide 1140 of the waveguide array 1114, only the first waveguide surface 1142 is a planar surface. The second waveguide surface 1144 (e.g., light emitting surface) of the first waveguide 1140 is a curved surface. Any of the embodiments discussed herein may include a planar light emitting surface (e.g., a second waveguide surface of a waveguide).

The portions of the opaque (or opaque) semiconductor substrate 1504 that are not removed by the etching process form opaque spacer structures that optically isolate each waveguide from its neighboring waveguides. First spacer structure 1582 and second spacer structure 1584 optically isolate first waveguide 1540 from the other waveguides of waveguide array 1514, as shown in step 1606. Because the first and second baffle structures 1582, 1584 are oriented along the longitudinal dimension of the first waveguide 1540, the baffle structures may be used to further collimate light emitted by the second surface 1544 of the first waveguide 1540 and/or reduce the beam divergence of light emitted by the second surface 1544 of the first waveguide 1540. Although not shown in the 2D plane of fig. 16A, the baffle structure may be a 3D baffle structure that completely surrounds the light beam emitted by the second waveguide surface 1544 for the first waveguide 1540. In some embodiments, the first and second baffle structures 1582, 1584 may form a 3D continuous baffle structure surrounding the light beam emitted by the first waveguide 1540.

Similar to step 1212, a second dielectric layer 1524 may be formed over the waveguide array 1514 at step 1608. The second dielectric layer 1524 may cover a second waveguide surface, such as a light emitting surface of a waveguide (including but not limited to the second waveguide surface 1544 of the first waveguide 1540). As shown in the illustration for step 1608, the second dielectric layer 1524 may substantially encapsulate the diaphragm structures (e.g., the first diaphragm structure 1582 and the second diaphragm structure 1584).

Process 1600 may proceed to step 1610. The vertical (or longitudinal) orientation of the waveguide array 1514 has been flipped over for purposes of illustration of step 1610 at least for clarity. At step 1610, an etching process may be performed on the second dielectric layer 1524. The etching process may be specific to the oxide material of the second dielectric layer 1524 (e.g., siO ₂ ). That is, the etching process of step 1608 does not significantly etch (or remove) the semiconductor material (e.g., si) of the diaphragm structures (e.g., first diaphragm structure 1582 and second diaphragm structure 1584), or the semiconductor material of semiconductor material layer 1550 and/or the waveguide (e.g., gaN). An etching process may be performed to remove portions of the second dielectric layer 1524 such that for each waveguide Only dielectric lens structures (e.g., dielectric lens structures 1560) remain (e.g., first baffle waveguide 1540).

Fig. 16B illustrates a method 1620 for fabricating the slab waveguide array 1514 of fig. 15 in accordance with certain embodiments. Method 1620 may include at least a portion of one or more steps of semiconductor process 1600 of fig. 16A. The method 1620 begins at block 1622, where an array of crystal structures is grown on a layer of crystal material deposited on a semiconductor substrate at block 1622. Similar to step 1602 of process 1600 of fig. 16A, the crystal structure forming waveguide array 1514 may be a grown layer 1550 of crystalline material. A layer of crystalline material may be deposited and/or formed on at least a portion of a semiconductor wafer (e.g., crystal growth substrate 1504).

At block 1624, a reflective layer (e.g., metallization layer 1552) may be formed and/or deposited over portions of the array of crystal structures (e.g., waveguide array 1514). Similar to step 1204 of process 1200, a first dielectric layer (e.g., first dielectric layer 1522) may be formed and/or deposited over the reflective layer, and/or portions of the waveguide array. The reflective layer may provide at least partial optical isolation of each waveguide in the array of waveguides from each other waveguide, as shown in step 1604 of process 1600.

At block 1626, portions of the semiconductor substrate are removed (e.g., by a semiconductor etching process performed on the semiconductor substrate) to form one or more spacer structures for the light emitting surface of each waveguide of the waveguide array. For example, as shown in the illustration for step 1606 of the process 1600, the first and second spacer structures 1582, 1584 can be formed by etching the semiconductor substrate 1504 to block (or confine) light emitted by the second waveguide surface 1544 of the first waveguide 1540 via an absorption process. At block 1628, as shown in the illustration for step 1608 of the process 1600, a second dielectric layer may be formed to cover the crystalline material layer (e.g., crystalline material layer 1550) and/or the light emitting surface of the waveguide (e.g., second waveguide surface 1544 of the first waveguide 1540). At block 1630, as shown in the illustration for step 1610 of process 1600, portions of the second dielectric layer are removed (e.g., by an etching process performed on the second dielectric layer) to form one or more dielectric lens structures of the light emitting surface of each waveguide of the waveguide array. For example, as shown in the illustration for step 1610 of process 1600, dielectric lens structure 1560 may be formed by etching second dielectric layer 1524 to shape the light beam emitted via planar second waveguide surface 1544 of first waveguide 1540.

Embossing tool for manufacturing waveguide array

Various embodiments may include making "soft" or "hard" embossing and/or embossing tools. Such an embossing tool may be used to fabricate the waveguide via an embossing and/or embossing process (e.g., a nanoimprint lithography process) with materials other than crystalline materials (e.g., gaN) used to grow a crystalline structure comprising the waveguide body. For example, these tools may be used to imprint and/or emboss waveguides similar to those described herein in an amorphous material (e.g., silicon dioxide or another refractive material). The processes 1760 and 1780 of fig. 17A-17B are directed to the manufacture of "soft" stamping and/or embossing tools. The processes 1860 and 1880 of fig. 18A-18B are directed to the manufacture of "hard" stamping and/or embossing tools.

Fig. 17A illustrates a semiconductor process 1760 for manufacturing a soft embossing tool 1700 for embossing an array of waveguides in an amorphous material, in accordance with certain embodiments. Part of the discussion regarding semiconductor process 1760 will refer to waveguide array 1114 of fig. 11B, and process 1200 of fig. 12A. Semiconductor process 1760 may begin at step 1762 with the formation of a crystalline material layer 1750 over semiconductor substrate 1704 at step 1762. Similar to step 1202 of process 1200, a crystalline structure array 1714 may be grown on a crystalline material layer 1750 deposited on a semiconductor substrate 1704. Thus, the semiconductor material of the substrate 1704 may be a crystal growth substrate. The shape of the crystal structure array 1714 is similar to the waveguide array 1114 due to the crystal growth process. Thus, based on the crystal growth process, the shape of the crystal structure is substantially uniform across the crystal structure array 1714. The process 1760 includes "transferring" the shape of the array of crystal structures 1714 (and thus the shape of the waveguide array 1114 of fig. 11B) to the soft embossing tool 1700. Thus, reference points 1702 are shown in the illustration of the steps for process 1760 to track the transfer of the shape of crystal structure array 1704 to soft embossing tool 1700.

At step 1764, a layer 1706 of elastic (or soft) material may be formed (or deposited) on the array of crystal structures 1714. In some non-limiting embodiments, the elastic material layer 1706 may be a polymer layer, such as, but not limited to, a silicone (or silicone-like) material layer. In some embodiments, the resilient material layer 1706 may be composed of Polydimethylsiloxane (PDMS). Note the reference point 1702 in the illustration of step 1764. Because the elastic material layer 1706 "matches" the crystal structure array 1714, the shape of the elastic material layer 1706 is complementary to the shape of the crystal structure array 1714. At step 1766, a transfer wafer 1754 may be bonded to the resilient material layer 1706.

At step 1768, the semiconductor substrate 1704 and the array of crystal structures 1714 may be removed (or physically separated) from the layer of elastomeric material 1706 to form the soft embossing tool 1700. Embossing tool 1700 may include a layer of elastomeric material 1706 that is complementary in shape to the shape of waveguide array 1114 in fig. 11B. In some embodiments, the embossing tool may also include a transfer wafer 1704. In other embodiments, the layer of elastic material 1706 may be transferred to another rigid body (e.g., another wafer). For clarity, the vertical orientation of the resilient material layer 1706 and the transfer wafer 1704 has been flipped in the illustration of step 1768. Because the embossing tool 1700 (e.g., the elastomeric layer 1706) has a shape that is complementary to the waveguide array 1114 of fig. 11B, embossing the waveguide material (e.g., a material having waveguide properties and/or a material that refracts light) with the embossing tool 1700 will result in a waveguide that is shaped as the shape of the waveguide array 1114.

Fig. 17B illustrates a method 1780 for fabricating the soft imprinting tool 1700 of fig. 17A, in accordance with certain embodiments. Method 1780 may include at least a portion of one or more steps of semiconductor process 1760 of fig. 17A. The method 1780 begins at block 1782 with growing an array of crystal structures on a layer of crystal material deposited on a semiconductor substrate at block 1782. For example, as in step 1762 of process 1760, the crystal structure forming crystal structure array 1714 may be a grown layer 1750 of crystalline material. A layer of crystalline material may be deposited and/or formed on at least a portion of a semiconductor wafer (e.g., crystal growth substrate 1704).

At block 1784, similar to step 1764 of process 1760, an elastic material layer (e.g., elastic material layer 1706) may be formed (or deposited) on the array of crystalline structures. At block 1786, a transfer wafer (e.g., transfer wafer 1754) may be bonded to the layer of elastomeric material, similar to step 1766 of process 1760. At block 1788, similar to step 1768, a soft embossing tool (e.g., soft embossing tool 1700) may be formed by removing the semiconductor substrate and the array of crystal structures from the layer of elastomeric material. At block 1790, a soft embossing tool may be employed to form a waveguide array (e.g., via a nanoimprint lithography process). At block 1792, an arrayed waveguide may be employed to fabricate a light source.

Fig. 18A illustrates a semiconductor process 1860 for manufacturing a hard embossing tool 1800 for embossing an array of waveguides in an amorphous material, in accordance with certain embodiments. Part of the discussion regarding semiconductor process 1860 will refer to waveguide array 1114 of fig. 11B, and process 1200 of fig. 12A. Semiconductor process 1860 may begin at step 1862 with the formation of a layer 1850 of crystalline material on semiconductor substrate 1804 at step 1862. Similar to step 1202 of process 1200, a crystal structure array 1814 can be grown on a layer 1850 of crystal material deposited on a semiconductor substrate 1804. Thus, the semiconductor material of the substrate 1804 may be a crystal growth substrate. The shape of the array of crystal structures 1814 is similar to the waveguide array 1114 due to the crystal growth process. Thus, based on the crystal growth process, the shape of the crystal structure is substantially uniform across the crystal structure array 1814. Process 1860 includes "transferring" the shape of crystal structure array 1814 (and thus the shape of waveguide array 1114) to hard embossing tool 1800. Thus, a reference point 1802 is shown in the illustration of the steps for process 1860 to track the transfer of the shape of the crystal structure array 1804 to the soft embossing tool 1800.

At step 1864, a photoresist material layer 1806 may be formed (or deposited) over the array of crystalline structures 1814. Note the reference point 1802 in the illustration of step 1864. Because the photoresist layer 1806 matches the array of crystal structures 1814, the shape of the photoresist layer 1806 complements the shape of the array of crystal structures 1814. In addition to soft and/or elastomeric materials (e.g., PDMS used in step 1764 of process 1760 of fig. 17A), photoresist materials may be used in step 1864 so that one or more "hard" layers (e.g., metal layers) may be formed when the hard embossing tool 1800 is manufactured (see, e.g., steps 1870 and 1874 of process 1860). At step 1866, a first transfer wafer 1854 may be bonded to the photoresist layer 1806.

At step 1868, the semiconductor substrate 1804 and the array of crystalline structures 1814 may be removed (or physically separated) from the photoresist layer 1806. Note that the vertical orientation of first transfer wafer 1854 and photoresist layer 1806 has been flipped in the illustration for step 1868. In step 1870, a first "hard" material layer 1808 may be formed from the photoresist layer 1806. The hard material of the first hard material layer 1808 may be a first metal, such as, but not limited to, copper (Cu). Thus, the first hard layer 1808 may be a first metal layer. Because the first metal layer 1808 matches the photoresist layer 1806, the shape of the first hard metal layer 1808 may be complementary to the shape of the photoresist layer 1806. That is, the shape of the first metal layer 1808 is complementary to the shape of the array of crystal structures 1814 (i.e., the shape of the array of crystal structures 1814: the shape of the array of waveguides to be fabricated via the hard embossing tool 1800). In order to emboss the waveguide array, the shape of the embossing tool may need to be similar to the shape of the waveguide array to be embossed. Thus, the embossing tool 1800 may require the shape of the photoresist layer 1806. Accordingly, the shape of the first metal layer 1808 may be transferred to a second metal layer (see, e.g., second metal layer 1810 of step 1874). Also at step 1870, a second transfer wafer 1856 may be bonded to the first metal layer 1808.

In step 1872, the first transfer wafer 1854 and photoresist layer 1806 may be removed from the first metal layer 1808. Note that: in the illustration of step 1872, the vertical orientation of second transfer wafer 1856 and first metal layer 1808 has been flipped. In step 1874, the shape of the first metal layer may be transferred to the second metal layer. For example, the second metal layer 1810 may be formed of the first metal layer 1808. In a non-limiting embodiment, the second metal layer may be composed of a second metal, such as, but not limited to, nickel. Because the second metal layer 1810 matches the first metal layer 1808, the shape of the second metal layer 1810 is complementary to the shape of the first metal layer 1808 (e.g., complementary to the shape of the waveguide array to be embossed). And at step 1874, a third transfer wafer 1858 may be bonded to the second metal layer 1810.

At step 1876, hard embossing tool 1800 may be formed by removing second transfer wafer 1856 and first metal layer 1808 from second metal (or hard) layer 1810. Again, for clarity, the vertical orientation of third transfer wafer 1858 and second metal layer 1810 has been flipped. Thus, the hard transfer tool may include a second metal layer 1810 and a third transfer wafer 1858 (or another rigid body). The hard embossing tool may be used to emboss or emboss the waveguide array in a manner similar to that of the soft embossing tool 1700.

Fig. 18B illustrates a method 1880 for manufacturing the hard imprint tool 1800 of fig. 18A, in accordance with certain embodiments. Method 1880 may include at least a portion of one or more steps of semiconductor process 1860 of fig. 18A. Method 1880 begins at block 1882 where an array of crystal structures is grown at block 1882 on a layer of crystal material deposited on a semiconductor substrate. For example, as in step 1862 of process 1860, the crystal structure forming crystal structure array 1814 may be a grown layer 1850 of crystalline material. A layer of crystalline material may be deposited and/or formed on at least a portion of a semiconductor wafer (e.g., crystal growth substrate 1804).

At block 1884, similar to step 1864 of process 1860, a photoresist layer (e.g., elastomeric layer 1806) may be formed (or deposited) on the array of crystalline structures. Thus, at block 1884, the complementary shape of the array of crystal structures may be transferred to the photoresist layer. At block 1886, similar to step 1866, a first transfer wafer (e.g., first transfer wafer 1854) may be bonded to the photoresist layer. At block 1888, similar to step 1868, the semiconductor substrate and the array of crystal structures may be removed from the photoresist layer. At block 1890, similar to step 1870, a first metal layer (e.g., first metal layer 1808) may be formed and/or deposited on the photoresist layer. Thus, at block 1890, a complementary shape of the layer of photoresist layer may be transferred to the first metal layer. And at block 1890, a second transfer wafer (e.g., second transfer wafer 1856) may be bonded to the first metal layer. At block 1892, similar to step 1872, the first transfer wafer and photoresist layer may be removed from the first metal layer.

In step 1894, similar to step 1874, a second metal layer (e.g., second metal layer 1810) may be formed on the first metal layer. Thus, at block 1894, the complementary shape of the first metal layer may be transferred to the second metal layer. And at block 1894, a third transfer wafer (e.g., third transfer wafer 1858) may be bonded to the second metal layer. At block 1896, a hard embossing tool (e.g., hard embossing tool 1800) may be formed by removing the second transfer wafer and the first metal layer from the second metal layer.

Artificial reality system

Embodiments disclosed herein may be used to implement components of an artificial reality system or may be implemented in conjunction with an artificial reality system. An artificial reality is a form of reality that has been somehow adjusted before being presented to a user, which may include, for example, virtual reality, augmented reality, mixed reality (mixed reality), mixed reality (hybrid reality), or some combination and/or derivative thereof. The artificial reality content may include entirely generated content or generated content in combination with captured (e.g., real world) content. The artificial reality content may include video, audio, haptic feedback, or some combination thereof, and any of these may be presented in a single channel or in multiple channels (such as stereoscopic video producing a three-dimensional effect to the viewer). Further, in some embodiments, the artificial reality may also be associated with an application, product, accessory, service, or some combination thereof for creating content in the artificial reality and/or otherwise for the artificial reality (e.g., performing an activity in the artificial reality), for example. The artificial reality system providing the artificial reality content may be implemented on a variety of platforms including an HMD connected to a host computer system, a standalone HMD, a mobile device or computing system, or any other hardware platform capable of providing the artificial reality content to one or more viewers.

Fig. 19 is a simplified block diagram of an example electronic system 1900 for implementing an example near-eye display (e.g., an HMD device) of some examples disclosed herein. The electronic system 1900 may be used as an electronic system for the HMD device described above or other near-eye display. In this example, the electronic system 1900 may include a memory 1920 and one or more processors 1910. The one or more processors 1910 may be configured to execute instructions for performing the operations at the various components and may be, for example, general purpose processors or microprocessors suitable for implementation within portable electronic devices. One or more processors 1910 may be communicatively coupled with various components within the electronic system 1900. To achieve such communicative coupling, one or more processors 1910 may communicate with other illustrated components via a bus 1940. Bus 1940 may be any subsystem suitable for transmitting data within electronic system 1900. Bus 1940 may include multiple computer buses and additional circuitry for transmitting data.

The memory 1920 may be coupled to one or more processors 1910. In some embodiments, memory 1920 may provide both short-term storage and long-term storage, and may be divided into several units. The memory 1920 may be volatile memory, such as static random-access memory (SRAM) and/or dynamic random-access memory (DRAM), and/or the memory 1620 may be non-volatile memory, such as read-only memory (ROM), flash memory, or the like. In addition, the memory 1920 may include a removable storage device, such as a Secure Digital (SD) card. Memory 1920 may provide storage of computer readable instructions, data structures, program modules, and other data for electronic system 1900. In some embodiments, memory 1920 may be distributed among different hardware modules. A set of instructions and/or code may be stored on memory 1920. The instructions may take the form of executable code that is executable by the electronic system 1900, and/or may take the form of source code and/or installable code that, when compiled and/or installed on the electronic system 1900 (e.g., using any of a variety of commonly used compilers, installers, compression/decompression utilities, etc.), may take the form of executable code.

In some embodiments, memory 1920 may store a plurality of application modules 1922 to 1924, which may include any number of applications. Examples of applications may include gaming applications, conferencing applications, video playback applications, or other suitable applications. These applications may include depth sensing functionality or eye tracking functionality. The application modules 1922 to 1924 may include particular instructions to be executed by the one or more processors 1910. In some embodiments, some or portions of the application modules 1922 through 1924 may be executed by other hardware modules 1980. In some embodiments, memory 1920 may additionally include secure memory that may include additional security controls to prevent copying of secure information or unauthorized other access to secure information.

In some embodiments, memory 1920 may include an operating system 1925 loaded in the memory. The operating system 1925 may be operable to initiate execution of instructions provided by the application modules 1922 to 1924, and/or to manage the other hardware modules 1980 and interact with the wireless communication subsystem 1930, which wireless communication subsystem 1930 may include one or more wireless transceivers. The operating system 1925 may be adapted to perform other operations on the various components of the electronic system 1900, including threading, resource management, data storage control, and other similar functions.

Wireless communication subsystem 1930 may include, for example, infrared communication devices, wireless communication devices, and/or chipsets (such asDevices, IEEE 802.11 devices, wi-Fi devices, wiMax devices, cellular communication facilities, etc.And/or similar communication interfaces. Electronic system 1900 may include one or more antennas 1934 for wireless communication as part of wireless communication subsystem 1930 or as a separate component coupled to any portion of the system. Depending on the desired functionality, wireless communication subsystem 1930 may include separate transceivers to communicate with base transceiver stations and other wireless devices and access points, which may include communicating with different data networks and/or network types, such as Wireless Wide Area Networks (WWANs), wireless local area networks (wireless local area network, WLANs), or wireless personal area networks (wireless personal area network, WPANs). The WWAN may be, for example, a WiMax (IEEE 802.16) network. The WLAN may be, for example, an IEEE 802.11x network. The WPAN may be, for example, a bluetooth network, IEEE 802.15x, or some other type of network. The techniques described herein may also be used for any combination of WWAN, WLAN, and/or WPAN. The wireless communication subsystem 1930 may allow data to be exchanged with the network, other computer systems, and/or any other devices described herein. The wireless communication subsystem 1930 may include means for transmitting or receiving data (e.g., an identifier of an HMD device, location data, geographic map, heat map, photograph, or video) using one or more antennas 1934 and one or more wireless links 1932. The wireless communication subsystem 1930, the one or more processors 1910, and the memory 1920 may together comprise at least a portion of one or more of the means for performing some of the functions disclosed herein.

Embodiments of the electronic system 1900 may also include one or more sensors 1990. The one or more sensors 1990 may include, for example, image sensors, accelerometers, pressure sensors, temperature sensors, proximity sensors, magnetometers, gyroscopes, inertial sensors (e.g., modules having both accelerometers and gyroscopes), ambient light sensors, or any other similar module operable to provide sensory output and/or receive sensory input, such as a depth sensor or a position sensor. For example, in some embodiments, the one or more sensors 1990 may include one or more Inertial Measurement Units (IMUs) and/or one or more position sensors. The IMU may generate calibration data indicative of an estimated position of the HMD device relative to an initial position of the HMD device based on received measurement signals from one or more of the plurality of position sensors. The position sensor may generate one or more measurement signals in response to movement of the HMD device. Examples of position sensors may include, but are not limited to, one or more accelerometers, one or more gyroscopes, one or more magnetometers, other suitable types of sensors that detect motion, a type of sensor for error correction of an IMU, or any combination thereof. The position sensor may be located outside the IMU, inside the IMU, or any combination thereof. At least some of the sensors may sense using a structured light pattern.

Electronic system 1900 may include a display module 1960. The display module 1960 may be a near-eye display and may graphically present information, such as images, video, and various instructions, from the electronic system 1900 to a user. Such information may be obtained from one or more application modules 1922 to 2724, virtual reality engine 1926, one or more other hardware modules 1980, a combination thereof, or any other suitable means for resolving graphical content to a user (e.g., via operating system 1925). The display module 1960 may use LCD technology, LED technology (including, for example, OLED, ILED, μ LED, AMOLED, TOLED, etc.), light emitting polymer display (light emitting polymer display, LPD) technology, or some other display technology.

Electronic system 1900 may include a user input/output module 1970. The user input/output module 1970 may allow a user to send an action request to the electronic system 1900. An action request may be a request to perform a particular action. For example, the action request may be to start an application or end an application, or to perform a particular action within an application. The user input/output module 1970 may include one or more input devices. Exemplary input devices may include: a touch screen, a touch pad, one or more microphones, one or more buttons, one or more dials, one or more switches, a keyboard, a mouse, a game controller, or any other suitable device for receiving an action request and transmitting the received action request to electronic system 1900. In some embodiments, user input/output module 1970 may provide haptic feedback to a user in accordance with instructions received from electronic system 1900. For example, haptic feedback may be provided when an action request is received or has been performed.

Electronic system 1900 may include a camera 1950 that may be used to take pictures or videos of a user, for example, to track the eye position of the user. The camera 1950 may also be used to take photographs or videos of the environment, for example, for VR applications, AR applications, or MR applications. The camera 1950 may include, for example, a Complementary Metal Oxide Semiconductor (CMOS) image sensor having millions or tens of millions of pixels. In some implementations, the camera 1950 may include two or more cameras that may be used to capture 3D images.

In some embodiments, electronic system 1900 may include a plurality of other hardware modules 1980. Each of the other hardware modules 1980 may be a physical module within the electronic system 1900. While each of the other hardware modules 1980 may be permanently configured as a structure, some of the other hardware modules 1980 may be temporarily configured to perform a particular function or be temporarily activated. Examples of other hardware modules 1980 may include, for example, audio output and/or input modules (e.g., microphone or speaker), near field communication (near field communication, NFC) modules, rechargeable batteries, battery management systems, wired/wireless battery charging systems, and the like. In some embodiments, one or more functions of other hardware modules 1980 may be implemented in software.

In some embodiments, memory 1920 of electronic system 1900 may also store virtual reality engine 1926. The virtual reality engine 1926 may execute applications within the electronic system 1900 and receive position information, acceleration information, velocity information, predicted future positions, or any combination thereof, of the HMD device from the various sensors. In some embodiments, the information received by virtual reality engine 1926 may be used to generate signals (e.g., display instructions) to display module 1960. For example, if the received information indicates that the user has seen to the left, the virtual reality engine 1926 may generate content for the HMD device reflecting movement of the user in the virtual environment. Further, the virtual reality engine 1926 may perform actions within the application and provide feedback to the user in response to action requests received from the user input/output module 1970. The feedback provided may be visual, audible or tactile feedback. In some implementations, the one or more processors 1910 may include one or more Graphics Processing Units (GPUs) that may execute a virtual reality engine 1926.

In various embodiments, the hardware and modules described above may be implemented on a single device or on multiple devices that may communicate with each other using wired or wireless connections. For example, in some implementations, some components or modules (e.g., GPU, virtual reality engine 1926, and applications (e.g., tracking applications)) may be implemented on a console separate from the head mounted display device. In some implementations, one console may be connected to or support more than one HMD.

In alternative configurations, different components and/or additional components may be included in electronic system 1900. Similarly, the functionality of one or more of the components may be distributed among the components in a different manner than described above. For example, in some embodiments, electronic system 1900 may be modified to include other system environments, such as an AR system environment and/or an MR environment.

The methods, systems, and devices discussed above are examples. Various embodiments may omit, replace, or add various procedures or components as appropriate. For example, in alternative configurations, the described methods may be performed in a different order than described, and/or various stages may be added, omitted, and/or combined. Furthermore, features described with respect to certain embodiments may be combined in various other embodiments. The different aspects and elements of the embodiments may be combined in a similar manner. Furthermore, technology is evolving and many elements are examples, which do not limit the scope of the disclosure to these specific examples.

Numerous specific details are set forth in the description in order to provide a thorough understanding of the embodiments. However, the embodiments may be practiced without these specific details. For example, well-known circuits, processes, systems, structures, and techniques have been shown without unnecessary detail in order to avoid obscuring the embodiments. The description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the invention. Rather, the foregoing description of these embodiments will provide those skilled in the art with an enabling description for implementing the various embodiments. Various changes may be made in the function and arrangement of elements without departing from the scope of the disclosure.

Furthermore, some embodiments are described as processes depicted as flow charts or block diagrams. Although each process may describe multiple operations as a sequential process, many of these operations can be performed in parallel or concurrently. Furthermore, the order of these operations may be rearranged. The process may have additional steps not included in the figures. Furthermore, embodiments of the methods may be implemented in hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the various tasks may be stored in a computer readable medium such as a storage medium. The processor may perform the plurality of related tasks.

It will be apparent to those skilled in the art that substantial variations may be made in accordance with specific requirements. For example, customized or specialized hardware might also be used and/or particular elements might be implemented in hardware, software (including portable software, such as applets, etc.), or both. In addition, connections to other computing devices, such as network input/output devices, may be employed.

Referring to the figures, components that may include memory may include non-transitory machine readable media. The terms "machine-readable medium" and "computer-readable medium" may refer to any storage medium that participates in providing data that causes a machine to operation in a specific fashion. In the embodiments provided above, various machine-readable media may be involved in providing instructions/code to a processing unit and/or other device or devices for execution. Additionally or alternatively, a machine-readable medium may be used to store and/or carry such instructions/code. In many implementations, the computer readable medium is a physical and/or tangible storage medium. Such a medium may take many forms, including but not limited to, non-volatile media, and transmission media. Common forms of computer-readable media include, for example, magnetic and/or optical media, such as a Compact Disc (CD) or digital versatile disc (digital versatiledisk, DVD), punch cards, paper tape, any other physical medium with patterns of holes, RAM, programmable read-only memory (programmable read-only memory, PROM), erasable programmable read-only memory (erasable programmable read-only memory, EPROM), erasable programmable read-only memory (FLASH-EPROM), any other memory chip or cartridge (cartridge), a carrier wave as described hereinafter, or any other medium from which a computer can read instructions and/or code. The computer program product may include code and/or machine-executable instructions that may represent procedures, functions, subroutines, programs, routines, application programs (apps), subroutines, modules, software packages, classes, or any combination of instructions, data structures, or program statements.

Those of skill in the art will understand that information and signals used to communicate the messages described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The terms "and" or "as used herein may include a variety of meanings that are also intended based at least in part on the context in which they are used. Generally, "or" if used in association with a list (e.g., A, B or C) is intended to mean A, B and C (used herein in an inclusive sense), and A, B or C (used herein in an exclusive sense). Furthermore, the terms "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe some combination of features, structures, or characteristics. It should be noted, however, that this is merely an illustrative example and claimed subject matter is not limited to this example. Furthermore, the term "at least one" if used in connection with a list (e.g., A, B or C) can be construed as any combination of A, B and/or C (e.g., A, AB, AC, BC, AA, ABC, AAB, AABBCCC, etc.).

Furthermore, while certain embodiments have been described using specific combinations of hardware and software, it should be recognized that other combinations of hardware and software are possible. Some embodiments may be implemented in hardware alone, or in software alone, or in a combination of hardware and software. In one example, software may be implemented using a computer program product containing computer program code or instructions executable by one or more processors to perform any or all of the steps, operations, or processes described in this disclosure, wherein the computer program may be stored on a non-transitory computer readable medium. The various processes described herein may be implemented on the same processor or on different processors in any combination.

Where a device, system, component, or module is described as being configured to perform certain operations or functions, such configuration may be achieved, for example, by: designing a plurality of electronic circuits to perform the operation; programming programmable electronic circuitry (e.g., a microprocessor) to perform the operation (e.g., by executing computer instructions or code to perform the operation); or a processor or core programmed to execute code or instructions stored on a non-transitory storage medium; or any combination thereof. Processes may communicate using a variety of techniques, including but not limited to conventional techniques for inter-process communication, and different pairs of processes may use different techniques, or the same pair of processes may use different techniques at different times.

The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that additions, subtractions, deletions, and other modifications and changes may be made without departing from the broader scope as set forth in the claims. Thus, although specific embodiments have been described, these specific embodiments are not intended to be limiting. Various modifications and equivalents fall within the scope of the claims appended hereto.

From the foregoing, it will be seen that this invention is one well adapted to attain all the ends and objects hereinabove set forth together with other advantages which are obvious and which are inherent to the system and method. It will be understood that certain features and subcombinations are of utility and may be employed without reference to other features and subcombinations. This is contemplated by and is within the scope of the claims.

The subject matter of the present invention is described with specificity herein to meet statutory requirements. However, the description itself is not intended to limit the scope of this patent. Rather, the inventors have contemplated that the claimed subject matter might also be embodied in other ways, to include different steps or combinations of steps similar to the ones described in this document, in conjunction with other present or future technologies. Furthermore, although the terms "step" and/or "block" may be used herein to connote different elements of methods employed, the terms should not be interpreted as implying any particular order among or between various steps herein disclosed unless and except when the order of individual steps is explicitly described.

Claims

1. A light source, the light source comprising:

a first semiconductor die including a Light Emitting Device (LED) having a Light Emitting Surface (LES) that emits light out of the LED with a first beam divergence; and

a second semiconductor die bonded to the first semiconductor die, the second semiconductor die including a waveguide, the waveguide comprising:

a first waveguide surface configured to receive light emitted by the LES of the LED at the first beam divergence;

a second waveguide surface; and

a waveguide body comprising a transparent crystalline material that transmits light received by the first waveguide surface to the second waveguide surface, wherein the second waveguide surface and the waveguide body are configured such that the second waveguide surface emits light received by the first waveguide surface out of the waveguide with a second beam divergence that is less than the first beam divergence.

2. The light source of claim 1, wherein the waveguide body has:

i. a tapered shape having a taper angle associated with a growth process of the transparent crystalline material on a semiconductor substrate such that a first surface area of the first waveguide surface is less than a second surface area of the second waveguide surface; or alternatively

A mesa shape formed at least in part by removing a portion of the transparent crystalline material from the second semiconductor die via an etching process.

3. The light source of claim 1 or 2, wherein the waveguide further comprises:

a reflective layer encapsulates a portion of the waveguide body and is configured to reduce transmission losses associated with the waveguide body and to reduce beam divergence of light received by the first waveguide surface.

4. The light source of claim 1, 2 or 3, wherein the second semiconductor die further comprises:

a first dielectric layer encapsulating at least a portion of the waveguide body; and preferably wherein the first dielectric layer covers the first waveguide surface, and the second semiconductor die further comprises:

a second dielectric layer covering the second waveguide surface; and

a layer of transparent crystalline material interposed between the first dielectric layer and the second dielectric layer.

5. The light source of any of claims 1 to 4, wherein the second semiconductor die further comprises:

an opaque spacer structure positioned around at least a portion of a perimeter of the second waveguide surface and extending beyond a plane of the second semiconductor die to define a columnar volume extending beyond the plane of the second semiconductor die, wherein the spacer structure is configured to limit transmission of light emitted by the second waveguide surface and exiting the second semiconductor die within the columnar volume extending beyond the plane of the second semiconductor die.

6. The light source of any of the preceding claims, wherein the second waveguide surface has a curved shape formed at least in part by removing a portion of the transparent crystalline material from the second semiconductor die via an etching process, such that the curved shape of the second waveguide surface is configured to reduce beam divergence of light emitted by the second waveguide surface and exiting the second semiconductor die.

7. The light source of any of the preceding claims, wherein the shape of the second waveguide surface is a planar shape, and the second semiconductor die further comprises:

a convex dielectric lens covering the second waveguide surface, the convex dielectric lens receiving light emitted by the second waveguide surface at the second beam divergence, wherein the convex dielectric lens emits light received by the convex lens at a third beam divergence that is less than the second beam divergence.

8. The light source according to any of the preceding claims, further comprising:

a transparent glass substrate bonded to the second semiconductor die and covering the second waveguide surface such that the second semiconductor die is interposed between the first semiconductor die and the glass substrate.

9. A light source as claimed in any one of the preceding claims, wherein the transparent crystalline material is gallium nitride (GaN) grown on a semiconductor substrate.

10. A light source according to any of the preceding claims, wherein,

the first semiconductor die includes an LED array including the LEDs; and is also provided with

The second semiconductor die includes a waveguide array including the waveguides, wherein there is a one-to-one correspondence between each LED of the LED array and each waveguide of the waveguide array such that the LEDs uniquely correspond to the waveguides.

11. The light source of claim 10, wherein the waveguide array is formed at:

i. on the continuous layer of transparent crystalline material, a waveguide body of each waveguide of the waveguide array protruding from the continuous layer of transparent crystalline material, a proximal surface of each waveguide of the waveguide array comprising a portion of the continuous layer of transparent crystalline material, and a distal surface of each waveguide of the waveguide array being displaced from the continuous layer of transparent crystalline material; or alternatively

A discontinuous layer of transparent crystalline material, the discontinuous layer comprising an array of separate dielectric layer portions formed via an etching process, and there being a one-to-one correspondence between each dielectric layer portion of the array of separate dielectric layer portions and each waveguide of the array of waveguides.

12. The light source of any of the preceding claims, wherein the light source is included in a wearable device that generates at least one of a virtual reality environment or an augmented reality environment for a user wearing the wearable device.

13. A light source as claimed in any one of the preceding claims, wherein the optical coupling efficiency between the LED and the waveguide is at least 0.70; and/or preferably wherein each spatial dimension of each defect in the optical surface finish of the waveguide is LESs than 5 nanometers (nm; and/or preferably wherein the LED is a micro light emitting diode and the LES of the LED has a spatial dimension of LESs than 10 microns.

14. A method of manufacturing a light source, the method comprising:

fabricating a first semiconductor die comprising a Light Emitting Device (LED) having a Light Emitting Surface (LES) that emits light out of the LED with a first beam divergence;

fabricating a second semiconductor die, the second semiconductor die comprising a waveguide having a first waveguide surface, a second waveguide surface, and a waveguide body, the waveguide body comprising a transparent crystalline material; and

The second semiconductor die is bonded to the first semiconductor die such that the first waveguide surface is configured to receive light emitted by the LES of the LED at the first beam divergence, wherein the waveguide body is configured to transmit light received by the first waveguide surface to the second waveguide surface, and the second waveguide surface is configured to emit light received by the first waveguide surface out of the waveguide at a second beam divergence that is LESs than the first beam divergence.

15. An apparatus, the apparatus comprising:

a second waveguide surface; and