CN116868342A

CN116868342A - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Info

Publication number: CN116868342A
Application number: CN202180093116.2A
Authority: CN
Inventors: 吴颖; 侯朝昭; 许俊豪
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-05-31
Filing date: 2021-05-31
Publication date: 2023-10-10
Also published as: WO2022252041A1

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a field effect transistor. The field effect transistor includes a gate, a drain, a source, and an oxide semiconductor channel. The source electrode and the drain electrode are respectively positioned at two ends of the oxide semiconductor channel. The drain electrode and the source electrode are respectively contacted with a plurality of surfaces of the oxide semiconductor channel to increase contact areas of the source electrode and the drain electrode with the oxide semiconductor channel, thereby reducing contact resistance. Since the contact resistance of the semiconductor device is reduced, the current at the same voltage is increased, thereby improving the current driving capability and response speed of the field effect transistor.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Technical Field

The present disclosure relates to the field of electronics, and more particularly to semiconductor devices and methods of manufacturing the same.

Background

With the development of semiconductor technology, the integration level of integrated circuit chips manufactured using semiconductor materials is increasing. For example, the number of field-effect transistors (FETs) housed in integrated circuits is increasing. On the other hand, the size of integrated circuit chips is also becoming smaller to accommodate the trend of miniaturization of electronic devices. For example, in a Complementary Metal Oxide Semiconductor (CMOS) FET that uses a silicon material as a conductive channel, the channel length is becoming smaller. The size of CMOS FETs is correspondingly smaller, so that more CMOS FETs can be integrated per unit area of chip.

In conventional chip manufacturing processes, the process temperature of CMOS devices based on silicon channel materials often exceeds 1000 ℃, which makes the CMOS device manufacturing process difficult to be compatible with back end of line (BEOL) processes requiring relatively low temperatures (e.g., below 500 ℃).

Disclosure of Invention

In view of the foregoing, embodiments of the present disclosure are directed to providing a semiconductor device, an integrated circuit, a chip, an electronic assembly and an electronic apparatus including the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device may be BEOL compatible.

According to a first aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a field effect transistor. The field effect transistor includes a first gate, an oxide semiconductor channel, a first dielectric, a first drain, and a first source. The oxide semiconductor channel has opposite first and second ends with a middle portion on either side of the middle portion. The first dielectric is disposed between the oxide semiconductor channel and the first gate. The first drain is disposed in contact with at least a first end of the oxide semiconductor channel. The first source is disposed in contact with at least a second end of the oxide semiconductor channel. The first drain electrode is in contact with a first surface and a second surface of a first end of the oxide semiconductor channel. The first source electrode is in contact with the third surface and the fourth surface of the second end of the oxide semiconductor channel. The first surface is different from the second surface and the third surface is different from the fourth surface. By forming a channel using an Oxide Semiconductor (OS) material, a manufacturing process of manufacturing a field effect transistor including an OS channel can be made compatible with a back-end process. This is because the fabrication process of the field effect transistor of the OS channel may be less than 500 degrees celsius, unlike the fabrication process of the CMOS transistor, which typically requires more than 1000 degrees celsius. Processing temperatures below 500 degrees celsius do not affect the structure formed by the back-end process, for example, do not cause impurities to be diffused into interconnects such as copper interconnects. In addition, by bringing the respective surfaces of the source and drain into contact with the OS channel, the contact area of the OS channel with the source and drain is increased, thereby significantly reducing the contact resistance of the transistor. Compared with the case of increasing only the contact of the OS channel with the respective single surfaces of the source and drain, the driving capability and response speed of the transistor can be significantly improved due to the increase in the contact area of the source and drain with the OS channel, while not affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, a first end of the oxide semiconductor channel is embedded in the first drain and a second end of the oxide semiconductor channel is embedded in the first source. By embedding the end portions of the OS channel in the drain and source electrodes, the contact area of the OS channel with the drain and source electrodes is further increased, thereby further improving the driving capability and response speed of the transistor without affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, the entire surface of the first end of the oxide semiconductor channel is in contact with the first drain electrode, and the entire surface of the second end of the oxide semiconductor channel is in contact with the first source electrode. By fully contacting the end of the OS channel with the drain and the source, the contact area of the OS channel with the drain and the source is further increased, thereby further improving the driving capability and response speed of the transistor without affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, a middle portion of an OS channel of a transistor includes a first portion, a second portion contiguous with the first portion, and a third portion contiguous with the second portion. The direction of extension of the first portion is angled, for example between 45 degrees and 135 degrees, for example 90 degrees, to the direction of extension of the second portion. The direction of extension of the second portion is angled, for example between 45 degrees and 135 degrees, for example 90 degrees, to the direction of extension of the third portion. The first portion is in contact with the first source electrode and the third portion is in contact with the first drain electrode. By forming the OS channel having the middle portion of the U-shape or the inverted U-shape, the contact area of the OS channel with the drain and the source can be further increased, thereby further improving the driving capability and the response speed of the transistor without affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, the transistor further includes a second gate and a second dielectric. An oxide semiconductor channel is disposed between the second gate and the first gate. A second dielectric is disposed between the oxide semiconductor channel and the second gate. By providing a double gate structure including a first gate and a second gate in the transistor, a control voltage can be applied to both the first gate and the second gate to better overcome the short channel effect to control the on and off of the channel, thereby enabling the device to be further scaled down. On the other hand, since on and off of the channel can be controlled by using the double gate, the doping level of the OS channel can be more flexible, and the selection of the OS material can be more flexible.

In one possible implementation, a middle portion of an OS channel of a transistor includes a first portion, a second portion contiguous with the first portion, and a third portion contiguous with the second portion, wherein the second portion is located between a first gate and a second gate. The direction of extension of the first portion is angled, for example at an angle between 70 degrees and 110 degrees, for example 90 degrees, to the direction of extension of the second portion. The direction of extension of the second portion is angled, for example at an angle between 70 degrees and 110 degrees, for example at 90 degrees, to the direction of extension of the third portion. The first portion is in contact with the first source electrode and the third portion is in contact with the first drain electrode. By forming the OS channel having the middle portion of the U-shape or the inverted U-shape, the contact area of the OS channel with the drain and the source can be further increased, thereby further improving the driving capability and the response speed of the transistor without affecting the miniaturization of the transistor having the OS channel. In addition, due to the use of the double gate structure, the size of the device can be further reduced and the selection of the OS material can be more flexible.

In one possible implementation, the first gate includes a fin gate. The fin gate wraps around a first surface, a second surface, and a third surface of a portion of the intermediate portion of the oxide semiconductor channel. In one possible implementation, the first surface of the fin gate and the second surface of the fin gate are parallel to each other, and the first surface of the fin gate and the second surface of the fin gate are perpendicular to the third surface of the fin gate. Compared with a single-gate and double-gate control structure, the fin gate can control an OS channel from three surfaces, so that the short channel effect can be better overcome to control the on and off of the channel, and the size of the device can be further reduced.

In one possible implementation, the first gate surrounds a side surface of a portion of the intermediate portion of the oxide semiconductor channel. The gate-all-around transistor can be formed by making the gate surround a side surface of a part of the middle portion of the OS channel. Compared with a single-gate and double-gate control structure, the fin gate can control an OS channel from three surfaces, so that the short channel effect can be better overcome to control the on and off of the channel, and the size of the device can be further reduced.

In one possible implementation, the transistor further includes an embedded dielectric. An embedded dielectric is disposed inside the oxide semiconductor channel. The transistor with the OS channel is an unconditional transistor and the OS channel is also doped with a certain doping concentration, e.g. n-type doping. For doped OS channels, the switching characteristics of transistor devices are relatively sensitive to channel thickness. When an OS channel of solid structure is employed, variations in hole size (diameter of the OS channel) may cause device-to-device fluctuations, for example, the switching threshold voltages of different transistors may be different accordingly, which is very disadvantageous for transistor control. In contrast, when a dielectric is embedded in the OS channel, the thickness of the OS channel can be precisely controlled by atomic layer deposition. Thus, the electrical performance of each transistor can be continuous and consistent, and chip circuit design and control can be simplified.

In one possible implementation, the OS channel of the transistor is elongated or cylindrical.

In one possible implementation, the semiconductor device further includes an isolation region. The isolation region is stacked over the underlying complementary metal oxide transistor circuit. A field effect transistor is stacked over the isolation region. Since the isolation region and the field effect transistor located on the isolation region are sequentially stacked above the lower-layer complementary metal oxide transistor circuit, circuits with different functions can be realized in the vertical direction, thereby increasing the function and integration density of the semiconductor device and correspondingly reducing the occupied area of the semiconductor device.

In one possible implementation, the semiconductor device further includes a second gate and a second dielectric. An oxide semiconductor channel is disposed between the second gate and the first gate. A second dielectric is disposed between the oxide semiconductor channel and the second gate. The second gate and the second dielectric are located in the recess of the isolation region. By providing a double gate structure including a first gate and a second gate in the transistor, a control voltage can be applied to both the first gate and the second gate to better overcome the short channel effect to control the on and off of the channel, thereby enabling the device to be further scaled down. On the other hand, since on and off of the channel can be controlled by using the double gate, the doping level of the OS channel can be more flexible, and the selection of the OS material can be more flexible. In addition, since the second gate electrode and the second dielectric are embedded in the isolation region, the height of the semiconductor device can be reduced, and the integration of the semiconductor device can be improved.

In one possible implementation, the OS channel is disposed vertically, e.g., perpendicular to the isolation region surface. The vertical arrangement is advantageous because the horizontal arrangement tends to increase the area of the semiconductor device, but the space in the vertical direction of the chip is not fully utilized. By providing at least a part of the transistors as transistors with vertically arranged channels, the switching performance of the transistors can be improved while the occupation space of the semiconductor device can be greatly reduced, which is particularly advantageous for three-dimensional monolithic integrated chips.

According to a second aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a field effect transistor. The field effect transistor includes an oxide semiconductor channel, a dielectric, a gate, a drain, and a source. The dielectric surrounds a side surface of a portion of the intermediate portion of the oxide semiconductor channel. The gate surrounds a side surface of the dielectric. The drain is disposed in contact with a first end of the oxide semiconductor channel. The source electrode is disposed in contact with a second end of the oxide semiconductor channel, the second end being opposite to the first end. By forming a channel using an oxide semiconductor material, a manufacturing process for manufacturing a field effect transistor including an OS channel can be made compatible with a back-end process. This is because the fabrication process of the field effect transistor of the OS channel may be less than 500 degrees celsius, unlike the fabrication process of the CMOS transistor, which typically requires more than 1000 degrees celsius. Processing temperatures below 500 degrees celsius do not affect the structure formed by the back-end process, for example, do not cause impurities to be diffused into interconnects such as copper interconnects.

In one possible implementation, the drain is disposed around a side surface of the first end and the source is disposed around a side surface of the second end. By having the source and drain surrounding the side surfaces of the OS channel, the contact area of the OS channel with the source and drain is increased, thereby significantly reducing the contact resistance of the transistor. Compared with the case where only the end surfaces of the OS channel are in contact with the respective surfaces of the source and drain, the driving capability and response speed of the transistor can be significantly improved due to the increase in the contact areas of the source and drain with the OS channel, while not affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, the first end is embedded in the drain and the second end is embedded in the source. By embedding the end portions of the OS channel in the drain and source electrodes, the contact area of the OS channel with the drain and source electrodes is further increased, thereby further improving the driving capability and response speed of the transistor without affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, the semiconductor device further includes an embedded dielectric. An embedded dielectric is disposed inside the oxide semiconductor channel. An embedded dielectric is disposed inside the oxide semiconductor channel. The transistor with the OS channel is an unconditional transistor and the OS channel is also doped with a certain doping concentration, e.g. n-type doping. For doped OS channels, the switching characteristics of transistor devices are relatively sensitive to channel thickness. When using an OS channel of solid structure, variations in hole size may cause device-to-device fluctuations, for example, the switching threshold voltages of different transistors may be different accordingly, which is very detrimental to transistor control. In contrast, when a dielectric is embedded in the OS channel, the thickness of the OS channel can be precisely controlled by atomic layer deposition. Thus, the electrical performance of each transistor can be continuous and consistent, and chip circuit design and control can be simplified.

In one possible implementation, an isolation region is also included. Isolation regions are stacked over underlying CMOS circuitry, and field effect transistors are stacked over the isolation regions. The isolation region is stacked over the underlying complementary metal oxide transistor circuit. A field effect transistor is stacked over the isolation region. Since the isolation region and the field effect transistor located on the isolation region are sequentially stacked above the lower-layer complementary metal oxide transistor circuit, circuits with different functions can be realized in the vertical direction, thereby increasing the function and integration density of the semiconductor device and correspondingly reducing the occupied area of the semiconductor device.

According to a third aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first oxide semiconductor channel, a first dielectric, a first gate, a first drain, and a first source. The first dielectric surrounds a side surface of a portion of the intermediate portion of the first oxide semiconductor channel. The first gate surrounds a side surface of the first dielectric. The first drain is disposed in contact with a first end of the first oxide semiconductor channel. The first source is disposed in contact with a second end of the first oxide semiconductor channel, the second end being opposite to the first end. The second field effect transistor includes a second oxide semiconductor channel, a second dielectric, a second gate, a second drain, and a second source. The second dielectric surrounds a side surface of a portion of the intermediate portion of the second oxide semiconductor channel. The second gate surrounds a side surface of the second dielectric. The second drain is coupled to the first source and is disposed in contact with a third end of the second oxide semiconductor channel. And a second source electrode disposed in contact with a fourth end of the second oxide semiconductor channel, the fourth end being opposite to the third end. By forming the channel using an OS material, a manufacturing process for manufacturing a field effect transistor including the OS channel can be made compatible with a back-end process. This is because the fabrication process of the field effect transistor of the OS channel may be less than 500 degrees celsius, unlike the fabrication process of the CMOS transistor, which typically requires more than 1000 degrees celsius. Processing temperatures below 500 degrees celsius do not affect the structure formed by the back-end process, for example, do not cause impurities to be diffused into interconnects such as copper interconnects.

In one possible implementation, the second drain is integrally formed with the first source. By integrally forming one drain and one source of two field effect transistors, the steps of the processing process, the cost, and the size of the semiconductor device can be reduced.

In one possible implementation, the first drain is disposed around a side surface of the first end, and the first source is disposed around a side surface of the second end. The second drain electrode is disposed around a side surface of the third terminal, and the second source electrode is disposed around a side surface of the fourth terminal. By having the source and drain surrounding the side surfaces of the OS channel, the contact area of the OS channel with the source and drain is increased, thereby significantly reducing the contact resistance of the transistor. Compared with the case where only the end surfaces of the OS channel are in contact with the respective surfaces of the source and drain, the driving capability and response speed of the transistor can be significantly improved due to the increase in the contact areas of the source and drain with the OS channel, while not affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, the first end is embedded in the first drain and the second end is embedded in the first source. The third terminal is embedded in the second drain and the fourth terminal is embedded in the second source. By embedding the end portions of the OS channel in the drain and source electrodes, the contact area of the OS channel with the drain and source electrodes is further increased, thereby further improving the driving capability and response speed of the transistor without affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, the first field effect transistor is a depletion mode field effect transistor and the first gate is connected to the first source through a via. By connecting the gate and source of the depletion-mode field effect transistor, a logic device having an OS channel, such as an inverter, a NAND gate (NAND), or a NOR gate (NOR), can be effectively formed. In another possible implementation, the first field effect transistor is an enhancement mode field effect transistor and the first gate is connected to the first drain through a via. By connecting the gate and drain of the enhancement mode field effect transistor, an inverter, a NAND gate (NAND), or a NOR gate (NOR) with an OS channel can be effectively formed.

In one possible implementation, the first field effect transistor and the second field effect transistor are formed in the same horizontal layer. In another possible implementation, the first field effect transistor is stacked over the second field effect transistor. By implementing different transistors in the vertical direction, the functionality and integration density of the semiconductor device are increased and the footprint of the semiconductor device is correspondingly reduced.

In one possible implementation, the semiconductor device further includes a first embedded dielectric and a second embedded dielectric. The first embedded dielectric is disposed inside the first oxide semiconductor channel. A second embedded dielectric is disposed within the second oxide semiconductor channel. An embedded dielectric is disposed inside the oxide semiconductor channel. An embedded dielectric is disposed inside the oxide semiconductor channel. The transistor with the OS channel is an unconditional transistor and the OS channel is also doped with a certain doping concentration, e.g. n-type doping. For doped OS channels, the switching characteristics of transistor devices are relatively sensitive to channel thickness. When using an OS channel of solid structure, variations in hole size may cause device-to-device fluctuations, for example, the switching threshold voltages of different transistors may be different accordingly, which is very detrimental to transistor control. In contrast, when a dielectric is embedded in the OS channel, the thickness of the OS channel can be precisely controlled by atomic layer deposition. Thus, the electrical performance of each transistor can be continuous and consistent, and chip circuit design and control can be simplified.

In one possible implementation, the semiconductor device further includes an isolation region. An isolation region is stacked over the underlying CMOS circuit, wherein a first field effect transistor and a second field effect transistor are stacked over the isolation region. The isolation region is stacked over the underlying complementary metal oxide transistor circuit. A field effect transistor is stacked over the isolation region. Since the isolation region and the field effect transistor located on the isolation region are sequentially stacked above the lower-layer complementary metal oxide transistor circuit, circuits with different functions can be realized in the vertical direction, thereby increasing the function and integration density of the semiconductor device and correspondingly reducing the occupied area of the semiconductor device.

According to a fourth aspect of the present disclosure, a circuit assembly is provided. The circuit assembly includes a circuit board and the semiconductor device described above. The semiconductor device is disposed on the circuit board.

According to a fifth aspect of the present disclosure, an electronic device is provided. The electronic device comprises a power supply means and a circuit assembly according to the fourth aspect of the present disclosure, powered by the power supply means.

According to a sixth aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes forming an oxide semiconductor channel on a substrate; forming a first drain at a first end of the oxide semiconductor channel such that the first drain is in contact with at least a first surface and a second surface of the first end of the oxide semiconductor channel, the first surface being different from the second surface; and forming a first source electrode at the second end of the oxide semiconductor channel such that the first source electrode is in contact with at least a third surface and a fourth surface of the second end of the oxide semiconductor channel, the first end and the second end being opposite, and the third surface being different from the fourth surface. The method further includes forming a first dielectric over a portion of a middle portion of the oxide semiconductor channel, the middle portion of the oxide semiconductor channel being located between a first end of the oxide semiconductor channel and a second end of the oxide semiconductor channel; and forming a first gate on the first dielectric. In one possible implementation, the substrate is, for example, an isolation region. By forming a channel using an oxide semiconductor material, a manufacturing process for manufacturing a field effect transistor including an OS channel can be made compatible with a back-end process. This is because the fabrication process of the field effect transistor of the OS channel may be less than 500 degrees celsius, unlike the fabrication process of the CMOS transistor, which typically requires more than 1000 degrees celsius. Processing temperatures below 500 degrees celsius do not affect the structure formed by the back-end process, for example, do not cause impurities to be diffused into interconnects such as copper interconnects. In addition, by bringing the respective surfaces of the source and drain into contact with the OS channel, the contact area of the OS channel with the source and drain is increased, thereby significantly reducing the contact resistance of the transistor. Compared with the case of increasing only the contact of the OS channel with the respective single surfaces of the source and drain, the driving capability and response speed of the transistor can be significantly improved due to the increase in the contact area of the source and drain with the OS channel, while not affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, forming the first drain at the first end of the oxide semiconductor channel such that the first drain contacts at least the first surface and the second surface of the first end of the oxide semiconductor channel includes: forming a first drain at a first end of the oxide semiconductor channel such that the first end of the oxide semiconductor channel is embedded in the first drain; and forming a first source at the second end of the oxide semiconductor channel such that the first source contacts at least the third and fourth surfaces of the second end of the oxide semiconductor channel comprises: a first source is formed at the second end of the oxide semiconductor channel such that the second end of the oxide semiconductor channel is embedded in the first source. By embedding the end portions of the OS channel in the drain and source electrodes, the contact area of the OS channel with the drain and source electrodes is further increased, thereby further improving the driving capability and response speed of the transistor without affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, forming the first drain at the first end of the oxide semiconductor channel such that the first drain contacts at least the first surface and the second surface of the first end of the oxide semiconductor channel includes: forming a first drain at a first end of the oxide semiconductor channel such that an entire surface of the first end of the oxide semiconductor channel is in contact with the first drain, and forming a first source at a second end of the oxide semiconductor channel such that the first source is in contact with at least a third surface and a fourth surface of the second end of the oxide semiconductor channel comprises: the entire surface of the second end of the oxide semiconductor channel is in contact with the first source electrode. By fully contacting the end of the OS channel with the drain and the source, the contact area of the OS channel with the drain and the source is further increased, thereby further improving the driving capability and response speed of the transistor without affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, the method further includes forming a second gate and a second dielectric. An oxide semiconductor channel is formed between the second gate and the first gate. A second dielectric is formed between the oxide semiconductor channel and the second gate. By providing a double gate structure including a first gate and a second gate in the transistor, a control voltage can be applied to both the first gate and the second gate to better overcome the short channel effect to control the on and off of the channel, thereby enabling the device to be further scaled down. On the other hand, since on and off of the channel can be controlled by using the double gate, the doping level of the OS channel can be more flexible, and the selection of the OS material can be more flexible.

In one possible implementation, forming the OS channel includes forming an intermediate portion of the OS channel, the intermediate portion including a first portion, a second portion contiguous with the first portion, and a third portion contiguous with the second portion, wherein the second portion is located between the first gate and the second gate. The direction of extension of the first portion is angled, for example at an angle between 70 degrees and 110 degrees, for example 90 degrees, to the direction of extension of the second portion. The direction of extension of the second portion is angled, for example at an angle between 70 degrees and 110 degrees, for example at 90 degrees, to the direction of extension of the third portion. The first portion is in contact with the first source electrode and the third portion is in contact with the first drain electrode. By forming the OS channel having the middle portion of the U-shape or the inverted U-shape, the contact area of the OS channel with the drain and the source can be further increased, thereby further improving the driving capability and the response speed of the transistor without affecting the miniaturization of the transistor having the OS channel. In addition, due to the use of the double gate structure, the size of the device can be further reduced and the selection of the OS material can be more flexible.

In one possible implementation, forming the first gate on the dielectric includes forming a fin gate on the dielectric. The first surface of the fin gate and the second surface of the fin gate are parallel to each other, and the first surface of the fin gate and the second surface of the fin gate are perpendicular to the third surface of the fin gate. Compared with a single-gate and double-gate control structure, the fin gate can control an OS channel from three surfaces, so that the short channel effect can be better overcome to control the on and off of the channel, and the size of the device can be further reduced.

In one possible implementation, forming the first gate on the dielectric includes forming the first gate on the dielectric surrounding a side surface of a portion of the intermediate portion of the oxide semiconductor channel. The gate all around transistor may be formed by having the gate surround a side surface of a portion of the middle portion of the OS channel. Compared with a single-gate and double-gate control structure, the fin gate can control an OS channel from three surfaces, so that the short channel effect can be better overcome to control the on and off of the channel, and the size of the device can be further reduced.

In one possible implementation, forming an oxide semiconductor channel on a substrate includes: an embedded dielectric is formed inside the oxide semiconductor channel. An embedded dielectric is disposed inside the oxide semiconductor channel. The transistor with the OS channel is an unconditional transistor and the OS channel is also doped with a certain doping concentration, e.g. n-type doping. For doped OS channels, the switching characteristics of transistor devices are relatively sensitive to channel thickness. When an OS channel of solid structure is employed, variations in hole size (diameter of the OS channel) may cause device-to-device fluctuations, for example, the switching threshold voltages of different transistors may be different accordingly, which is very disadvantageous for transistor control. In contrast, when a dielectric is embedded in the OS channel, the thickness of the OS channel can be precisely controlled by atomic layer deposition. Thus, the electrical performance of each transistor can be continuous and consistent, and chip circuit design and control can be simplified.

In one possible implementation, forming an oxide semiconductor channel on a substrate includes forming an isolation region on the substrate, the substrate including complementary metal oxide transistor (CMOS) circuitry; and forming an oxide semiconductor channel on the isolation region. Since the isolation region and the field effect transistor located on the isolation region are sequentially stacked above the lower-layer complementary metal oxide transistor circuit, circuits with different functions can be realized in the vertical direction, thereby increasing the function and integration density of the semiconductor device and correspondingly reducing the occupied area of the semiconductor device.

In one possible implementation, forming an oxide semiconductor channel on a substrate includes: forming a first portion of an oxide semiconductor channel on the substrate, the first portion of the oxide semiconductor channel being in contact with the first source; forming a second portion of the oxide semiconductor channel over the substrate, the second portion of the oxide semiconductor channel being contiguous with the first portion; and forming a third portion of the oxide semiconductor channel over the substrate, the third portion of the oxide semiconductor channel being contiguous with the second portion and in contact with the first drain, the first portion extending in a first direction at an angle to the second portion extending in a second direction at a second angle to the third portion extending in a direction, wherein the first and second angles are each between 45 ° and 135 °. By forming the OS channel having the middle portion of the U-shape or the inverted U-shape, the contact area of the OS channel with the drain and the source can be further increased, thereby further improving the driving capability and the response speed of the transistor without affecting the miniaturization of the transistor having the OS channel.

According to a seventh aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method comprises the following steps: forming an oxide semiconductor channel over a substrate; a dielectric formed around a side surface of a portion of the intermediate portion at a side surface of a portion of the intermediate portion of the oxide semiconductor channel; forming a gate electrode surrounding a side surface of the dielectric at the side surface of the dielectric; forming a drain electrode at the first end of the oxide semiconductor channel in contact with the first end of the oxide semiconductor channel; and forming a source electrode at a second end of the oxide semiconductor channel in contact with the second end of the oxide semiconductor channel, the second end being opposite to the first end. By forming a channel using an oxide semiconductor material, a manufacturing process for manufacturing a field effect transistor including an OS channel can be made compatible with a back-end process. This is because the fabrication process of the field effect transistor of the OS channel may be less than 500 degrees celsius, unlike the fabrication process of the CMOS transistor, which typically requires more than 1000 degrees celsius. Processing temperatures below 500 degrees celsius do not affect the structure formed by the back-end process, for example, do not cause impurities to be diffused into interconnects such as copper interconnects.

In one possible implementation, forming a drain at the first end of the oxide semiconductor channel in contact with the first end of the oxide semiconductor channel includes: forming a drain electrode at a first end of the oxide semiconductor channel around a side surface of the first end; and forming a source electrode in contact with the second end of the oxide semiconductor channel at the second end of the oxide semiconductor channel includes: a source electrode is formed at the second end of the oxide semiconductor channel around a side surface of the second end. By having the source and drain surrounding the side surfaces of the OS channel, the contact area of the OS channel with the source and drain is increased, thereby significantly reducing the contact resistance of the transistor. Compared with the case where only the end surfaces of the OS channel are in contact with the respective surfaces of the source and drain, the driving capability and response speed of the transistor can be significantly improved due to the increase in the contact areas of the source and drain with the OS channel, while not affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, forming a drain at the first end of the oxide semiconductor channel in contact with the first end of the oxide semiconductor channel includes: forming a drain electrode wrapping the first end at the first end of the oxide semiconductor channel; and forming a source electrode in contact with the second end of the oxide semiconductor channel at the second end of the oxide semiconductor channel includes: a source electrode is formed at the second end of the oxide semiconductor channel that wraps around the second end. By embedding the end portions of the OS channel in the drain and source electrodes, the contact area of the OS channel with the drain and source electrodes is further increased, thereby further improving the driving capability and response speed of the transistor without affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, forming the oxide semiconductor channel over the substrate further includes forming an embedded dielectric inside the oxide semiconductor channel. An embedded dielectric is disposed inside the oxide semiconductor channel. The transistor with the OS channel is an unconditional transistor and the OS channel is also doped with a certain doping concentration, e.g. n-type doping. For doped OS channels, the switching characteristics of transistor devices are relatively sensitive to channel thickness. When using an OS channel of solid structure, variations in hole size may cause device-to-device fluctuations, for example, the switching threshold voltages of different transistors may be different accordingly, which is very detrimental to transistor control. In contrast, when a dielectric is embedded in the OS channel, the thickness of the OS channel can be precisely controlled by atomic layer deposition. Thus, the electrical performance of each transistor can be continuous and consistent, and chip circuit design and control can be simplified.

In one possible implementation, forming the OS channel on the substrate further comprises forming an isolation region on the substrate and forming the OS channel on the isolation region, the substrate comprising CMOS circuitry. Isolation regions are stacked over underlying CMOS circuitry, and field effect transistors are stacked over the isolation regions. The isolation region is stacked over the underlying complementary metal oxide transistor circuit. A field effect transistor is stacked over the isolation region. Since the isolation region and the field effect transistor located on the isolation region are sequentially stacked above the lower-layer complementary metal oxide transistor circuit, circuits with different functions can be realized in the vertical direction, thereby increasing the function and integration density of the semiconductor device and correspondingly reducing the occupied area of the semiconductor device.

In one possible implementation, forming the OS via over the substrate includes forming an OS channel disposed vertically over the substrate, e.g., perpendicular to the isolation region surface. The vertical arrangement is advantageous because the horizontal arrangement tends to increase the area of the semiconductor device, but the space in the vertical direction of the chip is not fully utilized. By providing at least a part of the transistors as transistors with vertically arranged channels, the switching performance of the transistors can be improved while the occupation space of the semiconductor device can be greatly reduced, which is particularly advantageous for three-dimensional monolithic integrated chips.

According to an eighth aspect of the present disclosure, a method for forming a semiconductor device is provided. The method includes forming a first field effect transistor on a substrate. The first field effect transistor includes a first oxide semiconductor channel, a first dielectric, a first gate, a first drain, and a first source. The first dielectric surrounds a side surface of a portion of the intermediate portion of the first oxide semiconductor channel. The first gate surrounds a side surface of the first dielectric. The first drain is disposed in contact with a first end of the first oxide semiconductor channel. The first source is disposed in contact with a second end of the first oxide semiconductor channel, the second end being opposite to the first end. The method further includes forming a second field effect transistor on the substrate. The second field effect transistor includes a second oxide semiconductor channel, a second dielectric, a second gate, a second drain, and a second source. The second dielectric surrounds a side surface of a portion of the intermediate portion of the second oxide semiconductor channel. The second gate surrounds a side surface of the second dielectric. The second drain is coupled to the first source and is disposed in contact with a third end of the second oxide semiconductor channel. And a second source electrode disposed in contact with a fourth end of the second oxide semiconductor channel, the fourth end being opposite to the third end. By forming the channel using an OS material, a manufacturing process for manufacturing a field effect transistor including the OS channel can be made compatible with a back-end process. This is because the fabrication process of the field effect transistor of the OS channel may be less than 500 degrees celsius, unlike the fabrication process of the CMOS transistor, which typically requires more than 1000 degrees celsius. Processing temperatures below 500 degrees celsius do not affect the structure formed by the back-end process, for example, do not cause impurities to be diffused into interconnects such as copper interconnects.

In one possible implementation, the first drain is formed around a side surface of the first end, and the first source is formed around a side surface of the second end. The second drain electrode is formed around a side surface of the third terminal, and the second source electrode is formed around a side surface of the fourth terminal. By having the source and drain surrounding the side surfaces of the OS channel, the contact area of the OS channel with the source and drain is increased, thereby significantly reducing the contact resistance of the transistor. Compared with the case where only the end surfaces of the OS channel are in contact with the respective surfaces of the source and drain, the driving capability and response speed of the transistor can be significantly improved due to the increase in the contact areas of the source and drain with the OS channel, while not affecting the miniaturization of the transistor having the OS channel.

In one possible implementation, forming the first transistor further includes forming a first embedded dielectric in the first gate and forming the second transistor further includes forming a second embedded dielectric in the second gate. The first embedded dielectric is disposed inside the first oxide semiconductor channel. A second embedded dielectric is disposed within the second oxide semiconductor channel. An embedded dielectric is disposed inside the oxide semiconductor channel. An embedded dielectric is disposed inside the oxide semiconductor channel. The transistor with the OS channel is an unconditional transistor and the OS channel is also doped with a certain doping concentration, e.g. n-type doping. For doped OS channels, the switching characteristics of transistor devices are relatively sensitive to channel thickness. When using an OS channel of solid structure, variations in hole size may cause device-to-device fluctuations, for example, the switching threshold voltages of different transistors may be different accordingly, which is very detrimental to transistor control. In contrast, when a dielectric is embedded in the OS channel, the thickness of the OS channel can be precisely controlled by atomic layer deposition. Thus, the electrical performance of each transistor can be continuous and consistent, and chip circuit design and control can be simplified.

In one possible implementation, the method further includes forming an isolation region over the underlying CMOS circuit, and the first field effect transistor and the second field effect transistor are formed over the isolation region. The isolation region is stacked over the underlying complementary metal oxide transistor circuit. A field effect transistor is stacked over the isolation region. Since the isolation region and the field effect transistor located on the isolation region are sequentially stacked above the lower-layer complementary metal oxide transistor circuit, circuits with different functions can be realized in the vertical direction, thereby increasing the function and integration density of the semiconductor device and correspondingly reducing the occupied area of the semiconductor device.

It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:

FIG. 1 shows a schematic diagram of an electronic device according to one embodiment of the present disclosure;

FIG. 2 illustrates a simplified block diagram of an electronic component according to one embodiment of the present disclosure;

fig. 3 shows a schematic block diagram of a field effect transistor according to one embodiment of the present disclosure;

fig. 4 shows a schematic structural diagram of a field effect transistor according to another embodiment of the present disclosure;

fig. 5 shows a schematic structural diagram of a field effect transistor according to still another embodiment of the present disclosure;

fig. 6 shows a schematic block diagram of a back gate field effect transistor according to one embodiment of the present disclosure;

fig. 7 shows a schematic block diagram of a dual gate field effect transistor according to one embodiment of the present disclosure;

fig. 8 shows a schematic perspective block diagram of a field effect transistor according to one embodiment of the present disclosure;

fig. 9 illustrates a schematic block diagram of a portion of a horizontal ring gate field effect transistor according to one embodiment of the present disclosure;

fig. 10 shows a schematic structural diagram of the horizontal gate-all-around field effect transistor of fig. 9;

fig. 11 illustrates a schematic block diagram of a portion of a vertical gate-all-around field effect transistor according to one embodiment of the present disclosure;

fig. 12 shows a schematic structural diagram of the vertical gate-all-around field effect transistor of fig. 11;

FIG. 13 shows a schematic circuit diagram and schematic block diagram of an inverter according to one embodiment of the disclosure;

FIG. 14 shows a schematic block diagram of an inverter according to one embodiment of the disclosure;

FIG. 15 shows a schematic block diagram of an inverter according to one embodiment of the disclosure;

FIG. 16 shows a circuit schematic and schematic block diagram of an inverter according to one embodiment of the disclosure;

FIG. 17 shows a schematic block diagram of an inverter according to one embodiment of the disclosure;

FIG. 18 shows a schematic block diagram of an inverter according to one embodiment of the disclosure;

FIG. 19 shows a schematic circuit diagram and schematic block diagram of a NAND gate according to one embodiment of the present disclosure;

FIG. 20 shows a schematic circuit diagram and schematic block diagram of a NOR gate according to one embodiment of the present disclosure;

FIG. 21 shows a schematic circuit diagram and schematic block diagram of a NAND gate according to one embodiment of the present disclosure;

FIG. 22 shows a schematic circuit diagram and schematic block diagram of a NOR gate, according to one embodiment of the present disclosure;

fig. 23 shows a flowchart of a method for manufacturing a semiconductor device according to one embodiment of the present disclosure;

fig. 24 shows a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present disclosure; and

Fig. 25 shows a flowchart of a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.

In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. The term "and/or" means at least one of the two items associated therewith. For example, "a and/or B" means A, B, or a and B. Other explicit and implicit definitions are also possible below. Herein, "end surface" means a surface that is outermost in the direction of extension of the end and is at an angle to the direction of extension of the end and is non-parallel (e.g., perpendicular). The "upper surface of the end portion" means a surface of an upper portion of the end portion in its extending direction, for example, a surface on an upper side of the end portion in the drawing and perpendicular to the drawing plane. "side surface of the end" means a surface that is angled and non-parallel (e.g., perpendicular) to the upper surface and the end surface in the direction of extension of the end. In the case where the cross section of the end portion transverse to the direction in which the end portion extends is circular, elliptical, or other smooth continuous shape, only the end portion side surface and the end portion surface may be provided without an upper surface.

In the following description of the specific embodiments, some repetition is not described in detail, but it should be understood that the specific embodiments have mutual references and may be combined with each other.

As described above, in conventional chip manufacturing processes, the process temperature of CMOS devices based on silicon channel materials is often as high as thousands of degrees celsius, which makes the CMOS device manufacturing process difficult to be compatible with BEOL processes requiring relatively low temperatures, such as below 500 degrees celsius. For example, during the fabrication of CMOS FETs, the channel regions in the FETs are often doped, such as by high energy particle implantation, to form various conductive channels. However, such doping can cause the temperature of at least a portion of the region in the FET to be as high as thousands of degrees celsius, for example 1050 ℃. For BEOL processes such as interconnects, the temperatures that can be tolerated by metal lines such as copper (Cu) lines used for interconnects are often below 1000 ℃, e.g., BEOL processes typically require below 450 ℃. High energy ion implantation can cause ions or other elements to diffuse into the interconnect under high temperature conditions, affecting the performance of the interconnect and thus the device. Thus, it is difficult to grow and stack CMOS devices over the areas formed by BEOL processes after BEOL processes are used.

In some embodiments of the present disclosure, by using an oxide semiconductor material to form a channel in a FET, the temperature of the processing process of the FET may be controlled to a relatively low temperature, for example below 500 ℃ or 450 ℃. Herein, OS material means a material comprising an electronic structure of (n-1) d ¹⁰ ns ⁰ Metal oxides of the metal ion class, e.g. In ₂ O ₃ [In ³⁺ :(Kr)(4d) ¹⁰ (5s) ⁰ (5p) ⁰ ]，Ga ₂ O ₃ [Ga ³⁺ :(Ar)(3d) ¹⁰ (4s) ⁰ (4p) ⁰ ]，SnO ₂ [Sn ⁴⁺ :(Kr)(4d) ¹⁰ (5s) ⁰ (5p) ⁰ ]， ZnO[Zn ²⁺ :(Ar)(3d) ¹⁰ (4s) ⁰ ]And the corresponding doped oxides, e.g. Sn-doped In ₂ O ₃ (ITO), W-doped In ₂ O ₃ ,InGaZnO _x ,InAlZnO _x Etc. The electronic structure (n-1) d described above ¹⁰ ns ⁰ Wherein n represents a main quantum number, s, p and d represent different electron orbitals, respectively, and Kr and Ar represent primordia in an electron arrangement, respectively. OS due to the presence of s-orbital metal ions not filled with electrons, the mobility of OS material can reach 10-100cm even in amorphous state ² /(V-s). The electron mobility of the OS is comparable to that of polysilicon. Second, since the bandgap of OS is above 3 electron volts (eV), which is much greater than that of polysilicon by 1.1eV, the leakage of OS FET is much smaller than that of polysilicon FET at the same size. Thus, the drive capability of the OS FET can reach or even exceed that of the polysilicon FET. Meanwhile, the uniformity of the amorphous OS device is far better than that of polysilicon because no grain boundary exists. By using an OS material to form the channel of the FET, the process temperature of the OS FET can be controlled below 400 ℃ so that the fabrication process of the OS FET can be compatible with BEOL processes. For example, the OS FET may be fabricated after the BEOL process.

Fig. 1 shows a schematic diagram of an electronic device 100 according to one embodiment of the present disclosure. In one embodiment, the electronic device 100 is, for example, a smart phone. Other electronic devices are also possible, such as a computer, tablet computer or other intelligent terminal device. The electronic device 100 includes an integrated circuit assembly 10 as well as other components not shown, such as other chips, sensors, etc. The integrated circuit assembly 10 may be formed as at least a portion of an integrated circuit system. In one embodiment, the integrated circuit assembly 10 may include a plurality of packaged chips on a circuit board such as a printed circuit board (printed circuit board, PCB) or a flexible circuit board (flexbile printed circuit, FPC). Each packaged chip may have one or more chips packaged therein. In another embodiment, the integrated circuit assembly 30 itself is a single chip, e.g., a (system in a parckage, siP) chip with multiple chips integrated therein. The present disclosure is not limited in any way herein to the form of the integrated circuit assembly 30.

Fig. 2 illustrates a simplified block diagram of the electronic assembly 10 according to one embodiment of the present disclosure. In one embodiment, the integrated circuit assembly 10 may be, for example, a printed circuit board with integrated chips. The integrated circuit assembly 10 may include a first chip 12, a second chip 14, and a second chip 16. The integrated circuit assembly 10 may also include other chips or components not shown. The first chip 12 may communicate with the second chip 14 to communicate commands and/or data, and may also communicate with the third chip 16 to communicate commands and/or data. It will be appreciated that the first chip 12, the second chip 14 and the third chip 16 may also communicate with other chips or components, respectively. The present disclosure does not impose any limitation on this. In one embodiment, at least one of the first chip 12, the second chip 14, and the third chip 16 is, for example, a three-dimensional monolithic integrated (M3D) chip. The M3D chip can significantly improve chip performance and reduce power consumption by stacking components of different functions, such as logic units, memory units, sensor units, RF units, etc., together in a vertical direction. Meanwhile, in some embodiments of the present disclosure, at least a portion of the M3D chip may include an OS FET to form different circuit components, and the different circuit components may be integrated through BEOL processes without bonding of different wafers, and thus device costs may be effectively reduced.

In one embodiment, the first chip 12 may be an M3D chip. In this M3D chip, the underlying circuit 12-1 may be formed by a CMOS process, followed by forming an interconnect layer 12-2 including interconnect lines therein over the CMOS device layer 12-1, and then forming a logic device layer 12-3 including OS FETs over the interconnect layer 12-2. The logic device layer 12-3 located above the interconnect layer 12-2 may include a plurality of FETs 30-1, 30-2 … … -Q, where Q represents a positive integer and the plurality of FETs 30-1, 30-2 … … -Q have the same or similar structure. Therefore, the FET 30 will be hereinafter referred to as a representative FET of the plurality of FETs 30-1, 30-2 … … 30-Q. It will be appreciated that there are other types or configurations of FETs in the first chip 12, which the present disclosure is not limited to.

Fig. 3 shows a schematic block diagram of FET 30 according to one embodiment of the present disclosure. It will be appreciated that there may be further interconnect layers and/or circuit layers above the logic device layer, which is not limiting in this disclosure. In addition, the underlying circuitry may also include OS FETs, rather than CMOS FETs. For example, the FET 30 may also be located in an underlying circuit.

In one embodiment, FET 30 includes a gate 38, a drain 34, a source 36, a dielectric 39, and an OS channel 31.FET 30 is a planar FET in which dielectric 39 may include a gate oxide, such as HfO ₂ And a dielectric 39 is located between gate 38 and OS channel 31 to electrically isolate gate 38 from the OS channel. An OS channel 31 is located over isolation region 32, and a drain 34 and a source 36 are located across OS channel 31. The OS channel 31 may be selectively turned on by applying a voltage to the gate 38. Since the channel 31 is made of an OS material, the FET 30 may be compatible with BEOL processes, i.e., there may be CMOS or other circuit layers below the isolation region 32. The FET 30 may be formed after the formation of the lower layer wiring so that the FET 30 may be stacked over the lower layer circuit. Since the individual circuit components are vertically stacked together, off-chip wire bonding may be eliminated, effectively reducing manufacturing costs, enhancing device performance, and reducing power consumption.

The OS material is typically n-doped by nature of the material itself. Unlike Si channel devices, the channel region is not currently doped by ion implantation or the like, and the manner of ion implantation is not compatible with BEOL processes. The OS FET is therefore a junction-free device, i.e. the doping concentration of the channel and the source and drain are substantially the same. To ensure the normal switching characteristics of the device, the doping concentration of the channel cannot be too high, otherwise the FET cannot be effectively turned off. It has been found through research that the drive capability and response speed of OS FETs are not ideal due to the limitation of channel doping, especially in FETs with small channel dimensions such as the order of nanometers. In some embodiments of the present disclosure, it is proposed to use a fully or partially clad contact structure to effectively increase the contact area of the source and drain with the channel contact, thereby improving the driving capability and response speed of the OS FET. Specifically, the larger the contact area of the source and drain, the smaller the contact resistance. The smaller the total resistance of the OS FET device, the larger the current will be at the same voltage, thereby improving the driving capability and response speed.

In fig. 3, the OS channel 31 includes a first end 311, a middle portion 312, and a second end 313, wherein a portion of the middle portion 312 is located under the gate 38 and the dielectric 39 to be controlled by the gate 38, the first end 311 is embedded in the drain 34, e.g., all surfaces of the first end 311 or all surfaces except a lower surface in contact with an underlying isolation layer are in contact with the drain 34, and the second end 313 is embedded in the source 36, e.g., all surfaces of the second end 313 or all surfaces except a lower surface in contact with an underlying isolation layer are in contact with the source 36. More specifically, the drain 34 is in contact with the surfaces of the first end 311 of the OS channel 31, and the source 36 is in contact with the surfaces of the second end 313 of the OS channel 31. In one embodiment, the channel 31 has a bar-like structure, and an upper surface of the first end 311, an end surface remote from the second end 313, and both side surfaces in the channel extending direction are in contact with the drain electrode 34. An upper surface of the second end portion 313, an end surface remote from the first end portion 311, and both side surfaces in the channel extending direction are in contact with the source electrode 36, wherein the end surface represents a surface that is outermost in the end extending direction (lateral direction shown in the drawing) and is perpendicular to the end extending direction, and the side surface of the end portion represents a surface perpendicular to both the upper surface and the side surface in the end extending direction. The end surfaces and side surfaces hereinafter have the same meaning and are not described in detail. In some embodiments, where the OS channel is cylindrical or elliptical, as shown in fig. 9 and 11, there may be no upper surface but only end and side surfaces. In this context, the embedded means that the end surface of the end of the OS channel, and the portions of the upper surface and the side surface that meet the end surface are in full contact with the drain and the source without exposed portions. Accordingly, in the case where the OS channel is cylindrical or elliptical, the embedded means that the end surface and the portion of the side surface of the OS channel that meets the end surface are in full contact with the drain and the source without exposing the portions. In order to protrude the difference between the end portions and the middle portion, the end portions and the middle portion are represented using different patterns in fig. 3, and in the case where the end portions are embedded in the source and drain electrodes, the end portion periphery is shown in dotted lines. It will be appreciated, however, that the end portions and the intermediate portion are actually integrally formed and are illustrated for distinction only.

Although the contact resistance can be reduced by increasing the area of the drain or source in contact with the upper surface of the channel, this results in an increase in the size of the FET and is counter to the miniaturization of FET devices. Accordingly, the contact area of the source and drain of the FET 30 having an OS channel with the OS channel is greatly increased compared to a conventional FET device in which only the upper surface of the channel is in contact with the drain or source, thereby significantly reducing the contact resistance. Therefore, as described above, the driving capability and response speed of the FET 30 can be significantly improved due to the increase in the contact area of the source and drain with the OS channel, while not affecting the miniaturization of the FET 30 having the OS channel. Although fig. 3 illustrates one implementation of source and drain contacts to an OS channel, the scope of the present disclosure is not limited in this regard.

Fig. 4 shows a schematic structural diagram of a FET 40 according to another embodiment of the present disclosure. Similar to FET 30, FET 40 includes drain 44, gate 48, dielectric 49, source 46, OS channel 41, and isolation region 42. Like parts have like numerals and thus are not described in detail herein for the same or similar parts. The various portions of FET 40 may be found in the description above for the various portions of fig. 3. FET 40 differs from FET 30 in the manner in which the ends of the OS channel are in contact with drain 44 and source 46. In fig. 4, the ends of the OS channel are not embedded in the drain 44 and source 46. Specifically, the drain 44 is in contact with a first surface and a second surface of the first end of the OS channel 41, and the source 46 is in contact with a third surface and a fourth surface of the second end of the OS channel 41, wherein the first surface is different from the second surface and the third surface is different from the fourth surface. For example, the drain electrode 44 partially covers the first end portion of the OS channel 41 to be in contact with the upper surface and the end surface of the first end portion, and both side surfaces of the first end portion of the OS channel 41 in the channel extending direction are exposed. Similarly, the source 46 partially covers the second end portion of the OS channel 41 to be in contact with the upper surface and the end surface of the second end portion, and both side surfaces of the second end portion of the OS channel 41 in the channel extending direction are exposed. Alternatively, the drain electrode 44 may also partially cover the upper surface and both side surfaces of the first end portion of the OS channel 41, and the source electrode 46 may also cover the upper surface and both side surfaces of the second end portion of the OS channel 41. By partially cladding two or more surfaces of both end portions of the OS channel 41, the contact area of the source and drain contacts can be effectively increased, thereby improving the driving capability and response speed of the OS FET.

Fig. 5 shows a schematic structural diagram of a FET 50 according to yet another embodiment of the present disclosure. Similar to FETs 30 and 40, FET 50 includes drain 54, gate 58, dielectric 59, source 56, OS channel 51, and isolation region 52. Like parts have like numerals and thus are not described in detail herein for the same or similar parts. The various portions of FET 40 may be found in the description above for the various portions of fig. 3 and 4. FET 50 differs from FET 30 and FET 40 in the manner in which the ends of the OS channel contact drain 54 and source 56. Specifically, the OS channel 51 is embedded in the drain 54 and the source 56, respectively, after extending upward to a certain height at both ends of the intermediate portion 512. The drain electrode 54 is in contact with the upper surface, the lower surface, the end surface, and both side surfaces of the first end 511 of the OS channel 51. In addition, the drain electrode 54 is also in contact with the surface of the upward extension of the middle portion 511. Similarly, the source 56 is in contact with the upper surface, the lower surface, the end surface, and both side surfaces of the second end 513 of the OS channel 51. Further, the source 56 is also in contact with the surface of the upward extension of the middle portion 511. By fully cladding two or more surfaces of both end portions of the OS channel 51, the contact area of the source and drain contacts can be effectively increased, thereby improving the driving capability and response speed of the OS FET.

Some embodiments of FETs with top gates are described above with respect to fig. 3-5, however the present disclosure is not so limited. In some embodiments, FETs with back gates may also be used. FIG. 6 shows a schematic of a back gate FET 60 according to one embodiment of the present disclosureStructure diagram. In one embodiment, FET 60 includes a gate 68, a drain 64, a source 66, a dielectric 69, and an OS channel. FET 60 is a planar FET in which dielectric 69 may include a gate oxide, such as HfO ₂ And a dielectric 69 is located between gate 68 and the OS channel to electrically isolate gate 68 from the OS channel. A gate electrode 68 is located on the isolation region 62, and a dielectric layer 69 covers both side surfaces and upper surfaces of the gate electrode 68 and an upper surface of the isolation region 62, and an OS channel covers both side surfaces and upper surfaces of the dielectric layer 69 and is isolated from the gate electrode 68. Two end portions 611 and 613 of the OS channel are respectively located on the dielectric layer 69, and a middle portion 612 of the OS channel covers an upper surface and side surfaces of the middle portion of the dielectric layer 69. The upper surface of the middle portion of the OS channel may also have an additional isolation region 65 to protect and isolate the OS channel. The OS channel may be selectively turned on by applying a voltage to gate 68. Since the channel is made of an OS material, FET 60 may be compatible with BEOL processing, i.e., there may be CMOS circuit layers or other circuit layers below isolation region 62. The FET 60 may be formed after the formation of the lower layer wiring so that the FET 60 may be stacked over the lower layer circuit. Since the individual circuit components are vertically stacked together, off-chip wire bonding may be eliminated, effectively reducing manufacturing costs, enhancing device performance, and reducing power consumption.

In one embodiment, the first end 611 of the OS channel is embedded in the drain 64 such that the drain 64 is in contact with the upper surface, end surface, and both side surfaces of the first end 611 of the OS channel. In addition, the drain electrode 64 is also in contact with the surface of the downward extension of the middle portion 611. Similarly, the second end 613 is embedded in the source 66 such that the source 66 is in contact with the upper surface, end surface, and both side surfaces of the second end 613 of the OS channel. In addition, the source 66 is also in contact with the surface of the downward extension of the middle portion 611. By fully cladding two or more surfaces of both end portions of the OS channel, the contact area of the source and drain contacts can be effectively increased, thereby improving the driving capability and response speed of the OS FET. While one implementation of a back gate FET is shown with respect to fig. 6, it is to be understood that the present disclosure is not so limited. For example, the manner of contact of the OS channel with the source and drain for FIGS. 3-5 may also be applied to the back gate FET 60.

Fig. 7 shows a schematic block diagram of a dual gate FET 70 according to one embodiment of the present disclosure. In one embodiment, FET 70 includes a first gate 78, a second gate 782, a drain 74, a source 76, a first dielectric 79, a second dielectric 792, and an OS channel. A first gate 78 is disposed on the isolation region 72, and a first dielectric layer 79 covers both side surfaces and an upper surface of the first gate 78. Dielectric 69 may include a gate oxide, such as HfO ₂ . The OS channel overlies the first dielectric layer 69 and is isolated from the first gate 78. Two ends 611 and 613 of the OS channel are respectively located on the first dielectric layer 69, and a middle portion 612 of the OS channel is covered on the middle portion of the first dielectric layer 69. The second dielectric layer 792 is formed flat on the middle portion 612 of the OS channel, and the second gate 782 is disposed on the second dielectric layer 792. Both sides of the second gate 782 and the second dielectric 792 may be provided with first and second isolation sidewalls 751 and 752 to electrically isolate the second gate 782 from the drain 74 and the source 76. In one embodiment, the first and second isolation sidewalls 751 and 752 can comprise silicon oxide, silicon nitride, or a combination thereof. Since the channel is made of an OS material, FET 70 may be compatible with BEOL processing, i.e., there may be CMOS circuit layers or other circuit layers below isolation region 72. The FET 70 may be formed after the formation of the lower layer wiring so that the FET 70 may be stacked over the lower layer circuit. Since the individual circuit components are vertically stacked together, off-chip wire bonding may be eliminated, effectively reducing manufacturing costs, enhancing device performance, and reducing power consumption.

In one embodiment, the first end 711 of the OS channel is embedded in the drain 74 such that the drain 74 is in contact with the upper surface, end surface, and both side surfaces of the first end 711 of the OS channel. In addition, the drain 74 is also in contact with the surface of the downward extension of the middle portion 711. Similarly, the second end 713 is embedded in the source 76 such that the source 76 is in contact with the upper surface, end surfaces, and both side surfaces of the second end 713 of the OS channel. In addition, the source 76 is also in contact with the surface of the downward extension of the middle portion 711. By fully cladding two or more surfaces of both end portions of the OS channel, the contact area of the source and drain contacts can be effectively increased, thereby improving the driving capability and response speed of the OS FET. While one implementation of a back gate FET is shown with respect to fig. 7, it is to be understood that the present disclosure is not so limited. For example, the manner of contact of the OS channel to the source and drain for FIGS. 3-5 may also be applied to the dual gate FET 70. The first gate 78 and the second gate 782 in the dual gate FET 70 may both be applied with control voltages to better overcome short channel effects to control the on and off of the channel compared to the planar Shan Shan FET, so that the device size may be further reduced. On the other hand, since on and off of the channel can be controlled by using the double gate, the doping level of the OS channel can be more flexible, and the selection of the OS material can be more flexible.

Fig. 8 shows a schematic block diagram of a FET 80 according to one embodiment of the present disclosure. In one embodiment, FET 80 may be a fin FET. The difference from the planar FET 30 in fig. 3 is only the arrangement of the gate 88 and the OS channel, and thus various features other than the gate with respect to the FET 30 in fig. 3 may be similarly applied to the FET 80, and will not be described again here. In one embodiment, FET 80 may include an OS channel on isolation region 82, source 86, drain 84, and gate 88. For ease of illustration of the structure, the dielectric layer is not shown here, but it will be appreciated that a dielectric layer is sandwiched between gate 88 and the middle portion 812 of the OS channel. In fig. 8, fin gate 88 surrounds the upper surface and both sides of the strip-shaped OS channel to increase the area of gate 88 opposite the OS channel. Fin gate 88 may control the OS channel from three surfaces relative to single gate and dual gate control structures, thereby better overcoming short channel effects to control channel turn-on and turn-off, allowing device size to be further reduced.

Although only a single OS channel is shown in fig. 8, this is merely illustrative and not limiting on the scope of the present disclosure. More OS channels may be stacked over the OS channels in fig. 8, the two ends of the more OS channels may be embedded in the source 86 and drain 84, respectively, and the middle portion of the more OS channels may extend through the gate 88. Alternatively, a plurality of OS channels may be disposed in parallel on the isolation region 82, both ends of the plurality of OS channels may be embedded in the source and drain electrodes 86 and 84, respectively, and a middle portion of the plurality of OS channels may penetrate the gate electrode 88. It will be appreciated that there may be more arrangements of the OS channels. By using multiple OS channels, the current drive capability and corresponding speed of the FET can be further improved.

Fig. 9 shows a schematic block diagram of a portion of a horizontal gate-all FET 90 according to one embodiment of the disclosure. A horizontal gate-all-around (GAA) FET 90 includes an OS channel 91, a gate 98 surrounding a side surface of a portion of the OS channel 91, and a dielectric 99 interposed between the gate 98 and the OS channel 91. A cross-sectional view at gate 98 is shown on the right side of fig. 9, wherein dielectric 99 surrounds a side surface of OS channel 91 and gate 98 surrounds a side surface of dielectric 99. In one embodiment, both ends of the OS channel 91 may be embedded in a drain and a source, respectively, not shown in fig. 9, so that both side surfaces and end surfaces of the end are in contact with the drain/source, thereby reducing contact resistance and increasing driving capability and response speed of the FET 90. The gate 98 in fig. 9 completely encloses a side surface of a portion of the cylindrical OS channel compared to fig. 8, so that short channel effects can be better overcome to control the on and off of the channel, so that the device size can be further reduced. In this case, the doping limit of the OS channel and the cladding of the source and drain to the OS channel can be further reduced. In some embodiments, the source and drain may each only surround side surfaces of the OS end portion. In other embodiments, the source and drain may contact only end surfaces of the ends of the OS channel, respectively, perpendicular to the OS channel extension direction. Furthermore, while the OS channel is shown as cylindrical in fig. 9, other shapes of OS are possible. For example, in one embodiment, the OS channel may be elongated.

Fig. 10 shows a schematic block diagram of a horizontal gate-all FET 90 according to one embodiment of the disclosure. A horizontal gate-all-around FET 90 is disposed horizontally over an isolation region 92. Dielectric 99 of horizontal ring gate FET 90 surrounds a middle portion 912 of the OS channel and gate 98 surrounds ring dielectric 99. The first end 911 of the OS channel is embedded in the drain 94 and the second end 913 of the OS channel is embedded in the source 96. Although half of the ring-shaped gate 98 is shown embedded in the isolation region 92 in fig. 10 to save space, the ring-shaped gate 98 may be disposed on the upper surface of the isolation region 92. In one embodiment, more OS channels and more dielectric layers sandwiched between the OS channels and the fully surrounding gate may be provided in the gate 98 to further enhance the drive capability and response speed of the FET.

Fig. 11 shows a schematic block diagram of a portion of a vertical gate-all FET 110 according to one embodiment of the disclosure. The vertical gate-all-around FET 110 includes an OS channel 111, a gate 118 surrounding a side surface of a portion of the OS channel 111, and a dielectric 119 interposed between the gate 118 and the OS channel 111. A cross-sectional view at gate 118 is shown on the right side of fig. 11. Compared to the horizontal gate-all-around FET 90 of fig. 9, the vertical gate-all-around FET 110 is different in that the FET 110 is arranged vertically and an embedded dielectric 115 is arranged inside the OS channel. As shown on the right side of fig. 11, an embedded dielectric 115 is embedded in the middle portion of the OS channel 111, a dielectric 119 surrounds the side surface of the OS channel 111, and a gate 118 surrounds the side surface of the dielectric 119. The material of embedded dielectric 115 may be the same as or different from the material of dielectric 119, which is not limited by the present disclosure. Various aspects of the horizontal gate-all FET 90 with respect to fig. 9 may be similarly applied to the vertical gate-all FET 110, and are not described in detail herein. The vertical arrangement is advantageous because the horizontal arrangement tends to increase the area of the chip, but the space in the vertical direction of the chip is not fully utilized. By providing at least a portion of the FETs as vertical gate-all-around FETs, the chip footprint (footprint) can be greatly reduced while improving the switching performance of the FETs, which is particularly advantageous for M3D chips.

Fig. 12 shows a schematic structural diagram of the vertical gate-all-around FET 110 of fig. 11. Vertical gate-around FET 110 is vertically disposed over isolation region 112. The middle portion 1112 of the OS channel has embedded therein an embedded dielectric 115, and an upper surface of the embedded dielectric 1115 is substantially flush with the middle portion 1112, while a lower surface of the embedded dielectric 1115 may be slightly higher than a lower surface of the embedded dielectric. This structure can reduce the deposition step when forming the middle portion 1112 of the OS channel using an ALD process, because the OS channel material for encapsulation need not be deposited on the upper surface portion of the embedded electrolyte 115. The dielectric 119 of the vertical ring gate FET 110 surrounds the middle portion 1112 of the OS channel and the gate 118 surrounds at least a portion of the ring dielectric 119. The first end 1111 of the OS channel is embedded in the drain 114 and the second end 1113 of the OS channel is embedded in the source 116. Alternatively, the first end 1111 and the second end 1113 may not be provided, and the end face of the middle portion 1112 of the os channel may be in direct contact with the source 116 and the drain 114. For the FET using the full-surrounding gate, the end face contact mode is feasible, because the full-surrounding gate improves the switching characteristic of the FET, reduces the influence caused by the short channel effect, and can promote doping to relieve the requirement of a source region and a drain region on contact resistance. In one embodiment, more OS channels and more dielectric layers sandwiched between the OS channels and the fully surrounding gate may be provided in the gate 118 to further enhance the drive capability and response speed of the FET. Furthermore, while the OS channel is shown as cylindrical in FIG. 11, other shapes of OS are possible. For example, in one embodiment, the OS channel may be elongated. Further, while the OS channel is shown in fig. 12 as a fully closed-end hollow tube (macroni) structure, this is merely illustrative and not limiting of the scope of the present disclosure. At least one of both ends of the OS channel may not be closed. For example, the embedded dielectric 115 may be exposed from one or both end surfaces of the OS channel, and the exposed end surfaces of the OS channel and the embedded dielectric may be in contact with the surface of the source drain region or embedded inside the source drain region. The various variations of the macroni structure described above may be applied to the macroni structure of the various embodiments herein, and will not be described in detail.

As described above, the OS FET is a jointless FET, and the OS channel is also doped with a certain doping concentration, for example n-type doping. For doped OS channels, the switching characteristics of FET devices are relatively sensitive to channel thickness. When an OS channel of solid structure is employed, variations in hole size (diameter of the OS channel) may cause device-to-device fluctuations, for example, the switching threshold voltages of different FETs may be different accordingly, which is very disadvantageous for FET control. In contrast, when a hollow tube structure is employed, the thickness of the OS channel can be precisely controlled by atomic layer deposition (atomic layer deposition, ALD). It will be appreciated that other deposition processes may be used. Thus, the electrical performance of each FET can be made continuous and uniform, and chip circuit design and control can be simplified.

Various implementations of the OS FET and their advantages are described above. It will be appreciated that it is particularly advantageous to implement logic circuits using OS FETs in logic circuits, particularly M3D chips. This will be described below in connection with a specific implementation of a logic device using an OS FET in accordance with some embodiments. The OS FETs for M3D may be combined into various types of logic gates. In some embodiments, the OS FET is primarily an electron channel FET (FET). Thus in some embodiments, unlike conventional logic gates for field effect transistors where both electron and hole channels are present, the logic gates for OS channel based FETs include only field effect transistors with electron channels. It is understood that current and future hole-conducting PFETs may also be similarly adapted.

Fig. 13 shows a schematic circuit diagram and a schematic block diagram of an inverter 130 according to one embodiment of the present disclosure. An inverter is one of the most basic logic gates. A schematic circuit diagram of the inverter 130 is shown on the left side of fig. 13. Inverter 130 includes a depletion mode FET M1 and a drive FET M2, both of which are OS FETs. Accordingly, aspects of the OS FET described above with respect to FIGS. 3-12 may be applied to the OS FET in inverter 130 of FIG. 13.

The drain of FET M1 is coupled to the supply voltage VDD, the source of FET M1 is coupled to the drain of FET M2 and to the output node OUT, and the gate of FET M1 is coupled to the source of FET M1. The source of FET M2 is grounded and the gate of FET M2 is coupled to input node IN. Two OS FETs in series have different threshold voltages (Vth), where Vth of FET M2>0V, vth of FET M1<0V. Due to the gate-source power of FET M1The gate-source voltage vgs=0v is extremely short-circuited, and thus the FET M1 is always in the on state. When the input voltage of the inverter 130 is less than Vth (simply referred to as low potential, corresponding to logic state "1") of the FET M2, the FET M2 is in an off state. At this time, the resistance (R _DTr ) Is far greater than the resistance (R) _LTr ) Inverter 130 therefore outputs a high potential (corresponding to logic state "0"). When the input voltage of the inverter 130 is greater than Vth (high potential corresponding to logic state "0") of the FET M2, the FET M2 is in an on state. At this time, R of FET M2 _DTr R is much smaller than FET M1 _LTr Inverter 130 outputs a low potential (corresponding to logic state "1"). For depletion-mode inverters, the Vth of FET M1 determines its R _LTr And thus directly affects the voltage range that inverter 130 is capable of outputting. Vth for both OS FETs of the depletion mode inverter may be adjusted using at least one of the back gate (back-gate) of the dual gate structure in fig. 7, the thickness of the OS channel, and the dipole of the gate dielectric/OS channel interface.

The right side of fig. 13 shows a specific implementation of the left side circuit schematic. In one embodiment, the inverter 130 may be located on the isolation region 132, and the isolation region 132 may be located above the underlying circuit 20. In another embodiment, the bottom layer circuit 20 may not be provided, and the inverter 130 is the bottom layer circuit. Inverter 130 includes FETs M1 and M2 connected in series, where the OS channel extends from source 134 of FET M2 all the way to drain 136 of FET M1, and the OS channel includes first portion 1311, second portion 1312, third portion 1313, fourth portion 1314, and fifth portion 1315. By using the OS channel, the temperature of the fabrication process of the inverter 130 can be controlled below 450 ℃, so that the fabrication process of the inverter 130 can be compatible with BEOL processes, and the inverter 130 can also be stacked on the underlying circuit such as a CMOS circuit sub-class.

The source 134 of FET M2 is coupled to ground GND and the first portion 1311 of the OS channel is embedded in the source 134 to reduce contact resistance. The dielectric 1391 of the FET M2 is stacked on the upper surface of the middle portion of the second portion 1312, and the gate 1381 of the FET M2 is stacked on the dielectric 1391 to control turning on or off of the FET M2 according to the received input voltage IN. The drain of FET M2 and the source of FET M1 are integrally implemented as source drain region 1346. Source drain region 1346 is simultaneously coupled to output node OUT. By sharing the source drain regions 1346, the footprint of the inverter can be reduced and the cost reduced, making the device more compact. Alternatively, the drain of FET M2 and the source of FET M1 may be implemented separately.

The third portion 1313 of the OS channel extends through the source drain region 1346 such that the upper surface and both side surfaces of the third portion 1313 are in contact with the source drain region 1346. In FET M1, a fourth portion 1314 of the OS channel overlies isolation region 132 and dielectric 1392 overlies fourth portion 1314 of the OS channel. A second gate 1382 is disposed over dielectric 1392 and second gate 1382 is shorted to source drain region 1346. A fifth portion 1315 of the OS channel is embedded in the drain 136 of FET M1 to reduce contact resistance, drain 136 being coupled to the supply voltage VDD. In the example of fig. 13, two FETs in inverter 130 share a single elongated OS channel. Alternatively, the two FETs may also each have a separate OS channel. Although in fig. 13 the two FETs in the inverter are implemented as a planar top single gate structure. However, inverter 130 may also be implemented with a back gate FET, a dual gate FET, a fin FET, a horizontal GAA FET, and a vertical GAA FET. By increasing the area of the OS channel in contact with the source or drain, the contact resistance can be significantly reduced, such that the total resistance of the OS FET is reduced and the current at the same voltage is increased. Accordingly, the driving capability and response speed of the inverter 130 including the OS FET M1 and the OS FET M2 can be significantly improved.

Fig. 14 shows a schematic block diagram of an inverter 140 according to one embodiment of the present disclosure. In one embodiment, the inverter 140 may be one vertical GAA FET implementation of the circuit diagram of the inverter 130 in fig. 13, wherein two vertical GAA FETs in the inverter 140 employ a macroni channel structure. Accordingly, aspects of the OS FET described above with respect to FIGS. 9-12 may be applied to the OS FET in the inverter 140 of FIG. 14, and are not described in detail herein.

In one embodiment, inverter 140 is located in a stacked circuit in an M3D chip. Specifically, the inverter 140 is located on the isolation region 142, and the isolation region 142 is located on the underlying circuit 120. In other embodiments, the bottom layer circuit 20 may not be present, and the inverter 140 is the bottom layer circuit. The inverter 140 includes two FETs arranged in parallel in the same layer. FET M2 includes a source 144 located on an upper surface of isolation region 142, a first OS channel extending from source 144 to shared source drain 1446, a first GAA gate 1481, a dielectric 1491 located between first GAA gate 1481 and second portion 1412 of the first OS channel, and shared source drain 1446. The source 144 is coupled to ground GND, the first GAA gate 1481 is coupled to the input node IN, and the shared source drain 1446 is coupled to the output node OUT. By using the OS channel, the temperature of the fabrication process of the inverter 140 can be controlled below 450 ℃, so that the fabrication process of the inverter 140 can be compatible with BEOL processes, and the inverter 140 can also be stacked on the underlying circuit such as a CMOS circuit sub-class.

The first OS channel includes a first portion 1411 embedded in source 144, a second portion 1412, and a third portion 1413 embedded in shared source drain 1446. An end surface and a ring-shaped side surface of the first portion 1411 are in contact with the source 144 to reduce contact resistance, and an end surface and a ring-shaped side surface of the third portion 1413 are in contact with the shared source drain region 1446 to reduce contact resistance. In some embodiments, the first portion 1411 and the third portion 1413 may not be present, but rather the second portion 1412 directly terminates the source 144 and the shared source drain 1446. Alternatively, the first portion 1411 and the third portion 1413 may extend through the source 144 and the shared source drain 1446 such that the source 144 and the shared source drain 1446 are in contact with only the annular side surfaces of the OS channel. The second portion 1412 has a first embedded dielectric 1451 inside.

FET M1 includes a drain 146 located on an upper surface of isolation region 142, a second OS channel extending from drain 146 to shared source drain region 1446, a second GAA gate 1482, a dielectric 1492 located between second GAA gate 1482 and fifth portion 1415 of the second OS channel, and shared source drain region 1446. Drain 146 is coupled to supply voltage VDD and second GAA gate 1482 is coupled to shared source drain region 1446 through via 1445.

The second OS channel includes a fourth portion 1414 embedded in the shared source drain region 1446, a fifth portion 1415, and a sixth portion 1416 embedded in the drain 146. In some embodiments, fourth portion 1414 and sixth portion 1416 may not be present, but rather drain 146 and shared source drain region 1446 may be directly terminated by fifth portion 1415. Alternatively, fourth portion 1414 and sixth portion 1416 may extend through shared source drain region 1446 and drain 146 such that drain 146 and shared source drain region 1446 are in contact with only annular side surfaces of the OS channel. The fifth portion 1415 has a second embedded dielectric 1452 inside. By increasing the area of the OS channel in contact with the source or drain, the contact resistance can be significantly reduced, such that the total resistance of the OS FET is reduced and the current at the same voltage is increased. Accordingly, the driving capability and response speed of the inverter 140 including the OS FET M1 and the OS FET M2 can be significantly improved.

The OS FET in the inverter 140 is a non-junction FET and the first OS channel and the second OS channel also have a certain doping concentration, e.g. n-type doping. For doped OS channels, the switching characteristics of FET devices are relatively sensitive to channel thickness. When using an OS channel of solid structure, variations in hole size can lead to device-to-device fluctuations, for example, the switching threshold voltages of different FETs can be different accordingly, which is very detrimental to FET control. In contrast, when a macroni structure is employed, the thickness of the OS channel can be precisely controlled by ALD. Thus, the electrical performance of each FET can be made continuous and uniform, and chip circuit design and control can be simplified. It will be appreciated that other deposition processes may be used. Although the configuration of the source 144 and drain 146 below and the shared source drain 1446 above is shown in fig. 14, the configuration in fig. 14 may be reversed such that the shared source drain 1446 is below and the source 144 and drain 146 above.

Fig. 15 shows a schematic block diagram of an inverter 150 according to one embodiment of the present disclosure. In one embodiment, the inverter 140 may be another vertical GAA FET implementation of the circuit diagram of the inverter 130 in fig. 13, wherein two vertical GAA FETs in the inverter 150 employ a macroni channel structure. Accordingly, aspects of the OS FET described above with respect to FIGS. 9-12 and 14 may be applied to the OS FET in inverter 150 of FIG. 15, and are not described in detail herein. By using the OS channel, the temperature of the fabrication process of the inverter 150 can be controlled below 450 ℃, so that the fabrication process of the inverter 150 can be compatible with BEOL processes, and the inverter 150 can also be stacked on the underlying circuit such as a CMOS circuit sub-class.

In one embodiment, FET M2 of inverter 150 includes source 154 on an upper surface of isolation region 152, a first OS channel extending from source 154 to shared source drain region 1546, first GAA gate 1581, dielectric 1591 between first GAA gate 1581 and second portion 1512 of first OS channel, and shared source drain region 1546. The source 154 is coupled to ground GND, the first GAA gate 1581 is coupled to the input node IN, and the shared source drain 1546 is coupled to the output node OUT.

The first OS channel includes a first portion 1511 embedded in the source 154, a second portion 1512, and a third portion 1513 that extends through the shared source drain region 1546. The end surface and the annular side surface of the first portion 1511 contact the source 154 to reduce the contact resistance, and the annular side surface of the third portion 1513 contacts the shared source drain region 1546 to reduce the contact resistance. In some embodiments, the first portion 1511 and the third portion 1513 may not be present, but rather the second portion 1512 directly terminates the source 154 and the shared source drain region 1546. Alternatively, the first portion 1511 may extend through the source 154 such that the source 154 is in contact with only the annular side surface of the OS channel. The second portion 1512 has a first embedded dielectric 1551 inside.

FET M1 includes a drain 156, a second OS channel extending from drain 156 to shared source drain region 1546, a second GAA gate 1582, a dielectric 1592 between second GAA gate 1582 and fourth portion 1514 of second OS channel, and shared source drain region 1546. The drain 156 is coupled to the supply voltage VDD and the second GAA gate 1582 is coupled to the shared source drain region 1546 through the via 1545.

The second OS channel includes a third portion 1513 embedded in the shared source drain region 1546, a fourth portion 1514, and a fifth portion 1515 embedded in the drain 156. In some embodiments, the third portion 1513 and the fifth portion 1516 may not be present, but the fourth portion 1414 directly terminates the drain 156 and the shared source drain region 1546. Alternatively, the fifth portion 1516 may extend through the shared source drain region 1446 and the drain 146 such that the drain 146 is in contact with only the annular side surface of the OS channel. The fourth portion 1514 has a second embedded dielectric 1552 inside. Alternatively, FET M1 may have separate OS channel and source, and FET M2 may have separate OS channel and drain. By increasing the area of the OS channel in contact with the source or drain, the contact resistance can be significantly reduced, such that the total resistance of the OS FET is reduced and the current at the same voltage is increased. Accordingly, the driving capability and response speed of the inverter 150 including the OS FET M1 and the OS FET M2 can be significantly improved.

Similarly, the electrical performance of each FET can be continuous and consistent, which can simplify chip circuit design and control. Further, the vertically stacked inverter 150 in fig. 15 can save nearly half the occupied area, which can greatly increase the integration level of the semiconductor device, compared to the laterally arranged inverter 140 in fig. 14. Although the configuration of FET M2 below and FET M1 above is shown in fig. 15, the configuration in fig. 15 may be reversed such that FET M1 below and FET M2 above. The depletion mode FET based inverter design is described above with reference to fig. 14 and 15, however the present disclosure is not limited thereto. An inverter based on enhancement FETs may also be used.

Fig. 16 shows a circuit schematic and a schematic block diagram of an inverter 160 according to one embodiment of the present disclosure. A schematic circuit diagram of inverter 160 is shown on the left side of fig. 16. Inverter 160 includes enhancement FET M3 and drive FET M2, which are both OS FETs. Accordingly, aspects of the OS FET described above with respect to FIGS. 3-12 may be applied to the OS FET in inverter 160 of FIG. 16. By using the OS channel, the temperature of the fabrication process of the inverter 160 can be controlled below 450 ℃, so that the fabrication process of the inverter 160 can be compatible with BEOL processes, and the inverter 160 can also be stacked on the underlying circuit such as a CMOS circuit sub-class.

Drain of FET M3The pole is coupled to the supply voltage VDD, the source of FET M3 is coupled to the drain of FET M2 and the output node OUT, and the gate of FET M3 is coupled to the supply voltage VDD. The source of FET M2 is grounded and the gate of FET M2 is coupled to input node IN. The two OS FETs in series have substantially the same threshold voltage (Vth). For example, vth is greater than 0. The gate-source voltage vgd=0v due to the drain-gate electrode shorting of FET M3. When the input IN is high (corresponding to logic state "0"), FET M2 is turned on and is IN a low resistance state. FET M3 is also on at this time, but R _DTr Far less than R _LTr The output signal is therefore low (corresponding to logic state "1"). When the input is low (corresponding to logic state "1"), FET M2 is turned off and is in a high resistance state, R _DTr Far greater than R _LTr The output signal is therefore high (corresponding to logic state "0").

The right side of fig. 16 shows one specific implementation of the left side circuit schematic. In one embodiment, inverter 160 may be located on isolation region 162. Inverter 160 includes FET M3 and FET M2 connected in series, wherein the OS channel extends from source 164 of FET M2 all the way to drain 166 of FET M3, and the OS channel includes first portion 1611, second portion 1612, third portion 1613, fourth portion 1614, and fifth portion 1615. The source 164 of FET M2 is coupled to ground GND and the first portion 1611 of the OS channel is embedded in the source 164 to reduce contact resistance. The dielectric 1691 of the FET M2 is stacked on the upper surface of the middle portion of the second portion 1612, and the gate 1681 of the FET M2 is stacked on the dielectric 1691 to control the turn-on or turn-off of the FET M2 according to the received input voltage IN. The drain of FET M2 and the source of FET M3 are integrally implemented as source drain region 1646. Source drain region 1646 is coupled to output node OUT simultaneously. By sharing the source and drain regions 1646, the footprint of the inverter can be reduced and the cost reduced, making the device more compact.

The third portion 1613 of the OS channel extends through the source drain region 1646 such that the upper surface and both side surfaces of the third portion 1613 are in contact with the source drain region 1646. In FET M3, a fourth portion 1614 of the OS channel overlies isolation region 162 and dielectric 1692 overlies fourth portion 1614 of the OS channel. A second gate 1682 is disposed over dielectric 1692 and the second gate 1682 is shorted to the source drain region 1646. A fifth portion 1615 of the OS channel is embedded in the drain 166 of FET M3 to reduce contact resistance, drain 166 being coupled to the supply voltage VDD. In the example of fig. 16, two FETs in inverter 160 share a single elongated OS channel, and the two FETs in the inverter are implemented as a planar top single gate structure. However, inverter 160 may also be implemented with a back gate FET, a dual gate FET, a fin FET, a horizontal GAA FET, and a vertical GAA FET. By increasing the area of the OS channel in contact with the source or drain, the contact resistance can be significantly reduced, such that the total resistance of the OS FET is reduced and the current at the same voltage is increased. Accordingly, the driving capability and response speed of the inverter 160 including the OS FET M3 and the OS FET M2 can be significantly improved.

Fig. 17 shows a schematic block diagram of an inverter 170 according to one embodiment of the present disclosure. In one embodiment, the inverter 170 may be one vertical GAA FET implementation of the circuit diagram of the inverter 160 in fig. 16, wherein two vertical GAA FETs in the inverter 170 employ a macroni channel structure. Accordingly, aspects of the OS FET described above with respect to FIGS. 9-12 may be applied to the OS FET in the inverter 170 of FIG. 17, and are not described in detail herein. By using the OS channel, the temperature of the fabrication process of the inverter 170 can be controlled below 450 ℃, so that the fabrication process of the inverter 170 can be compatible with BEOL processes, and the inverter 170 can also be stacked on the bottom layer such as the CMOS circuit sub-class.

In one embodiment, inverter 170 is located in a stacked circuit in an M3D chip. Specifically, inverter 170 is located on isolation region 172. Inverter 170 includes two FETs arranged in parallel in the same layer. FET M2 includes a source 174 located on an upper surface of isolation region 172, a first OS channel extending from source 174 to shared source drain region 1746, a first GAA gate 1781, a dielectric 1791 located between first GAA gate 1781 and a second portion 1712 of the first OS channel, and shared source drain region 1746. The source 174 is coupled to ground GND, the first GAA gate 1781 is coupled to the input node IN, and the shared source drain region 1746 is coupled to the output node OUT.

The first OS channel includes a first portion 1711 embedded in the source 174, a second portion 1712, and a third portion 1713 embedded in the shared source drain region 1746. An end surface and a ring-shaped side surface of the first portion 1711 are in contact with the source 174 to reduce contact resistance, and an end surface and a ring-shaped side surface of the third portion 1713 are in contact with the shared source drain region 1746 to reduce contact resistance. In some embodiments, the first portion 1711 and the third portion 1713 may not be present, but rather the second portion 1712 directly terminates the source 174 and the shared source drain region 1746. Alternatively, the first portion 1711 and the third portion 1713 may extend through the source 174 and the shared source drain region 1746 such that the source 174 and the shared source drain region 1746 are in contact with only the annular side surface of the OS channel. The interior of the second portion 1712 has a first embedded dielectric 1751.

FET M3 includes a drain 176 on the upper surface of isolation region 172, a second OS channel extending from drain 176 to shared source drain region 1746, a second GAA gate 1782, a dielectric 1792 between second GAA gate 1782 and fifth portion 1715 of the second OS channel, and shared source drain region 1746. Drain 176 is coupled to supply voltage VDD and second GAA gate 1782 is coupled to drain 176 through via 1745.

The second OS channel includes a fourth portion 1714 embedded in the shared source drain region 1746, a fifth portion 1715, and a sixth portion 1716 embedded in the drain 176. In some embodiments, fourth portion 1714 and sixth portion 1716 may not be present, but rather fifth portion 1715 may terminate directly to drain 176 and shared source drain region 1746. Alternatively, the fourth and sixth portions 1714, 1716 may extend through the shared source drain region 1746 and the drain 176 such that the drain 176 and shared source drain region 1746 are in contact with only the annular side surfaces of the OS channel. The interior of fifth portion 1715 has a second embedded dielectric 1752. By increasing the area of the OS channel in contact with the source or drain, the contact resistance can be significantly reduced, such that the total resistance of the OS FET is reduced and the current at the same voltage is increased. Accordingly, the driving capability and response speed of the inverter 170 including the OS FET M3 and the OS FET M2 can be significantly improved.

The OS FET in the inverter 170 is a non-junction FET and the first OS channel and the second OS channel also have a certain doping concentration, e.g., n-type doping. For doped OS channels, the switching characteristics of FET devices are relatively sensitive to channel thickness. When using an OS channel of solid structure, variations in hole size can lead to device-to-device fluctuations, for example, the switching threshold voltages of different FETs can be different accordingly, which is very detrimental to FET control. In contrast, when a macroni structure is employed, the thickness of the OS channel can be precisely controlled by ALD. Thus, the electrical performance of each FET can be made continuous and uniform, and chip circuit design and control can be simplified. It will be appreciated that other deposition processes may be used. Although the configuration of the source 174 and drain 176 below and the shared source drain 1746 above is shown in fig. 17, the configuration in fig. 17 may be reversed such that the shared source drain 1746 is below and the source 174 and drain 176 above.

Fig. 18 shows a schematic block diagram of an inverter 180 according to one embodiment of the present disclosure. In one embodiment, the inverter 180 may be another vertical GAA FET implementation of the circuit diagram of the inverter 160 in fig. 16, where two vertical GAA FETs in the inverter 180 employ a macroni channel structure. Accordingly, aspects of the OS FET described above with respect to FIGS. 9-12 and 16 may be applied to the OS FET in inverter 180 of FIG. 18, and are not described in detail herein. By using the OS channel, the temperature of the fabrication process of the inverter 180 can be controlled below 450 ℃, so that the fabrication process of the inverter 180 can be compatible with BEOL processes, and the inverter 180 can also be stacked on the underlying circuit such as a CMOS circuit sub-class.

In one embodiment, FET M2 of inverter 180 includes source 184 located on an upper surface of isolation region 182, a first OS channel extending from source 184 to shared source drain region 1846, first GAA gate 1881, dielectric 1891 located between first GAA gate 1881 and second portion 1812 of first OS channel, and shared source drain region 1846. The source 184 is coupled to ground GND, the first GAA gate 1881 is coupled to the input node IN, and the shared source drain region 1846 is coupled to the output node OUT.

The first OS channel includes a first portion 1811 embedded in the source 184, a second portion 1812, and a third portion 1813 throughout the shared source drain region 1846. The end surface and annular side surface of the first portion 1811 contact the source 184 to reduce contact resistance, and the annular side surface of the third portion 1813 contacts the shared source drain region 1846 to reduce contact resistance. In some embodiments, the first portion 1811 and the third portion 1813 may not be present, but the second portion 1812 directly terminates the source 184 and the shared source drain region 1846. Alternatively, the first portion 1811 may extend through the source 184 such that the source 184 is in contact with only the annular side surface of the OS channel. The interior of the second portion 1812 has a first embedded dielectric 1851.

FET M3 includes drain 186, a second OS channel extending from drain 186 to shared source drain 1846, second GAA gate 1882, dielectric 1892 between second GAA gate 1882 and fourth portion 1814 of the second OS channel, and shared source drain 1846. Drain 186 is coupled to supply voltage VDD and second GAA gate 1882 is coupled to drain 186 through via 1845.

The second OS channel includes a third portion 1813 embedded in the shared source drain region 1846, a fourth portion 1814, and a fifth portion 1815 embedded in the drain 186. In some embodiments, the third and fifth portions 1813 and 1816 may not be present, but the fourth portion 1814 directly terminates the drain 186 and the shared source drain region 1846. Alternatively, the fifth portion 1816 may extend through the shared source drain region 1846 and the drain 186 such that the drain 186 is in contact with only the annular side surface of the OS channel. The interior of the fourth portion 1814 has a second embedded dielectric 1852. By increasing the area of the OS channel in contact with the source or drain, the contact resistance can be significantly reduced, such that the total resistance of the OS FET is reduced and the current at the same voltage is increased. Accordingly, the driving capability and response speed of the inverter 180 including the OS FET M3 and the OS FET M2 can be significantly improved.

Similarly, the electrical performance of each FET can be continuous and consistent, which can simplify chip circuit design and control. Further, the vertically stacked inverter 180 in fig. 18 can save nearly half the occupied area, which can greatly increase the integration level of the semiconductor device, compared to the laterally arranged inverter 180 in fig. 16. Although the configuration of FET M2 below and FET M3 above is shown in fig. 18, the configuration in fig. 18 may be reversed such that FET M3 below and FET M2 above.

Fig. 19 shows a circuit schematic and a schematic structural diagram of a NAND gate (NAND) 190 according to one embodiment of the present disclosure. In contrast to inverter 130, NAND 190 can be considered as having one FET M4 in series between FET M2 of inverter 130 and ground GND. The gate of FET M2 receives a first input IN_A of NAND 190, while the gate of FET M4 receives a second input IN_B of NAND 190. For NAND 190, OS FETs M2 and M4, which connect the two inputs, are connected in series to form a pull-down network (PDN) in the NAND. The output OUT outputs a logic "0" only when both FET M2 and FET M4 are on (inputs are both logic "1"), and is a logic "1" when at least one of FET M2 and FET M4 is off. Accordingly, aspects of FET M1 and FET M2 in fig. 13 may be applied to FET M1, FET M2, and FET M4 in NAND 190, and are not described here.

The right side of fig. 19 shows one specific implementation of the left side circuit schematic. In one embodiment, NAND 190 can be located on isolation region 192. In another embodiment, isolation region 192 may have underlying circuitry below. NAND 190 includes OS FET M1, OS FET M2, and OS FET M4 connected in series, where the OS channel extends from source 1941 of FET M4 all the way to drain 196 of FET M1, and the OS channel includes first portion 1911, second portion 1912, third portion 1913, fourth portion 1914, fifth portion 1915, sixth portion 1916, and seventh portion 1917. By using the OS channel, the temperature of the fabrication process of NAND 190 can be controlled below 450 ℃, so that the fabrication process of NAND 190 can be compatible with BEOL processes, and NAND 190 can also be stacked over the underlying CMOS circuitry.

The source 1941 of FET M4 is coupled to ground GND, the gate of FET M4 is coupled to the second input IN_B, and the drain of FET M4 is integrally formed with the source of FET M2 as a first shared source drain 194. The gate of FET M2 is coupled to the first input in_a and the drain of FET M2 is integrally formed with the source of FET M1 as a second shared source drain 1946. The second shared source drain 1946 is coupled to the output node OUT. The gate of FET M1 is coupled to the second shared source drain 1946 through via 1945 and the drain of FET M1 is coupled to the supply voltage VDD.

The end surface and annular side surface of the first portion 1911 of the OS channel are in contact with the source 1941 to reduce contact resistance and the annular side surface of the third portion 1913 of the OS channel is in contact with the shared source drain region 194 to reduce contact resistance. The annular side surface of the fifth portion 1915 of the OS channel is in contact with the shared source drain region 1946 to reduce contact resistance, and the end surface and annular side surface of the seventh portion 1917 of the OS channel are in contact with the drain 196 to reduce contact resistance. In some embodiments, the first portion 1911 and the seventh portion 1917 may not be present, but the source 194 may be directly terminated by the second portion 1912 and the drain 196 may be directly terminated by the sixth portion 1916. Alternatively, the first portion 1911 may extend through the source 194 such that the source 194 is in contact with only the annular side surface of the OS channel, and the seventh portion 1917 may extend through the drain 196 such that the drain 196 is in contact with only the annular side surface of the OS channel. The second portion 1912 has a first embedded dielectric 1951 inside, the fourth portion 1914 has a second embedded dielectric 1952 inside, and the sixth portion 1916 has a third embedded dielectric 1953 inside. The size, shape, and material of the first, second, and third embedded dielectrics 1951, 1952, and 1953 may be the same or different from each other. In other embodiments, any of the second portion, the fourth portion 1914, and the sixth portion 1916 may not have an embedded dielectric.

FET M4 includes a source 1941, an OS channel extending from source 1941 to shared source drain region 194, a first GAA gate 1981, a dielectric 1991 between first GAA gate 1981 and the OS channel, and shared source drain region 194.FET M2 includes shared source drain region 194, an OS channel extending from shared source drain region 194 to shared source drain region 1946, a second GAA gate 1982, a dielectric 1992 between second GAA gate 1982 and the OS channel, and shared source drain region 1946.FET M1 includes a drain 196, an OS channel extending from drain 196 to shared source drain region 1946, a third GAA gate 1983, a dielectric 1993 between third GAA gate 1983 and the OS channel, and shared source drain region 1946.

The second OS channel includes a third portion 1913 embedded in the shared source drain region 1946, a fourth portion 1914, and a fifth portion 1915 embedded in the drain 196. In some embodiments, the third portion 1913 and the fifth portion 1916 may not be present, but the fourth portion 1914 directly terminates the drain 196 and the shared source drain region 1946. Alternatively, the fifth portion 1916 may extend through the shared source drain region 1946 and the drain electrode 196 such that the drain electrode 196 is in contact with only the annular side surface of the OS channel. Having the second embedded dielectric 1952 inside the fourth portion 1914 alternatively, the FETs M1 and M2 may have respective OS channels and source drain regions, respectively, instead of the shared source drain region 1946.FET M2 and FET M4 may have respective OS channels and source and drain regions, respectively, rather than sharing source and drain regions 194. By increasing the area of the OS channel in contact with the source or drain, the contact resistance can be significantly reduced, such that the total resistance of the OS FET is reduced and the current at the same voltage is increased. Accordingly, the driving capability and response speed of NAND 190 including OS FET M1, OS FET M2, and OS FET M4 can be significantly improved.

As described above, the OS FET is a non-junction FET, and the OS channel is also doped with a certain doping concentration, such as n-type doping. For doped OS channels, the switching characteristics of FET devices are relatively sensitive to channel thickness. When using an OS channel of solid structure, variations in hole size can lead to device-to-device fluctuations, for example, the switching threshold voltages of different FETs can be different accordingly, which is very detrimental to FET control. In contrast, when a macroni structure is employed, the thickness of the OS channel can be precisely controlled by ALD. It will be appreciated that other deposition processes may be used. Thus, the electrical performance of each FET can be made continuous and uniform, and chip circuit design and control can be simplified. Further, compared to laterally arranged NAND, the vertically stacked NAND190 in fig. 19 can save approximately 2/3 of the occupied area, which can greatly increase the integration level of the semiconductor device. Although the configuration of FET M4 below and FET M1 above is shown in fig. 19, the configuration in fig. 19 may be reversed such that FET M1 below and FET M4 above.

Further, while NAND190 is shown in FIG. 19 as being vertically stacked with three FETs, this is merely illustrative and not limiting of the scope of the present disclosure. The three FETs of NAND190 may also be arranged horizontally in the same layer. Alternatively, one FET of NAND190 may also be stacked on both FETs. Although a gate structure is shown in fig. 19 as GAA, other gate structures may be used, such as top single gate, back single gate, double gate, and fin gate.

Fig. 20 shows a schematic circuit diagram and a schematic block diagram of a NOR gate (NOR) 200 according to one embodiment of the present disclosure. In contrast to inverter 130, nor 200 may be considered to have one FET M4 in parallel between the drain of FET M2 of inverter 130 and ground GND. The gate of FET M2 receives a first input IN_A of NOR 200, and the gate of FET M4 receives a second input IN_B of NOR 200. For NOR 200, OS FETs M2 and M4 connected to two inputs are connected in parallel to form a PDN in the NOR. The output node OUT outputs a logic "0" when at least one of the FETs M2 and M4 is on (input is logic "1"), and outputs OUT a logic "1" only when neither of the FETs M2 and M4 is on (input is logic "0"). Accordingly, aspects of the FETs M1 and M2 in fig. 13 may be applied to the FETs M1, M2, and M4 in the NOR 200, and will not be described again.

The right side of fig. 20 shows one specific implementation of the left side circuit schematic. In one embodiment, NOR 200 may be located on isolation region 202. In another embodiment, isolation region 202 may have underlying circuitry below. NOR 200 includes OS FET M2 and OS FET M4, each including an OS channel, and OS FET M1, including an OS channel, stacked on OS FET M2 and OS FET M4. By using an OS channel, the temperature of the fabrication process of NOR 200 can be controlled below 450 ℃, so that the fabrication process of NOR 200 can be compatible with BEOL processes, and NOR 200 can also be stacked on top of underlying CMOS circuitry.

The source 204 may be shared by the FETs M4 and M2 and coupled to ground GND, the gate of the FET M4 is coupled to the second input in_b, and the drains of the FETs M4 and M2 are integrally formed with the source of the FET M2 as a shared source drain 2046. The gate of FET M2 is coupled to the first input IN_A. The shared source drain 2046 is coupled to the output node OUT. The gate of FET M1 is coupled to shared source drain 2046 through via 2045, and the drain of FET M1 is coupled to supply voltage VDD. Alternatively, FETs M1, M2, and M4 may have respective independent source and drain regions instead of shared source and drain region 2046.

The first and annular side surfaces of the first OS channel 2011 of FET M4 are in contact with the source 2041 to reduce contact resistance, and the annular side and second end surfaces of the first OS channel 2011 are in contact with the shared source drain 2046 to reduce contact resistance. The first and annular side surfaces of the second OS channel 2012 of FET M2 contact the source 2041 to reduce contact resistance, and the annular side and second end surfaces of the second OS channel 2012 contact the shared source drain 2046 to reduce contact resistance. The first and annular side surfaces of the third OS channel 2013 of FET M1 are in contact with shared source drain region 2046 to reduce contact resistance, and the annular side and second end surfaces of the third OS channel 2013 are in contact with drain 206 to reduce contact resistance.

First, second and third embedded dielectrics 2051, 2052 and 2053 are respectively in the first, second and third OS channels 2011, 2012 and 2013. The size, shape, and material of the first, second, and third embedded dielectrics 2051, 2052, and 2053 may be the same or different from one another. In other embodiments, any one of the first, second, and third OS channels 2011, 2012, 2013 may not have an embedded dielectric. By increasing the area of the OS channel in contact with the source or drain, the contact resistance can be significantly reduced, such that the total resistance of the OS FET is reduced and the current at the same voltage is increased. Accordingly, the driving capability and response speed of the NOR 200 including the OS FET M1, the OS FET M2, and the OS FET M4 can be significantly improved.

As described above, the OS FET is a non-junction FET, and the OS channel is also doped with a certain doping concentration, such as n-type doping. For doped OS channels, the switching characteristics of FET devices are relatively sensitive to channel thickness. When an OS channel of solid structure is employed, variations in hole size (diameter of the OS channel) may cause device-to-device fluctuations, for example, the switching threshold voltages of different FETs may be different accordingly, which is very disadvantageous for FET control. In contrast, when a macroni structure is employed, the thickness of the OS channel can be precisely controlled by ALD. It will be appreciated that other deposition processes may be used. Thus, the electrical performance of each FET can be made continuous and uniform, and chip circuit design and control can be simplified. Furthermore, the vertically stacked NOR 200 of fig. 20 can save approximately 1/3 of the footprint compared to a laterally arranged NOR, which can greatly increase the integration of the semiconductor device. Although the configuration of the FETs M4 and M2 below and the FETs M1 above is shown in fig. 20, the configuration in fig. 20 may be reversed so that the FETs M1 below and the FETs M4 and M2 above.

Further, while NOR 200 is shown in fig. 20 as one FET stacked on two FETs, this is merely illustrative and not limiting of the scope of the present disclosure. The three FETs of NOR 200 may also be arranged horizontally in the same layer. Alternatively, three FETs of NAND 190 may also be vertically stacked. Although a gate structure is shown in fig. 20 as GAA, other gate structures may be used, such as top single gate, back single gate, double gate, and fin gate.

Fig. 21 shows a circuit schematic and a schematic structural diagram of the NAND 210 according to one embodiment of the present disclosure. Unlike NAND 190 of FIG. 19, which is based on depletion-mode FET M1, NAND 210 includes enhancement-mode FETs. In contrast to inverter 160, NAND 210 can be considered as having one FET M4 in series between FET M2 of inverter 160 and ground GND. The gate of FET M2 receives a first input IN_A of NAND 210, while the gate of FET M4 receives a second input IN_B of NAND 210. For NAND 210, OS FETs M2 and M4, which connect the two inputs, are connected in series to form a PDN in the NAND. The output OUT outputs a logic "0" only when both FET M2 and FET M4 are on (inputs are both logic "1"), and is a logic "1" when at least one of FET M2 and FET M4 is off. Accordingly, aspects of the FETs M3 and M2 in fig. 13 may be applied to the FETs M3, M2, and M4 in the NAND 210, and will not be described again here.

The right side of fig. 21 shows one specific implementation of the left side circuit schematic. In one embodiment, the NAND 210 can be located on the isolation region 212. In another embodiment, isolation region 212 may have underlying circuitry below. NAND 210 includes OS FET M3, OS FET M2, and OS FET M4 connected in series, where the OS channel extends from source 2141 of FET M4 all the way to drain 216 of FET M3, and the OS channel includes first portion 2111, second portion 2112, third portion 2113, fourth portion 2114, fifth portion 2115, sixth portion 2116, and seventh portion 2117. By using the OS channel, the temperature of the fabrication process of the NAND 210 can be controlled below 450 ℃, so that the fabrication process of the NAND 210 can be compatible with BEOL processes, and the NAND 210 can also be stacked over an underlying CMOS circuit.

The source 2141 of FET M4 is coupled to ground GND, the gate of FET M4 is coupled to the second input IN_B, and the drain of FET M4 is integrally formed with the source of FET M2 as a first shared source drain 214. Alternatively, FET M4 may have an independent drain and FET M2 has an independent source. The gate of FET M2 is coupled to the first input in_a and the drain of FET M2 is integrally formed with the source of FET M3 as a second shared source drain 2146. Alternatively, FET M2 may have an independent drain and FET M3 a independent source. The second shared source drain 2146 is coupled to the output node OUT. The gate of FET M3 is coupled to supply voltage VDD through via 2145, and the drain of FET M3 is coupled to supply voltage VDD.

The end surface and annular side surface of the first portion 2111 of the OS channel is in contact with the source 2141 to reduce contact resistance and the annular side surface of the third portion 2113 of the OS channel is in contact with the shared source drain region 214 to reduce contact resistance. The annular side surface of the fifth portion 2115 of the OS channel is in contact with the shared source drain region 2146 to reduce contact resistance, and the end surface and annular side surface of the seventh portion 2117 of the OS channel are in contact with the drain 216 to reduce contact resistance. In some embodiments, the first portion 2111 and the seventh portion 2117 may not be present, but rather the second portion 2112 directly terminates the source 214 and the sixth portion 2116 directly terminates the drain 216. Alternatively, the first portion 2111 may extend through the source 214 such that the source 214 is in contact with only the annular side surface of the OS channel, and the seventh portion 2117 may extend through the drain 216 such that the drain 216 is in contact with only the annular side surface of the OS channel. The second portion 2112 has a first embedded dielectric 2151 inside, the fourth portion 2114 has a second embedded dielectric 2152 inside, and the sixth portion 2116 has a third embedded dielectric 2153 inside. The size, shape, and material of the first, second, and third embedded dielectrics 2151, 2152, and 2153 may be the same or different from one another. In other embodiments, any of the second portion, fourth portion 2114, and sixth portion 2116 may not have an embedded dielectric.

FET M4 includes source 2141, an OS channel extending from source 2141 to shared source drain 214, a first GAA gate 2181, a dielectric 2191 between first GAA gate 2181 and the OS channel, and shared source drain 214.FET M2 includes shared source drain region 214, an OS channel extending from shared source drain region 214 to shared source drain region 2146, a second GAA gate 2182, a dielectric 2192 between second GAA gate 2182 and the OS channel, and shared source drain region 2146.FET M3 includes drain 216, an OS channel extending from drain 216 to shared source drain 2146, a third GAA gate 2183, a dielectric 2193 between third GAA gate 2183 and the OS channel, and shared source drain 2146.

The second OS channel includes a third portion 2113 embedded in the shared source drain region 2146, a fourth portion 2114, and a fifth portion 2115 embedded in the drain 216. In some embodiments, the third portion 2113 and the fifth portion 2116 may not be present, but the fourth portion 2114 directly terminates the drain 216 and the shared source drain region 2146. Alternatively, the fifth portion 2116 may extend through the shared source drain region 2146 and the drain 216 such that the drain 216 is in contact with only the annular side surface of the OS channel. The fourth portion 2114 has a second embedded dielectric 2152 inside. By increasing the area of the OS channel in contact with the source or drain, the contact resistance can be significantly reduced, such that the total resistance of the OS FET is reduced and the current at the same voltage is increased. Accordingly, the driving capability and response speed of the NAND 210 including the OS FET M3, the OS FET M2, and the OS FET M4 can be significantly improved.

As described above, the OS FET is a non-junction FET, and the OS channel is also doped with a certain doping concentration, such as n-type doping. For doped OS channels, the switching characteristics of FET devices are relatively sensitive to channel thickness. When using an OS channel of solid structure, variations in hole size can lead to device-to-device fluctuations, for example, the switching threshold voltages of different FETs can be different accordingly, which is very detrimental to FET control. In contrast, when a macroni structure is employed, the thickness of the OS channel can be precisely controlled by ALD. It will be appreciated that other deposition processes may be used. Thus, the electrical performance of each FET can be made continuous and uniform, and chip circuit design and control can be simplified. Further, compared to laterally arranged NAND, the vertically stacked NAND210 in fig. 21 can save approximately 2/3 of the occupied area, which can greatly increase the integration level of the semiconductor device. Although the configuration of FET M4 below and FET M3 above is shown in fig. 21, the configuration in fig. 21 may be reversed such that FET M3 below and FET M4 above.

Further, while NAND210 is shown in FIG. 21 as a vertical stack of three FETs, this is merely illustrative and not limiting of the scope of the present disclosure. The three FETs of NAND210 may also be arranged horizontally in the same layer. Alternatively, one FET of the NAND210 may also be stacked on two FETs. Although a gate structure is shown in fig. 21 as GAA, other gate structures may be used, such as top single gate, back single gate, double gate, and fin gate.

Fig. 22 shows a schematic circuit diagram and a schematic block diagram of the NOR220 according to one embodiment of the present disclosure. Unlike NOR 200 in fig. 20, which is based on depletion mode FET M1, NOR220 includes an enhancement mode FET. The right side of fig. 22 shows one specific implementation of the left side circuit schematic. In one embodiment, NOR220 may be located on isolation region 222. In another embodiment, isolation region 222 may have underlying circuitry below it. NOR220 includes OS FET M2 and OS FET M4, each including an OS channel, and OS FET M3, including an OS channel, stacked on OS FET M2 and OS FET M4. By using an OS channel, the temperature of the fabrication process of NOR220 can be controlled below 450 ℃, so that the fabrication process of NOR220 can be compatible with BEOL processes, and NOR220 can also be stacked on top of underlying CMOS circuitry.

The source 224 may be shared by the FETs M4 and M2 and coupled to ground GND, the gate of the FET M4 is coupled to the second input in_b, and the drains of the FETs M4 and M2 are integrally formed with the source of the FET M2 to share the source drain 2246. Alternatively, FETs M3, M4, and M2 may each have a respective independent source-drain region. The gate of FET M2 is coupled to the first input IN_A. The shared source drain 2246 is coupled to the output node OUT. The gate of FET M3 is coupled to the supply voltage VDD through via 2245, and the drain of FET M3 is coupled to the supply voltage VDD.

The first and annular side surfaces of the first OS channel 2211 of FET M4 are in contact with the source 2241 to reduce contact resistance, and the annular side and second end surfaces of the first OS channel 2211 are in contact with the shared source drain 2246 to reduce contact resistance. The first and annular side surfaces of the second OS channel 2212 of FET M2 are in contact with the source 2241 to reduce contact resistance, and the annular side and second end surfaces of the second OS channel 2212 are in contact with the shared source drain 2246 to reduce contact resistance. The first and annular side surfaces of the third OS channel 2213 of FET M3 are in contact with the shared source drain region 2246 to reduce contact resistance, and the annular side and second end surfaces of the third OS channel 2213 are in contact with the drain 226 to reduce contact resistance.

First, second and third embedded dielectrics 2251, 2252 and 2253 are provided in the first, second and third OS channels 2211, 2212 and 2213, respectively. The size, shape, and material of the first embedded dielectric 2251, the second embedded dielectric 2252, and the third embedded dielectric 2253 may be the same or different from one another. In other embodiments, any one of the first, second, and third OS channels 2211, 2212, and 2213 may not have an embedded dielectric. By increasing the area of the OS channel in contact with the source or drain, the contact resistance can be significantly reduced, such that the total resistance of the OS FET is reduced and the current at the same voltage is increased. Accordingly, the driving capability and response speed of NOR 220 including OS FET M3, OS FET M2, and OS FET M4 can be significantly improved.

As described above, the OS FET is a non-junction FET, and the OS channel is also doped with a certain doping concentration, such as n-type doping. For doped OS channels, the switching characteristics of FET devices are relatively sensitive to channel thickness. When an OS channel of solid structure is employed, variations in hole size (diameter of the OS channel) may cause device-to-device fluctuations, for example, the switching threshold voltages of different FETs may be different accordingly, which is very disadvantageous for FET control. In contrast, when a macroni structure is employed, the thickness of the OS channel can be precisely controlled by ALD. It will be appreciated that other deposition processes may be used. Thus, the electrical performance of each FET can be made continuous and uniform, and chip circuit design and control can be simplified. Furthermore, the vertically stacked NOR 220 in fig. 22 can save approximately 1/3 of the footprint compared to a laterally arranged NOR, which can greatly increase the integration of the semiconductor device. Although the configuration of the FETs M4 and M2 below and the FETs M3 above is shown in fig. 22, the configuration in fig. 22 may be reversed so that the FETs M3 below and the FETs M4 and M2 above.

Further, while NOR 220 is shown in fig. 22 as one FET stacked on top of two FETs, this is merely illustrative and not limiting of the scope of the present disclosure. The three FETs of NOR 220 may also be arranged horizontally in the same layer. Alternatively, three FETs of NAND 190 may also be vertically stacked. Although a gate structure is shown in fig. 22 as GAA, other gate structures may be used, such as top single gate, back single gate, double gate, and fin gate.

Fig. 23 illustrates a method 2300 for fabricating a semiconductor device according to one embodiment of the disclosure. The method may be used to fabricate the semiconductor device shown in fig. 3-22, and thus the various aspects described above with respect to fig. 3-22 may be applied to method 2300 and are not described in detail herein. At 2302, an oxide semiconductor channel is formed over a substrate. In one embodiment, the substrate may be, for example, an isolation region or other silicon substrate. Below the isolation region may be a circuit layer on which CMOS logic circuits have been formed. The CMOS circuit layer includes various interconnect structures formed using back-end-of-line processes. Since the processing process required to form the channel of semiconductor oxide is typically below 500 degrees celsius, the formation of the OS channel may be compatible with the interconnect lines formed by the back-end process. At 2304, a first drain is formed at a first end of the oxide semiconductor channel such that the first drain is in contact with at least a first surface and a second surface of the first end of the oxide semiconductor channel, the first surface being different from the second surface. At 2306, a first source is formed at a second end of the oxide semiconductor channel such that the first source is in contact with at least a third surface and a fourth surface of the second end of the oxide semiconductor channel, the first end and the second end being opposite, and the third surface being different from the fourth surface. By bringing respective surfaces of the source and drain into contact with the OS channel, the contact area of the OS channel with the source and drain is increased, thereby significantly reducing the contact resistance of the transistor. Compared with the case of increasing only the contact of the OS channel with the respective single surfaces of the source and drain, the driving capability and response speed of the transistor can be significantly improved due to the increase in the contact area of the source and drain with the OS channel, while not affecting the miniaturization of the transistor having the OS channel.

At 2308, a first dielectric is formed over a middle portion of the oxide semiconductor channel, the middle portion of the oxide semiconductor channel being located between a first end of the oxide semiconductor channel and a second end of the oxide semiconductor channel. At 2310, a first gate is formed on the first dielectric. The first dielectric isolates the OS channel from the first gate, and can control on or off of the OS channel by applying a voltage to the first gate.

Fig. 24 illustrates a method 2400 for fabricating a semiconductor device according to another embodiment of the present disclosure. The method may be used to fabricate the semiconductor device shown in fig. 9-22, and thus the various aspects described above with respect to fig. 9-22 may be applied to method 2400, which is not described in detail herein. At 2402, an oxide semiconductor channel is formed over the substrate. In one embodiment, the substrate may be, for example, an isolation region or other silicon substrate. Below the isolation region may be a circuit layer on which CMOS logic circuits have been formed. The CMOS circuit layer includes various interconnect structures formed using back-end-of-line processes. Since the processing process required to form the channel of semiconductor oxide is typically below 500 degrees celsius, the formation of the OS channel may be compatible with the interconnect lines formed by the back-end process. At 2404, a dielectric surrounding the side surface of the intermediate portion is formed at the side surface of the intermediate portion of the oxide semiconductor channel. At 2406, a gate is formed at a side surface of the dielectric surrounding the side surface of the dielectric. The dielectric isolates the gate from the OS channel and may control the on or off of the OS channel by the gate applied voltage.

At 2408, a drain is formed at the first end of the oxide semiconductor channel in contact with the first end of the oxide semiconductor channel. At 2410, forming a drain at the first end of the oxide semiconductor channel in contact with the first end of the oxide semiconductor channel. By forming the gate electrode completely surrounding the side surface of a portion of the cylindrical OS channel, the on and off of the channel can be controlled better against the short channel effect, so that the size of the device can be further reduced. In this case, the doping limit of the OS channel and the cladding of the source and drain to the OS channel can be further reduced. In some embodiments, the source and drain may each only surround side surfaces of the OS end portion. In other embodiments, the source and drain may contact only end surfaces of the ends of the OS channel, respectively, perpendicular to the OS channel extension direction.

Fig. 25 illustrates a method 2500 for fabricating a semiconductor device according to another embodiment of the present disclosure. The method may be used to fabricate the semiconductor device shown in fig. 13-22, and thus the various aspects described above with respect to fig. 13-22 may be applied to method 2500, which is not described in detail herein. At 2502, a first field effect transistor is formed over a substrate. The first field effect transistor includes a first oxide semiconductor channel, a first dielectric, a first gate, a first drain, and a first source. The first dielectric surrounds a side surface of the intermediate portion of the first oxide semiconductor channel. The first gate surrounds a side surface of the first dielectric. The first drain is disposed in contact with a first end of the first oxide semiconductor channel. The first source is disposed in contact with a second end of the first oxide semiconductor channel, the second end being opposite to the first end.

At 2504, a second field effect transistor is formed over a substrate. The second field effect transistor includes a second oxide semiconductor channel, a second dielectric, a second gate, a second drain, and a second source. The second dielectric surrounds a side surface of the intermediate portion of the second oxide semiconductor channel. The second gate surrounds a side surface of the second dielectric. The second drain is coupled to the first source and is disposed in contact with a third end of the second oxide semiconductor channel. And a second source electrode disposed in contact with a fourth end of the second oxide semiconductor channel, the fourth end being opposite to the third end. By forming the channel using an OS material, a manufacturing process for manufacturing a field effect transistor including the OS channel can be made compatible with a back-end process. This is because the fabrication process of the field effect transistor of the OS channel may be less than 500 degrees celsius, unlike the fabrication process of the CMOS transistor, which typically requires more than 1000 degrees celsius. Processing temperatures below 500 degrees celsius do not affect the structure formed by the back-end process, for example, do not cause impurities to be diffused into interconnects such as copper interconnects.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

Claims

A semiconductor device, comprising:

a field effect transistor comprising:

a first gate;

an oxide semiconductor channel having a middle portion and opposing first and second ends on opposite sides of the middle portion;

a first dielectric disposed between the oxide semiconductor channel and the first gate;

a first drain electrode disposed in contact with the first end of the oxide semiconductor channel; and

a first source electrode disposed in contact with the second end of the oxide semiconductor channel, wherein the first drain electrode is in contact with at least a first surface and a second surface of the first end of the oxide semiconductor channel, and the first source electrode is in contact with at least a third surface and a fourth surface of the second end of the oxide semiconductor channel, the first surface being different from the second surface, and the third surface being different from the fourth surface.
The semiconductor device of claim 1, wherein the first end of the oxide semiconductor channel is embedded in the first drain and the second end of the oxide semiconductor channel is embedded in the first source.
The semiconductor device according to claim 1 or 2, wherein the transistor further comprises:

a second gate electrode, wherein the oxide semiconductor channel is disposed between the second gate electrode and the first gate electrode; and

and a second dielectric disposed between the oxide semiconductor channel and the second gate.
The semiconductor device of any one of claims 1-3, wherein the first gate comprises a fin gate that wraps around an upper surface, a first side surface, and a second side surface of a portion of a middle portion of the oxide semiconductor channel.
The semiconductor device according to any one of claims 1 to 3, wherein the first gate surrounds a side surface of a part of the intermediate portion of the oxide semiconductor channel.
The semiconductor device according to claim 5, wherein the transistor further comprises an embedded dielectric, the embedded dielectric being disposed inside the oxide semiconductor channel.
The semiconductor device according to any one of claims 1-6, further comprising:

isolation regions stacked over underlying complementary metal oxide transistor (CMOS) circuitry, the field effect transistors being stacked over the isolation regions.
The semiconductor device according to any one of claims 1-7, wherein the intermediate portion of the oxide transistor comprises:

a first portion in contact with the first source;

a second portion contiguous with the first portion; and

and a third portion connected to the second portion and contacting the first drain electrode, wherein the extending direction of the first portion forms a first angle with the extending direction of the second portion, and the extending direction of the second portion forms a second angle with the extending direction of the third portion, wherein the first angle and the second angle are both between 45 degrees and 135 degrees.
A semiconductor device, comprising:

a field effect transistor comprising:

an oxide semiconductor channel;

a dielectric surrounding a side surface of a portion of the intermediate portion of the oxide semiconductor channel;

a gate surrounding a side surface of the dielectric;

a drain electrode disposed in contact with a first end of the oxide semiconductor channel; and

and a source electrode disposed in contact with a second end of the oxide semiconductor channel, the second end being opposite to the first end.
The semiconductor device according to claim 9, wherein the drain is provided around a side surface of the first end; and

The source is disposed around a side surface of the second end.
The semiconductor device according to claim 9 or 10, wherein the first end is embedded in the drain and the second end is embedded in the source.
The semiconductor device according to any one of claims 9-11, wherein the field effect transistor further comprises:

an embedded dielectric is disposed inside the oxide semiconductor channel.
The semiconductor device of any of claims 9-12, further comprising:

isolation regions stacked over underlying CMOS circuitry, the field effect transistors being stacked over the isolation regions.
A semiconductor device, comprising:

a first field effect transistor comprising:

a first oxide semiconductor channel;

a first dielectric surrounding a side surface of a portion of the intermediate portion of the first oxide semiconductor channel;

a first gate surrounding a side surface of the first dielectric;

a first drain electrode disposed in contact with a first end of the first oxide semiconductor channel; and

a first source electrode provided in contact with a second end of the first oxide semiconductor channel, the second end being opposite to the first end; and

A second field effect transistor comprising:

a second oxide semiconductor channel;

a second dielectric surrounding a side surface of a portion of the intermediate portion of the second oxide semiconductor channel;

a second gate surrounding a side surface of the second dielectric;

a second drain coupled to the first source and disposed in contact with a third end of the second oxide semiconductor channel; and

and a second source electrode disposed in contact with a fourth end of the second oxide semiconductor channel, the fourth end being opposite to the third end.
The semiconductor device of claim 14, wherein the second drain is integrally formed with the first source.
The semiconductor device according to claim 14 or 15, wherein

The first field effect transistor is a depletion type field effect transistor, and the first gate is connected to the first source through a via; or (b)

The first field effect transistor is an enhancement mode field effect transistor and the first gate is connected to the first drain through a via.
The semiconductor device according to any one of claims 14-16, wherein the first field effect transistor and the second field effect transistor are formed in the same horizontal layer.
The semiconductor device of any of claims 14-16, wherein the first field effect transistor is stacked over the second field effect transistor.
The semiconductor device of any of claims 14-18, wherein the first end is embedded in the first drain and the second end is embedded in the first source; and

the third terminal is embedded in the second drain and the fourth terminal is embedded in the second source.
The semiconductor device of any of claims 14-19, further comprising:

a first embedded dielectric disposed inside the first oxide semiconductor channel; and

a second embedded dielectric disposed inside the second oxide semiconductor channel.
The semiconductor device of any of claims 14-20, further comprising:

an isolation region stacked over an underlying CMOS circuit, wherein the first field effect transistor and the second field effect transistor are stacked over the isolation region.
A circuit assembly, comprising:

a circuit board; and

the semiconductor device according to any one of claims 1-21, provided on the circuit board.
An electronic device, comprising:

a power supply device;

the circuit assembly of claim 22, powered by the power supply.
A method for fabricating a semiconductor device, comprising:

forming an oxide semiconductor channel on a substrate;

forming a first drain at a first end of the oxide semiconductor channel such that the first drain is in contact with at least a first surface and a second surface of the first end of the oxide semiconductor channel, the first surface being different from the second surface;

forming a first source electrode at a second end of the oxide semiconductor channel such that the first source electrode is in contact with at least a third surface and a fourth surface of the second end of the oxide semiconductor channel, the first end and the second end being opposite, and the third surface being different from the fourth surface;

forming a first dielectric over a portion of a middle portion of the oxide semiconductor channel, the middle portion of the oxide semiconductor channel being located between a first end of the oxide semiconductor channel and a second end of the oxide semiconductor channel; and

a first gate is formed on the first dielectric.
The method of claim 24, wherein forming a first drain at a first end of the oxide semiconductor channel such that the first drain contacts at least a first surface and a second surface of the first end of the oxide semiconductor channel comprises: forming a first drain at a first end of the oxide semiconductor channel such that the first end of the oxide semiconductor channel is embedded in the first drain; and

forming a first source at a second end of the oxide semiconductor channel such that the first source contacts at least a third surface and a fourth surface of the second end of the oxide semiconductor channel includes: a first source is formed at a second end of the oxide semiconductor channel such that the second end of the oxide semiconductor channel is embedded in the first source.
The method of claim 24 or 25, wherein forming an oxide semiconductor channel on the substrate comprises: an embedded dielectric is formed inside the oxide semiconductor channel.
The method of any of claims 24-26, wherein forming an oxide semiconductor channel on a substrate comprises:

Forming an isolation region on the substrate, the substrate comprising complementary metal oxide transistor (CMOS) circuitry; and

the oxide semiconductor channel is formed on the isolation region.
The method of any of claims 21-27, wherein forming an oxide semiconductor channel on a substrate comprises:

forming a first portion of an oxide semiconductor channel on the substrate, the first portion of the oxide semiconductor channel being in contact with the first source;

forming a second portion of an oxide semiconductor channel over the substrate, the second portion of the oxide semiconductor channel contiguous with the first portion; and

a third portion of an oxide semiconductor channel is formed over the substrate, the third portion of the oxide semiconductor channel being contiguous with the second portion and in contact with the first drain, the first portion extending in a first angle with an extension of the second portion, the second portion extending in a second angle with an extension of the third portion, wherein the first angle and the second angle are both between 45 ° and 135 °.
A method for fabricating a semiconductor device, comprising:

Forming an oxide semiconductor channel over a substrate;

forming a dielectric surrounding a side surface of a portion of the intermediate portion at a side surface of a portion of the intermediate portion of the oxide semiconductor channel;

forming a gate around a side surface of the dielectric at the side surface of the dielectric;

forming a drain electrode at a first end of the oxide semiconductor channel in contact with the first end of the oxide semiconductor channel; and

a source electrode is formed at a second end of the oxide semiconductor channel in contact with the second end of the oxide semiconductor channel, the second end being opposite the first end.
The semiconductor device according to claim 29, wherein forming a drain at the first end of the oxide semiconductor channel in contact with the first end of the oxide semiconductor channel comprises: forming the drain around a side surface of the first end at the first end of the oxide semiconductor channel; and

forming a source electrode in contact with the second end of the oxide semiconductor channel at the second end of the oxide semiconductor channel includes: the source electrode is formed at a second end of the oxide semiconductor channel around a side surface of the second end.
The semiconductor device according to claim 29, wherein forming a drain at the first end of the oxide semiconductor channel in contact with the first end of the oxide semiconductor channel comprises: forming the drain electrode wrapping the first end at the first end of the oxide semiconductor channel; and

forming a source electrode in contact with the second end of the oxide semiconductor channel at the second end of the oxide semiconductor channel includes: the source electrode is formed at a second end of the oxide semiconductor channel to cover the second end.
The semiconductor device of any of claims 29-31, wherein forming an oxide semiconductor channel over a substrate further comprises:

an embedded dielectric is formed inside the oxide semiconductor channel.
A method for forming a semiconductor device, comprising:

forming a first field effect transistor on a substrate, the first field effect transistor comprising:

a first oxide semiconductor channel;

a first dielectric surrounding a side surface of a portion of the intermediate portion of the first oxide semiconductor channel;

a first gate surrounding a side surface of the first dielectric;

A first drain electrode formed to be in contact with a first end of the first oxide semiconductor channel; and

a first source electrode formed in contact with a second end of the first oxide semiconductor channel, the second end being opposite to the first end; and

forming a second field effect transistor on the substrate, the second field effect transistor comprising:

a second oxide semiconductor channel;

a second dielectric surrounding a side surface of a portion of the intermediate portion of the second oxide semiconductor channel;

a second gate surrounding a side surface of the second dielectric;

a second drain formed to be coupled to the first source and to be in contact with a third end of the second oxide semiconductor channel; and

and a second source electrode formed in contact with a fourth end of the second oxide semiconductor channel, the fourth end being opposite to the third end.