CN116864533A

CN116864533A - High-voltage semiconductor device and method for manufacturing the same

Info

Publication number: CN116864533A
Application number: CN202210311169.3A
Authority: CN
Inventors: 吴欣翰; 张凯焜; 江品宏
Original assignee: United Microelectronics Corp
Current assignee: United Microelectronics Corp
Priority date: 2022-03-28
Filing date: 2022-03-28
Publication date: 2023-10-10
Also published as: US20230307524A1; US11923435B2; US20240154027A1

Abstract

The invention discloses a high-voltage semiconductor device and a manufacturing method thereof, wherein the high-voltage semiconductor device comprises a semiconductor substrate, a first drift region, a grid structure, a first sub-grid structure, a first gap wall structure, a second gap wall structure and a first insulation structure. The first drift region is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and separated from the first sub-gate structure. The first sub-gate structure and the first insulation structure are disposed on the first drift region. The first spacer structure is disposed on a sidewall of the gate structure. The second spacer structure is disposed on a sidewall of the first sub-gate structure. At least a portion of the first insulating structure is located between the first spacer structure and the second spacer structure. The first insulating structure is directly connected with the first drift region between the first spacer structure and the second spacer structure.

Description

High-voltage semiconductor device and method for manufacturing the same

Technical Field

The present invention relates to a high voltage semiconductor device and a method for fabricating the same, and more particularly, to a high voltage semiconductor device having an insulating structure connected to a drift region and a method for fabricating the same.

Background

Among power devices having high voltage processing capability, double-Diffused MOS (DMOS) transistor devices continue to be of interest. Common DMOS transistor elements include vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS) transistor elements. Because of the high operating bandwidth and efficiency and the planar structure that is easy to integrate with other integrated circuits, LDMOS transistor devices are widely used in high voltage operating environments, such as a CPU power supply (CPU), a power management system (power management system), a DC/AC converter (AC/DC converter), and a high-power or high-band power amplifier. The main feature of the LDMOS transistor device is to mitigate the high voltage between the source terminal and the drain terminal by providing a lateral diffusion drift region with a low doping concentration and a large area, so that a higher breakdown voltage (breakdown voltage) of the LDMOS transistor device can be obtained. However, as feature sizes continue to shrink, there is a continuing effort in the relevant art to improve the electrical performance of high voltage semiconductor devices or/and the integration of fabrication processes with other devices through design adjustments in the structures and/or fabrication processes.

Disclosure of Invention

The present invention provides a high voltage semiconductor device and a method of fabricating the same, which are connected to a drift region using an insulating structure and prevent silicide from being formed on a specific portion of the drift region, thereby improving electrical performance of the high voltage semiconductor device.

An embodiment of the invention provides a semiconductor device, which comprises a semiconductor substrate, a first drift region, a gate structure, a first sub-gate structure, a first spacer structure, a second spacer structure and a first insulation structure. The first drift region is disposed in the semiconductor substrate, the gate structure is disposed on the semiconductor substrate, and the first sub-gate structure is disposed on the first drift region and separated from the gate structure. The first spacer structure is disposed on a sidewall of the gate structure, the second spacer structure is disposed on a sidewall of the first sub-gate structure, and the first insulating structure is disposed on the first drift region. At least a portion of the first insulating structure is located between the first spacer structure and the second spacer structure, a first portion of the first drift region is located between the first spacer structure and the second spacer structure, and the first insulating structure is directly connected to the first portion of the first drift region.

An embodiment of the invention provides a method for manufacturing a semiconductor device, which comprises the following steps. A first drift region is formed in a semiconductor substrate. A gate structure is formed on a semiconductor substrate. A first sub-gate structure is formed on the first drift region, and the first sub-gate structure and the gate structure are separated from each other. A first spacer structure is located on the sidewall of the gate structure, a second spacer structure is located on the sidewall of the first sub-gate structure, and a first insulating structure is located on the first drift region. At least a portion of the first insulating structure is located between the first spacer structure and the second spacer structure. A portion of the first drift region is located between the first spacer structure and the second spacer structure, and the first insulating structure is directly connected to the portion of the first drift region.

Another embodiment of the present invention provides a semiconductor device including a semiconductor substrate, a first drift region, a gate structure, a spacer structure, a first source/drain doped region, a first silicide layer, and a first insulating structure. The first drift region is disposed in the semiconductor substrate, the gate structure is disposed on the semiconductor substrate, and the spacer structure is disposed on a sidewall of the gate structure. The first source/drain doped region is disposed in the first drift region, and the first source/drain doped region is separated from the spacer structure. The first silicide layer is disposed on the first source/drain doped region, and the first silicide layer is separated from the spacer structure. A portion of the first drift region is located between the spacer structure and the first source/drain doped region. The first insulating structure is disposed on the first drift region and is directly connected to a portion of the first drift region between the spacer structure and the first source/drain doped region.

Drawings

Fig. 1 is a schematic view of a high voltage semiconductor device according to a first embodiment of the present invention;

fig. 2 is a partially enlarged schematic view of a high voltage semiconductor device according to a first embodiment of the present invention;

fig. 3 to 7 are schematic views illustrating a method for fabricating a high voltage semiconductor device according to a first embodiment of the present invention, in which

FIG. 4 is a schematic top view of the situation of FIG. 3;

FIG. 5 is a schematic view of the situation after FIG. 3;

FIG. 6 is a schematic view of the situation after FIG. 5;

FIG. 7 is a schematic view of the situation after FIG. 6;

FIG. 8 is a flow chart illustrating a method for fabricating a high voltage semiconductor device according to an embodiment of the present invention;

fig. 9 is a schematic diagram illustrating a method for fabricating a high voltage semiconductor device according to another embodiment of the present invention;

FIG. 10 is a schematic top view of the situation of FIG. 9;

fig. 11 is a schematic view of a high voltage semiconductor device according to a second embodiment of the present invention;

fig. 12 is a partially enlarged schematic view of a high voltage semiconductor device according to a second embodiment of the present invention;

fig. 13 is a schematic diagram showing a method for manufacturing a high-voltage semiconductor device according to a second embodiment of the present invention;

fig. 14 is a schematic view of a high voltage semiconductor device according to a third embodiment of the present invention;

fig. 15 is a schematic diagram illustrating a method for manufacturing a high voltage semiconductor device according to a third embodiment of the present invention.

Description of the main reference signs

10. Semiconductor substrate

12A first drift region

12B second drift region

22. Oxide layer

22A gate oxide layer

22B gate oxide layer

22G gate oxide layer

24A sub dummy gate

24B sub dummy gate

24G dummy gate

32. Mask layer

42. First patterned mask layer

44. Second patterned mask layer

52A source/drain doped regions

52B source/drain doped regions

54A silicide layer

54B silicide layer

56. Insulating layer

60. Gate material

60A sub-grid structure

60B sub-grid structure

60G grid structure

62. Dielectric layer

91. Patterning manufacturing process

92. Silicide production process

101. High voltage semiconductor device

102. High voltage semiconductor device

103. High voltage semiconductor device

BS1 first insulation structure

BS2 second insulation structure

CT1 contact structure

CT2 contact structure

CT3 contact structure

D1 First direction

D2 Second direction

D3 Third direction of

P1 first part

P2 second part

P3 third part

S1 to S5 steps

SP1 spacer structure

SP2 spacer structure

SP3 spacer structure

Detailed Description

The following detailed description of the invention discloses enough details to enable those skilled in the art to practice the invention. The embodiments set forth below should be considered as illustrative and not limiting. It will be apparent to persons skilled in the relevant art that various changes and modifications in form and detail can be made therein without departing from the spirit and scope of the invention.

Before further describing the embodiments, specific terminology is used throughout the description below.

The terms "on …," "over …," and "over …" should be read in the broadest sense such that "on …" means not only "directly on" something but also includes the meaning of something with other intervening features or layers therebetween, and "over …" or "over …" means not only "over" or "over" something, but also may include the meaning of "over" or "over" something without other intervening features or layers therebetween (i.e., directly on something).

As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise, do not imply that a particular claim element is given any preceding ordinal number, nor is it intended to be a separate ordinal number, or method of manufacture, for that particular claim element and claim element.

The term "etching" is generally used herein to describe a fabrication process used to pattern a material such that at least a portion of the material is left behind after etching is complete. When a material is "etched," at least a portion of the material may remain after the etching is complete. In contrast, when "removing" material, substantially all of the material may be removed in the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

The term "forming" or "disposing" is used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any viable layer formation technique including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like.

Please refer to fig. 1 and fig. 2. Fig. 1 is a schematic diagram of a high voltage semiconductor device 101 according to a first embodiment of the present invention, and fig. 2 is a schematic diagram of the present embodimentA partially enlarged schematic view of the high voltage semiconductor device 101. As shown in fig. 1 and 2, the high voltage semiconductor device 101 includes a semiconductor substrate 10, a first drift region 12A, a gate structure 60G, a sub-gate structure 60A, a spacer structure SP1, a spacer structure SP2, and a first insulating structure BS1. The first drift region 12A is disposed in the semiconductor substrate 10, the gate structure 60G is disposed on the semiconductor substrate 10, and the sub-gate structure 60A is disposed on the first drift region 12A and separated from the gate structure 60G. A spacer structure SP1 is disposed on the sidewall of the gate structure 60G, a spacer structure SP2 is disposed on the sidewall of the sub-gate structure 60A, and a first insulating structure BS1 is disposed on the first drift region 12A. At least a portion of the first insulating structure BS1 is located between the spacer structures SP1 and SP2, a first portion P1 of the first drift region 12A is located between the spacer structures SP1 and SP2, and the first insulating structure BS1 is directly connected to the first portion P1 of the first drift region 12A. In some embodiments, the first insulation structure BS1 is directly connected to the first portion P1 of the first drift region 12A, so that the silicide layer is prevented from being formed on the first drift region 12A between the spacer structures SP1 and SP2, thereby improving the electrical performance of the high voltage semiconductor device (e.g., but not limited to reducing the off-current of the high voltage semiconductor device, I _off ) Is effective in (1).

In some embodiments, a vertical direction (e.g., a third direction D3 shown in fig. 1-2) may be regarded as a thickness direction of the semiconductor substrate 10, and the semiconductor substrate 10 may have an upper surface and a bottom surface opposite to each other in the third direction D3, and the gate structure 60G, the sub-gate structure 60A, the spacer structure SP1, the spacer structure SP2, and the first insulation structure BS1 may be disposed on one side of the upper surface of the semiconductor substrate 10. In addition, the horizontal direction (e.g., a first direction D1, a second direction D2, and other directions orthogonal to the third direction D3 shown in fig. 1-2) substantially orthogonal to the third direction D3 may be substantially parallel to the upper surface or/and the bottom surface of the semiconductor substrate 10, but is not limited thereto. The distance in the third direction D3 between the component and the bottom surface of the semiconductor substrate 10 at the relatively higher position in the third direction D3 or/and the distance in the third direction D3 between the component and the bottom surface of the semiconductor substrate 10 at the relatively lower position in the third direction D3 or/and the distance in the third direction D3 between the lower part or/and the bottom surface of the semiconductor substrate 10, the lower part or bottom of each component may be closer to the bottom surface of the semiconductor substrate 10 than the upper part or top of this component in the third direction D3, another component above a certain component may be regarded as being relatively farther from the bottom surface of the semiconductor substrate 10 in the third direction D3, and another component below a certain component may be regarded as being relatively closer to the bottom surface of the semiconductor substrate 10 in the third direction D3.

Further illustrated, in some embodiments, the high voltage semiconductor device 101 may further include a gate oxide layer 22G and a gate oxide layer 22A, the gate oxide layer 22G may be disposed between the semiconductor substrate 10 and the gate structure 60G in the third direction D3, and the gate oxide layer 22A may be disposed between the first drift region 12A and the sub-gate structure 60A in the third direction D3. In some embodiments, the spacer structure SP1 and the first drift region 12A may sandwich a portion of the gate oxide layer 22G in the third direction D3, and the spacer structure SP2 and the first drift region 12A may sandwich a portion of the gate oxide layer 22A in the third direction D3, but not limited thereto. In other words, the gate oxide layer 22G may extend from below the gate structure 60G to below the spacer structure SP1, and the gate oxide layer 22A may extend from below the sub-gate structure 60A to below the spacer structure SP 2. In addition, in some embodiments, the gate oxide layer 22G and the gate oxide layer 22A may sandwich the first insulation structure BS1 in the first direction D1, and the first insulation structure BS1 may be directly connected to the gate oxide layer 22G and the gate oxide layer 22A, but is not limited thereto. In some embodiments, the material composition of the first insulating structure BS1, the material composition of the gate oxide layer 22G, and the material composition of the gate oxide layer 22A are the same, for example, but not limited to, the same insulating oxide material.

In some embodiments, a second portion P2 of the first drift region 12A may be located below the spacer structure SP1 in the third direction D3, a third portion P3 of the first drift region 12A may be located below the spacer structure SP2 in the third direction D3, and the second portion P2 and the third portion P3 may sandwich the first portion P1 of the first drift region 12A in the first direction D1. In other words, the first drift region 12A (e.g., the first portion P1) between the spacer structure SP1 and the spacer structure SP2 may be completely covered by the first insulating structure BS1, and the first drift region 12A (e.g., the first portion P1, the second portion P2, and the third portion P3) between the gate structure 60G and the sub-gate structure 60A may be completely covered by the first insulating structure BS1, the spacer structure SP1, and the spacer structure SP2, thereby avoiding forming a conductive material (e.g., a conductive silicide layer) directly on the first portion P1, the second portion P2, or/and the third portion P3 of the first drift region 12A.

In some embodiments, the high voltage semiconductor device 101 may further include a source/drain doped region 52A and a silicide layer 54A, the source/drain doped region 52A may be disposed in the first drift region 12A, and the silicide layer 54A may be disposed in the source/drain doped region 52A or/and disposed on the source/drain doped region 52A. The sub-gate structure 60A may be located between the gate structure 60G and the source/drain doped region 52A in the first direction D1, and the sub-gate structure 60A may be electrically separated from the gate structure 60G and the source/drain doped region 52A, respectively. By the arrangement of the sub-gate structure 60A, the distance between the gate structure 60G and the source/drain doped region 52A or/and the silicide layer 54A can be increased, and by the arrangement of the first insulating structure BS1, formation of a conductive silicide layer on the first drift region 12A located between the spacer structure SP1 and the spacer structure SP2 or/and on the first drift region 12A located between the gate structure 60G and the sub-gate structure 60A can be avoided, thereby improving the electrical performance (e.g., but not limited to reducing off-current) of the high voltage semiconductor device 101.

In some embodiments, the high voltage semiconductor device 101 may further include a second drift region 12B, a sub-gate structure 60B, a spacer structure SP3, a second insulating structure BS2, a gate oxide layer 22B, a source/drain doped region 52B, and a silicide layer 54B. The second drift region 12B may be disposed in the semiconductor substrate 10, and a portion of the first drift region 12A and a portion of the second drift region 12B may be located at opposite sides of the gate structure 60G in the first direction D1, respectively. The sub-gate structure 60B may be disposed on the second drift region 12B and separated from the gate structure 60G, and the sub-gate structure 60A and the sub-gate structure 60B may be located at opposite sides of the gate structure 60G in the first direction D1, respectively. The spacer structure SP3 may be disposed on a sidewall of the sub-gate structure 60B, the second insulating structure BS2 may be disposed on the second drift region 12B, and at least a portion of the second insulating structure BS2 may be located between the spacer structure SP1 and the spacer structure SP 3. A portion of the second drift region 12B may be located between the spacer structures SP1 and SP3, and the second insulating structure BS2 may be directly connected to the second drift region 12B located between the spacer structures SP1 and SP 3.

In some embodiments, the gate oxide layer 22B may be disposed between the second drift region 12B and the sub-gate structure 60B in the third direction D3, and the spacer structure SP3 and the second drift region 12B may sandwich a portion of the gate oxide layer 22B in the third direction D3, but is not limited thereto. In other words, the gate oxide layer 22B may extend from under the sub-gate structure 60B to under the spacer structure SP 3. In addition, in some embodiments, the gate oxide layer 22G and the gate oxide layer 22B may sandwich the second insulation structure BS2 in the first direction D1, and the second insulation structure BS2 may be directly connected to the gate oxide layer 22G and the gate oxide layer 22B, but not limited thereto. In some embodiments, the material composition of the second insulating structure BS2, the material composition of the gate oxide layer 22G, and the material composition of the gate oxide layer 22B are the same, for example, but not limited to, the same insulating oxide material.

In some embodiments, the source/drain doped region 52B may be disposed in the second drift region 12B, and the silicide layer 54B may be disposed in the source/drain doped region 52B or/and disposed on the source/drain doped region 52B. The sub-gate structure 60B may be located between the gate structure 60G and the source/drain doped region 52B in the first direction D1, and the sub-gate structure 60B may be electrically separated from the gate structure 60G and the source/drain doped region 52B, respectively. By the arrangement of the sub-gate structure 60B, the distance between the gate structure 60G and the source/drain doped region 52B or/and the silicide layer 54B may be increased, and by the arrangement of the second insulating structure BS2, the formation of a conductive silicide layer on the second drift region 12B located between the spacer structure SP1 and the spacer structure SP3 or/and on the second drift region 12B located between the gate structure 60G and the sub-gate structure 60B may be avoided. In some embodiments, the source/drain doped region 52A and the source/drain doped region 52B may be a source doped region and a drain doped region, respectively, for example, the source/drain doped region 52B may be a source doped region when the source/drain doped region 52A is a drain doped region, and the source/drain doped region 52A may be a source doped region when the source/drain doped region 52B is a drain doped region. In addition, the high voltage semiconductor device 101 may be regarded as a double diffused drain metal oxide semiconductor (double diffused drain MOS, DDDMOS) structure, but is not limited thereto.

In some embodiments, the high voltage semiconductor device 101 may further include an insulating layer 56, a dielectric layer 62, and a plurality of contact structures (e.g., contact structure CT1, contact structure CT2, and contact structure CT3 shown in fig. 1). The insulating layer 56 may cover the silicide layer 54A, the source/drain doped region 52A, the silicide layer 54B, and the source/drain doped region 52B, and the insulating layer 56 may be partially disposed between the spacer structures SP1 and SP2 and partially disposed between the spacer structures SP1 and SP 3. A dielectric layer 62 may be disposed on insulating layer 56 and cover gate structure 60G, sub-gate structure 60A, and sub-gate structure 60B. Contact structure CT1 may contact gate structure 60G through dielectric layer 62 to form an electrical connection, contact structure CT2 may contact silicide layer 54A or/and source/drain doped region 52A through dielectric layer 62 and insulating layer 56 to form an electrical connection, and contact structure CT3 may contact silicide layer 54B or/and source/drain doped region 52B through dielectric layer 62 and insulating layer 56 to form an electrical connection.

In some embodiments, the semiconductor substrate 10 may include a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable semiconductor materials. In addition, the first drift region 12A and the second drift region 12B may include doped regions formed by performing a doping process (e.g., an implantation process) on the semiconductor substrate 10, the semiconductor substrate 10 may be a semiconductor substrate having a first conductivity type or a region including the first conductivity type (e.g., a doped well region having the first conductivity type, not shown), and the first drift region 12A and the second drift region 12B may have a second conductivity type, and the second conductivity type may be complementary to the first conductivity type. For example, the first conductivity type may be p-type and the second conductivity type may be n-type, but not limited thereto. In some embodiments, the source/drain doped regions 52A and 52B may include doped regions formed in the semiconductor substrate 10 using a doping process (e.g., an implantation process). In some embodiments, the conductivity type of the source/drain doped region 52A and the source/drain doped region 52B may be the same as the conductivity type of the first drift region 12A and the second drift region 12B, but the doping concentration of the source/drain doped region 52A and the source/drain doped region 52B may be higher than the doping concentration of the first drift region 12A and the second drift region 12B, for example, the source/drain doped region 52A and the source/drain doped region 52B may be n-type heavily doped regions, respectively, but not limited thereto.

In some embodiments, the materials used to form the gate oxide layer 22G, the gate oxide layer 22A, the gate oxide layer 22B, the first insulating structure BS1, and the second insulating structure BS2 may include silicon oxide or other suitable oxide insulating materials. In some embodiments, the gate structures 60G, 60A, and 60B may be formed of the same material (e.g., the gate material 60), and the gate material 60 may include a gate dielectric layer (not shown) and a gate layer (not shown) disposed on the gate dielectric layer, the gate dielectric layer may include a high-k dielectric material or other suitable dielectric material, and the gate layer may include a non-metal conductive material (e.g., doped polysilicon) or a metal conductive material, such as a metal gate structure stacked by a work function layer and a low-resistance layer. In some embodiments, the spacer structures SP1, SP2 and SP3 may each comprise a single layer or multiple layers of dielectric material, such as silicon nitride, silicon oxide, silicon carbonitride or other suitable dielectric materials. The silicide layers 54A and 54B may include silicide conductive materials such as metal silicide materials, but are not limited thereto. The metal silicide may include cobalt-metal silicide (cobalt-silicide), nickel-metal silicide (nickel-silicide), or other suitable metal silicide. The insulating layer 56 may comprise a single layer or multiple layers of insulating material, such as silicon nitride, silicon oxide, or other suitable insulating material, while the dielectric layer 62 may comprise a single layer or multiple layers of dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, low-k material, or other suitable dielectric material. In addition, each contact structure may include a low resistivity material (such as copper, aluminum, tungsten, etc.) and a barrier layer surrounding the low resistivity material (such as titanium nitride, tantalum nitride, or other suitable barrier materials with conductive capabilities), but is not limited thereto.

Please refer to fig. 1 to 8. Fig. 3 to 7 are schematic diagrams illustrating a method for fabricating a high voltage semiconductor device according to a first embodiment of the present invention, in which fig. 4 is a schematic plan view illustrating a situation of fig. 3 (for convenience of description, a portion of the structure is omitted in fig. 4 and a relative relationship between a patterned mask layer and a dummy gate and a sub-dummy gate is mainly illustrated), fig. 5 is a schematic diagram illustrating a situation after fig. 3, fig. 6 is a schematic diagram illustrating a situation after fig. 5, and fig. 7 is a schematic diagram illustrating a situation after fig. 6. Fig. 8 is a flow chart illustrating a method for fabricating a high voltage semiconductor device according to an embodiment of the invention. In some embodiments, fig. 1 may be regarded as a schematic diagram illustrating the situation after fig. 7, but is not limited thereto. As shown in fig. 1 and 2, the method for manufacturing the high voltage semiconductor device 101 of the present embodiment may include the following steps. A first drift region 12A is formed in the semiconductor substrate 10, a gate structure 60G is formed on the semiconductor substrate 10, and a sub-gate structure 60A is formed on the first drift region 12A. The sub-gate structure 60A and the gate structure 60G are separated from each other, the spacer structure SP1 is located on a sidewall of the gate structure 60G, the spacer structure SP2 is located on a sidewall of the sub-gate structure 60A, and the first insulating structure BS1 is located on the first drift region 12A. At least a portion of the first insulating structure BS1 is located between the spacer structures SP1 and SP2, a portion (e.g., the first portion P1) of the first drift region 12A is located between the spacer structures SP1 and SP2, and the first insulating structure BS1 is directly connected to the first portion P1 of the first drift region 12A.

Further, the manufacturing method of the present embodiment may include, but is not limited to, the following steps. As shown in fig. 3, 4 and 8, a first drift region 12A and a second drift region 12B are formed in the semiconductor substrate 10, then, step S1 may be performed, a dummy gate 24G, a sub-dummy gate 24A and a sub-dummy gate 24B are formed on the semiconductor substrate 10, the dummy gate 24G, the sub-dummy gate 24A and the sub-dummy gate 24B may extend along the second direction D2, the sub-dummy gate 24A and the sub-dummy gate 24B may be located on opposite sides of the dummy gate 24G in the first direction D1, respectively, and the dummy gate 24G and the sub-dummy gate 24A and the sub-dummy gate 24B are separated from each other. In some embodiments, an oxide layer 22 may be formed on the semiconductor substrate 10 prior to forming the dummy gate 24G, the sub-dummy gate 24A, and the sub-dummy gate 24B, and the dummy gate 24G, the sub-dummy gate 24A, and the sub-dummy gate 24B may be formed on the oxide layer 20.

Then, as shown in fig. 3, 5 and 8, step S2 may be performed to perform a patterning process 91 on the oxide layer 20, and a portion of the oxide layer 22 may be patterned into a gate oxide layer 22G, a gate oxide layer 22A, a gate oxide layer 22B, a first insulating structure BS1 and a second insulating structure BS2. The dummy gate 24G and the first drift region 12A may sandwich at least a portion of the gate oxide layer 22G in the third direction D3, the sub-dummy gate 24A and the first drift region 12A may sandwich at least a portion of the gate oxide layer 22A in the third direction D3, and the sub-dummy gate 24B and the second drift region 12B may sandwich at least a portion of the gate oxide layer 22B in the third direction D3.

In some embodiments, as shown in fig. 3 to 5, a first patterned mask layer 42 may be formed to cover the dummy gate 24G, the sub-dummy gate 24A, the sub-dummy gate 24B, the oxide layer 22 between the dummy gate 24G and the sub-dummy gate 24A, and the oxide layer 22 between the dummy gate 24G and the sub-dummy gate 24B before the patterning process 91, and the patterning process 91 may include an etching process using the first patterned mask layer 42 as a mask to remove a portion of the oxide layer 22 to form the gate oxide layer 22G, the gate oxide layer 22A, the gate oxide layer 22B, the first insulating structure BS1, and the second insulating structure BS2. In some embodiments, a mask layer 32 may be conformally formed over the oxide layer 22, dummy gate 24G, sub-dummy gate 24A, and sub-dummy gate 24B prior to forming the first patterned mask layer 42, and the first patterned mask layer 42 may be formed on the mask layer 32, with the material composition of the mask layer 32 being different from the material composition of the first patterned mask layer 42. For example, the first patterned mask layer 42 may comprise a patterned photoresist layer, and the mask layer 32 may comprise silicon nitride or other suitable mask material, but is not limited thereto.

As shown in fig. 3 and 5, the mask layer 32 and the oxide layer 22 not covered by the first patterned mask layer 42 may be at least partially removed by the patterning process 91, at least a portion of the oxide layer 22 between the dummy gate 24G and the sub-dummy gate 24A may become the first insulating structure BS1 after the patterning process 91, and at least a portion of the oxide layer 22 between the dummy gate 24G and the sub-dummy gate 24B may become the second insulating structure BS2 after the patterning process 91, so the gate oxide layer 22A, the first insulating structure BS1, the gate oxide layer 22G, the second insulating structure BS2, and the gate oxide layer 22B may be connected to each other to have the same material composition.

As shown in fig. 3, 5, 6 and 8, after the patterning process 91, the first patterned mask layer 42 and the mask layer 32 may be removed, and step S3 may be performed to form the spacer structures SP1, SP2 and SP3. Spacer structures SP1 are formed on sidewalls of the dummy gate 24G, spacer structures SP2 are formed on sidewalls of the sub dummy gate 24A, and spacer structures SP3 are formed on sidewalls of the sub dummy gate 24B. In some embodiments, the spacer structure SP1 and the first drift region 12A may sandwich a portion of the gate oxide layer 22G in the third direction D3, the spacer structure SP1 and the second drift region 12B may sandwich another portion of the gate oxide layer 22G in the third direction D3, the spacer structure SP2 and the first drift region 12A may sandwich a portion of the gate oxide layer 22A in the third direction D3, and the spacer structure SP3 and the second drift region 12B may sandwich a portion of the gate oxide layer 22B in the third direction D3. In addition, the gate oxide layer 22G and the gate oxide layer 22A may sandwich the first insulating structure BS1 in the first direction D1, the first insulating structure BS1 may be directly connected to the gate oxide layer 22G and the gate oxide layer 22A, the gate oxide layer 22G and the gate oxide layer 22B may sandwich the second insulating structure BS2 in the first direction D1, and the second insulating structure BS2 may be directly connected to the gate oxide layer 22G and the gate oxide layer 22B.

Furthermore, after the patterning process 91, source/drain doped regions 52A may be formed in the first drift region 12A and source/drain doped regions 52B may be formed in the second drift region 12B. In some embodiments, the spacer structures SP1, SP2 and SP3 may have multiple layers of spacers, and the source/drain doped regions 52A and 52B may be formed by performing a doping process using the spacers as masks, but not limited thereto. Accordingly, the sub dummy gate 24A may be located between the dummy gate 24G and the source/drain doped region 52A in the first direction D1, and the sub dummy gate 24B may be located between the dummy gate 24G and the source/drain doped region 52B in the first direction D1.

Then, as shown in fig. 7 and 8, step S4, that is, a silicide process 92 is performed to form the silicide layer 54A in the source/drain doped region 52A and/or on the source/drain doped region 52A, and form the silicide layer 54B in the source/drain doped region 52B and/or on the source/drain doped region 52B. In some embodiments, the silicide process 92 may include a self-aligned silicide process, wherein a metal layer (not shown) is used to cover the surfaces of the source/drain doped regions 52A and 52B, and a heat treatment is performed to react the metal layer with the source/drain doped regions 52A and 52B to form the silicide layers 54A and 54B, respectively, and the metal layer may be removed after the silicide layers 54A and 54B are formed.

It should be noted that, during the silicide formation process 92, the first drift region 12A between the dummy gate 24G and the sub-dummy gate 24A may be completely covered by the first insulating structure BS1, the gate oxide layer 22A, and the gate oxide layer 22G, while the second drift region 12B between the dummy gate 24G and the sub-dummy gate 24B may be completely covered by the second insulating structure BS2, the gate oxide layer 22B, and the gate oxide layer 22G, so that a conductive silicide layer may be avoided from being formed on the first drift region 12A between the spacer structure SP1 and the spacer structure SP2 or/and on the first drift region 12A between the gate structure 60G and the sub-gate structure 60A, and a conductive silicide layer may be avoided from being formed on the second drift region 12B between the spacer structure SP1 and the spacer structure SP3 or/and the second drift region 12B between the gate structure 60G and the sub-gate structure 60B.

In addition, in some embodiments, the dummy gate 24G, the sub-dummy gate 24A, and the sub-dummy gate 24B may each include a dummy gate material (not shown) and a cap layer (not shown) covering the dummy gate material, the dummy gate material may include polysilicon or other suitable materials, and the cap layer may include oxide, nitride, or other suitable materials, but is not limited thereto. In the silicide process 92, the cap layer may cover the dummy gate material, thereby avoiding the formation of silicide layers on the dummy gate 24G, the sub-dummy gate 24A, and the sub-dummy gate 24B, but is not limited thereto.

As shown in fig. 7, 8 and 1, after forming the silicide layer 54A and the silicide layer 54B, an insulating layer 56 may be formed, and step S5 is performed, that is, a replacement gate (replacement gate) manufacturing process is performed, in which the dummy gate 24G is replaced with the gate structure 60G, the sub-gate 24A is replaced with the sub-gate structure 60A, and the sub-dummy gate 24B is replaced with the sub-gate structure 60B. Accordingly, the sub-gate structure 60A may be formed on the first drift region 12A, the sub-gate structure 60B may be formed on the second drift region 12B, and the spacer structures SP1, SP2, and SP3 may be located on sidewalls of the gate structure 60G, the sub-gate structure 60A, and the sub-gate structure 60B, respectively. After forming the gate structure 60G, the sub-gate structure 60A, and the sub-gate structure 60B, the dielectric layer 62 and the respective contact structures may be formed. It should be noted that the method for fabricating the gate structure 60G, the sub-gate structure 60A and the sub-gate structure 60B according to the present invention is not limited to the steps shown in fig. 3 to 8, and the gate structure 60G, the sub-gate structure 60A and the sub-gate structure 60B may be formed by other suitable methods as required by the design. In addition, the first insulating structure BS1 and the second insulating structure BS2 of the present embodiment may be formed by using a patterning process (for example, the patterning process 91 shown in fig. 3) performed on the oxide layer, so that the effect of simplifying the manufacturing process or/and integrating the manufacturing process can be achieved.

The following description will be made with respect to different embodiments of the present invention, and for simplicity of explanation, the following description mainly describes the differences between the embodiments, and the same parts will not be repeated. In addition, like elements in the various embodiments of the present invention are labeled with like reference numerals to facilitate cross-reference between the various embodiments.

Please refer to fig. 6, 9 and 10. Fig. 9 is a schematic diagram of a method for fabricating a high voltage semiconductor device according to another embodiment of the present invention, and fig. 10 is a schematic plan view corresponding to the situation of fig. 9 (for convenience of description, a portion of the structure of fig. 10 has been omitted and the relative relationship between the patterned mask layer and the dummy gate and the sub-dummy gate is mainly shown). In some embodiments, fig. 9 may be regarded as a schematic diagram illustrating the situation after fig. 6, but is not limited thereto. As shown in fig. 6, 9 and 10, in some embodiments, after forming the spacer structure and the source/drain doped regions and before performing the silicide process 92, a second patterned mask layer 44 may be formed on the semiconductor substrate 10, and the second patterned mask layer 44 may cover the dummy gate 24G, the sub-dummy gate 24A, the sub-dummy gate 24B, the spacer structure SP1, the spacer structure SP2 and the first insulating structure BS1 between the dummy gate 24G and the sub-dummy gate 24A, and the spacer structure SP1, the spacer structure SP3 and the second insulating structure BS2 between the dummy gate 24G and the sub-dummy gate 24B.

In the silicide manufacturing process 92, the first drift region 12A between the spacer structure SP1 and the spacer structure SP2 and the second drift region 12B between the spacer structure SP1 and the spacer structure SP3 may be completely covered by the second patterned mask layer 44, the first insulating structure BS1 and the second insulating structure BS2, so as to avoid forming a conductive silicide layer on the first drift region 12A between the spacer structure SP1 and the spacer structure SP2 and the second drift region 12B between the spacer structure SP1 and the spacer structure SP3, but the second patterned mask layer 44 may be regarded as a structure for blocking silicide formation. In some embodiments, the effect of blocking silicide formation may be further enhanced by covering the first and second insulating structures BS1 and BS2 with the second patterned mask layer 44 in the silicide fabrication process 92. Furthermore, in some embodiments, the second patterned masking layer 44 may be completely removed after the silicide fabrication process 92 or at least partially remain between the spacer structures SP1 and SP2 and between the spacer structures SP1 and SP3, and the second patterned masking layer 44 may comprise nitride (e.g., silicon nitride) or other suitable masking material.

Please refer to fig. 11 and 12. Fig. 11 is a schematic diagram of a high-voltage semiconductor device 102 according to a second embodiment of the invention, and fig. 12 is a partially enlarged schematic diagram of the high-voltage semiconductor device 102 according to the embodiment. As shown in fig. 11 and 12, in the high voltage semiconductor device 102, the first insulating structure BS1 and the second insulating structure BS2 may be formed by a portion of the insulating layer 56, so that the spacer structure SP1 and the spacer structure SP2 may sandwich the first insulating structure BS1 in the first direction D1, and the spacer structure SP1 and the spacer structure SP3 may sandwich the second insulating structure BS2 in the first direction D1. In some embodiments, the spacer structures SP1, SP2, SP3, BS1 and BS2 may be processed by a planarization process to have a substantially coplanar upper surface (e.g., an uppermost surface), but not limited thereto.

Please refer to fig. 11 to fig. 13. Fig. 13 is a schematic diagram of a method for fabricating a high voltage semiconductor device according to a second embodiment of the invention, and fig. 11 may be regarded as a schematic diagram illustrating a situation after fig. 13, but is not limited thereto. As shown in fig. 11 to 13, in some embodiments, the gate oxide layer 22G, the gate oxide layer 22A, and the gate oxide layer 22B may be separated from each other, the spacer structure SP1 may be disposed on the sidewalls of the dummy gate 24G and the gate oxide layer 22G, the spacer structure SP2 may be disposed on the sidewalls of the sub-dummy gate 24A and the gate oxide layer 22A, and the spacer structure SP2 may be disposed on the sidewalls of the sub-dummy gate 24B and the gate oxide layer 22B. In addition, during the silicide formation process 92, the second patterned mask layer 44 may cover the dummy gate 24G, the sub dummy gate 24A, the sub dummy gate 24B, the spacer structure SP1, the spacer structure SP2 and the first drift region 12A between the dummy gate 24G and the sub dummy gate 24A, and the spacer structure SP1, the spacer structure SP3 and the second drift region 12B between the dummy gate 24G and the sub dummy gate 24B. In some embodiments, the second patterned mask layer 44 may directly contact the first drift region 12A between the spacer structures SP1 and SP2 and the second drift region 12B between the spacer structures SP1 and SP 3.

In some embodiments, after the silicide fabrication process 92, the insulating layer 56 may be formed, thereby forming a first insulating structure BS1 between the spacer structure SP1 and the spacer structure SP2 and a second insulating structure BS2 between the spacer structure SP1 and the spacer structure SP 3. Then, the above-mentioned replacement gate manufacturing process may be performed to form the gate structure 60G, the sub-gate structure 60A and the sub-gate structure 60B. In other words, the first insulating structure BS1 and the second insulating structure BS2 may be formed after the silicide formation process 92 and before the replacement gate formation process. Furthermore, in some embodiments, the second patterned mask layer 44 may be completely removed after the silicide manufacturing process 92 or at least partially remain between the spacer structures SP1 and SP2 and between the spacer structures SP1 and SP3 to become the first insulating structure BS1 and the second insulating structure BS2.

Please refer to fig. 14. Fig. 14 is a schematic diagram of a high voltage semiconductor device 103 according to a third embodiment of the present invention. As shown in fig. 14, the high voltage semiconductor device 103 includes a semiconductor substrate 10, a first drift region 12A, a gate structure 60G, a spacer structure SP1, source/drain doped regions 52A, a silicide layer 54A, and a first insulating structure BS1. The first drift region 12A is disposed in the semiconductor substrate 10, the gate structure 60G is disposed on the semiconductor substrate 10, and the spacer structure SP1 is disposed on a sidewall of the gate structure 60G. The source/drain doped region 52A is disposed in the first drift region 12A, and the source/drain doped region 52A and the spacer structure SP1 are separated from each other. The silicide layer 54A is disposed on the source/drain doped region 52A, the silicide layer 54A is separated from the spacer structure SP1, and a portion of the first drift region 12A is located between the spacer structure SP1 and the source/drain doped region 52A. The first insulating structure BS1 is disposed on the first drift region 12A, and the first insulating structure BS1 is directly connected to the portion of the first drift region 12A between the spacer structure SP1 and the source/drain doped region 52A.

In some embodiments, the high voltage semiconductor device 103 may further include a second drift region 12B, a source/drain doped region 52B, a silicide layer 54B, and a second insulating structure BS2. The second drift region 12B is disposed in the semiconductor substrate 10, and a portion of the first drift region 12A and a portion of the second drift region 12B may be located at opposite sides of the gate structure 60G in the first direction D1, respectively. The source/drain doped region 52B may be disposed in the second drift region 12B, and the source/drain doped region 52B and the spacer structure SP1 are separated from each other. A silicide layer 54B may be disposed on the source/drain doped region 52B, the silicide layer 54B and the spacer structure SP1 being separated from each other, and a portion of the second drift region 12B being located between the spacer structure SP1 and the source/drain doped region 52B. A second insulating structure BS2 may be disposed on the second drift region 12B, and the second insulating structure BS2 is directly connected to the portion of the second drift region 12B between the spacer structure SP1 and the source/drain doped region 52B.

In some embodiments, the high voltage semiconductor device 103 may not have the sub-gate structure in the above embodiments, but the first drift region 12A between the source/drain doped region 52A and the spacer structure SP1 may directly contact the first insulating structure BS1 and be entirely covered by the first insulating structure BS1, and the second drift region 12B between the source/drain doped region 52B and the spacer structure SP1 may directly contact the second insulating structure BS2 and be entirely covered by the second insulating structure BS2. In some embodiments, the first insulating structure BS1 and the second insulating structure BS2 may be formed by the insulating layer 56, so that the first insulating structure BS1 may further cover the source/drain doped region 52A and the silicide layer 54A in the third direction D3, the second insulating structure BS2 may further cover the source/drain doped region 52B and the silicide layer 54B in the third direction D3, and the upper surfaces (e.g., uppermost surfaces) of the first insulating structure BS1, the second insulating structure BS2, the spacer structure SP1 and the gate structure 60G may be substantially coplanar, but are not limited thereto.

Please refer to fig. 14 and 15. Fig. 15 is a schematic diagram illustrating a method for fabricating a high voltage semiconductor device according to a third embodiment of the present invention, and fig. 14 may be regarded as a schematic diagram illustrating a situation after fig. 15. As shown in fig. 14 and 15, during the silicide formation process 92, the second patterned mask layer 44 may cover the dummy gate 24G, the spacer structure SP1, the first drift region 12A between the spacer structure SP1 and the source/drain doped region 52A, and the second drift region 12B between the spacer structure SP1 and the source/drain doped region 52B. In some embodiments, the second patterned mask layer 44 may directly contact the first drift region 12A and the second drift region 12B, but is not limited thereto. In some embodiments, the second patterned masking layer 44 may be removed entirely or remain at least partially on the first and second drift regions 12A and 12B after the silicide fabrication process 92 to become the first and second insulating structures BS1 and BS2. In addition, in the process of forming the source/drain doped regions 52A and 52B, another patterned mask layer (not shown) may be used to cover the dummy gate 24G, the spacer structure SP1, a portion of the first drift region 12A and a portion of the second drift region 12B, and the distance between the formed source/drain doped regions and the spacer structure SP1 may be adjusted by adjusting the condition that the patterned mask layer covers the first drift region 12A and the second drift region 12B. In other words, the electrical performance of the high voltage semiconductor device 103 may be improved (e.g., without limitation, reducing off-current) by increasing the distance between the source/drain doped regions and the spacer structure SP1 and avoiding forming a conductive silicide layer on the first drift region 12A between the spacer structure SP1 and the source/drain doped region 52A and on the second drift region 12B between the spacer structure SP1 and the source/drain doped region 52B.

In summary, in the high voltage semiconductor device and the method for manufacturing the same of the present invention, the insulation structure is used to connect with the drift region and avoid silicide formation on a specific portion of the drift region, thereby improving the electrical performance of the high voltage semiconductor device. In addition, in some embodiments, the structure for blocking silicide formation can be formed by using the related manufacturing process of the gate oxide layer, thereby achieving the effect of simplifying the manufacturing process or/and integrating the manufacturing process.

The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.

Claims

1. A high voltage semiconductor device comprising:

a semiconductor substrate;

a first drift region disposed in the semiconductor substrate;

a gate structure disposed on the semiconductor substrate;

a first sub-gate structure disposed on the first drift region and separated from the gate structure;

the first spacer structure is arranged on the side wall of the grid structure;

the second spacer structure is arranged on the side wall of the first sub-grid structure; and

the first insulation structure is arranged on the first drift region, wherein at least one part of the first insulation structure is positioned between the first spacer structure and the second spacer structure, the first part of the first drift region is positioned between the first spacer structure and the second spacer structure, and the first insulation structure is directly connected with the first part of the first drift region.

2. The high voltage semiconductor device of claim 1, further comprising:

a first gate oxide layer, wherein the first spacer structure and the first drift region sandwich a portion of the first gate oxide layer; and

and a second gate oxide layer, wherein the second spacer structure and the first drift region sandwich a portion of the second gate oxide layer, and the first gate oxide layer and the second gate oxide layer sandwich the first insulating structure.

3. The high voltage semiconductor device of claim 2, wherein said first insulating structure is directly connected to said first gate oxide layer and said second gate oxide layer.

4. The high voltage semiconductor device of claim 2, wherein a material composition of said first insulating structure, a material composition of said first gate oxide layer and a material composition of said second gate oxide layer are the same as each other.

5. The high voltage semiconductor device as recited in claim 2, wherein said first spacer structure and said second spacer structure sandwich said first insulating structure.

6. The high voltage semiconductor device of claim 1, wherein a second portion of said first drift region is vertically below said first spacer structure, a third portion of said first drift region is vertically below said second spacer structure, and said second portion and said third portion sandwich said first portion of said first drift region in a horizontal direction.

7. The high voltage semiconductor device of claim 1, further comprising:

the first source/drain doped region is disposed in the first drift region, wherein the first sub-gate structure is disposed between the gate structure and the first source/drain doped region, and the first sub-gate structure is electrically separated from the gate structure and the first source/drain doped region.

8. The high voltage semiconductor device of claim 1, further comprising:

a second drift region disposed in the semiconductor substrate, wherein a portion of the first drift region and a portion of the second drift region are respectively located at two opposite sides of the gate structure in a horizontal direction;

a second sub-gate structure disposed on the second drift region and separated from the gate structure;

the third gap wall structure is arranged on the side wall of the second sub-grid structure; and

and a second insulating structure disposed on the second drift region, wherein at least a portion of the second insulating structure is located between the first spacer structure and the third spacer structure, a portion of the second drift region is located between the first spacer structure and the third spacer structure, and the second insulating structure is directly connected to the portion of the second drift region.

9. The high voltage semiconductor device of claim 8, further comprising:

the second source/drain doped region is disposed in the second drift region, wherein the second sub-gate structure is disposed between the gate structure and the second source/drain doped region, and the second sub-gate structure is electrically separated from the gate structure and the second source/drain doped region.

10. A method of fabricating a high voltage semiconductor device, comprising:

forming a first drift region in a semiconductor substrate;

forming a gate structure on the semiconductor substrate; and

forming a first sub-gate structure on the first drift region, wherein the first sub-gate structure and the gate structure are separated from each other, a first spacer structure is located on a sidewall of the gate structure, a second spacer structure is located on a sidewall of the first sub-gate structure, a first insulating structure is located on the first drift region, and wherein at least a portion of the first insulating structure is located between the first spacer structure and the second spacer structure,

wherein a portion of the first drift region is located between the first spacer structure and the second spacer structure, and the first insulating structure is directly connected to the portion of the first drift region.

11. The method of claim 10, wherein forming said gate structure and said first sub-gate structure comprises:

forming a dummy gate and a sub-dummy gate on the semiconductor substrate, wherein the dummy gate and the sub-dummy gate are separated from each other;

forming the first spacer structure and the second spacer structure, wherein the first spacer structure is formed on the sidewall of the dummy gate and the second spacer structure is formed on the sidewall of the sub-dummy gate; and

and performing a gate replacement manufacturing process, wherein the gate structure replaces the dummy gate, and the first sub-gate structure replaces the sub-dummy gate.

12. The method for manufacturing a high-voltage semiconductor device according to claim 11, further comprising:

forming an oxide layer on the semiconductor substrate before forming the dummy gate and the sub-dummy gate, wherein the dummy gate and the sub-dummy gate are formed on the oxide layer; and

the oxide layer is patterned into a first gate oxide layer and a second gate oxide layer, the dummy gate and the first drift region sandwich at least a portion of the first gate oxide layer, and the sub-dummy gate and the first drift region sandwich at least a portion of the second gate oxide layer.

13. The method for manufacturing a high-voltage semiconductor device according to claim 12, further comprising:

before the patterning process, a first patterning mask layer is formed to cover the dummy gate, the sub dummy gate, and the oxide layer between the dummy gate and the sub dummy gate, wherein the patterning process includes an etching process using the first patterning mask layer as a mask to remove a portion of the oxide layer, and at least a portion of the oxide layer between the dummy gate and the sub dummy gate becomes the first insulating structure after the patterning process.

14. The method of claim 13, wherein the first patterned mask layer is a patterned photoresist layer.

15. The method of claim 12, wherein the first spacer structure and the second spacer structure are formed after the patterning process, the first spacer structure and the first drift region sandwich a portion of the first gate oxide layer, the second spacer structure and the first drift region sandwich a portion of the second gate oxide layer, the first gate oxide layer and the second gate oxide layer sandwich the first insulating structure, and the first insulating structure is directly connected to the first gate oxide layer and the second gate oxide layer.

16. The method for manufacturing a high-voltage semiconductor device according to claim 11, further comprising:

forming a source/drain doped region in the first drift region prior to the replacement gate fabrication process, wherein the sub-dummy gate is located between the dummy gate and the source/drain doped region; and

a silicide process is performed to form a silicide layer on the source/drain doped regions.

17. The method for manufacturing a high-voltage semiconductor device according to claim 16, further comprising:

a second patterned masking layer is formed over the semiconductor substrate prior to the silicide formation process, wherein the portion of the first drift region between the first spacer structure and the second spacer structure is covered by the second patterned masking layer during the silicide formation process.

18. The method of claim 17, wherein said first insulating structure is covered by said second patterned masking layer during said silicide formation process.

19. The method of claim 17, wherein said first insulating structure is formed between said first spacer structure and said second spacer structure after said silicide formation process and before said replacement gate formation process.

20. The method for manufacturing a high-voltage semiconductor device according to claim 10, further comprising:

forming a second drift region in the semiconductor substrate, wherein a part of the first drift region and a part of the second drift region are respectively positioned at two opposite sides of the gate structure in the horizontal direction; and

forming a second sub-gate structure on the second drift region, wherein the second sub-gate structure and the gate structure are separated from each other, a third spacer structure is located on a sidewall of the second sub-gate structure, a second insulating structure is located on the second drift region, and at least a portion of the second insulating structure is located between the first spacer structure and the third spacer structure, wherein a portion of the second drift region is located between the first spacer structure and the third spacer structure, and the second insulating structure is directly connected to the portion of the second drift region.

21. A high voltage semiconductor device comprising:

a semiconductor substrate;

a first drift region disposed in the semiconductor substrate;

a gate structure disposed on the semiconductor substrate;

the spacer structure is arranged on the side wall of the grid structure;

a first source/drain doped region disposed in the first drift region, wherein the first source/drain doped region is separated from the spacer structure;

A first silicide layer disposed on the first source/drain doped region, wherein the first silicide layer is separated from the spacer structure, and a portion of the first drift region is located between the spacer structure and the first source/drain doped region; and

and a first insulating structure disposed on the first drift region, wherein the first insulating structure is directly connected to the portion of the first drift region between the spacer structure and the first source/drain doped region.

22. The high voltage semiconductor device as recited in claim 21, wherein said first drift region between said spacer structure and said first source/drain doped region is entirely covered by said first insulating structure.

23. The high voltage semiconductor device as recited in claim 21, wherein said first insulating structure further covers said first source/drain doped region and said first silicide layer.

24. The high voltage semiconductor device of claim 21, further comprising:

a second source/drain doped region disposed in the second drift region, wherein the second source/drain doped region is separated from the spacer structure;

A second silicide layer disposed on the second source/drain doped region, wherein the second silicide layer is separated from the spacer structure, and a portion of the second drift region is located between the spacer structure and the second source/drain doped region; and

and a second insulating structure disposed on the second drift region, wherein the second insulating structure is directly connected to the portion of the second drift region between the spacer structure and the second source/drain doped region.

25. The high voltage semiconductor device of claim 24, wherein said second drift region between said spacer structure and said second source/drain doped region is entirely covered by said second insulating structure.

26. The high voltage semiconductor device as recited in claim 24, wherein said second insulating structure further covers said second source/drain doped region and said second silicide layer.