CN116860185B - Data access apparatus, system, method, device, chip and medium for SRAM array - Google Patents

Data access apparatus, system, method, device, chip and medium for SRAM array Download PDF

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Publication number
CN116860185B
CN116860185B CN202311133321.4A CN202311133321A CN116860185B CN 116860185 B CN116860185 B CN 116860185B CN 202311133321 A CN202311133321 A CN 202311133321A CN 116860185 B CN116860185 B CN 116860185B
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sram
group
bank
command
read command
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CN116860185A (en
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吕永志
范志军
寿建能
杨作兴
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Shenzhen MicroBT Electronics Technology Co Ltd
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Shenzhen MicroBT Electronics Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
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Abstract

The embodiment of the invention provides a data access device, a system, a method, equipment, a chip and a medium of an SRAM array. The device comprises: m arbitration modules corresponding to M SRAM groups; the analysis module is used for receiving N data access requests in parallel, analyzing a read command and/or a write command from each data access request, wherein the read command and/or the write command have respective target SRAM groups, and respectively sending the read command and/or the write command to the arbitration module corresponding to the respective target SRAMs; each arbitration module is used for sending the read command or the write command to the corresponding SRAM group when judging that the read command and the write command of the SRAM group taking the corresponding SRAM group as the target do not exist at the same time, so that the read command or the write command is executed by the SRAM group; wherein M is a positive integer greater than or equal to 2 and N is a positive integer greater than or equal to 1. And a plurality of SRAM groups are accessed in parallel, so that the access efficiency is improved, and the problem of access conflict is solved.

Description

Data access apparatus, system, method, device, chip and medium for SRAM array
Technical Field
The present invention relates to the field of data storage, and more particularly, to a data Access device, system, method, apparatus, chip, and medium for a Static Random-Access Memory (SRAM) array.
Background
SRAM is a common memory device in chip design. Limited to SRAM manufacturing processes, monolithic SRAM capacity is typically limited. A System On Chip (SOC) requires a large amount of space for an SRAM, and generally uses an SRAM array including a plurality of sets of SRAMs to realize large-space storage.
Currently, for SRAM arrays that include multiple sets of SRAMs, when one set of SRAMs in the SRAM array is accessed, the other SRAM sets are idle and inaccessible (unreadable and unwritable), resulting in low access efficiency.
Disclosure of Invention
The embodiment of the invention provides a data selection device, a storage system and a system-in-chip of an SRAM array.
The technical scheme of the embodiment of the invention is as follows:
a data access device for an SRAM array, the SRAM array comprising M SRAM banks, the device comprising:
M arbitration modules corresponding to the M SRAM groups;
The analysis module is used for receiving N data access requests in parallel, analyzing a read command and/or a write command from each data access request, wherein the read command and/or the write command are provided with respective target SRAM groups, and respectively sending the read command and/or the write command to an arbitration module corresponding to the respective target SRAM groups;
Each of the M arbitration modules is configured to send a read command of the corresponding SRAM bank or a write command of the corresponding SRAM bank to the corresponding SRAM bank when it is determined that there are not a read command of the corresponding SRAM bank and a write command of the corresponding SRAM bank, so that the read command of the corresponding SRAM bank or the write command of the corresponding SRAM bank is executed by the corresponding SRAM bank.
Wherein M is a positive integer greater than or equal to 2 and N is a positive integer greater than or equal to 1.
In one embodiment, each arbitration module is configured to, when it is determined that there is a read command of the corresponding SRAM bank and a write command of the corresponding SRAM bank, perform arbitration on the read command of the corresponding SRAM bank and the write command of the corresponding SRAM bank based on a predetermined arbitration policy, and send the read command of the corresponding SRAM bank or the write command of the corresponding SRAM bank determined based on the arbitration result to the corresponding SRAM bank, and execute the read command of the corresponding SRAM bank or the write command of the corresponding SRAM bank based on the corresponding SRAM bank.
In one embodiment, the arbitration policy includes at least one of the following:
Polling an execution strategy;
Read command priority policy;
Write command priority policy;
Time sharing strategy.
In one embodiment, the parsing module is configured to receive the N data access requests in parallel from a full duplex data transmission bus; wherein the full duplex data transfer bus comprises at least one of:
Advanced extensible interface protocol (AXI) -simplified version (Lite); AXI-Full version (Full); AXI-data Stream version (Stream).
In one embodiment of the present invention, in one embodiment,
The read command comprises a first group of selection signals and a read control instruction, wherein the first group of selection signals are used for selecting a corresponding SRAM group in a read operation, and the read control instruction is used for reading data in the corresponding SRAM group;
The write command comprises a second group selection signal and a write control instruction, wherein the second group selection signal is used for selecting a corresponding SRAM group in a write operation, and the write control instruction is used for writing data in the corresponding SRAM group;
The arbitration module comprises:
A read command group select signal input for receiving the first group select signal;
the read control instruction input end is used for receiving the read control instruction;
an arbitration policy input for receiving an arbitration policy selection signal;
a write command group select signal input for receiving the second group select signal;
The write control instruction input end is used for receiving the write control instruction;
the command output end is used for sending a read control instruction or a write control instruction to the corresponding SRAM group;
the read state indication signal output end is used for outputting a read state indication signal to the corresponding SRAM group;
And the write state indication signal output end is used for outputting a write state indication signal to the corresponding SRAM group.
A data access system for an SRAM array, comprising:
An SRAM array comprising a plurality of SRAM banks, each SRAM bank comprising a plurality of SRAMs;
M arbitration modules corresponding to the M SRAM groups;
The analysis module is used for receiving N data access requests in parallel, analyzing a read command and/or a write command from each data access request, wherein the read command and/or the write command are provided with respective target SRAM groups, and respectively sending the read command and/or the write command to an arbitration module corresponding to the respective target SRAM groups;
Each of the M arbitration modules is configured to send a read command of the corresponding SRAM bank or a write command of the corresponding SRAM bank to the corresponding SRAM bank when it is determined that there are not a read command of the corresponding SRAM bank and a write command of the corresponding SRAM bank, so that the read command of the corresponding SRAM bank or the write command of the corresponding SRAM bank is executed by the corresponding SRAM bank.
Wherein M is a positive integer greater than or equal to 2 and N is a positive integer greater than or equal to 1.
In one embodiment, each arbitration module is configured to, when it is determined that there is a read command of the corresponding SRAM bank and a write command of the corresponding SRAM bank, perform arbitration on the read command of the corresponding SRAM bank and the write command of the corresponding SRAM bank based on a predetermined arbitration policy, and send the read command of the corresponding SRAM bank or the write command of the corresponding SRAM bank determined based on the arbitration result to the corresponding SRAM bank, and execute the read command of the corresponding SRAM bank or the write command of the corresponding SRAM bank based on the corresponding SRAM bank.
A system-in-chip comprising a data access device of an SRAM array as claimed in any one of the preceding claims or a data access system of an SRAM array as claimed in any one of the preceding claims.
A method of data access for an SRAM array, the SRAM array comprising M SRAM banks, the method comprising:
Receiving N data access requests;
Parsing a read command and/or a write command from each data access request, wherein the read command and/or the write command has a respective destination SRAM bank;
Performing arbitration processing for a read command and/or a write command of an SRAM group for each same SRAM, respectively, wherein: when it is determined that the read command of the same SRAM group as the target SRAM group and the write command of the same SRAM group as the target SRAM group do not exist at the same time, the read command of the same SRAM group as the target SRAM group or the write command of the same SRAM group as the target SRAM group is sent to the same SRAM group, and the read command of the same SRAM group as the target SRAM group or the write command of the same SRAM group as the target SRAM group is executed by the same SRAM group.
In one embodiment, the performing arbitration process includes:
When it is determined that the read command of the same SRAM group as the target SRAM group and the write command of the same SRAM group as the target SRAM group exist at the same time, performing arbitration on the read command of the same SRAM group as the target SRAM group and the write command of the same SRAM group as the target SRAM group based on a predetermined arbitration policy;
And transmitting the read command of the same SRAM group or the write command of the same SRAM group, which is determined based on the arbitration result and is used for the purpose of the same SRAM group, to the same SRAM group, so that the read command of the same SRAM group or the write command of the same SRAM group, which is used for the purpose of the same SRAM group, is executed by the same SRAM group.
An electronic device, comprising:
a memory;
A processor;
Wherein the memory has stored therein an application executable by the processor for causing the processor to perform the method of data access of an SRAM array as claimed in any one of the preceding claims.
A computer readable storage medium having stored thereon computer readable instructions which, when executed by a processor, cause the processor to perform a method of data access of an SRAM array of any one of the preceding claims.
According to the technical scheme, in the embodiment of the invention, a plurality of data access requests are received in parallel, each data access request is analyzed to respectively send a read command and/or a write command to an arbitration module corresponding to each target SRAM group, parallel processing of the plurality of data access requests is realized, a plurality of SRAM groups can be accessed in parallel, the access efficiency of the SRAM array is improved, and the conflict problem that the read command and the write command access the same SRAM group simultaneously can be solved based on the arbitration module.
Drawings
FIG. 1 is a schematic diagram of a prior art access SRAM array.
Fig. 2 is an exemplary block diagram of a data access device of an SRAM array of an embodiment of the present invention.
Fig. 3 is an exemplary block diagram of input/output ports of an arbitration module according to an embodiment of the present invention.
Fig. 4 is an exemplary block diagram of a data access method of an SRAM array according to an embodiment of the present invention.
Fig. 5 is an exemplary structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
For simplicity and clarity of description, the following description sets forth aspects of the invention by describing several exemplary embodiments. Numerous details in the embodiments are provided solely to aid in the understanding of the invention. It will be apparent, however, that the embodiments of the invention may be practiced without limitation to these specific details. Some embodiments are not described in detail in order to avoid unnecessarily obscuring aspects of the present invention, but rather only to present a framework. Hereinafter, "comprising" means "including but not limited to", "according to … …" means "according to at least … …, but not limited to only … …". The term "a" or "an" is used herein to refer to a number of components, either one or more, or at least one, unless otherwise specified.
FIG. 1 is a schematic diagram of a prior art access SRAM array. SRAM arrays typically comprise a plurality of SRAM banks, each SRAM bank comprising a plurality of SRAMs. The SRAM array shown in fig. 1 includes M SRAM banks, namely SRAM bank 1, SRAM bank 2, SRAM bank 3 … …, and SRAM bank M. Each SRAM group contains p SRAMs. Thus, the SRAM array contains m×p SRAMs in total.
Currently, SRAM groups are the direct access object of data access requests in technical practice. At the same time, the SRAM array can only handle one data access request (the data access request contains a read command or a write command, but cannot contain both a read command and a write command) and based on the one data access request, access one SRAM bank in the SRAM array, while the other SRAM banks cannot be accessed simultaneously.
For example, assuming that a data access party (e.g., a host) needs to read data from SRAM bank 1 in the SRAM array, the data access party sends a read command to the SRAM array with SRAM bank 1 as a destination address. In response to the command, the SRAM array returns the data in SRAM bank 1 to the data access party. However, when data access requires simultaneous (i.e., parallel) reading of data from SRAM bank 1 and writing of data to SRAM bank 2 in an SRAM array, this is not possible based on prior art techniques.
To solve the above problems, the applicant considered to send a read command addressed to SRAM bank 1 and a write command addressed to SRAM bank 2 in parallel to the SRAM array. However, the applicant further found that: because the SRAM array has no corresponding mechanism for cooperatively processing a plurality of parallel data access requests, the solution idea of simply sending the plurality of data access requests to the SRAM array in parallel cannot realize parallel access to a plurality of SRAM groups.
The embodiment of the invention provides a data access technical scheme of an SRAM array, a plurality of data access requests are received, each data access request is analyzed to respectively send a read command and/or a write command to an arbitration module corresponding to each target SRAM group, parallel processing of the plurality of data access requests is realized, a plurality of SRAM groups are accessed in parallel, and the access efficiency of the SRAM array is improved.
Fig. 2 is an exemplary block diagram of a data access device of an SRAM array of an embodiment of the present invention. The SRAM array shown in fig. 2 includes M SRAM banks, namely SRAM bank 1, SRAM bank 2, SRAM bank 3 … …, SRAM bank M. Each SRAM group contains p SRAMs. Thus, the SRAM array contains m×p SRAMs in total. The data access device includes:
M arbitration modules corresponding to the M SRAM groups, wherein each arbitration module is coupled with the corresponding SRAM group;
And the analysis module is connected with the M arbitration modules and is used for receiving N data access requests in parallel, analyzing a read command and/or a write command from each data access request, wherein the read command and/or the write command has a respective target SRAM group, and respectively sending the read command and/or the write command in each data access request to the arbitration module corresponding to the respective target SRAM group.
Each of the M arbitration modules is configured to send a read command of the corresponding SRAM bank or a write command of the corresponding SRAM bank to the corresponding SRAM bank when it is determined that there are not a read command of the corresponding SRAM bank and a write command of the corresponding SRAM bank, and execute the read command of the corresponding SRAM bank or the write command of the corresponding SRAM bank by the corresponding SRAM bank; wherein M is a positive integer greater than or equal to 2 and N is a positive integer greater than or equal to 1.
In an alternative embodiment, the M arbitration modules may be integrated into a single overall arbitration unit corresponding to the M SRAM banks to handle access arbitration processing of the M SRAM banks in its entirety. In another alternative embodiment, a portion of the M arbitration modules may be integrated into one or more (the specific number may depend on the specific integration policy) arbitration units, while the remaining portion of the arbitration modules remain functionally independent, with the integrated one or more arbitration units collectively processing access arbitration processing for SRAM banks corresponding to the one or more arbitration units while the remaining portion of the arbitration modules continue to independently processing access arbitration processing for SRAM banks corresponding to the remaining portion of the arbitration modules.
Therefore, parallel processing of a plurality of data access requests is realized, a plurality of SRAM groups can be accessed in parallel, and the access efficiency of the SRAM array is improved.
In one embodiment, the parsing module may receive N data access requests in parallel from the full duplex data transfer bus; wherein the full duplex data transfer bus comprises at least one of: AXI-Lite; AXI-Full; AXI-Stream. Wherein: both AXI-Lite and AXI-Full are based on memory mapped form to implement data transfer (i.e. include address bus), while AXI-Stream is in form of data Stream to implement transfer without address bus. AXI-Lite is a simplified version of AXI-Full, is suitable for small-batch data transmission, and is commonly used for transmitting commands; AXI-Full is suitable for large-scale and high-performance data transmission.
While the above exemplary description of a typical example of a full duplex data transfer bus, those skilled in the art will recognize that this description is exemplary only and is not intended to limit embodiments of the present invention.
In one embodiment, each data access request may include a write command and a read command at the same time, where the SRAM set for the write command and the SRAM set for the read command may be the same or different.
Example 1: the data access request 1 in fig. 2 may contain both a write command and a read command, wherein the destination SRAM bank of the write command is SRAM bank 1 and the destination SRAM bank of the read command is SRAM bank 2. That is, data access request 1 indicates that a write operation is initiated for SRAM bank 1 and a read operation is initiated for SRAM bank 2.
Example 2: the data access request 1 in fig. 2 contains both a write command and a read command, wherein the destination SRAM bank of the write command is SRAM bank 1 and the destination SRAM bank of the read command is SRAM bank 1. That is, the data access request 1 indicates that a write operation is initiated for SRAM bank 1 and a read operation is initiated for SRAM bank 1. In this case, having both read and write commands for the same SRAM bank typically results in a conflict problem that can be resolved by the arbitration mechanism of the arbitration module described in detail below.
In one embodiment, only one of the write command and the read command may be included in the data access request.
Example 1: the data access request 2 in fig. 2 contains only a write command, wherein the destination SRAM bank of the write command is SRAM bank 1. That is, the data access request 2 indicates that a write operation is initiated for the SRAM bank 1.
Example 2: the data access request 2 in fig. 2 contains only a read command, wherein the destination SRAM bank of the read command is SRAM bank 2. That is, the data access request 2 indicates that a read operation is initiated for SRAM bank 2.
The analysis module analyzes the read command and/or the write command in each data access request from the N data access requests, and sends all the analyzed read commands and/or all the analyzed write commands to the arbitration module corresponding to each target SRAM group.
Examples: it is assumed that the total number of data access requests received by the parsing module is 4, namely, a data access request 1, a data access request 2, a data access request 3 and a data access request 4.
The data access request 1 contains: (1) a write command 1 of an SRAM bank with the SRAM bank 1 as a target; (2) read command 1 of the SRAM group with the SRAM group 2 as the target.
The data access request 2 contains: (1) write command 2 of the SRAM bank targeted for SRAM bank 3.
The data access request 3 contains: (1) a write command 3 of the SRAM bank with the SRAM bank 4 as a destination; (2) read command 2 of the SRAM bank with the SRAM bank 5 as a target.
The data access request 4 contains: (1) a write command 4 of the SRAM bank with the SRAM bank 6 as a destination; (2) a read command 3 of the SRAM bank with the SRAM bank 7 as a target.
The parsing module sends a write command 1 (the SRAM group with the SRAM group 1 as a target) to the arbitration module 1 corresponding to the SRAM group 1; transmitting a read command 1 (SRAM bank with the SRAM bank 2 as a target) to the arbitration module 2 corresponding to the SRAM bank 2; sending a write command 2 (SRAM bank with SRAM bank 3 as a destination) to an arbitration module 3 corresponding to SRAM bank 3; sending a write command 3 (SRAM bank for the purpose of SRAM bank 4) to the arbitration module 4 corresponding to SRAM bank 4; sending the read command 2 (SRAM bank with the SRAM bank 5 as a destination) to the arbitration module 5 corresponding to the SRAM bank 5; sending the write command 4 (SRAM bank with the SRAM bank 6 as a destination) to the arbitration module 6 corresponding to the SRAM bank 6; the read command 3 (SRAM bank for the purpose of SRAM bank 7) is sent to the arbitration module 7 corresponding to SRAM bank 7.
Each of the arbitration modules 1 to 7 determines that a write command and a read command do not exist in itself at the same time, and thus can send the respective write command or read command to the respective corresponding SRAM group, respectively, to execute the commands in parallel by the SRAM group. Specifically: SRAM group 1 executes write command 1; SRAM group 2 executes read command 1; SRAM bank 3 executes write command 2; the SRAM bank 4 executes the write command 3; SRAM bank 5 executes read command 2; the SRAM bank 6 executes the write command 4; SRAM bank 7 executes read command 3, thereby enabling parallel access to 7 SRAM banks in the SRAM array.
The above describes an exemplary example in which the arbitration module does not receive both read and write commands from the parsing module. In practice, based on the specific configuration of the data access request, the arbitration module may also receive the read command and the write command from the parsing module at the same time, i.e. there is a read-write collision problem.
In one embodiment, each arbitration module is configured to, when it is determined that there is a read command of the corresponding SRAM bank as a destination SRAM bank and a write command of the corresponding SRAM bank as a destination SRAM bank at the same time, perform arbitration on the read command of the corresponding SRAM bank as a destination SRAM bank and the write command of the corresponding SRAM bank based on a predetermined arbitration policy, and send the read command of the corresponding SRAM bank as a destination SRAM bank or the write command of the corresponding SRAM bank determined based on the arbitration result to the corresponding SRAM bank to execute the read command of the corresponding SRAM bank as a destination SRAM bank or the write command of the corresponding SRAM bank as a destination SRAM bank.
When the arbitration module receives both a read command and a write command from the parsing module, a particular priority-executing command may be selected based on a predetermined arbitration policy. Therefore, the embodiment of the invention can execute arbitration based on the arbitration module, and solves the conflict problem that the read command and the write command access the same SRAM group at the same time.
Typically, the arbitration policy employed in each arbitration module is the same in order to ensure logical consistency. However, the arbitration policies employed in the various arbitration modules may also be different.
Preferably, the arbitration policy comprises:
(1) Polling an execution strategy;
(2) Read command priority policy;
(3) Write command priority policy;
(4) Time sharing strategy.
In the poll execution policy, the read command and the write command are polled for execution. In the read command priority policy, the read command is preferentially executed. In the write command priority policy, the write command is preferentially executed. In the time sharing strategy, corresponding commands are processed based on time periods. Such as: the initial period of time processes only read commands, while the next period of time processes write commands; or the start time period processes only write commands and the next time period processes read commands, etc.
The foregoing exemplary description describes typical examples of arbitration strategies, and those skilled in the art will recognize that such descriptions are merely exemplary and are not intended to limit the scope of embodiments of the present invention.
Examples: it is assumed that the total number of data access requests received by the parsing module is 4, namely, a data access request 1, a data access request 2, a data access request 3 and a data access request 4.
The data access request 1 contains: (1) a write command 1 of an SRAM bank with the SRAM bank 1 as a target; (2) read command 1 of the SRAM group with the SRAM group 2 as the target.
The data access request 2 contains: (1) a read command 2 of the SRAM bank with the SRAM bank 1 as a target.
The data access request 3 contains: (1) a write command 2 of the SRAM bank with the SRAM bank 4 as a destination; (2) read command 3 of the SRAM bank with the SRAM bank 5 as a target.
The data access request 4 contains: (1) a write command 3 of the SRAM bank with the SRAM bank 6 as a destination; (2) a read command 4 of the SRAM bank with the SRAM bank 7 as a target.
The analysis module sends a write command 1 and a read command 2 (both of which take the SRAM group 1 as a target SRAM group) to an arbitration module 1 corresponding to the SRAM group 1; transmitting a read command 1 (SRAM bank with the SRAM bank 2 as a target) to the arbitration module 2 corresponding to the SRAM bank 2; sending the write command 2 (SRAM bank with the SRAM bank 4 as a destination) to the arbitration module 4 corresponding to the SRAM bank 4; sending a read command 3 (SRAM bank for the purpose of SRAM bank 5) to the arbitration module 5 corresponding to SRAM bank 5; sending the write command 3 (SRAM bank with the SRAM bank 6 as a destination) to the arbitration module 6 corresponding to the SRAM bank 6; the read command 4 (SRAM bank for the purpose of SRAM bank 7) is sent to the arbitration module 7 corresponding to SRAM bank 7.
The arbitration module 2, the arbitration module 4, the arbitration module 5, the arbitration module 6 and the arbitration module 7 all determine that the write command and the read command do not exist at the same time, so that the respective write command or read command can be executed, and thus the respective 5 corresponding SRAM groups in the SRAM array are accessed in parallel.
The arbitration module 1 determines that a write command and a read command (write command 1 and read command 2) exist at the same time, performs arbitration based on a predetermined arbitration policy (assumed to be a read command priority policy), and the arbitration result is: the read command 2 is executed first to read data from the SRAM bank 1, and after the read command 2 is executed, the write command 1 is executed again to write data into the SRAM bank 1. Therefore, the arbitration module 1 sends the read command 2 to the SRAM bank 1 to read data from the SRAM bank 1, and then the arbitration module 1 sends the write command 1 to the SRAM bank 1 to write data to the SRAM bank 1.
In one embodiment, the read command includes a first set of select signals and read control instructions. The first group selection signal is used for selecting a corresponding SRAM group in a read operation, and the read control instruction is used for reading data in the corresponding SRAM group. For example, the read control instructions may include: (1) An SRAM chip select enable signal in the SRAM group for selecting an SRAM from the SRAM group; (2) an SRAM read enable signal for enabling a read operation of the SRAM; (3) read addresses in SRAM.
In one embodiment, the write command includes a second set of select signals and write control instructions. The second group selection signal is used for selecting a corresponding SRAM group in a write operation, and the write control instruction is used for writing data in the corresponding SRAM group. For example, the write control instructions may include: (1) An SRAM chip select enable signal in the SRAM group for selecting an SRAM from the SRAM group; (2) an SRAM write enable signal for enabling a write operation of the SRAM; (3) write address in SRAM.
Based on the specific command types, the embodiment of the invention also provides an input/output port structure of the arbitration module.
Fig. 3 is an exemplary block diagram of input/output ports of an arbitration module according to an embodiment of the present invention.
As shown in fig. 3, the input/output ports of the arbitration module include: a read command group select signal input for receiving a first group select signal; the read control instruction input end is used for receiving a read control instruction; an arbitration policy input for receiving an arbitration policy selection signal; a write command group select signal input for receiving a second group select signal; the write control instruction input end is used for receiving a write control instruction; the command output end is used for sending a read control instruction or a write control instruction to the corresponding SRAM group; the read state indication signal output end is used for outputting a read state indication signal to the corresponding SRAM group; and the write state indication signal output end is used for outputting a write state indication signal to the corresponding SRAM group. Wherein: the read status indication signal is used for indicating whether the SRAM group is in a readable state, for example, when the read status indication signal is at a high level, the SRAM group is indicated to be in a readable state; the write state indication signal is used to indicate whether the SRAM bank is in a writable state, for example, when the write state indication signal is at a high level, the SRAM bank is in the writable state.
The data access device and the data access system of the SRAM array described above may be applied to a system-on-chip. The embodiment of the invention also provides a system-on-chip comprising the data access system as claimed in any one of the above or the data access device of the SRAM array as claimed in any one of the above.
Fig. 4 is an exemplary block diagram of a data access method of an SRAM array according to an embodiment of the present invention. As shown in fig. 4, the method includes:
step 401: n data access requests are received.
Step 402: a read command and/or a write command is parsed from each data access request, wherein the read command and/or the write command has a respective SRAM bank of interest.
Step 403: performing arbitration processing for a read command and/or a write command of an SRAM group for each same SRAM, respectively, wherein: when it is determined that the read command of the same SRAM group as the destination SRAM group and the write command of the same SRAM group as the destination SRAM group do not exist at the same time, the read command of the same SRAM group as the destination SRAM group or the write command of the same SRAM group as the destination SRAM group is transmitted to the same SRAM group, and the read command of the same SRAM group as the destination SRAM group or the write command of the same SRAM group as the destination SRAM group is executed by the same SRAM group.
In one embodiment, performing the arbitration process includes:
When it is determined that there are a read command of the same SRAM group as a target SRAM group and a write command of the same SRAM group as a target SRAM group at the same time, performing arbitration on the read command of the same SRAM group as a target SRAM group and the write command of the same SRAM group as a target SRAM group based on a predetermined arbitration policy;
And transmitting the read command of the same SRAM group or the write command of the same SRAM group, which is determined based on the arbitration result and is used as a target SRAM group, to the same SRAM group so as to execute the read command of the same SRAM group or the write command of the same SRAM group, which is used as a target SRAM group, by the same SRAM group.
Fig. 5 is an exemplary structural diagram of an electronic device according to an embodiment of the present invention. The electronic device 500 includes: a processor 501 and a memory 502. Processor 501 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 501 may be implemented in at least one hardware form of digital signal Processing (DIGITAL SIGNAL Processing, DSP), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 501 may also include a main processor and a coprocessor, where the main processor is a processor for processing data in an awake state, and is also called a central processor (Central Processing Unit, CPU); a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 501 may be integrated with an image processor (Graphics Processing Unit, GPU) for use in connection with rendering and rendering of content to be displayed by the display screen. In some implementations, the processor 501 may also include an AI processor for processing computing operations related to machine learning. For example, the AI processor may be implemented as a neural network processor.
Memory 502 may include one or more computer-readable storage media, which may be non-transitory. Memory 502 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices.
In some embodiments, a non-transitory computer readable storage medium in memory 502 is used to store at least one instruction for execution by processor 501 to implement the data access method of the SRAM array provided by various embodiments in the present disclosure.
The foregoing is merely a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A data access apparatus for an SRAM array, the SRAM array comprising M SRAM banks, the apparatus comprising:
m arbitration modules corresponding to the M SRAM groups, each SRAM group respectively comprising a plurality of SRAMs;
The analysis module is used for receiving N data access requests in parallel, analyzing a read command and/or a write command from each data access request, wherein the read command and/or the write command are provided with respective target SRAM groups, and respectively sending the read command and/or the write command to an arbitration module corresponding to the respective target SRAM groups;
Each of the M arbitration modules is configured to send a read command of the corresponding SRAM bank or a write command of the corresponding SRAM bank to the corresponding SRAM bank when it is determined that there are not a read command of the corresponding SRAM bank and a write command of the corresponding SRAM bank, so that the read command of the corresponding SRAM bank or the write command of the corresponding SRAM bank is executed by the corresponding SRAM bank.
Wherein M is a positive integer greater than or equal to 2, and N is a positive integer greater than or equal to 1;
Each arbitration module is configured to, when it is determined that there are a read command of a corresponding SRAM bank and a write command of a corresponding SRAM bank at the same time, perform arbitration on the read command of the corresponding SRAM bank and the write command of the corresponding SRAM bank based on a predetermined arbitration policy, send a read command of the corresponding SRAM bank or a write command of the corresponding SRAM bank determined based on an arbitration result to the corresponding SRAM bank, and execute the read command of the corresponding SRAM bank or the write command of the corresponding SRAM bank based on the corresponding SRAM bank;
Wherein the arbitration policies employed by the M arbitration modules are the same.
2. The apparatus of claim 1, wherein the arbitration policy comprises at least one of:
Polling an execution strategy;
Read command priority policy;
Write command priority policy;
Time sharing strategy.
3. The apparatus of claim 1, wherein the device comprises a plurality of sensors,
The analysis module is used for receiving the N data access requests in parallel from the full duplex data transmission bus; wherein the full duplex data transfer bus comprises at least one of:
Advanced extensible interface protocol-simplified version; advanced extensible interface protocol-full version; advanced extensible interface protocol-data stream version.
4. The device according to any one of claims 1 to 3, wherein,
The read command comprises a first group of selection signals and a read control instruction, wherein the first group of selection signals are used for selecting a corresponding SRAM group in a read operation, and the read control instruction is used for reading data in the corresponding SRAM group;
The write command comprises a second group selection signal and a write control instruction, wherein the second group selection signal is used for selecting a corresponding SRAM group in a write operation, and the write control instruction is used for writing data in the corresponding SRAM group;
The arbitration module comprises:
A read command group select signal input for receiving the first group select signal;
the read control instruction input end is used for receiving the read control instruction;
an arbitration policy input for receiving an arbitration policy selection signal;
a write command group select signal input for receiving the second group select signal;
The write control instruction input end is used for receiving the write control instruction;
the command output end is used for sending a read control instruction or a write control instruction to the corresponding SRAM group;
the read state indication signal output end is used for outputting a read state indication signal to the corresponding SRAM group;
And the write state indication signal output end is used for outputting a write state indication signal to the corresponding SRAM group.
5. A data access system for an SRAM array, comprising:
An SRAM array comprising M SRAM banks, each SRAM bank comprising a plurality of SRAMs;
M arbitration modules corresponding to the M SRAM groups;
The analysis module is used for receiving N data access requests in parallel, analyzing a read command and/or a write command from each data access request, wherein the read command and/or the write command are provided with respective target SRAM groups, and respectively sending the read command and/or the write command to an arbitration module corresponding to the respective target SRAM groups;
Each of the M arbitration modules is configured to send a read command of the corresponding SRAM bank or a write command of the corresponding SRAM bank to the corresponding SRAM bank when it is determined that there are not a read command of the corresponding SRAM bank and a write command of the corresponding SRAM bank, so that the read command of the corresponding SRAM bank or the write command of the corresponding SRAM bank is executed by the corresponding SRAM bank.
Wherein M is a positive integer greater than or equal to 2, and N is a positive integer greater than or equal to 1;
Each arbitration module is configured to, when it is determined that there are a read command of a corresponding SRAM bank and a write command of a corresponding SRAM bank at the same time, perform arbitration on the read command of the corresponding SRAM bank and the write command of the corresponding SRAM bank based on a predetermined arbitration policy, send a read command of the corresponding SRAM bank or a write command of the corresponding SRAM bank determined based on an arbitration result to the corresponding SRAM bank, and execute the read command of the corresponding SRAM bank or the write command of the corresponding SRAM bank based on the corresponding SRAM bank;
Wherein the arbitration policies employed by the M arbitration modules are the same.
6. A system-on-chip comprising the data access device of the SRAM array of any one of claims 1-4 or the data access system of the SRAM array of claim 5.
7. A method of data access for an SRAM array, the SRAM array comprising M SRAM banks, each SRAM bank comprising a plurality of SRAMs, respectively, the method comprising:
Receiving N data access requests;
Parsing a read command and/or a write command from each data access request, wherein the read command and/or the write command has a respective destination SRAM bank;
And respectively executing arbitration processing for a read command and/or a write command of the SRAM group with each same SRAM group as a target, wherein: when it is determined that the read command of the same SRAM group and the write command of the same SRAM group do not exist at the same time, sending the read command of the same SRAM group or the write command of the same SRAM group to the same SRAM group, and executing the read command of the same SRAM group or the write command of the same SRAM group by the same SRAM group; when it is determined that the read command of the same SRAM group as the target SRAM group and the write command of the same SRAM group as the target SRAM group exist at the same time, performing arbitration on the read command of the same SRAM group as the target SRAM group and the write command of the same SRAM group as the target SRAM group based on a predetermined arbitration policy; transmitting a read command of the same SRAM group or a write command of the same SRAM group, which is determined based on the arbitration result and is used as a target SRAM group, to the same SRAM group, so that the same SRAM group executes the read command of the same SRAM group or the write command of the same SRAM group;
wherein the arbitration policy employed by the M SRAM banks is the same.
8. An electronic device, comprising:
a memory;
A processor;
Wherein the memory has stored therein an application executable by the processor for causing the processor to perform the method of data access of the SRAM array of claim 7.
9. A computer readable storage medium having stored thereon computer readable instructions which, when executed by a processor, cause the processor to perform the method of data access of an SRAM array of claim 7.
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