CN116848730A

CN116848730A - Antenna device and camera system

Info

Publication number: CN116848730A
Application number: CN202180092910.5A
Authority: CN
Inventors: 乡田达人; 小山泰史; 海部纪之
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 2021-02-03
Filing date: 2021-12-22
Publication date: 2023-10-03

Abstract

The antenna device of the present disclosure includes: an antenna array in which a plurality of antennas are arranged, each antenna including a negative differential resistance element and a resonance circuit; a voltage bias circuit that applies a voltage to the antenna array; a first shunt element connected between the antenna array and the voltage bias circuit in parallel relation to each of the negative differential resistance element and the voltage bias circuit, and in which a first resistor and a first capacitor of the first shunt element are connected in series; and a second shunt element connected between the first shunt element and the voltage bias circuit in parallel relation to each of the negative differential resistance element and the voltage bias circuit, and in the second shunt element, a second resistor and a second capacitor of the second shunt element are connected in series, wherein each of the first shunt element and the second shunt element has a low impedance with respect to a resistance value of the negative differential resistance element serving as a reference.

Description

Antenna device and camera system

Technical Field

The present disclosure relates to an antenna device that transmits or receives electromagnetic waves and to a camera system.

Background

An antenna including a negative differential resistance element and a resonance circuit may generate electromagnetic waves (hereinafter simply referred to as "terahertz waves") including at least a portion of a frequency band from millimeter waves to terahertz waves (at least 30GHz and not more than 30 THz). For example, PTL 1 discloses an antenna having negative differential resistance elements and resonance circuits each integrated in a semiconductor chip to generate terahertz waves.

In PTL 1, as a negative differential resistance element, a Resonant Tunneling Diode (RTD) is used, and a power supply that supplies a bias voltage to the negative differential resistance element is included. A bias voltage from a power supply is supplied to the negative resistance element via a bias supply unit including wiring and a conductor. Parasitic low-frequency oscillations (parasitic oscillations) other than terahertz waves generated from the antenna are often generated by the structure accompanying the bias supply unit. Accordingly, PTL 1 discloses a technique of placing a shunt (shunt) element in a bias supply unit and thereby suppressing parasitic oscillation.

CITATION LIST

Patent literature

[ PTL 1] Japanese patent application laid-open No.2015-180049

Disclosure of Invention

Technical problem

As means for enhancing the antenna output, there is a method of arranging a plurality of antennas each including a negative differential resistance element and a resonance circuit to provide an antenna array. In the case of mounting a chip integrated with such an antenna array on another substrate such as a ceramic package or a printed substrate, the chip and the substrate are connected using bonding wires, and a shunt element for suppressing parasitic oscillation is placed on the substrate.

Each of the bonding wire and the resistor and the capacitor each included in the shunt element has parasitic inductance. The parasitic inductance cannot be ignored in terms of normally generating the terahertz wave, and causes parasitic oscillation at a frequency (less than 30 GHz) lower than that of the terahertz wave. Parasitic oscillations may occur due to parasitic inductance, especially at 10MHz to 10 GHz. In such an antenna array, in order to cause terahertz waves to oscillate normally, it is necessary to optimize the circuit parameters and placement of the shunt element on the substrate, but in PTL 1, sufficient inspection has not been performed.

Accordingly, it is an object of the present disclosure to provide a technique of suppressing parasitic oscillation in an antenna apparatus having an antenna array including a negative differential resistance element and a resonance circuit.

Solution to the problem

For the above purpose, an antenna device of the present disclosure includes an antenna device that transmits or receives electromagnetic waves, the antenna device including: an antenna array in which a plurality of antennas are arranged, each antenna including a negative differential resistance element and a resonance circuit; a voltage bias circuit that applies a voltage to the antenna array; a first shunt element connected between the antenna array and the voltage bias circuit in parallel relation to each of the negative differential resistance element and the voltage bias circuit, and in which a first resistor and a first capacitor of the first shunt element are connected in series; and a second shunt element connected between the first shunt element and the voltage bias circuit in parallel relation to each of the negative differential resistance element and the voltage bias circuit, and in which a second resistor and a second capacitor of the second shunt element are connected in series, wherein each of the first shunt element and the second shunt element has a low impedance with respect to a resistance value of the negative differential resistance element serving as a reference.

Further, an antenna of the present disclosure includes an antenna device that transmits or receives electromagnetic waves, the antenna device including: a chip having an antenna array in which a plurality of antennas are arranged, each antenna including a negative differential resistance element and a resonance circuit; a substrate on which the chip is to be placed; and a voltage bias circuit that applies a voltage to the antenna array, wherein the chip has: a first shunt element connected in parallel with each of the negative differential resistance element and the voltage bias circuit and including at least a first capacitor; and a plurality of pads including at least each of the first pad and the second pad to supply a predetermined voltage to the antenna array, the substrate having: a second shunt element connected in parallel with each of the negative differential resistance element and the voltage bias circuit and including at least a second capacitor, and further disposed in the substrate, and wherein the antenna array is located between the first pad and the second pad. In addition, the camera system of the present disclosure includes: a camera system comprising an antenna device as described above; a detection device for detecting electromagnetic waves transmitted from the antenna device; and a processing unit that processes a signal from the detection device.

Advantageous effects of the invention

With the technology of the present disclosure, it is possible to provide an antenna device and a camera system that operate well because the configuration of the shunt element is optimized and parasitic oscillation is suppressed.

Drawings

Fig. 1 illustrates an example of a plan view of an antenna device according to a first embodiment.

Fig. 2 illustrates an example of a cross-sectional view of the antenna device according to the first embodiment.

Fig. 3 illustrates an example of a cross-sectional view of the antenna device according to the first embodiment.

Fig. 4A and 4B are explanatory diagrams illustrating an antenna array according to the first embodiment.

Fig. 5 is an equivalent circuit diagram of the antenna device according to the first embodiment.

Fig. 6 illustrates a diagram illustrating an antenna device according to the first embodiment.

Fig. 7 illustrates a diagram illustrating an antenna device according to the first embodiment.

Fig. 8 illustrates a diagram illustrating an antenna device according to the first embodiment.

Fig. 9A and 9B illustrate diagrams illustrating an antenna device according to the first embodiment.

Fig. 10 illustrates an example of a plan view of the antenna device according to the second embodiment.

Fig. 11 illustrates an example of a plan view of an antenna device according to the third embodiment.

Fig. 12 illustrates an example of a plan view of an antenna device according to the fourth embodiment.

Fig. 13 illustrates an example of a plan view of an antenna device according to the fourth embodiment.

Fig. 14 illustrates an example of a plan view of an antenna device according to the fourth embodiment.

Fig. 15 illustrates an example of a plan view of an antenna device according to the fifth embodiment.

Fig. 16 illustrates an example of a plan view of the antenna device according to the fifth embodiment.

Fig. 17 illustrates an equivalent circuit diagram of an antenna device according to the sixth embodiment.

Fig. 18 is an explanatory diagram illustrating an antenna array according to the sixth embodiment.

Fig. 19 illustrates an example of a cross-sectional view of an antenna device according to a sixth embodiment.

Fig. 20 is an explanatory diagram illustrating a modified antenna array according to the sixth embodiment.

Fig. 21 illustrates an example of a cross-sectional view of an antenna device according to a modification of the sixth embodiment.

Fig. 22 illustrates an example of a plan view of an antenna device according to the fourth embodiment.

Fig. 23 illustrates a schematic diagram for illustrating a camera system according to a seventh embodiment.

Detailed Description

A description will be given below of embodiments of the present disclosure using the drawings. Note that the present disclosure is not limited to the following embodiments, and may be appropriately modified within a range not departing from the gist thereof. In addition, in the drawings described below, components having the same functions are denoted by the same reference numerals, and the description thereof may be omitted or simplified.

(first embodiment)

A description will be given of an antenna device according to a first embodiment using fig. 1 to 9. Fig. 1 is a plan view illustrating a schematic configuration of an antenna device according to the present embodiment. Fig. 2 is a cross-sectional view taken along line A-A' in fig. 1.

As shown in fig. 1 and 2, in an antenna apparatus 100 according to the present embodiment, a chip 11 having a quadrangular shape is mounted on a substrate 10, and an antenna array 12 including a plurality of antennas 121 is arranged on the chip 11. Fig. 1 illustrates a configuration on the top surface of a chip 11. Each of the antennas 121 includes a negative differential resistance element and a resonance circuit, and transmits or receives electromagnetic waves in a terahertz frequency band, although details of the antenna 121 will be described later. The antenna 121 generates electromagnetic waves (hereinafter simply referred to as "terahertz waves") including a frequency band corresponding to at least a portion of the frequency band from millimeter waves to terahertz waves (at least 30GHz and not more than 30 THz). Further, the adjacent antennas 121 are configured to be capacitively coupled via microstrip lines (described later using fig. 4).

In addition to the antenna array 12, the chip 11 includes a resistive element 131 and a capacitive element 132 each included in the first shunt element 1300, a pad 141 to apply a bias voltage to the chip 11, and a pad 142 to apply a ground voltage to the chip 11. The pads 141 and 142 are used for making electrical connection with a circuit outside the chip 11, and for supplying a predetermined voltage from outside, for example. The pads 141 and 142 are made of conductors. Hereinafter, the pads are used for electrical connection with the outside. Specifically, the pad may be used for supplying a predetermined voltage from the outside and for supplying a predetermined voltage to the outside. In the present embodiment, the predetermined voltage may be a ground voltage, a power supply voltage, a voltage from a voltage bias circuit, or the like.

The antenna array 12 is placed at substantially the center of the chip 11, and the capacitive element 132 is placed adjacent to the antenna array 12. Placing the capacitive element 132 around the antenna array 12 can also enlarge the area of the capacitive element placed on the chip 11 and ensure a large capacitance. The capacitive element 132 is also divided to be arranged on the respective sides of the chip 11 having two facing sides (right and left sides of the chip 11 in the drawing) such that the antenna array 12 is interposed therebetween. This allows the resistive element 131, wiring, pads, and the like to be placed in a portion where the capacitive element 132 is not placed (upper side of the chip 11 in the drawing), and thus the chip size of the chip 11 can be reduced.

As shown in fig. 2, one terminal of the resistive element 131 is connected to one terminal of the capacitive element 132 via each of the wiring 133 and the via 134. The resistive element 131 and the capacitive element 132 are connected in series, and for easy placement connection, the resistive element 131 is preferably placed in the vicinity of the capacitive element 132. Alternatively, the resistive element 131 may also be placed on the capacitive element 132 in overlapping relation with the capacitive element 132. The other terminal of the resistive element 131 is connected to the pad 141 via the bias voltage line 130. The bias voltage line 130 is placed between the respective antennas 121 in the antenna array 12 to be commonly connected to the respective antennas 121 and applies a bias voltage to each of the antennas 121. The other terminal of the capacitive element 132 is connected to the pad 142 via a wiring and a via (not shown).

As the capacitance element 132, a MIM (Metal-Insulator-Metal) capacitor in which an insulating layer is interposed between Metal layers can be used. As the metal layer, a wiring layer in the chip 11 may be used, and as the insulating layer, an insulating layer and a dielectric layer each forming an antenna may be used. According to the present embodiment, as shown in fig. 2, as one electrode of the MIM capacitor, the ground metal layer 124 is used, and the ground metal layer 124 is connected to the pad 142 to which the ground voltage is applied. As the other electrode of the MIM capacitor, a metal layer 135 is formed via an insulating layer. The metal layer 135 is connected to the wiring 133 via the via 134. By configuring the MIM capacitor as such, the capacitor can be formed in a chip by a simple and convenient manufacturing process.

In addition to the above-described configuration, a configuration in which a capacitor is formed on a substrate other than the substrate of the chip 11 to be bonded to the top surface or the back surface of the chip 11 is also possible, and this configuration allows a capacitive element including a larger capacitance.

In the first shunt element 1300, the resistive element 131 is connected to the pad 141 to which the bias voltage is applied, and the capacitive element 132 is connected to the pad 142 to which the ground voltage is applied. However, it is also possible to reverse the connection relationship and connect the resistive element 131 to the pad 142 to which the ground voltage is applied, and connect the capacitive element 132 to the pad 141 to which the bias voltage is applied.

Preferably, on the chip 11, as the antennas 121 in the antenna array 12, 20 to 40 antennas are arranged. Further, the number of pads 141 for application of the bias voltage and the number of pads 142 for application of the ground voltage are set to be smaller than the number of antennas. This allows for efficient use of the space of the chip 11 and allows for further size reduction of the chip 11. Also, when the number of pairs of the resistive element 131 and the capacitive element 132 is not greater than the number of pads 141 for application of the bias voltage or not greater than the number of pads 142 for application of the ground voltage, the space of the chip 11 can be effectively used and further size reduction of the chip 11 is allowed.

The substrate 10 includes a resistive element 151 and a capacitive element 152 each included in the second shunt element 1500, a pad 161 to be connected to the pad 141 of the chip 11, and a pad 162 to be connected to the pad 142 of the chip 11. The pads 161 and 162 are used to make electrical connection with external circuits external to the chip 11. The pads 161 and 162 are made of conductors. The external circuit mentioned here is a chip 11. The substrate 10 further includes a connection terminal 181 to which a bias voltage is to be supplied from the voltage bias circuit 17 and a connection terminal 182 to which a ground voltage is to be supplied. For downsizing of the substrate 10, a surface mount component (SMD: surface Mount Device (surface mount device)) is preferably used as the resistive element 151 or the capacitive element 152. Since the wiring to be placed in the substrate 10 also has a resistance value, as the resistance element 151, the resistance of the wiring in the substrate 10 included in the path connecting the first shunt element 1300 and the second shunt element 1500 can also be used. This can reduce the number of components used in the chip 11 and achieve a reduction in the size of the chip 11. The connection terminals 181 and 182 may be pads as well.

The voltage bias circuit 17 is connected from the outside of the substrate 10 via connection terminals 181 and 182. Note that, instead of using such a configuration, it is also possible to place the voltage bias circuit 17 in the substrate 10 or in the chip 11.

The pad 141 of the chip 11 and the pad 161 of the substrate 10 are connected by a bonding wire 191. The pad 142 of the chip 11 and the pad 162 of the substrate 10 are connected by a bonding wire 192. In order to reduce the inductance of the bonding wires 191 and 192, it is preferable to dispose the pads 141 and 161 and the pads 142 and 162 close to each other and reduce the lengths of the bonding wires 191 and 192.

In order to shorten the bonding wires 191 and 192, the pads 141 and 142 are appropriately arranged at the end of the chip 11. Meanwhile, the pads 141 and 161 are appropriately arranged to face each other with the sides of the chip 11 interposed therebetween. Further, the pad 142 and the pad 162 are also suitably arranged to face each other with the edge of the chip 11 interposed therebetween.

One terminal 1512 of the resistive element 151 is connected to one terminal 1521 of the capacitive element 152 via a wiring 157. In other words, the resistive element 151 and the capacitive element 152 are connected in series. Thus, the resistive element 151 and the capacitive element 152 are preferably arranged adjacent to each other. More preferably, one terminal 1512 of the resistive element 151 is placed adjacent to one terminal 1521 of the capacitive element 152. This can reduce the length of the wiring 157 and reduce the inductance.

The other terminal 1511 of the resistive element 151 is connected to the pad 161 via the wiring 153, and is also connected to the connection terminal 181 via the wiring 154. The other terminal 1522 of the capacitive element 152 is connected to the pad 162 via the wiring 155, and is also connected to the connection terminal 182 via the wiring 156. It is preferable that the directions in which the terminals 1511 and 1512 of the resistive element 151 and the terminals 1521 and 1522 of the capacitive element 152 are arranged be set to be the same as the directions in which the pads 161 and 162 are arranged. Such an arrangement can shorten the wiring to be connected and reduce the inductance.

In the second shunt element 1500, the resistive element 151 is connected to the connection terminal 181 to which a bias voltage is to be applied, and the capacitive element 132 is connected to the connection terminal 182 to which a ground voltage is to be applied. However, it is also possible to reverse the connection relationship and connect the resistive element 131 to the connection terminal 182 to which the ground voltage is applied and connect the capacitive element 132 to the connection terminal 181 to which the bias voltage is applied.

In the present embodiment, it is assumed that the first shunt element 1300 and the second shunt element 1500 include examples of the resistive elements 131 and 151 and the capacitive elements 132 and 152, respectively. However, each of the first shunt element and the second shunt element may also be configured to include any one of a resistive element and a capacitive element. In the case where the shunt element includes a capacitive element, it becomes possible not only to suppress capacitive oscillation but also to reduce power consumption by cutting off DC current using the frequency characteristic of impedance.

The positional relationship between the components of the antenna device 100 is such that: between the antenna array 12 and the voltage bias circuit 17, a first shunt element 1300 is placed, and between the first shunt element 1300 and the voltage bias circuit 17, a second shunt element 1500 is placed.

Fig. 3 is a partial cross-sectional view of the antenna apparatus 100, which illustrates a configuration in which pads are formed on the back surface of the chip 11 to connect the chip 11 and the substrate 10 without using bonding wires 19. According to fig. 3, wiring present in the top surface of the chip 11 is connected to pads 141 present on the back surface of the chip 11 via the through-electrodes 135.

The through electrode 135 is formed by forming a through hole in the chip 11, then forming an insulating film for electrical isolation on the inner wall of the through hole, and filling the through hole with copper or the like which has low resistance and can easily form an electrode by an electrolytic plating method or the like. The through electrode 135 is smoothed by CMP (Chemical Mechanical Polishing (chemical mechanical polishing)) treatment or the like. After forming the through electrode 135, a pad 141 is formed on the back surface of the chip 11 so as to be electrically connected to the through electrode 135.

The pad 141 on the back surface of the chip 11 and the pad 161 on the substrate 10 are arranged to overlap each other and are connected by soldering or the like. In the case of providing electrical connection using the through electrode 135, no bonding wire is used, and thus inductance is reduced to easily suppress parasitic oscillation in the antenna device 100.

Fig. 4 is an explanatory diagram illustrating the antenna array 12 in the present embodiment. Fig. 4A is a top view of the antenna array 12, and fig. 4B is a cross-sectional view of the antenna array 12 along line B-B' in fig. 4A. In these figures, by way of example, two antennas 121 and 122 are illustrated as being included in the antenna array 12.

Generally, in an antenna array intended for power synthesis, each of intervals between respective antennas is set to a wavelength or less of a wavelength converted into an oscillating electromagnetic wave in vacuum, to an integer multiple of the wavelength, or more preferably to a half wavelength or less. In the present embodiment, the antennas 121 and 122 are arranged such that the interval between the antennas is not more than half a wavelength of the transmitted electromagnetic wave.

In the antenna array 12, the resonant circuit 1200 is configured to control the oscillation frequency by using a microstrip resonator including a metal layer 123 corresponding to a first conductor forming part of each of the antennas, a dielectric layer 128, and a grounded metal layer 124 corresponding to a second conductor forming part of each of the antennas. Each of the antennas 121 and 122 includes a resonant circuit 1200 and a negative differential resistance element 127. The bias voltage line 130 is connected to the metal layer 123 via a via 135, and a bias voltage is applied to the negative differential resistance element 127. The negative differential resistance element 127 generates an electromagnetic wave gain for maintaining oscillation. The respective antennas 121 and 122 synchronized to oscillate with the same phase are designed so as to reach a near oscillation frequency ω ₀ Is a frequency of (a) is a frequency of (b). Thus, the respective antennas comprising the half-wavelength resonators preferably have respective shapes similar to each other. The negative differential resistive elements 127 also preferably have the same respective shape and characteristics as each other. The microstrip line 125 is an inter-element structure for synchronizing the respective antennas to oscillate with the same phase as described above.

According to oscillation frequency omega after synchronization ₀ The microstrip line 125, which is a transmission line serving as a metal part of the link structure, has a length preferably selected to be 2pi from one end to the other end along the microstrip line 125. The electrical length of 2pi is as followsEffective oscillation wavelength lambda of effective dielectric constant conversion in surrounding structure ₀ Corresponding length. As the electrical length, 2pi is selected so as to synchronize the antennas 121 and 122 with the same phase and oscillate the antennas 121 and 122. In the case where the antennas 121 and 122 are synchronized in opposite phases, the electrical length may also be pi or 3 pi. Synchronization of the antennas 121 and 122 is possible even when the length of the microstrip line 125 is not exactly 2pi. Although depending on the magnitude of the coupling between elements formed via the microstrip line 125, an electrical length of about 2pi±10% is generally in an allowable range. Note that the allowable range is wider than when coupling is provided without the microstrip line 125. Note that the electrical length of the microstrip line can be easily checked using an electromagnetic field simulator or the like.

A part of the oscillation output of the antenna 121 is input to the adjacent antenna 122 via the microstrip line 125 with substantially the same phase. Meanwhile, a part of the oscillation output of the antenna 122 is input to the adjacent antenna 121 via the microstrip line 125 with substantially the same phase. In the antenna array in the present embodiment, in order to achieve such a mutual injection locking phenomenon between the antennas 121 and 122, the microstrip line 125 has been introduced.

The microstrip line 125 in this embodiment is characterized by capacitive coupling with the metal layer 123 of the resonant structure. Microstrip line 125 and metal layer 123 form a capacitor via insulating layer 129 only in metal-insulator-metal (MIM) region 126 and are DC-open. Thus, at oscillation frequency ω ₀ It is possible to ensure that an antenna of a size as large as that of direct coupling is coupled to the antenna. Furthermore, below ω ₀ The magnitude of the coupling is reduced and thus isolation between the antennas can be ensured. It is preferable that the microstrip line 125 in the present embodiment have such a property. Furthermore, below ω ₀ The microstrip line 125 having an open end serves as a capacitive element in the frequency region. The microstrip line 125 is a capacitive element when seen from the negative differential resistive element 127 on the antenna 121 side, and the metal layer 123 of the resonance structure on the antenna 122 side is also a capacitor. As a result, in the low frequency region, there is no fear of occurrence of the resonance frequency. Thus, can To suppress parasitic oscillations in the low frequency region.

With reference to fig. 4A and 4B, a description has been given of two individual antennas 121 and 122, and in the antenna array 12, the respective antennas may be arranged by being arranged in the same configuration as that of the antennas 121 and 122. Further, on the ground metal layer 124, a plurality of metal layers 123 corresponding to the number of arrays are placed via the dielectric layer 128, and negative differential resistance elements 127 corresponding to the metal layers 123 are placed. Adjacent antennas are capacitively coupled via microstrip lines 125. Each of the microstrip lines 125 has an electrical length of about 2pi. Thus, it becomes possible to synchronize all the negative differential resistance elements 127 with the same phase. As a result of thus arranging the antennas, not only the resultant electric power increases, but also sharp directivity is advantageously obtained.

Note that, inside the chip 11, the plurality of metal layers 123 are commonly connected via a strip-shaped conductor (not shown) to be connected to the pad 141 to which a bias voltage is to be applied, and the ground metal layer 124 is connected to the pad 142 inside the chip 11. With this configuration, when a voltage is applied to each of the pad 141 and the pad 142, a bias voltage is applied to the negative differential resistance element 127.

As each of the negative differential resistance elements 127, a resonant tunneling diode lattice-matched to an InP substrate may be used. Note that the negative differential resistance element 127 is not limited to a resonant tunneling diode, and an Esaki diode or a Gunn diode may be used. The resonant tunneling diode is configured to include a multiple quantum well structure containing InGaAs/inaias and InGaAs/AlAs and an electrical contact layer containing n-InGaAs on an InP substrate, for example. As the multiple quantum well structure, for example, a triple barrier structure is used. More specifically, the multiple quantum well structure is formed of a semiconductor multilayer film structure including AlAs (1.3 nm)/InGaAs (7.6 nm)/inaias (2.6 nm)/InGaAs (5.6 nm)/AlAs (1.3 nm). Of these layers, inGaAs is a well layer, and lattice-matched inaias and unmatched AlAs are barrier layers. By not performing carrier doping, these layers are intentionally left undoped. Such a multiple quantum well structure is inserted to include an electron concentration of 2×10 ¹⁸ cm ^-3 Between the electrical contact layers of n-InGaAs. Electric connectorThe current-voltage (I/V) characteristics of such a structure between the contact layers have 280kA/cm ² And the negative resistance region ranges from about 0.7V to about 0.9V. As a configuration of the diode, in the case of a mesa structure having a diameter of 2 μm, a peak current value of 10mA and a negative resistance value of-20Ω were obtained. When reactance generated by junction capacitance of a resonant tunneling diode connected to the lower portion of the metal layer 123 and having a diameter of 2 μm is considered, the oscillation frequency is about 0.55THz.

Next, fig. 5 illustrates an equivalent circuit diagram of the antenna device according to the present embodiment. The equivalent circuit of the chip 11 has a resistance r of each of the negative differential resistance elements included in the antenna array 12 (r represents an absolute value of the resistance of the negative differential resistance element). The equivalent circuit of the chip 11 also has the impedance Z of the resonant circuit 1200 included in the antenna array 12 and the resistance Rc of the resistive element 131 included in the first shunt element 1300. The equivalent circuit of the chip 11 also has a capacitance Cc of the capacitive element 132 included in the first shunt element 1300.

The first shunt element 1300 is configured to include a resistor Rc and a capacitor Cc connected in series. Further, the resistor r, the impedance Z of the resonance circuit 1200, and the first shunt element 1300 are connected in parallel to each other. More specifically, one terminal of the resistor r, one terminal of the impedance Z of the resonance circuit 1200, and one terminal of the resistor Rc are each connected to the first node n1. Meanwhile, the other terminal of the resistor Rc is connected to one terminal of the capacitor Cc. Further, the other terminal of the resistor r, the other terminal of the impedance Z of the resonance circuit 1200, and the other terminal of the capacitor Cc are connected to the ground voltage. The first node n1 is connected to the pad 141 of the chip 11, and the ground voltage is applied via the pad 142 of the chip 11.

The equivalent circuit of the substrate 10 is configured to include the resistance Rp of the resistive element 151 included in the second shunt element 1500, the capacitance Cp of the capacitive element 152 included therein, and the inductance L of the path connecting the first shunt element 1300 and the second shunt element 1500. The inductance L includes respective parasitic inductances of wiring connecting the first shunt element 1300 and the pad 141, bonding wires connecting the chip and the substrate, and wiring, pad, and the like connecting the bonding wires and the second shunt element 1500.

The second shunt element 1500 is configured to include a resistor Rp and a capacitor Cp connected in series. Further, the chip 11 and the second shunt element 1500 are connected via an inductance L. More specifically, one terminal of the inductance L is connected to the first node n1 in the equivalent circuit of the chip 11, and the other terminal of the inductance L and one terminal of the resistance Rp are connected to the second node n2. Meanwhile, the other terminal of the resistor Rp is connected to one terminal of the capacitor Cp. A ground voltage is applied to the other terminal of the capacitor Cp. The second node n2 is also connected to the terminal 181, and the voltage bias circuit V is connected thereto. Accordingly, a bias voltage is applied to the second node n2, and the bias voltage is applied to the resistor r via the inductance L.

The first shunt element 1300 (resistance Rc and capacitance Cc) is connected in parallel with the negative differential resistance element (resistance r), and is also connected in parallel with the second shunt element 1500 (resistance Rp and capacitance Cp) via the inductance L. Furthermore, the first shunt element 1300 is also connected in parallel with the voltage bias circuit V.

In such an antenna device, in order to suppress parasitic oscillation, each of the first shunt element 1300 and the second shunt element 1500 has a low impedance with respect to the resistance r of the negative differential resistance element 127 serving as a reference. In other words, in a frequency band lower than the terahertz frequency band, each of the first and second shunt elements 1300 and 1500 is preferably set to have a low impedance when seen from the negative differential resistance element 127. In this case, conditional expressions including the following expressions (1) and (2) are satisfied:

Rp+1/(2π×f×Cp)<r ... (1)

Rc+1/(2π×f×Cc)<r ... (2)

where r is the absolute value of the resistance value of the negative differential resistance element, rc is the resistance value of the resistance Rc corresponding to the first resistor, and Cc is the capacitance value of the capacitance Cc corresponding to the first capacitor. Further, rp is a resistance value of the resistance Rp corresponding to the second resistor, cp is a capacitance value of the capacitance Cp corresponding to the second capacitor, and L is an inductance of a path connecting the first shunt element 1300 and the second shunt element 1500. Also, f represents a frequency of parasitic oscillation as a target, which is a frequency smaller than a resonance frequency of each of the resonance circuits included in the antenna array 12. The frequency f is specifically smaller than 30GHz, and is specifically a frequency in the range of 10MHz to 10GHz in the case where the chip 11 is mounted on the substrate 10 used in the present embodiment.

However, LC resonance in the inductance L and the capacitance Cc may occur even when the expressions (1) and (2) are satisfied. In order to suppress LC resonance, it is necessary to ensure Rc so as to cause oscillation energy loss, and it is preferable to decrease L and increase Cc. Therefore, in order to suppress the capacitance oscillation, a conditional expression including the following expression (3) is also satisfied:

L/(Cc×r)<Rc ... (3)

fig. 6 is a diagram showing the frequency characteristics of the impedance when seen from the negative differential resistance element 127 when the value of the inductance L is changed based on the equivalent circuit in fig. 5. The broken line indicates the characteristic for l=1nh, the solid line indicates the characteristic for 5nH, the dot-dash line indicates the characteristic for 10nH, and the impedance has a peak at a specified frequency. Specifically, for l=1nh, the peak is 1.8Ω at 160MHz, for l=5nh, the peak is 16.8Ω at 50MHz, and for l=10nh, the peak is 8.5Ω at 71 MHz.

Fig. 7 is a diagram showing a relationship between the inductance L and the peak value of the inductance when seen from the negative differential resistance element 127 based on the frequency characteristic in fig. 6. According to fig. 7, as the inductance L increases, the peak value of the impedance increases.

At the frequency f of the capacitive oscillation to be suppressed, when the impedance of the line as seen from the negative differential resistance element 127 is not more than 10 times the absolute value of the negative differential resistance, the magnitude of loss due to the line for the gain of the negative differential resistance element 127 is no longer negligible. Therefore, oscillation of LC resonance can be suppressed. For example, in an antenna array having a chip size of 3mm square to 4mm square, 20 to 40 antennas may be arranged, and the combined resistance value of the negative differential resistance element 127 is at most 1Ω, that is, not more than 1Ω. Thus, as long as the resistance value is not more than ten times this resistance value, that is, 10Ω, parasitic oscillation can be suppressed. In other words, according to the diagram in FIG. 7, only L.ltoreq.5nH needs to be satisfied.

The inductance L includes respective parasitic inductances of wiring connecting the first shunt element 1300 and the pad 141, bonding wires connecting the chip and the substrate, and wiring, pad, and the like connecting the bonding wires and the second shunt element 1500. Each of these inductances of the paths connecting the first and second shunt elements 1300 and 1500 may be calculated using the following expressions (4) and (5). Among paths connecting the first and second flow dividing elements 1300 and 1500, a portion having a cross section that may be approximately circular in shape is calculated using expression (4), and a portion having a cross section that may be approximately quadrangular in shape is calculated using expression (5).

L1＝0.2×l1×[ln(4×l1/d)-0.75] [nH] ... (4)

L2＝0.2×l2×[ln{2×l2/(w+h)}+0.2235]×(w+h)/l2+0.5 [nH] ... (5)

Where l1 is the length (mm) of the portion of the path having a cross-section that may be approximated as a generally circular shape, and d is the diameter (mm) of its cross-section. Also, l2 is the length (mm) of the portion of the path having a cross section that may be approximately quadrilateral in shape, w is its width (mm), and h is its thickness (mm).

Fig. 8 is a diagram illustrating inductance of a path connecting the first shunt element 1300 and the second shunt element 1500 in the present embodiment. The path connecting the first shunt element 1300 and the second shunt element 1500 has a wiring (first portion P1) connecting the resistive element 131 included in the first shunt element 1300 and the pad 141, and a pad 141 (second portion P2). The path also has a bonding wire 19 (third portion P3), a pad 161 (fourth portion P4), and a wiring (fifth portion P5) connecting the pad 161 and the resistive element 151 included in the second shunt element 1500.

The length of the path connecting the first and second shunt elements 1300, 1500 is preferably no greater than 4mm, which is suitable for reducing parasitic inductance and suppressing parasitic oscillations. More preferably, the length of the path is no greater than 2mm.

A description will be given below of an example of the size of each portion of the path and the inductance calculated using expression (4) or expression (5).

The first portion P1 has a length of 0.3mm, a width of 0.2mm, and a thickness of 0.5 μm, and the inductance L1 of this region is calculated to be 0.1nH using expression (5).

Assuming that the second portion P2 is a region from the end of the pad 141 to a substantially central portion of the pad 141 to which the bonding wire 19 is connected, the inductance L2 of the second portion P2 is calculated. The length of this region was 0.1mm, the width was 0.2mm, and the thickness was 0.5 μm, and the inductance L2 of this region was calculated to be 0.02nH using expression (5).

The third portion P3 is a bonding wire having a length of 1.0mm and a cross-sectional diameter of 20 μm, and the inductance L3 of this region is calculated to be 0.91nH using expression (4).

Assuming that the fourth portion P4 is a region from the end of the pad 161 to the substantially central portion of the pad 161 to which the bonding wire 19 is connected, the inductance L4 of the fourth portion P4 is calculated. This region has a length of 0.6mm, a width of 1.2mm, and a thickness of 35 μm, and the inductance L4 is calculated to be 0.11nH using expression (5).

The fifth portion P5 has a length of 0.8mm, a width of 0.6mm, and a thickness of 35 μm, and the inductance L5 of this region is calculated to be 0.26nH using expression (5).

Thus, the inductance of the path connecting the first and second shunt elements 1300, 1500 may be calculated as the sum of the inductances L1, L2, L3, L4, and L5 to be 1.4nH.

In the present embodiment, the inductance is calculated using expression (4) assuming that the bonding wire 19 has a circular cross section, but it is also possible to use a ribbon bonding wire having a quadrangular cross section. In the case of the ribbon bonding wire, the inductance can be calculated using expression (5). The ribbon bond wire can have a large cross-sectional area and can reduce inductance.

Fig. 9A and 9B are diagrams illustrating calculation of inductance of wiring. A description will be given here by using the wiring 153 connecting the pad 161 and the resistive element 151 included in the second shunt element 1500. The wiring connecting the resistive element 131 and the pad 141 included in the first shunt element 1300 may also be considered in the same manner.

Fig. 9A is a diagram illustrating an example of a configuration in which the wiring 153 has a bent portion. In the example shown in fig. 9A, the wiring 153 is configured to include a bent portion having two 90-degree bent portions. The inductance of the wiring 153 in the example shown in fig. 9A can be calculated by dividing the wiring 153 into three rectangular portions. The three rectangular portions are a first rectangular portion RS1 connected to the pad 161, a second rectangular portion RS2 connected to the first rectangular portion, and a third rectangular portion RS3 connected to the second rectangular portion. The third rectangular portion RS3 is connected to the resistive element 151. The first rectangular portion RS1 has a length l21, a width w1 and a thickness h1, the second rectangular portion RS2 has a length l22, a width w2 and a thickness h2, and the third rectangular portion RS3 has a length l23, a width w3 and a thickness h3. Using expression (5), the respective inductances of the respective rectangular portions are calculated, and the sum thereof is assumed as the inductance of the wiring 153.

An example of a method of determining the lengths l21, l22, and l23 will be described. Assume that an intersection point of a line X passing through the middle in the width direction of the first rectangular portion RS1 and extending in the length direction and a line Y passing through the middle in the width direction of the second rectangular portion RS2 and extending in the length direction is a point a. It is also assumed that the intersection point of the line Y and the line Z passing through the middle in the width direction of the third rectangular portion RS3 and extending in the length direction is a point B. Then, it is assumed that the distance between the end of the pad 161 and the point a is the length l21 of the first rectangular portion RS3, the distance between the point a and the point B is the length l22 of the second rectangular portion RS2, and the distance between the point B and the end of the resistive element 151 is the length l23 of the third rectangular portion RS 3.

As a method of determining the length l21, the length l22, and the length l23, a determination method other than the above determination method may be employed as long as the wiring 153 is divided and a rectangular portion can be specified.

Next, fig. 9B is a diagram illustrating an example in which the wiring 153 is configured to extend straight while its width gradually increases from the resistive element 151 toward the pad 161. Even for the wiring 153 thus configured, by replacing the wiring 153 with the rectangular portion RS4 shown in the drawing, the inductance of the wiring 153 can be calculated by using expression (5). The rectangular portion RS4 has a length l24, a width w4 and a thickness h4.

Next, an example of a method of determining the length l24 and the width w4 of the rectangular portion RS4 will be described. A center point C of a portion V-V' along which the wiring 153 and the pad 161 contact is defined, and a point D which allows contact with the resistive element 151 while having the shortest distance to the point C is defined. Assume that the distance between point C and point D is length l24. It is also assumed that the distance between the ends of the wiring in the direction perpendicular to the line segment CD via the intermediate E between the point C and the point D is the width w4.

Therefore, according to the determination method described using fig. 9A and 9B, the inductance of the wiring can be calculated.

According to the present embodiment, parasitic oscillation can be suppressed by configuring the shunt element so as to satisfy expression (1), expression (2), and expression (3). Further, when determining the inductance L of the path connecting the first shunt element 1300 and the second shunt element 1500 used in expression (3), the calculation methods described using expression (4), expression (5), fig. 8, and fig. 9 may be applied.

(second embodiment)

A description will be given of an antenna device according to a second embodiment of the present disclosure using fig. 10. In the second embodiment, unlike in the first embodiment, the pads and the pads are connected with a plurality of bonding wires. Note that, in the present embodiment, description of the same components as those in the first embodiment is omitted.

In the antenna device 200 shown in fig. 10, the chip 21 includes a pad 241 for applying a bias voltage and a pad 242 for applying a ground voltage. Further, the substrate 20 includes a pad 261 for connection to the pad 241 of the chip 21 and a pad 262 for connection to the pad 242 of the chip 21. The substrate 20 also has a plurality of bonding wires 291 for connecting the pads 241 and 261 and a plurality of bonding wires 292 for connecting the pads 242 and 262. Except for these, the antenna array, the first shunt element, the second shunt element, and the like in the antenna device 200 are the same as those in the antenna device 100 in the first embodiment.

In order to reduce the inductance of the bonding wires 291 and 292, it is preferable to dispose the pads 241 and 261 and the pads 242 and 262 adjacent to each other so as to shorten the bonding wires 291 and 292.

To shorten the bonding wires 291 and 292, pads 241 and 242 are preferably placed on the ends of the chip 21. When it is assumed that the side of the chip 21 traversed by the plurality of bonding wires 291 and 292 is the first side 271, the bonding pads 241 and 261 are arranged to face each other with the first side 271 interposed therebetween. Further, the pads 242 and 262 are also arranged to face each other with the first edge 271 interposed therebetween. Further, the plurality of bonding wires 291 and 292 are arranged side by side to be spaced apart from each other in a direction parallel to the first edge 271.

The plurality of bonding wires 291 and 292 are electrically connected in parallel. The combined inductance Lm of the M bonding wires connected in parallel can be calculated using the following expression (6).

1/Lm＝Σ(1/Li) (i＝1, 2, 3, ..., M) ... (6)

Where Li is the inductance of the i-th bonding wire among the M bonding wires, and when the bonding wire has a circular cross section, the calculation is performed using expression (4), and when the bonding wire has a quadrangular cross section, the calculation is performed using expression (5). Note that whether the bonding wire has a circular cross section or a quadrangular cross section may be appropriately determined, and the combined inductance Lm of the bonding wire may be appropriately calculated using expressions (4) and (5).

By electrically connecting the plurality of bonding wires 291 and 292 in parallel in this manner, the combined inductance of the bonding wires 291 and 292 can be reduced, allowing parasitic oscillation to be easily suppressed.

In the present embodiment, the areas of the pads 241 and 242 are set to be larger than those of the pads 141 and 142 in the first embodiment, and the areas of the pads 261 and 262 are set to be larger than those of the pads 161 and 162 in the first embodiment. Thus, it is possible to increase the number of bonding wires providing connection between pads and reduce the combined inductance of a plurality of bonding wires.

The pads 241, 242, 261, and 262 are configured such that their dimensions in a direction parallel to the first side 271 of the chip 21 are larger than their dimensions in a direction perpendicular to the first side 271. This may increase the number of bond wires that may be placed and reduce the combined inductance of the bond wires.

The pads 241, 242, 261, and 262 may also be divided per bonding wire in the same manner as in the first embodiment. In this case, it is only necessary to provide a configuration in which a wiring layer under a metal layer forming a pad is provided for connection. However, such a configuration of placing a plurality of bonding wires on one pad as shown in fig. 10 avoids the need to secure a space separating the pads, and allows easy patterning. Thus, by adopting the configuration shown by way of example in fig. 10, a low-cost printed substrate or ceramic package can be used as the substrate 20 and allows cost reduction.

(third embodiment)

A description will be given of an antenna device according to a third embodiment of the present disclosure using fig. 11. The third embodiment is different from the first embodiment in that additional resistive elements and capacitive elements are included in the first shunt element and the second shunt element to be connected in parallel. In the present embodiment, descriptions of the same components as those in the first and second embodiments are omitted.

In the antenna device 300 in the present embodiment shown in fig. 11, the chip 31 includes a first shunt element including a resistive element 331 and a capacitive element 332, and another first shunt element including a resistive element 333 and a capacitive element 332. Further, in the antenna device 300, the chip 31 includes pads 341 and 343 for applying a bias voltage and a pad 342 for applying a ground voltage. Further, the substrate 30 includes a second shunt element including a resistive element 351 and a capacitive element 352, and another second shunt element including a resistive element 353 and a capacitive element 354.

The substrate 30 further includes a pad 361 for connection to the pad 341 of the chip 31, a pad 362 for connection to the pad 342 of the chip 31, and a pad 363 for connection to the pad 343 of the chip 31. Pad 341 and pad 361 are connected by bond wire 391, pad 342 and pad 362 are connected by bond wire 392, and pad 343 and pad 363 are connected by bond wire 393. The substrate 30 further includes connection terminals 381 and 383 to which a bias voltage is applied from the voltage bias circuit 37 and a connection terminal 182 to which a ground voltage is applied.

In fig. 11, pads 341, 342, and 343 of chip 31 are connected one-to-one with pads 361, 362, and 363 of substrate 30 with respective bonding wires 391, 392, and 393. However, as in the second embodiment, two pads may also be connected with a plurality of bonding wires. Alternatively, as shown in fig. 3, two pads may also be connected with through electrodes instead of using bonding wires 391, 392 and 393.

The antenna array 32 is placed at substantially the center of the chip 31 in the same manner as in the first embodiment, and the capacitive element 332 is placed adjacent to the antenna array 32. One terminal of the resistive element 331 is connected to one terminal of the capacitive element 332 via a wiring and a via (not shown). One terminal of the resistive element 333 is connected to one terminal of the capacitive element 332 via a wiring and a via (not shown). Resistive elements 331 and 333 are preferably placed in close proximity to capacitive element 332. Alternatively, the resistive elements 331 and 333 may also be placed on the capacitive element 332 in overlapping relation with the capacitive element 332. The other terminal of the resistive element 331 is connected to the pad 341 via the bias voltage line 330. A bias voltage line 330 is also placed between the respective antennas 321 of the antenna array 32 to be connected to each of the antennas 321. Accordingly, a bias voltage is applied to each of the antennas 321. The other terminal of the capacitance element 332 is connected to the pad 342 via a wiring and a via (not shown). The other terminal of the resistive element 333 is connected to the pad 343 via the bias voltage line 330.

One terminal 3512 of the resistive element 351 is connected to one terminal 3521 of the capacitive element 352 via a wiring. In other words, the resistive element 351 and the capacitive element 352 are connected in series. Thus, the resistive element 351 and the capacitive element 352 are preferably arranged adjacent to each other. More preferably, one terminal 3512 of the resistive element 351 is placed adjacent to one terminal 3521 of the capacitive element 352 so that wiring can be shortened and inductance can be reduced.

The other terminal 3511 of the resistive element 351 is connected to the pad 361 via a wire and is also connected to the connection terminal 381 via a wire. Meanwhile, the other terminal 3522 of the capacitive element 352 is connected to the pad 362 via a wiring, and is also connected to the connection terminal 382 via a wiring.

One terminal 3532 of the resistive element 353 is connected to one terminal 3541 of the capacitive element 354 via wiring. In other words, the resistive element 353 and the capacitive element 354 are connected in series. Thus, the resistive element 353 and the capacitive element 354 are preferably arranged adjacent to each other. More preferably, one terminal 3532 of the resistive element 353 and one terminal 3541 of the capacitive element 354 are arranged adjacent to each other so that wiring can be shortened and inductance can be reduced.

The other terminal 3531 of the resistive element 353 is connected to the pad 363 via a wire, and is also connected to the connection terminal 383 via a wire. Meanwhile, the other terminal 3542 of the capacitive element 354 is connected to the pad 362 via a wiring, and is also connected to the connection terminal 382 via a wiring.

In fig. 11, terminals 3511 and 3512 of the resistive element 351, terminals 3521 and 3522 of the capacitive element 352, terminals 3531 and 3532 of the resistive element 353, and terminals 3541 and 3542 of the capacitive element 354 are arranged side by side in one direction (left-right direction in the drawing) on the substrate 30. In the present embodiment, the pads 361, 362, and 363 are also arranged side by side in the same direction as the direction in which the terminals 3511, 3512, 3521, 3522, 3531, 3532, 3541, and 3542 are arranged. By thus arranging the terminals and pads, the connection wiring can be shortened and the inductance can be reduced.

Since a bias voltage is supplied from the voltage bias circuit 37 to the two connection terminals 381 and 383, the other terminal 3511 of the resistive element 351 and the other terminal 3531 of the resistive element 353 are electrically connected. Meanwhile, the other terminal 3522 of the capacitive element 352 and the other terminal 3542 of the capacitive element 354 are commonly connected via wiring. As a result, the resistive element 351 and the capacitive element 352 each included in the second shunt element are electrically connected in parallel with the resistive element 353 and the capacitive element 354 each included in the other second shunt element. As each of the resistive elements 351 and 353 and the capacitive elements 352 and 354, for example, SMD (surface mounted device) is adopted, and such a component has not only a resistive component and a capacitive component but also parasitic inductance. Thus, among the two pairs of the first shunt element and the second shunt element, the second shunt elements (the resistive element 351, the capacitive element 352, the resistive element 353, and the capacitive element 354) in the respective pairs are connected in parallel. Therefore, parasitic inductance can be reduced and parasitic oscillation can be suppressed.

Further, since the bonding wire 391 and the bonding wire 393 each serving as a path for supplying the bias voltage are connected in parallel, the combined inductance of the bonding wires is also reduced.

Further, since the wiring placed in the substrate 30 also has a resistance value, as each of the resistance elements 351 and 353, the resistance of the wiring in the substrate 30 connecting the first shunt element and the second shunt element can also be used. This can reduce the number of components to be placed on the substrate 30, which is advantageous in size reduction.

In the chip 31, elements and pads arranged on the chip 31 and elements, pads, wirings, and the like arranged on the substrate 30 are symmetrically arranged with respect to an axis passing through the center of the antenna array 32. Examples of the axis passing through the center of the antenna array 32 include an axis AX extending in a direction perpendicular to the top surface of the substrate 30 and an axis extending in a direction parallel to the top surface of the substrate 30. Symmetry is determined here based on an axis extending in a direction parallel to the top surface of the substrate. The center of the antenna array 32 may be determined based on the planar shape of the conductors of the antenna array 32. The center of the antenna array 32 may also be the center of gravity of the conductors of the antenna array 32. The center of gravity may be determined based on the cross-sectional shape and the planar shape. Accordingly, in the substrate 30, a plurality of pairs of first and second shunt elements connected to each other are arranged, and at least two pairs of the plurality of pairs of first and second shunt elements are placed at positions symmetrical to each other with respect to an axis passing through the center of the antenna array. This improves the directivity of the terahertz wave generated from the antenna array 32 and enhances the front-side intensity of the terahertz wave.

In the present embodiment, a configuration is adopted in which bias voltages are supplied from two paths using the connection terminals 381 and 383 and ground voltages are supplied from one path using the connection terminal 182. However, it is also possible to use a configuration in which a ground voltage is supplied from two paths using the connection terminals 381 and 383 and a bias voltage is supplied from one path using the connection terminal 182.

(fourth embodiment)

A description will be given of an antenna device according to a fourth embodiment of the present disclosure using fig. 12 to 14. The antenna device according to the fourth embodiment is different from the antenna device according to the first embodiment in that pads are arranged on both sides of two facing sides where a chip is present, i.e., the pads and the chip are arranged such that the chip is interposed between the pads. In the present embodiment, descriptions of the same components as those in the above-described embodiments are omitted.

In the antenna device 400 according to the present embodiment shown in fig. 12, the chip 41 includes a pad 441 for applying a bias voltage and a pad 442 for applying a ground voltage in the same manner as in the first embodiment. Further, unlike in the first embodiment, the antenna device 400 includes a pad 443 for applying a bias voltage and a pad 444 for applying a ground voltage.

On the chip 41, pads 441 and 442 are arranged on the side where the first side 411 of the chip 41 is present, when seen from the antenna array 42. Meanwhile, on the chip 41, when seen from the antenna array 42, the pads 443 and 444 are arranged on the side where the second side 412 of the chip 41 facing the first side 411 is present. This results in a configuration in which antenna array 421 is placed between pads 441 and 442 and pads 443 and 444. Thus, the two pairs of first and second shunt elements are arranged such that the antenna array is interposed between each pair of first and second shunt elements.

Further, in the chip 41, a resistive element 431, a capacitive element 432, and a resistive element 433 included in the first shunt element are arranged.

One terminal of the resistance element 431 is connected to one terminal of the capacitance element 432 via a wiring and a via (not shown). Preferably, the resistive element 431 is placed in the vicinity of the capacitive element 432. Alternatively, the resistive element 431 may also be placed on the capacitive element 432 in overlapping relation with the capacitive element 432. Meanwhile, the other terminal of the resistance element 431 is connected to the pad 441 via the bias voltage line 430. The bias voltage line 430 is also arranged between the respective antennas 421 of the antenna array 42 to be commonly connected to the respective antennas 421, and a bias voltage is applied to each of the antennas 421.

One terminal of the resistive element 433 is connected to one terminal of the capacitive element 432 via a wiring and a via (not shown). Preferably, the resistive element 433 is placed in the vicinity of the capacitive element 432. Alternatively, the resistive element 433 may also be placed on the capacitive element 432 in overlapping relation with the capacitive element 432. Meanwhile, the other terminal of the resistive element 433 is connected to the pad 443 via the bias voltage line 430. The other terminal of the capacitive element 432 is connected to pads 442 and 444 via a wiring path (not shown).

On the chip 41, between the pads 441 and 442 and the pads 443 and 444, a resistive element 431 and a resistive element 433 are arranged. Meanwhile, between the resistive element 431 and the resistive element 433, the antenna array 42 around which the capacitive element 432 is placed. Accordingly, the pads and the first shunt element are symmetrically arranged with respect to an axis passing through the center of the antenna array 42 (axis BX as c on the top surface of the substrate 40). Accordingly, in the substrate 40, a plurality of pairs of first and second shunt elements connected to each other are arranged, and at least two pairs of the plurality of pairs of first and second shunt elements are arranged at positions symmetrical to each other with respect to an axis passing through the center of the antenna array. This improves the directivity of the terahertz wave generated from the antenna array 42 and enhances the front-side intensity of the terahertz wave.

In the substrate 40, in a first region 413 (a region surrounded by a dotted line in the drawing) existing on the side of the chip 41 having the first side 411, the resistance element 451 and the capacitance element 452 each included in the second shunt element are arranged in the same manner as in the first embodiment. Further, in the first region 413, a pad 461 to be connected to a pad 441 of the chip 41 with a bonding wire 491 and a pad 462 to be connected to a pad 442 of the chip 41 with a bonding wire 492 are arranged. Further, in the first region 413, a connection terminal 481 to which a bias voltage is to be supplied from the voltage bias circuit 471 and a connection terminal 482 to which a ground voltage is to be supplied are arranged.

Further, in the substrate 40, in a second region 414 (a region surrounded by a dotted line in the drawing) existing on the side of the chip 41 having the second side 412, a resistive element 453 and a capacitive element 454 each included in the second shunt element are arranged. Further, in the second region 414, a pad 463 to be connected to a pad 443 of the chip 41 with a bonding wire 493 and a pad 464 to be connected to a pad 444 of the chip 41 with a bonding wire 494 are arranged. Further, in the second region 414, a connection terminal 483 to which a bias voltage is to be supplied from the voltage bias circuit 472 and a connection terminal 484 to which a ground voltage is to be supplied are arranged.

In the description given above, the voltage bias circuits 471 and 472 are provided as separate circuits, but the substrate 40 may be configured such that one voltage bias circuit supplies the bias voltage and the ground voltage.

Thus, the substrate 40 has a configuration in which the chip 41 is placed between the first region 413 and the second region 414. In this configuration, between pads 441 and 442 and pads 443 and 443, the antenna array 42 is placed. In other words, the first region 413, the chip 41, and the second region 414 are sequentially arranged in a direction along a line segment connecting the side 411 and the side 412. Such a configuration can reduce the impedance of the wiring to which the bias voltage is supplied. Further, the chip 41 is placed between the resistance element 451 or the capacitance element 452 and the resistance element 453 or the capacitance element 454. As a result, in the same manner as in the case of the first shunt element, the pads and the second shunt element are symmetrically arranged with respect to an axis passing through the center of the antenna array 42. Examples of axes passing through the center of the antenna array 42 include an axis BX extending in a direction perpendicular to the top surface of the substrate 40 and an axis extending in a direction parallel to the top surface of the substrate 40. Symmetry is determined here based on an axis extending in a direction parallel to the top surface of the substrate. Accordingly, in the substrate 40, a plurality of pairs of first and second shunt elements connected to each other are arranged, and at least two pairs of the plurality of pairs of first and second shunt elements are arranged at positions symmetrical to each other with respect to an axis passing through the center of the antenna array. This improves the directivity of the terahertz wave generated from the antenna array 42 and enhances the front-side intensity of the terahertz wave.

Further, according to the present embodiment, the bias voltage to be applied to the antenna array 42 is supplied from the side of the chip 41 having the two facing sides 411 and 412. As a result, the impedance of the wiring to which the bias voltage is supplied is smaller than in the case where the bias voltage is supplied from the side having any one of the sides of the chip 41, and thus the voltage drop is reduced. Accordingly, the inter-antenna variation of the bias voltage to be applied to the negative differential resistance element of each of the antennas is reduced to improve the uniformity of the antenna output.

The resistor element 451 and the capacitor element 452 included in the second shunt element are connected in parallel with the resistor element 453 and the capacitor element 454. As each of the resistance elements 451 and 453 and the capacitance elements 452 and 454, for example, SMD is adopted, and such an assembly has not only a resistance component and a capacitance component but also parasitic inductance. Thus, by connecting the resistance element 451 and the capacitance element 452 in parallel with the resistance element 453 and the capacitance element 454, parasitic inductance can be reduced and parasitic oscillation can be suppressed.

Also, since the wiring placed in the substrate 40 also has a resistance value, as each of the resistance elements 451 and 453, the resistance of the wiring can also be used, and thus the number of components to be placed on the substrate 40 can be reduced, which is advantageous in size reduction.

Fig. 13 is a diagram illustrating an antenna device according to a modification of the present embodiment. Note that, in the present modification, description of the same components as those in the above-described embodiment is omitted. The configuration of the antenna device 500 shown in fig. 13 corresponds to a configuration obtained by further applying the typical features of the present embodiment to the configuration shown in the third embodiment. In the present modification, the same components as those in the third embodiment are denoted by the same reference numerals, and the description thereof is omitted.

In the antenna device 500, on the side of the top surface of the chip 51 where the first side 511 of the chip 51 exists, the resistive elements 531 and 533 and the pads 541, 542, and 543 are arranged in the same manner as in the third embodiment. Meanwhile, on the side of the chip 51 where the second side 512 facing the first side 511 exists, resistive elements 534 and 535 and pads 544, 545, and 546 are arranged.

Between the first side 511 and the second side 512 of the chip 51, an antenna array 52 in which a plurality of antennas 521 are arranged is placed. Around the antenna array 52, a capacitive element 532 is placed. The capacitance element 532 is connected to each of the resistance elements 531, 533, 534, and 535 to be included in the first shunt element.

The respective one terminals of the resistance elements 531, 533, 534, and 535 are connected to one terminal of the capacitance element 532 via wirings and vias (not shown). The resistive elements 531, 533, 534, and 535 are preferably arranged in the vicinity of the capacitive element 532. Alternatively, the resistive elements 531, 533, 534, and 535 may also be placed on the capacitive element 532 in overlapping relation with the capacitive element 532. The respective other terminals of the resistance elements 531, 533, 534, and 535 are connected to the pad 541 via the bias voltage line 530. A bias voltage line 530 is also placed between the respective antennas 521 in the antenna array 52 to be commonly connected to the respective antennas 521, and a bias voltage is applied to each of the antennas 521. The other terminal of the capacitive element 532 is connected to pads 542 and 545 via wiring and vias (not shown).

On the chip 51, between the pads 541, 542, and 543 and the pads 544, 545, and 546, the resistive elements 531 and 533 and the resistive elements 534 and 535 are arranged. Further, between the resistive elements 531 and 533 and the resistive elements 534 and 535, the antenna array 52 around which the capacitive element 532 is placed. Thus, the pads and the first shunt element are symmetrically arranged with respect to an axis passing through the center of the antenna array 52. Examples of axes passing through the center of the antenna array 52 include an axis CX extending in a direction perpendicular to the top surface of the substrate 50 and an axis extending in a direction parallel to the top surface of the substrate 50. Symmetry is determined here based on an axis extending in a direction parallel to the top surface of the substrate. Accordingly, in the substrate 50, a plurality of pairs of first and second shunt elements connected to each other are arranged, and at least two pairs of the plurality of pairs of first and second shunt elements are arranged at positions symmetrical to each other with respect to an axis passing through the center of the antenna array. This improves the directivity of the terahertz wave generated from the antenna array 52 and enhances the front-side intensity of the terahertz wave.

In the substrate 50, in a first region 513 (a region surrounded by a dotted line in the drawing) existing on the side of the chip 51 having the first side 511, a pad 561 to be connected to a pad 541 of the chip 51 with a bonding wire 591 is placed in the same manner as in the third embodiment. Further, in the first region 513, a pad 562 to be connected to the pad 542 with a bonding wire 592 and a pad 563 to be connected to the pad 543 with a bonding wire 593 are arranged. Also, in the first region 513, resistive elements 551 and 553 and capacitive elements 552 and 554 included in the second shunt element are arranged. Further, in the first region 513, connection terminals 581 and 583 to which bias voltages are to be supplied from the voltage bias circuit 571 and a connection terminal 582 to which a ground voltage is to be supplied are arranged. Note that the interconnection relationship among the respective pads, the second shunt element, and the connection terminals is the same as that described in the third embodiment.

In the description given above, the voltage bias circuits 571 and 572 are provided as separate circuits, but the substrate 50 may be configured such that one voltage bias circuit supplies the bias voltage and the ground voltage.

Also, in the substrate 50, in a second region 514 (a region surrounded by a dotted line in the drawing) existing on the side of the chip 51 having the second side 512, a pad 564 to be connected to the pad 544 of the chip 51 with a bonding wire 594 is placed. Further, in the second region 514, a pad 565 to be connected to the pad 545 with a bonding wire 595 and a pad 566 to be connected to the pad 546 with a bonding wire 596 are arranged. Also, in the second region 514, resistive elements 555 and 557 and capacitive elements 556 and 558 included in the second shunt element are arranged. In the second region 514, connection terminals 584 and 586 to which bias voltages are to be supplied from the voltage bias circuit 572 and a connection terminal 585 to which a ground voltage is to be supplied are arranged. Note that the connection relationship among the respective pads, the second shunt element, and the connection terminals in the second region 514 is also the same as that described in the third embodiment.

Accordingly, the substrate 50 has a configuration in which the chip 51 is placed between the first region 513 and the second region 514. In this configuration, the antenna array 52 is placed between the pad 541 and the pad 544, between the pad 542 and the pad 545, or between the pad 543 and the pad 546. Further, between the resistive elements 551 and 553 and the capacitive elements 552 and 554 and between the resistive elements 555 and 557 and the capacitive elements 556 and 558, the chip 51 is placed. As a result, the pads and the second shunt element are symmetrically arranged with respect to an axis passing through the center of the antenna array 52. Examples of axes passing through the center of the antenna array 52 include an axis CX extending in a direction perpendicular to the top surface of the substrate 50 and an axis extending in a direction parallel to the top surface of the substrate 50. Symmetry is determined here based on an axis extending in a direction parallel to the top surface of the substrate. Accordingly, in the substrate 50, a plurality of pairs of first and second shunt elements connected to each other are arranged, and at least two pairs of the plurality of pairs of first and second shunt elements are arranged at positions symmetrical to each other with respect to an axis passing through the center of the antenna array. This improves the directivity of the terahertz wave generated from the antenna array 52 and enhances the front-side intensity of the terahertz wave.

Further, by supplying the bias voltage from the two facing sides 511 and 512 of the chip 51, the impedance of the wiring to which the bias voltage is supplied decreases, and thus the voltage drop decreases. Accordingly, the inter-antenna variation of the bias voltage to be applied to the negative differential resistance element of each of the antennas is reduced to improve the uniformity of the antenna output.

Further, the resistive element 551 and the capacitive element 552 included in the second shunt element are connected in parallel with the resistive element 553 and the capacitive element 554. Also, the resistive element 555 and the capacitive element 556 included in the second shunt element are connected in parallel with the resistive element 557 and the capacitive element 558. Thus, in the antenna device 500, the number of resistive elements and capacitive elements connected in parallel is greater than the number of resistive elements and capacitive elements connected in parallel in the antenna device 400. Therefore, it is possible to further reduce parasitic inductance included in the resistive element and the capacitive element and suppress parasitic oscillation.

Also, since the wiring placed in the substrate 50 also has a resistance value, as each of the resistance elements 551, 553, 555, and 557, the resistance of the wiring can also be used, and thus the number of components to be placed on the substrate 50 can be reduced, which is advantageous in size reduction.

Fig. 14 is a diagram illustrating an antenna device according to a modification of the present embodiment. The configuration of the antenna device 600 shown in fig. 14 corresponds to a configuration obtained by further applying the typical features of the second embodiment to the configuration of the antenna device 500 shown in fig. 13. Thus, the antenna device according to the present modification is characterized in that the number of bonding wires providing connection between pads in the above-described antenna device is different. In the configuration of the antenna device shown in fig. 14, description of the same components as those of the antenna device 500 shown in fig. 13 is omitted.

As shown in fig. 14, in the antenna device 600, pads 641, 642, and 643 are arranged on a side of the top surface of the chip 61 where the first side 611 of the chip 61 exists. Further, on the side of the chip 61 where the second side 612 thereof facing the first side 611 is present, pads 644, 645 and 646 are arranged.

In the substrate 60, in a first region 613 (region surrounded by dotted lines in the drawing) existing on the side of the chip 61 having the first side 611, pads 661, 662, and 663 are arranged in the same manner as in the configuration shown in fig. 13. Meanwhile, in a second region 614 (a region surrounded by a dotted line in the drawing) of the chip 61 existing on the side having the second side 612, pads 664, 665, and 666 are arranged.

Pad 641 and pad 661 are connected by a plurality of bonding wires 691, pad 642 and pad 662 are connected by a plurality of bonding wires 692, and pad 643 and pad 663 are connected by a plurality of bonding wires 693. Meanwhile, pad 644 and pad 664 are connected with a plurality of bonding wires 694, pad 645 and pad 665 are connected with a plurality of bonding wires 695, and pad 646 and pad 666 are connected with a plurality of bonding wires 696.

Also in the present modification, by electrically connecting a plurality of bonding wires in parallel, the combined inductance of the bonding wires can be reduced and parasitic oscillation can be suppressed in the same manner as in the second embodiment.

(fifth embodiment)

Next, a description will be given of an antenna device according to a fifth embodiment of the present disclosure using fig. 15 and 16. The antenna device according to the fifth embodiment is characterized in that pads are arranged in the vicinity of the respective sides of the chip. In this embodiment, descriptions of the same components as those in other embodiments are omitted.

In the antenna device 700 according to the present embodiment shown in fig. 15, the chip 71 includes pads 741 and 743 for applying bias voltage and a pad 742 for applying ground voltage. The antenna device 700 further includes a pad 741 for applying a bias voltage and a pad 742 for applying a ground voltage.

In the antenna device 700 according to the present embodiment, on the chip 71, the pad 741 is placed in the vicinity of the first side 711, and the pad 742 is placed in the vicinity of the second side 712. Also, on the chip 71, a pad 743 is placed in the vicinity of the third side 713 facing the first side 711, and a pad 744 is placed in the vicinity of the fourth side 714 facing the second side 712. A bias voltage is applied to each of the pads 741 and 743, and a ground voltage is applied to each of the pads 742 and 744. Pads 741, 742, 743, and 744 are arranged around the antenna array 72 so as to surround the antenna array 72.

In the chip 71, the resistive elements 731 and 733 and the capacitive element 732 included in the first shunt element are arranged. One terminal of the resistance element 731 and one terminal of the resistance element 733 are connected to one terminal of the capacitance element 132 via wirings and vias (not shown). Preferably, the resistive element 731 and the resistive element 733 are arranged adjacent to the capacitive element 732. Alternatively, the resistive element 731 may also be placed on the capacitive element 732 in overlapping relation with the capacitive element 732. The other terminal of the resistance element 731 is connected to the pad 741 via the bias voltage line 730, and the other terminal of the resistance element 733 is connected to the pad 743 via the bias voltage line 730. A bias voltage line 730 is also placed between the respective antennas 721 in the antenna array 72 to be commonly connected to the respective antennas 721, and applies a bias voltage. The other terminal of the capacitor 732 is connected to each of the pad 742 and the pad 744 via a wiring and a via (not shown).

In the substrate 70, in a first region 715 existing on the side of the chip 71 having the first side 711, a resistive element 751 and a resistive element 758 included in the second shunt element and a pad 761 to be connected to a pad 741 of the chip 71 with a bonding wire 791 are arranged. In the first region 715, a connection terminal 781 to which a bias voltage is to be supplied from the voltage bias circuit 771 is disposed. One terminal of the resistance element 751 and one terminal of the resistance element 758 are connected to the pad 761, and the pad 761 is connected to the connection terminal 781.

Also, in the second region 716 existing on the side of the chip 71 having the second side 712, the capacitive element 752 and the capacitive element 753 included in the second shunt element, and the pad 762 to be connected to the pad 742 of the chip 71 with the bonding wire 792 are arranged. In addition, in the second region 716, a connection terminal 782 to be supplied with a ground voltage from the voltage bias circuit 772 is placed. One terminal of the capacitive element 752 and one terminal of the capacitive element 753 are connected to a pad 762, and the pad 762 is connected to the connection terminal 782.

Also, in the third region 717 existing on the side of the chip 71 having the third side 713, the resistance elements 754 and 755 included in the second shunt element, and the pad 763 to be connected to the pad 743 of the chip 71 with the bonding wire 793 are arranged. In the third region 717, a connection terminal 783 to which a bias voltage is to be supplied from the voltage bias circuit 773 is disposed. One terminal of the resistance element 754 and one terminal of the resistance element 755 are connected to the pad 763, and the pad 763 is connected to the connection terminal 783.

Also, in the fourth region 718 existing on the side of the chip 71 having the fourth side 714, the resistive elements 756 and 757 included in the second shunt element, and the pads 764 to be connected to the pads 744 of the chip 71 with the bonding wires 794 are arranged. In the fourth region 718, a connection terminal 784 to which a ground voltage is to be supplied from the voltage bias circuit 774 is disposed. One terminal of the resistance element 756 and one terminal of the resistance element 757 are connected to the pad 764, and the pad 764 is connected to the connection terminal 784.

In the vicinity of a first corner 726 formed between a first side 711 and a second side 712 of the chip 71, a resistive element 751 and a capacitive element 752 are arranged, and the other terminal of the resistive element 751 is connected to the other terminal of the capacitive element 752. Meanwhile, in the vicinity of a second corner 727 formed between the second side 712 and the third side 713 of the chip 71, a resistive element 753 and a capacitive element 754 are arranged, and the other terminal of the resistive element 753 is connected to the other terminal of the capacitive element 754. Further, in the vicinity of a third corner 728 formed between the third side 713 and the fourth side 714 of the chip 71, a resistive element 755 and a capacitive element 756 are arranged, and the other terminal of the resistive element 755 is connected to the other terminal of the capacitive element 756. Meanwhile, in the vicinity of a fourth corner 729 formed between the fourth side 714 and the first side 711 of the chip 71, a resistive element 757 and a capacitive element 758 are arranged, and the other terminal of the resistive element 757 is connected to the other terminal of the capacitive element 758.

The resistive element 751 and the capacitive element 752, the resistive element 753 and the capacitive element 754, the resistive element 755 and the capacitive element 756, and the resistive element 757 and the capacitive element 758 included in the second shunt element are electrically connected in parallel to each other by a connection relationship between the resistive element and the capacitive element. This can further reduce parasitic inductance included in each of the elements and suppress parasitic oscillation.

In fig. 15, the voltage bias circuits 771, 772, 773, and 774 are provided as separate circuits, but the substrate 70 may be configured such that the bias voltage and the ground voltage are supplied by one voltage bias circuit.

Also, in fig. 15, the resistive element 751 and the capacitive element 752 each included in the second shunt element are arranged such that the direction in which the two terminals of the resistive element 751 are arranged and the direction in which the two terminals of the capacitive element 752 are arranged are perpendicular to each other. Further, the resistive element 753 and the capacitive element 754, the resistive element 755 and the capacitive element 756, and the resistive element 757 and the capacitive element 758 are also configured to be similarly arranged.

Also, since the wiring placed in the substrate 70 also has a resistance value, as each of the resistance elements 751, 753, 755, and 757, the resistance of the wiring can also be used, and thus the number of components to be placed on the substrate 40 can be reduced, which is advantageous in size reduction.

Thus, in the present embodiment, on the side where four individual sides of the chip 71 exist, the respective pads are arranged, and the bias voltage or the ground voltage is supplied from each side. In other words, this configuration is as follows. The pads, the chips 71, and the pads are sequentially arranged in a direction along a line segment connecting two facing sides, and the pads, the chips 71, and the pads are sequentially arranged in a direction along a line segment connecting other facing sides. The directions along the line segments connecting the two facing sides and the directions along the line segments connecting the other two facing sides intersect each other. Due to the configuration in the present embodiment, the impedance of the wiring to which the bias voltage is supplied becomes smaller than that in the case where the bias voltage or the ground voltage is supplied from one side of either or both of the existing sides of the chip 71, and thus the voltage drive is reduced. Accordingly, the inter-antenna variation of the bias voltage to be applied to the negative differential resistance element of each of the antennas is reduced to improve the uniformity of the antenna output.

Further, since the pads are arranged on the sides of the chip 71 where the respective sides exist, a plurality of bonding wires can be electrically connected in parallel while increasing the size of the pads. This can reduce the combined inductance of the bond wires and further suppress parasitic oscillations.

Further, by disposing the resistive element and the capacitive element of the second shunt element in the vicinity of the four corners 726 to 729 of the chip 71 on the substrate 70, the space of the substrate can be effectively used, the substrate size is reduced, and the manufacturing cost is reduced.

The pads and the second shunt element are symmetrically arranged with respect to an axis passing through the center of the antenna array 72. Examples of axes passing through the center of the antenna array 72 include an axis DX extending in a direction perpendicular to the top surface of the substrate 70 and an axis extending in a direction parallel to the top surface of the substrate 70. Symmetry is determined here based on an axis extending in a direction parallel to the top surface of the substrate. Accordingly, on the substrate 70, a plurality of pairs of first and second shunt elements connected to each other are arranged, and at least two pairs of the plurality of pairs of first and second shunt elements are arranged at positions symmetrical to each other with respect to an axis passing through the center of the antenna array. This improves the directivity of the terahertz wave generated from the antenna array 72 and enhances the front-side intensity of the terahertz wave.

Fig. 16 is a diagram illustrating an antenna device according to a modification of the present embodiment. In the present modification, description of the same components as those in the above-described embodiment is omitted. In the antenna device 800 shown in fig. 16, in the vicinity of each of the corners 826 to 829 of the chip 81, a resistive element 851 and a capacitive element 852, a resistive element 853 and a capacitive element 854, a resistive element 855 and a capacitive element 856, and a resistive element 857 and a capacitive element 858 are arranged. Further, the resistive elements 851, 853, 855, and 857 and the capacitive elements 852, 854, 856, and 858 are arranged obliquely with respect to respective directions in which the respective sides of the chip extend. Also, the direction in which the two terminals of the resistive element 851 are arranged is the same as the direction in which the two terminals of the capacitive element 852 are arranged, and the resistive element 853 and the capacitive element 854, the resistive element 855 and the capacitive element 856, and the resistive element 857 and the capacitive element 858 are similarly arranged.

Since the respective elements are arranged in this manner, it is possible to shorten the wiring connecting the resistive element, the capacitive element, and the pad, reduce parasitic inductance included in the wiring, and suppress parasitic oscillation.

(sixth embodiment)

Next, a description will be given of an antenna array in an antenna device according to a sixth embodiment of the present disclosure using fig. 17 to 22. In this embodiment, descriptions of the same components as those in other embodiments are omitted.

Fig. 17 illustrates an equivalent circuit diagram of the antenna device 900 according to the present embodiment. An example of the configuration of the equivalent circuit diagram shown in fig. 17 corresponds to the configuration in the equivalent circuit diagram of the antenna device 100 according to the first embodiment shown in fig. 5, in which the antennas 121 in the antenna array 12 are arranged in a 3×3 matrix configuration. The antenna array 912 has 3×3 negative differential resistive elements r11, r12, r13, r21, r22, r23, r31, r32, and r33, resistive elements Rai (i=1, 2,3,..12), and capacitive elements Cai (i=1, 2,3,..12). In the antenna array 912, a negative differential resistance element and a plurality of third shunt elements in which the resistance element and the capacitance element are connected in series are arranged. Further, the 3×3 negative differential resistance element and the plurality of third shunt elements are configured to be connected in parallel with each other. One terminal of the negative differential resistance element, one terminal of the resistance element Rai of the plurality of third shunt elements, and one terminal of the resistance element Rc of the first shunt element are commonly connected. Meanwhile, the other terminal of the resistance element Rai is connected to one terminal of the capacitance element Cai. Further, the other terminal of the negative differential resistance element and the other terminal of the capacitance element Cai in the plurality of third shunt elements are connected to the ground potential. Other components of the antenna array 912 are the same as those in fig. 5, and thus a description thereof is omitted here.

In the antenna array 912, the combined resistances of the 3×3 negative differential resistance elements r11, r12, r13, r21, r22, r23, r31, r32, and r33 correspond to the resistance r shown in fig. 5. Meanwhile, the combined impedance of the parasitic impedance of the third shunt element and the wiring corresponds to the impedance Z shown in fig. 5.

Fig. 18 is an example of a top view of an antenna array 912 deployed in a 3×3 matrix configuration corresponding to the equivalent circuit diagram of fig. 17. Fig. 19 is a cross-sectional view taken along line C-C' in fig. 18. A description of the configuration described using fig. 4 is omitted, and the same components as those in fig. 4 are denoted by the same reference numerals. As described using fig. 4, adjacent antennas are coupled to each other via microstrip lines 125a to 125h, and injection-locked (synchronized) with each other at the oscillation frequency fTHz of the terahertz wave. Fig. 18 illustrates an example of a configuration in which one antenna includes two negative differential resistance elements 127a and 127 b. In order to improve the directivity of the terahertz wave, the two negative differential resistance elements 127a and 127b are preferably arranged symmetrically with respect to a line passing through the center of one antenna.

In order to suppress parasitic oscillations in the frequency band below the oscillation frequency fTHz, a bias voltage line 130 is provided with a third shunt element. The third shunt element is arranged in parallel with the negative differential resistance element so as to provide a structure that causes a short circuit in a frequency band lower than fTHz to suppress parasitic oscillation. Each of the third shunt elements has a structure in which a resistive element or an element obtained by connecting a resistor and a capacitor in series is placed in parallel with a negative differential resistive element. In the third shunt element, the values of the resistance and the capacitance are such that the impedance of the element is equal to or slightly lower than the absolute value of the combined negative differential resistance of the plurality of negative differential resistance elements disposed adjacent thereto.

In fig. 18, in a region surrounded by a broken line 137' in a plan view, a conductor layer 137 serving as one electrode of the capacitive element included in the third shunt element is placed. Meanwhile, in the region surrounded by the broken wire 138', a resistor 138 serving as a resistance element is placed. The conductor layer 137 and the resistor 138 are placed in a layer below the wiring layer forming the bias voltage line 130. The third shunt element is arranged around each antenna. The bias voltage line 130 is connected to the metal layer 123 forming a part of each of the antennas to supply a bias voltage, and each of the third shunt elements is preferably placed in the vicinity of the connection portion thereof, and may be appropriately placed between the antennas. Such placement allows for a configuration in which one of the third shunt elements is shared with its neighboring two antennas. As a result, layout efficiency improves to allow chip size reduction, and parasitic oscillation is easily suppressed due to an increase in flexibility of size adjustment of capacitance and resistance of the shunt element.

As shown in the cross-sectional view of fig. 19, a dielectric layer 136 is disposed on the ground metal layer 124. Note that since the dielectric layer 136 is used as a dielectric material of the capacitor of the third shunt element, silicon nitride (e=7) having a relatively high dielectric constant is preferably used for downsizing of the MIM capacitor structure.

Further, on the dielectric layer 136, a conductor layer 137 is stacked. Thus, in the antenna array 912, a metal-insulator-metal (MIM) capacitor structure in which the ground metal layer 124, the dielectric layer 136, and the conductor layer 137 are stacked in order is formed, which corresponds to the capacitive element of each of the third shunt elements. This capacitive element is placed in a layer below the bias voltage line 130 placed between the antennas. The conductor layer 137 is placed in a layer between the bias voltage line 130 and the ground metal layer 124. The resistor 138 is connected to the conductor layer 137, and the resistor 138 is connected to the bias voltage line 130. This resistor 138 corresponds to the resistive element of each of the third shunt elements.

Thus, in the present embodiment, the ground metal layer 124 and the bias voltage line 130 are electrically connected via the capacitance element and the resistance element each included in the third shunt element. A plurality of third shunt elements are arranged in the array antenna in such a way as to be connected to the bias voltage line 130 at respective portions between the antennas. In the present embodiment, the third shunt element is connected to the ground metal layer 124, but need only be connected to a conductive layer of a fixed potential, and may also be connected to another conductive layer.

Note that the configuration in which the third shunt element is placed at the node of the high-frequency electric field at the oscillation frequency fTHz which remains unchanged in the antenna is a configuration which has high impedance at the frequency fTHz and is more suitable for selectively oscillating only the high frequency at the frequency fTHz. However, there is a risk of unexpected low frequency multimode oscillations occurring as a result of the increase in the number of arrays in the antenna array and the sharing of bias voltage lines. Thus, in the present embodiment, the bias voltage line 130 in the array antenna is configured to be set to an impedance lower than that of the negative resistance element in a frequency band lower than the oscillation frequency fTHz. This can suppress oscillation of another mode even when the number of arrays in the antenna array increases, and allows stable single-frequency oscillation in the terahertz band to be obtained. In the third shunt element, particularly at 10GHz or higher, parasitic oscillation in a frequency band smaller than the frequency fTHz can be effectively suppressed.

Fig. 20 is a top view of an antenna array 1012, which is a modification of the antenna array 912 shown in fig. 18, and fig. 21 is a cross-sectional view along a line D-D' in fig. 20. For the same components as those in fig. 18 and 19, the same reference numerals are used, and the description thereof is omitted. The antenna array 1012 is different from the antenna array 912 shown in fig. 18 and 19 in that each of the resistive elements included in the third shunt element includes a resistor 138a and a resistor 138b.

As shown in fig. 20, in the antenna array 1012, a resistor 138a and a resistor 138b are arranged between the antenna 1112 and the antenna 1113. The two resistors 138a and 138b correspond to the resistive element of each of the third shunt elements, and are connected in parallel to be connected in series to the capacitive element 137. The resistance elements 138a and 138b are arranged in the vicinity of the connection portions between the antennas 1112 and 1113 and the bias voltage line 130, and are arranged in a space created by patterning and removal of the wiring layer forming the bias voltage line 130.

As shown in the cross-sectional view of fig. 21, each of the resistor 138a and the resistor 138b is placed at the same height as the bias voltage line 130. One end portions of the resistor 138a and the resistor 138b are connected to the bias voltage line 130, and the other end portions thereof are connected to the conductor layer 137 by using the same wiring layer as that of the bias voltage line 130.

The third shunt element placed in the region 137″ that is not interposed between the antenna 1111 and the other antenna at the end of the antenna array 1012 may also be configured such that either one of the resistor 138a and the resistor 138b (138 a in the drawing) is placed as a resistive element.

The configuration of the antenna array 1012 shown in fig. 20 and 21 is only required so that the wiring layer forming the bias voltage line 130 is removed by patterning at the position where the resistor 138a and the resistor 138b are placed, and the material forming the resistor is formed in the resulting space. As a result, manufacturing becomes easier than in the conventional antenna array, and occurrence of defects can also be suppressed.

Additional description of the first, second and third shunt elements will be given herein using fig. 22. Fig. 22 illustrates an example of a configuration in which pads are arranged along two facing sides of a chip described in the fourth embodiment and the pads are connected with a plurality of bonding wires. Note that, in the following description, the same components as those described in the fourth embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

Each of the first shunt elements includes a resistive element 531 and a capacitive element 532, and is placed around the antenna array 52 in the chip 51. As the capacitance element 532, a mim capacitor is suitable.

Each of the second shunt elements includes a resistive element 551 and a capacitive element 552, and is placed on the substrate 50 on which the chip 51 is to be mounted. As the resistive element 551 and the capacitive element 552, a Surface Mount Device (SMD) is suitably used, and as the capacitive element 552, for example, a ceramic capacitor is used.

Each of the third shunt elements includes a resistive element (not shown) and a capacitive element 521, and is placed in the chip 51 to be placed in the antenna array 52 similarly to the first shunt element. As the capacitance element 521, a mim capacitor is suitable.

The sizes of the areas of the respective capacitive elements included in the three shunt elements or the capacitance values thereof are preferably set larger in the order of the third shunt element, the first shunt element, and the second shunt element (capacitive element 521< capacitive element 532< capacitive element 552). Suitable arrangements may be made as long as the capacitance value of the capacitive element 521 is at least 1pF and less than 100pF, the capacitance value of the capacitive element 532 is at least 100pF and less than 10nF, and the capacitance value of the capacitive element 552 is at least 10nF and less than 100 μf. Suitable arrangements may also be made as long as the resistance value of each of the first shunt element, the second shunt element, and the third shunt element is at least 0.01Ω and less than 10Ω.

The number of third shunt elements is determined according to the number of antennas in the antenna array 2, and is preferably more than the number of first shunt elements and more than the number of second shunt elements. This can suppress parasitic oscillation and improve output.

In the case where the number of antennas in the antenna array 2 is small in order to adjust the output to a low level or the like, the number of third shunt elements may also be set smaller than the number of first shunt elements and the number of second shunt elements.

When the number of second flow dividing elements is set to the number of first flow dividing elements or more, the number of second flow dividing elements connected in parallel may be increased. As a result, the parasitic inductance of the SMD can be reduced, thereby suppressing parasitic oscillation. Furthermore, as a result of the reduced number of first shunt elements, the chip area can be reduced, which contributes to a reduction in the cost of the antenna array.

When the number of second shunt elements is smaller than the number of first shunt elements, the number of SMDs included in the second shunt elements may be reduced. Since the area required for mounting the SMDs on the substrate is relatively large, the reduction in the number of SMDs allows the substrate to be reduced in size, which contributes to the reduction in cost of the antenna array.

As the resistor forming the resistance element of the first shunt element and the third shunt element in the chip, ta, ti, mo, mn, al, ni, nb, W, ru and the like can be suitably used. Also, as the resistor, an alloy film, an oxide film, a nitride film, a silicide film, or the like (for example, tiW, tiN, taN, WN, WSiN, taSiN, nbN, moN, mnO, or RuO) thereof can be suitably used. Further, as the resistor, polysilicon, a diffusion resistance film obtained by doping Si with impurities, or the like can be suitably used.

As materials of the wiring and the conductive layer each used in the chip, a material having a resistivity of not more than 1X 10-6Ω·m is preferable. Specifically, as the material, a metal or a metal compound such as Ag, au, cu, W, ni, cr, ti, al, auIn alloy or TiN is suitably used.

The dielectric layer included in the MIM capacitor is required to have insulating properties (properties that appear as an insulator/high resistor that is non-conductive to DC voltage), blocking properties (properties that prevent diffusion of metallic materials for electrodes), and workability (properties that allow processing with submicron precision). As a specific example of a material satisfying this requirement, an inorganic insulator material such as silicon dioxide (epsilon=4), silicon nitride (epsilon=7), aluminum oxide, or aluminum nitride is suitably used.

The negative resistance element includes an electrode and a semiconductor layer, and when the electrode is a conductor ohmically connected to the semiconductor layer, the electrode is adapted to reduce ohmic loss or RC delay generated by the series resistance. In the case of using an electrode as an ohmic electrode, as a material thereof, for example, ti/Pd/Au, ti/Pt/Au, auGe/Ni/Au, tiW, mo, erAs, or the like is suitably used.

(seventh embodiment)

A description will be given of a detection system according to the present embodiment using fig. 23. The detection system may also be a system capable of capturing images, such as a camera system. In the present embodiment, by way of example, a camera system will be described. Fig. 23 is a schematic diagram for illustrating a configuration of the camera system 2300 using terahertz waves.

The camera system 2300 has an oscillation device 2301, a detection device 2302, and a processing unit 2303. As for the oscillation device 2301, the antenna device described in each of the embodiments can be applied. The detection device 2302 may detect electromagnetic waves transmitted from the antenna device, and may also be an antenna device using another semiconductor element such as, for example, a schottky barrier diode. The terahertz wave emitted from the oscillation device 2301 is reflected by the object 2305 and detected by the detection device 2302. The processing unit 2303 processes signals detected by the detecting device 2302. The image data generated by the processing unit 2303 is output from the output unit 2304. Such a configuration allows terahertz images to be acquired.

In the oscillation device 2301 and the detection device 2302, an optical unit may also be provided. Each of the optical units includes at least one material transparent to terahertz waves, such as polyethylene, teflon (registered trademark), high-resistance silicon, or polyolefin resin, and may further include a plurality of layers.

The camera system described in the present embodiment is merely exemplary, and may be another form. In particular, the information to be acquired by the system is not limited to image information, and a detection system that performs signal detection may also be used.

Each of the embodiments shows only a specific example in realizing the present application, and since these, the technical scope of the present application should not be construed as limiting. In other words, the present application may be embodied in various forms without departing from its technical scope or essential characteristics.

The present application claims priority based on japanese patent application No.2021-015981 filed on 3 of 2 nd of 2021 and priority based on japanese patent application No.2021-199839 filed on 9 of 12 th of 2021, and all contents disclosed therein are incorporated by reference.

REFERENCE SIGNS LIST

A 12 antenna array, a 17 voltage bias circuit, a 100 antenna device, 131, 151 resistive elements, 132, 152 capacitive elements, 1200 resonant circuits, 1300 first shunt elements, 1500 second shunt elements.

Claims

1. An antenna apparatus that transmits or receives electromagnetic waves, the antenna apparatus comprising:

an antenna array in which a plurality of antennas are arranged, each antenna including a negative differential resistance element and a resonance circuit;

a voltage bias circuit that applies a voltage to the antenna array;

a first shunt element connected between the antenna array and the voltage bias circuit in parallel relation to each of the negative differential resistance element and the voltage bias circuit, and in which a first resistor and a first capacitor of the first shunt element are connected in series; and

A second shunt element connected between the first shunt element and the voltage bias circuit in parallel relation to each of the negative differential resistance element and the voltage bias circuit, and in which a second resistor and a second capacitor of the second shunt element are connected in series, wherein

Each of the first shunt element and the second shunt element has a low impedance with respect to a resistance value of the negative differential resistance element serving as a reference.

2. The antenna device according to claim 1,

wherein the following expressions (1) to (3) are satisfied:

Rp+1/(2π×f×Cp)<r ... (1)

Rc+1/(2π×f×Cc)<r ... (2)

L/(Cc×r)<Rc ... (3)

where r is an absolute value of a resistance value of the negative differential resistance element, rp is a resistance value of the second resistor, cp is a capacitance value of the second capacitor, rc is a resistance value of the first resistor, cc is a capacitance value of the first capacitor, L is an inductance of a path connecting the first shunt element and the second shunt element, and f is a frequency smaller than a resonance frequency of the resonance circuit.

3. The antenna device according to claim 1 or 2,

wherein the inductance L of the path connecting the first shunt element and the second shunt element satisfies the following expression (4):

L≤5 nH ... (4)

Wherein, in the case where the path is divided into a first portion in which the cross section of the path can be approximated to a circular shape and a second portion in which the cross section of the path can be approximated to a quadrangular shape, the inductance L1 of the first portion is calculated according to the following expression (5), and the inductance L2 of the second portion is calculated according to the following expression (6):

L1＝0.2×l1×[ln(4×l1/d)-0.75] ... (5)

L2＝0.2×l2×[ln{2×l2/(w+h)}+0.2235]×(w+h)/l2+0.5] ... (6)

where l1 is the length of the first portion, d is the diameter of the cross section of the first portion, l2 is the length of the second portion, w is the width of the second portion, and h is the thickness of the second portion.

4. The antenna device according to claim 1 to 3,

wherein a plurality of pairs of first and second flow dividing elements are arranged, and

wherein at least two pairs of first and second shunt elements are placed at positions symmetrical to each other with respect to an axis passing through the center of the antenna array.

5. The antenna device according to claim 4,

wherein the two pairs of first and second shunt elements are arranged such that the antenna array is interposed between the two pairs of first and second shunt elements.

6. The antenna device according to claim 4 or 5,

Wherein the first shunt element is arranged on a chip, the antenna array is to be placed on the chip,

wherein the chip is a chip having a quadrangular shape, and

wherein the second shunt element comprised in each pair of first and second shunt elements is arranged in the vicinity of a corner of the chip.

7. The antenna device according to claim 4,

wherein the second shunt elements comprised in said respective two pairs of first and second shunt elements are connected in parallel.

8. The antenna device according to any of claims 1-7,

wherein a first shunt element is placed on the chip on which the antenna array is to be placed, and

wherein the second shunt element is placed on the substrate on which the chip is to be placed.

9. The antenna device according to claim 8,

wherein the path connecting the first shunt element and the second shunt element comprises a first pad placed on the chip and a second pad placed on the substrate, an

Wherein a bias voltage is supplied to the antenna array via each of the first pad and the second pad.

10. The antenna device of claim 9, further comprising:

A third pad disposed on the chip and a fourth pad disposed on the substrate,

wherein a ground voltage is supplied to the antenna array via each of the third pad and the fourth pad,

wherein the chip is a chip having a quadrangular shape,

wherein the bias voltage is supplied to the antenna array from a side of the chip where the first side thereof exists via each of the first pad and the second pad, and

wherein the ground voltage is supplied to the antenna array from a side of the chip where a second side thereof is different from the first side via each of the third pad and the fourth pad.

11. The antenna device according to claim 9 or 10,

wherein the first pad and the second pad are connected using a plurality of bonding wires connected in parallel.

12. The antenna device according to any of claims 8-10,

wherein the second resistor is a wiring placed in the substrate.

13. An antenna apparatus that transmits or receives electromagnetic waves, the antenna apparatus comprising:

a chip having an antenna array in which a plurality of antennas are arranged, each antenna including a negative differential resistance element and a resonance circuit;

A substrate on which the chip is to be placed; and

a voltage bias circuit applying a voltage to the antenna array, wherein

The chip has:

a first shunt element connected in parallel with each of the negative differential resistance element and the voltage bias circuit and including at least a first capacitor; and

a plurality of pads including at least each of the first pad and the second pad to supply a predetermined voltage to the antenna array,

the substrate has:

a second shunt element connected in parallel with each of the negative differential resistance element and the voltage bias circuit and including at least a second capacitor, and further disposed in the substrate, and wherein

The antenna array is located between the first pad and the second pad.

14. The antenna device according to any of claims 1-13,

wherein the combined resistance value of the negative differential resistive elements in the antenna array is not greater than 1Ω.

15. The antenna device according to any of claims 1-14,

wherein the length of the path connecting the first and second shunt elements is no greater than 4mm.

16. The antenna device according to claim 15,

wherein the length of the path connecting the first and second shunt elements is no greater than 2mm.

17. The antenna device according to any of claims 1-16,

wherein the frequency band of electromagnetic waves comprises at least a portion of a frequency band of at least 30GHz and not greater than 30 THz.

18. The antenna device according to any of claims 1-17,

wherein the negative differential resistance element is a resonant tunneling diode.

19. The antenna device according to any of claims 1-18,

wherein the first capacitor is a MIM (metal-insulator-metal) capacitor.

20. The antenna device of any of claims 1-19, further comprising:

a third shunt element connected in parallel with the negative differential resistive element in the antenna array and including at least a third capacitor.

21. The antenna device according to claim 20,

wherein a plurality of third shunt elements are arranged between the antennas.

22. The antenna device according to claim 21,

wherein each of the third shunt elements is shared between two antennas each adjacent to the third shunt element.

23. The antenna device according to claim 20,

wherein the respective areas or capacitance values of the third capacitor, the first capacitor, and the second capacitor become larger stepwise in order.

24. The antenna device according to claim 20,

wherein the number of third flow splitting elements is greater than the number of first flow splitting elements and greater than the number of second flow splitting elements.

25. The antenna device according to claim 20,

wherein the number of third flow splitting elements is less than the number of first flow splitting elements and less than the number of second flow splitting elements.

26. The antenna device according to any of claims 1-19,

wherein the number of second shunt elements is greater than the number of first shunt elements.

27. The antenna device according to any of claims 1-19,

wherein the number of second flow splitting elements is smaller than the number of first flow splitting elements.

28. A camera system, comprising:

the antenna device according to any one of claims 1 to 27;

a detection device for detecting electromagnetic waves transmitted from the antenna device; and

a processing unit that processes signals from the detection device.