CN116846189A

CN116846189A - ACOT control circuit and chip applied to voltage converter

Info

Publication number: CN116846189A
Application number: CN202310800375.5A
Authority: CN
Inventors: 刘胜; 郝军哲
Original assignee: Junying Semiconductor Shanghai Co ltd
Current assignee: Junying Semiconductor Shanghai Co ltd
Priority date: 2023-06-30
Filing date: 2023-06-30
Publication date: 2023-10-03

Abstract

Embodiments of the present disclosure provide an ACOT control circuit, a chip, applied to a voltage converter, the ACOT control circuit being a fast ACOT control circuit with internal dual ramp compensation, comprising: the device comprises an error amplifying circuit, a double-slope compensation circuit, a pulse width modulation comparator and a conduction time control circuit, wherein the double-slope compensation circuit is used for generating a double-slope signal, and the double-slope signal and a voltage outer ring output signal are overlapped to generate a compensated outer ring output signal; then comparing the compensated outer loop output signal with an output voltage feedback signal to obtain a first pulse width modulation signal; finally, after the upper tube of the voltage converter is turned on and the preset conduction time passes through according to the conduction time control circuit, if the first pulse width modulation signal is still at a high level, the preset conduction time signal is shielded, and the conduction time is automatically prolonged. The problem that the output voltage undershoot generated when the load jump occurs in the voltage converter in the conventional ACOT control scheme is overlarge is solved.

Description

ACOT control circuit and chip applied to voltage converter

Technical Field

The embodiment of the disclosure relates to the technical field of integrated circuits, in particular to an ACOT control circuit and an ACOT control chip applied to a voltage converter.

Background

The self-adaptive constant on-time (ACOT) control voltage converter has the advantages of high transient response speed, simple design, high light load efficiency, relatively stable frequency when the input/output duty ratio is changed, and the like, and is widely applied to DC-DC power chips of consumer or industrial control types.

In general, taking control of a Buck voltage converter as an example, an ACOT control Buck voltage converter mainly includes an inner ring and an outer ring. The voltage outer loop formed by the error amplifying circuit (EA) with frequency compensation mainly plays a role of stabilizing the average value of the output voltage. A PWM comparator based voltage inner loop which, upon detection of an output voltage (V _out ) When the voltage is lower, a trigger signal is given to turn on the upper tube of the Buck voltage converter, and when the set conduction time (t _on ) Then the upper pipe is turned off again; next, after a set minimum off time (t _off，min ) Then, if the PWM comparator detects that the output voltage is lower again, the upper tube is turned on again; the above process is repeated.

In the most primitive Constant-on-time (COT) control, the on-time is fixed, so the switching frequency changes when the input-output duty ratio D changes. Taking Buck voltage converter as an example, the switching frequency f _sw And on time t _on The relation of (2) is: f (f) _sw ＝D/t _on 。

ACOT control has a conduction time t compared to COT control _on Can adaptively change in equal proportion with the change of the input/output duty ratio D, thereby ensuring the switching frequency f _sw Is relatively stable. However, when the load jumps, its on-time is still unchanged, so its transient response is equivalent to the original COT control scheme. Because the on time of the original COT control scheme is fixed, the rising slope of the inductance current is limited, and therefore, when the load current is rapidly switched from light load to heavy load (load jump), the output capacitor cannot be rapidly charged, and the undershoot (undershoot) of the output voltage is overlarge.

In summary, the problem that the output voltage undershoot generated by the ACOT control scheme when the load jump occurs in the voltage converter is needed to be solved.

Disclosure of Invention

The embodiment described herein provides an ACOT control circuit and a chip applied to a voltage converter, and aims to solve the problem that the output voltage undershoot generated when the load jump of the voltage converter occurs in the existing ACOT control scheme is too large.

According to a first aspect of the present disclosure, there is provided an ACOT control circuit applied to a voltage converter, the ACOT control circuit including: the voltage converter comprises an error amplifying circuit, a double-slope compensating circuit, a pulse width modulation comparator and a conduction time control circuit, wherein the error amplifying circuit is configured to receive a feedback signal of the output voltage of the voltage converter and compare the feedback signal with a reference voltage to obtain a voltage outer ring output signal; the dual-slope compensation circuit is configured to generate a dual-slope signal based on an input voltage and an output voltage of the voltage converter, and superimpose the dual-slope signal and the voltage outer-loop output signal to generate a compensated outer-loop output signal, wherein the slope of the dual-slope signal is related to the slope of an inductance current of the voltage converter; the pulse width modulation comparator is configured to compare the compensated outer loop output signal with the feedback signal to obtain a first pulse width modulation signal; the on-time control circuit is used for generating a second pulse width modulation signal for controlling the upper tube and the lower tube of the voltage converter, and is configured to switch on the upper tube of the voltage converter according to the first pulse width modulation signal and shield a preset on-time signal if the first pulse width modulation signal is still at a high level after a preset on-time is passed, and the switch of the upper tube is determined by the height of the first pulse width modulation signal.

Optionally, the on-time control circuit includes: the switching device comprises a preset switching time control circuit, a shortest switching time control circuit, an OR gate and three NAND gates, wherein the preset switching time control circuit is configured to determine the preset switching time according to the input/output duty ratio of the voltage converter, and generate a first indication signal according to the second pulse width modulation signal and the preset switching time, and the first indication signal is used for indicating whether to enter the preset switching time or not; the shortest turn-off time control circuit is configured to generate a second indicating signal according to the second pulse width modulation signal and the shortest turn-off time, wherein the second indicating signal is used for indicating whether the shortest turn-off time is reached; the two input ends of the OR gate are respectively coupled with the first indication signal and the first pulse width modulation signal, the output end of the OR gate is coupled with one input end of a second NAND gate, the two input ends of the first NAND gate are respectively coupled with the second indication signal and the first pulse width modulation signal, and the output end of the first NAND gate is coupled with one input end of a third NAND gate; the other input end of the second NAND gate is coupled with the output end of the third NAND gate, the output end of the second NAND gate is coupled with the other input end of the third NAND gate, and the output end of the third NAND gate is used as the output end of the on-time control circuit and outputs the second pulse width modulation signal.

Optionally, the dual ramp compensation circuit includes: a current generation circuit configured to generate a first current proportional to a voltage difference between the input voltage and the output voltage and a second current proportional to the output voltage from the input voltage and the output voltage; the signal compensation circuit is configured to charge and discharge a compensation capacitor according to the current generated by the current generation circuit to generate the double-slope signal, and superimpose the double-slope signal and the voltage outer ring output signal to generate a compensated outer ring output signal.

Optionally, the current generating circuit includes: the first current generation circuit is configured to generate the first current by scaling and low-pass filtering the input voltage and then differencing the second current; the second current generation circuit is configured to generate the second current after scaling and low-pass filtering the output voltage.

Optionally, the first current generating circuit includes: the circuit comprises a first voltage dividing resistor pair, a first low-pass filter module, a first operational amplifier, first to third transistors and a first resistor, wherein the first voltage dividing resistor pair is coupled between the input voltage and a ground terminal; the first low-pass filter module is coupled between the middle node of the two divider resistors in the first divider resistor pair and the positive input end of the first operational amplifier; the negative input end of the first operational amplifier is respectively coupled with one end of the first resistor and the source electrode of the first transistor, and the output end of the first operational amplifier is coupled with the grid electrode of the first transistor; the drain electrode of the first transistor is respectively coupled with the drain electrode of the second transistor, the grid electrode of the second transistor and the grid electrode of the third transistor; the source electrode of the second transistor and the source electrode of the third transistor are both coupled with a power supply voltage, and the drain electrode of the third transistor is coupled with the second current generated by the second current generating circuit and outputs the first current; the other end of the first resistor is coupled with the grounding end; the second current generation circuit includes: the second voltage division resistor pair, the second low-pass filter module, the second operational amplifier, the fourth transistor, the fifth transistor and the two second resistors, wherein the second voltage division resistor pair is coupled between the output voltage and the ground terminal; the second low-pass filter module is coupled between the middle node of the two divider resistors in the second divider resistor pair and the positive input end of the second operational amplifier; the negative input end of the second operational amplifier is respectively coupled with one end of the first second resistor, the source electrode of the fourth transistor, the source electrode of the fifth transistor and one end of the second resistor, and the output end of the second operational amplifier is respectively coupled with the grid electrode of the fourth transistor and the grid electrode of the fifth transistor; the drain electrode of the fourth transistor generates the second current and is coupled with the drain electrode of the third transistor in the first current generation circuit, and the drain electrode of the fifth transistor outputs the second current; the other ends of the two second resistors are coupled to the ground terminal.

Optionally, the signal compensation circuit includes: the compensation capacitor, two first current sources, two second current sources and a sixth-twelfth transistor, wherein the current value of the first current source is equal to the value of the first current, the current value of the second current source is equal to the value of the second current, one end of the first current source and one end of the first second current source are both coupled with a power supply voltage, the other end of the first current source is respectively coupled with the drain electrode of the sixth transistor and the source electrode of the eighth transistor, and the other end of the first second current source is respectively coupled with the drain electrode of the eighth transistor, one end of the compensation capacitor, the drain electrode of the ninth transistor and one end of the second first current source; the source electrode of the sixth transistor is respectively coupled with the drain electrode of the seventh transistor and the other end of the compensation capacitor, and the source electrode of the seventh transistor is respectively coupled with one end of the second current source and the source electrode of the ninth transistor; the source electrode of the tenth transistor is coupled with the other end of the compensation capacitor, and the drain electrode of the tenth transistor is coupled with one end of the compensation capacitor; the drain electrode of the eleventh transistor is coupled with the source electrode of the tenth transistor and the source electrode of the eleventh transistor respectively, and the source electrode of the twelfth transistor is coupled with the drain electrode of the tenth transistor and the drain electrode of the twelfth transistor respectively; the other end of the second first current source and the other end of the second current source are coupled with a grounding end; the grid electrode of the sixth transistor is controlled by a first clock signal, the grid electrode of the seventh transistor is controlled by a second clock signal, the grid electrode of the eighth transistor is controlled by an opposite signal of the first clock signal, the grid electrode of the ninth transistor is controlled by an opposite signal of the second clock signal, the grid electrode of the tenth transistor is controlled by a third clock signal, and the grid electrodes of the eleventh transistor and the twelfth transistor are both controlled by an opposite signal of the third clock signal; the other end of the compensation capacitor is further coupled with the voltage outer ring output signal, and one end of the compensation capacitor outputs the compensated outer ring output signal.

Optionally, the first clock signal is obtained according to a gate signal of an upper tube of the voltage converter, the second clock signal is obtained according to a gate signal of a lower tube of the voltage converter, and the third clock signal is obtained according to the gate signal of the upper tube and the gate signal of the lower tube.

Optionally, the error amplifying circuit includes: the output end of the error amplifier outputs the voltage outer ring output signal; one end of the first capacitor and one end of the second capacitor are both coupled with the output end of the error amplifier, the other end of the second capacitor is coupled with the grounding end, and the other end of the first capacitor is coupled with the grounding end after being connected with the third resistor in series.

Optionally, a ratio of the first current to the output voltage is equal to a ratio of the second current to the voltage difference.

Optionally, the signal compensation circuit further includes a clock signal generating circuit, where the clock signal generating circuit includes first to seventh inverters, first to third transmission gates, a first one-shot circuit, a second one-shot circuit, and a flip-flop, where an input end of the first inverter receives a gate signal of the upper pipe, an output end of the first inverter is coupled to an input end of the second inverter, an output end of the second inverter is respectively coupled to an input end of the third inverter and an input end of the first transmission gate, an output end of the third inverter outputs an opposite signal of the first clock signal, and an output end of the first transmission gate outputs the first clock signal; the input end of the fourth inverter receives the gate signal of the lower tube, the output end of the fourth inverter is coupled with the input end of the fifth inverter, the output end of the fifth inverter is coupled with the input end of the sixth inverter and the input end of the second transmission gate respectively, the output end of the sixth inverter outputs the opposite signal of the second clock signal, and the output end of the second transmission gate outputs the second clock signal; the input end of the first one-shot circuit receives the output signal of the second inverter, the output end of the first one-shot circuit is coupled with one input end of the trigger, the input end of the second one-shot circuit receives the output signal of the fourth inverter, the output end of the second one-shot circuit is coupled with the other input end of the trigger, the output ends of the trigger are respectively coupled with the input end of the third transmission gate and the input end of the seventh inverter, the output end of the third transmission gate outputs a third clock signal, and the output end of the seventh inverter outputs the opposite signal of the third clock signal.

According to a second aspect of the present disclosure, there is provided a chip comprising the ACOT control circuit of any one of the first aspects applied to a voltage converter.

In the ACOT control circuit applied to the voltage converter, the double-slope compensation circuit generates a double-slope signal related to the slope of the inductive current based on the input voltage and the output voltage of the voltage converter, and then superimposes the double-slope signal and the voltage outer loop output signal to generate a compensated outer loop output signal; the pulse width modulation comparator compares the compensated outer ring output signal with the feedback signal to output a first pulse width modulation signal capable of reflecting whether the current output voltage is under-voltage or not, and if the current output voltage is under-voltage, the first pulse width modulation signal is high. And after the upper tube of the voltage converter is turned on according to the first pulse width modulation signal and the preset conduction time passes, if the first pulse width modulation signal is still at a high level, shielding the preset conduction time signal, and determining the switch of the upper tube according to the height of the first pulse width modulation signal. That is, after the preset on-time, if the first pwm signal is still high (the output voltage is in an under-voltage state), the actual on-time will not be cut off, and a period of time will be adaptively prolonged along with the first pwm signal based on the preset on-time, so that the actual on-time is longer than the preset on-time. Therefore, the ACOT control circuit in the embodiment of the disclosure can automatically prolong the on-time according to the first pulse width modulation signal without being controlled by the preset on-time under the condition that the load jumps and the output voltage is under-voltage, so that the problem that the rising slope of the inductance current is limited due to the fixed on-time is solved, and the problem that the output voltage undershoots too much is avoided.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will be given, it being understood that the drawings described below relate only to some embodiments of the present disclosure, not to limitations of the present disclosure, in which:

FIG. 1 shows a schematic block diagram of an ACOT control circuit applied to a voltage converter in accordance with an embodiment of the present disclosure;

FIG. 2 illustrates an exemplary circuit diagram of a conduction time control circuit in an ACOT control circuit applied to a voltage converter in accordance with an embodiment of the present disclosure;

FIG. 3 illustrates an exemplary circuit diagram of a first current generation circuit and a second current generation circuit in an ACOT control circuit applied to a voltage converter in accordance with an embodiment of the present disclosure;

FIGS. 4 and 6 illustrate exemplary circuit diagrams of a signal compensation circuit applied in an ACOT control circuit of a voltage converter in accordance with embodiments of the present disclosure;

FIG. 5 illustrates an exemplary circuit diagram of a clock signal generation circuit applied in an ACOT control circuit of a voltage converter in accordance with an embodiment of the present disclosure;

FIGS. 7-8 are schematic diagrams illustrating the generation of a dual ramp signal and its reset key waveforms corresponding to the ACOT control circuit of an embodiment of the present disclosure in different modes;

FIG. 9 illustrates an exemplary circuit diagram of an error amplification circuit in an ACOT control circuit for a voltage converter, in accordance with one embodiment of the present disclosure;

FIG. 10 is a waveform comparison diagram showing a conventional ACOT control mode corresponding to an ACOT control circuit of an embodiment of the present disclosure when a load jumps;

elements in the figures are illustrated schematically and not drawn to scale.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by those skilled in the art based on the described embodiments of the present disclosure without the need for creative efforts, are also within the scope of the protection of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or joined through one or more intermediate parts. In addition, terms such as "first" and "second" are used merely to distinguish one component (or portion of a component) from another component (or another portion of a component).

In order to solve the problem that the output voltage generated by the ACOT control scheme when the voltage converter generates load jump is undershoot and overlarge, a novel ACOT control circuit structure applied to the voltage converter is provided. The ACOT control circuit provided by the embodiment of the disclosure is a rapid ACOT control mode with internal double-slope compensation, and can automatically prolong the on time when a load jumps, so that the ACOT control circuit has rapid transient response and smaller output undervoltage. The following describes in detail an ACOT control circuit applied to a voltage converter of the present disclosure.

Fig. 1 shows a schematic block diagram of an ACOT control circuit 100 applied to a voltage converter according to an embodiment of the present disclosure. It should be noted that fig. 1 also shows other structures of the voltage converter (which may be a Buck converter), including an upper tube MD1 (HG is a gate signal of MD 1), a lower tube MD2 (LG is a gate signal of MD 2), an inductance L, an output capacitor Cout, and an output capacitor equivalent series resistance R _ESR Load resistor R and voltage dividing network R _f1 And R is _f2 . As shown in fig. 1, the ACOT control circuit includes: the error amplifying circuit 110, the double-slope compensating circuit 120, the pulse width modulation comparator 130 and the on-time control circuit 140, wherein the error amplifying circuit 110 belongs to a voltage outer ring, and the pulse width modulation comparator 130 belongs to a voltage inner ring.

Wherein the error amplifying circuit 110 is configured toFor receiving the feedback signal V of the output voltage Vout of the voltage converter _fb And will feed back the signal V _fb Comparing with reference voltage Vref to obtain voltage outer loop output signal V _EAO ；

A dual-ramp compensation circuit 120 configured to generate a dual-ramp signal based on the input voltage Vin and the output voltage Vout of the voltage converter, and to output the dual-ramp signal and the voltage-loop output signal V _EAO Superposition to generate compensated outer loop output signal V _EAO,ripple The slope of the dual ramp signal is related to the slope of the inductor current of the voltage converter. The inductor current is the current of the inductor L in fig. 1. The dual ramp signal comprises an upward ramp and a downward ramp, the slope of the ramp signal is related to the slope of the inductor current, specifically the slope of the downward ramp is in direct proportion to the slope of the rise of the inductor current, the slope of the upward ramp is in direct proportion to the slope of the fall of the inductor current, and the two proportionality coefficients are the same. Since the inductor current rises and falls in steady state, the slope of the ramp signal is set to ensure that the ramp signal rises and falls, so that the voltage outer loop output signal V is changed when the slope of the ramp signal changes (due to the change of the input voltage, etc.) _EAO The circuit is kept unchanged, and the stability of the working state of the circuit is facilitated.

A pulse width modulation comparator 130 configured to output a compensated outer loop output signal V _EAO,ripple And feedback signal V _fb Comparing to obtain a first pulse width modulation signal PWM1; the first pulse width modulation signal PWM1 is an external ring output signal V after compensation _EAO,ripple And feedback signal V _fb The signal of the comparison result is, as shown in FIG. 1, the compensated outer loop output signal V _EAO,ripple Coupled to the positive input of the PWM comparator 130 is a feedback signal V for outputting a voltage Vout _fb Coupled to the negative input of the PWM comparator 130, the first PWM signal PWM1 indicates whether the output voltage Vout is low or low, and the upper tube MD1 needs to be turned on.

The on-time control circuit 140 is configured to generate a second pulse width modulation signal PWM2 for controlling the switching of the upper tube MD1 and the lower tube MD2 of the voltage converter, and is configured as a rootThe upper tube MD1 of the voltage converter is turned on according to the first pulse width modulation signal PWM1 and a preset conduction time t is passed _on Then, if the first PWM signal PWM1 is still at the high level, the preset on-time t is masked _on The signal (hereinafter, first indication signal) determines the switch of the upper tube MD1 according to the level of the first PWM signal PWM 1. As shown in fig. 1, the second pulse width modulation signal PWM2 is used to be input into the driver to generate a driving signal to drive the upper tube MD1 and the lower tube MD2. The first PWM signal PWM1 and the second PWM signal PWM2 vary consistently from low to high. In the prior art, the preset conduction time t is not automatically prolonged _on At this time, the first PWM signal PWM1 outputted from the PWM comparator 130 is the on time of the upper tube MD1 and the lower tube MD2 of the direct control voltage converter, and is controlled by the preset on time t _on Determining the time for which the upper tube MD1 is turned on, although in the embodiment of the present disclosure, the automatic extension of the preset conduction time t is increased _on But the pulse width modulation signal outputted by the modulation comparator controls the turn-on time of the upper tube MD1 and the lower tube MD2 of the voltage converter, i.e. the second pulse width modulation signal PWM2 is consistent with the change of the first pulse width modulation signal PWM1 from low to high.

In fig. 1, when the upper tube MD1 of the high-voltage converter is turned on, the voltage outer ring outputs a signal V _EAO Superimposing the downward slope and the feedback signal V of the output voltage Vout _fb Comparing until the PWM comparator 130 turns low (i.e., the first PWM signal PWM1 is low), at which time, if the first indication signal is already low, the upper tube MD1 is allowed to be turned off; when the upper tube MD1 is turned off, the voltage outer ring outputs a signal V _EAO Superimposing the upward slope and the feedback signal V of the output voltage Vout _fb The comparison is performed until the PWM comparator 130 turns high (i.e., the first PWM signal PWM1 and the second PWM signal PWM2 are high), and then the upper tube MD1 is allowed to turn on. It can be seen that the down-ramp and up-ramp determine the falling edge and rising edge, respectively, of the PWM signal (the second pulse width modulation signal PWM 2) input into the driver.

The embodiment of the disclosure is applied to an ACOT control circuit of a voltage converter, and a dual-slope compensation circuit 120 is based onGenerating a dual ramp signal related to the slope of the inductor current at the input voltage Vin and the output voltage Vout of the voltage converter, and then outputting the dual ramp signal and the voltage outer loop output signal V _EAO Superposition to generate compensated outer loop output signal V _EAO,ripple The method comprises the steps of carrying out a first treatment on the surface of the The pulse width modulation comparator 130 outputs the compensated outer loop output signal V _EAO,ripple And feedback signal V _fb The comparison output can reflect the first PWM signal PWM1 of whether the current output voltage Vout is under voltage, and if the current output voltage Vout is under voltage, the first PWM signal PWM1 is high. The on-time control circuit 140 turns on the upper tube MD1 of the voltage converter according to the first PWM signal PWM1 and passes through a preset on-time t _on Then, if the first PWM signal PWM1 is still at the high level, the preset on-time t is masked _on The signal determines the switch of the upper tube MD1 according to the height of the first pulse width modulation signal PWM 1. I.e. after a preset on-time t has elapsed _on After that, if the first PWM signal PWM1 is still high (the output voltage Vout is in the under-voltage state), the actual on-time will not be cut off, and the first PWM signal PWM1 will follow the preset on-time t _on On the basis of the self-adaption to prolong the period of time to ensure that the actual on-time is longer than the preset on-time t _on Longer. Therefore, the ACOT control circuit in the embodiment of the disclosure can not be subjected to the preset conduction time t under the condition that the load jumps and the output voltage Vout is under-voltage _on The control of (2) can automatically prolong the on time according to the first pulse width modulation signal PWM1, thereby improving the problem of limiting the rising slope of the inductor current due to the fixed on time and further avoiding the problem of undershoot of the output voltage Vout to be overlarge.

Further, as shown in fig. 2, the on-time control circuit 140 includes: a preset on-time control circuit 140, a shortest off-time control circuit 142, an or gate 143, and three nand gates, wherein the preset on-time control circuit 140 is configured to determine a preset on-time t according to an input/output duty cycle (a duty cycle D determined by an input voltage Vin and an output voltage Vout) of the voltage converter _on And according to the second PWM signal PWM2 and the preset on-time t _on Generating a first indication signalThe first indication signal is used for indicating whether to enter a preset conduction time t _on I.e. the upper tube MD1 starts to enter the preset conduction time t when being opened _on The first indication signal is high, and the upper tube MD1 is opened to reach the preset conduction time t _on Then, the first indication signal is low; a shortest off-time control circuit 142 configured to control the switching time of the pulse width modulation signal PWM2 according to the second pulse width modulation signal PWM2 and the shortest off-time t _off,min Generating a second indication signal for indicating whether the minimum off-time t is reached _off,min That is, the shortest turn-off time control circuit 142 starts to count after the upper tube MD1 is turned off, the second indication signal is high, and when the turn-off time of the upper tube MD1 reaches the shortest turn-off time t _off,min Thereafter, the second indication signal is low; the two input ends of the or gate 143 are respectively coupled to the first indication signal and the first PWM signal PWM1, the output end of the or gate 143 is coupled to one input end of the second nand gate 145, the two input ends of the first nand gate 144 are respectively coupled to the second indication signal and the first PWM signal PWM1, and the output end of the first nand gate 144 is coupled to one input end of the third nand gate 146; the other input terminal of the second nand gate 145 is coupled to the output terminal of the third nand gate 146, the output terminal of the second nand gate 145 is coupled to the other input terminal of the third nand gate 146, and the output terminal of the third nand gate 146 is used as the output terminal of the on-time control circuit 140 to output the second pulse width modulation signal PWM2.

Analysis of the ACOT control principle in an embodiment of the present disclosure is performed in conjunction with fig. 1 and 2: when the load jumps and the load current changes and causes the output voltage Vout to be under-voltage, the pulse width modulation comparator 130 turns high to turn on the upper tube MD1, and the upper tube MD1 is turned on to reach the preset conduction time t _on Thereafter, if the downward slope still does not touch V _fb That is, the first PWM signal PWM1 is still at the high level, the or gate 143 of the on-time control circuit 140 masks the preset on-time t _on (preset on time t) _on The switching of the upper tube MD1 is determined by the height of the first pulse width modulation signal PWM1, so that the effect of automatically prolonging the conduction time is achieved. In additionWhen the voltage converter is in a steady state, the output voltage Vout is at a normal value, so that the pwm comparator 130 turns high, and the pwm comparator 130 turns low again due to the downward slope after the upper tube MD1 is turned on, and the or gate 143 in the on-time control circuit 140 is controlled by the first indication signal only, i.e. the on-time of the upper tube MD1 is controlled by the preset on-time t _on And determining that the working condition is consistent with the traditional ACOT control at the moment. Therefore, the fast ACOT control mode with internal double-slope compensation provided by the embodiment of the disclosure can adaptively prolong the on time during load jump, reduce undershoot of the output voltage Vout to be overlarge, and has faster transient response than the traditional ACOT control; and the actual on-time is kept in the steady state and is determined by the input-output duty ratio D (because the steady state is still determined by the preset on-time t _on By determining the on time of the upper tube MD1, the on time t is preset _on The switching frequency is relatively stable because the actual on time is determined by the input/output duty ratio D in the steady state.

Further, the dual slope compensation circuit 120 includes: a current generation circuit configured to generate a first current g proportional to a voltage difference between an input voltage Vin and an output voltage Vout from the input voltage Vin and the output voltage Vout, a signal compensation circuit 123 _m1 X (Vin-Vout), a second current g proportional to the output voltage Vout _m1 X Vout. A signal compensation circuit 123 configured to generate a dual ramp signal according to the current (first current, second current) generated by the current generation circuit and charge and discharge the compensation capacitor Cc, and output the dual ramp signal and the voltage outer loop output signal V _EAO Superposition to generate compensated outer loop output signal V _EAO,ripple 。

Further, as shown in fig. 3, the current generation circuit includes: a first current generating circuit 121 and a second current generating circuit 122, wherein the first current generating circuit 121 is configured to scale and low-pass filter an input voltage Vin and then to generate a second current g _m1 The difference of x Vout generates a first current g _m1 X (Vin-Vout); specifically, the first current generation circuit 121 comprises: a first voltage dividing resistor pair R _in1 、R _in2 A first low-pass filter module 1211, a first operational amplifier A1, first to third transistors (M1-M3), a first resistor R1, wherein a first voltage dividing resistor pair R _in1 、R _in2 Coupled in series between an input voltage Vin and ground; the first low-pass filter 1211 is coupled to the first voltage dividing resistor pair R _in1 、R _in2 The middle node of the two voltage dividing resistors and the positive input end of the first operational amplifier A1; the negative input end of the first operational amplifier A1 is respectively coupled with one end of the first resistor R1 and the source electrode of the first transistor M1, and the output end of the first operational amplifier A1 is coupled with the grid electrode of the first transistor M1; the drain of the first transistor M1 is coupled to the drain of the second transistor M2, the gate of the second transistor M2, and the gate of the third transistor M3, respectively; the source of the second transistor M2 and the source of the third transistor M3 are both coupled to the power supply voltage VDD, the drain of the third transistor M3 is coupled to the second current g generated by the second current generating circuit 122 _m1 X Vout, and outputs a first current g _m1 X (Vin-Vout); the other end of the first resistor R1 is coupled with the grounding end; a second current generation circuit 122 configured to generate a second current g by scaling and low-pass filtering the output voltage Vout _m1 X Vout. The second current generation circuit 122 includes: second voltage-dividing resistor pair R _o1 、R _o2 A second low-pass filtering module 1221, a second operational amplifier A2, a fourth transistor M4, a fifth transistor M5, two second resistors R2, wherein the second pair of voltage dividing resistors R _o1 、R _o2 Coupled between the output voltage Vout and ground; the second low-pass filter module 1221 is coupled to the second pair of voltage dividing resistors R _o1 、R _o2 The middle node of the two voltage dividing resistors and the positive input end of the second operational amplifier A2; the negative input terminal of the second operational amplifier A2 is coupled to one terminal of the first second resistor 1222, the source of the fourth transistor M4, the source of the fifth transistor M5, and one terminal of the second resistor 1223, and the output terminal of the second operational amplifier A2 is coupled to the gate of the fourth transistor M4 and the gate of the fifth transistor M5, respectively; the drain of the fourth transistor M4 generates a second current g _m1 X Vout and coupled to the first current generationThe drain of the third transistor M3 and the drain of the fifth transistor M5 in the circuit 121 outputs a second current g _m1 X Vout; the other ends of the two second resistors R2 are coupled to the ground terminal. Further, the first low-pass filtering module 1211 and the second low-pass filtering module 1221 are a multi-stage low-pass filtering structure composed of a plurality of capacitors and a plurality of resistors. The first current g _m1 The ratio of x (Vin-Vout) to the output voltage Vout is equal to the second current g _m1 The ratio of xVout to voltage difference, as shown in FIG. 3, is g _m1 。

Further, as shown in fig. 4, the signal compensation circuit 123 includes: compensation capacitor Cc, two first current sources (I ₁₁ 、I ₁₂ ) Two second current sources (I ₂₁ 、I ₂₂ ) Sixth to twelfth transistors, a first current source (I ₁₁ 、I ₁₂ ) The current value of (2) is equal to the first current g _m1 X (Vin-Vout), a second current source (I ₂₁ 、I ₂₂ ) The current value of (2) is equal to the second current g _m1 The value of xVout, wherein the first current source I ₁₁ A first and a second current source I ₂₁ One end of the first current source I is coupled to the power supply voltage VDD ₁₁ The other ends of the (B) are respectively coupled to a sixth transistor M _s1 Drain of (c) and eighth transistor M _s4 A first and a second current source I ₂₁ The other ends of (a) are respectively coupled to the eighth transistor M _s4 A drain electrode of the compensation capacitor Cc, one end of the ninth transistor M _s3 Drain of (2), second first current source I ₁₂ Is a member of the group; sixth transistor M _s1 The source electrodes of the third and fourth transistors are respectively coupled to the seventh transistor M _s2 A seventh transistor M having the other end of the compensation capacitor Cc and the drain electrode thereof _s2 The sources of the first and second current sources are respectively coupled to ₂₂ A ninth transistor M _s3 A source of (a); tenth transistor M _c2 A tenth transistor M having its source coupled to the other end of the compensation capacitor Cc _c2 The drain electrode of the capacitor is coupled with one end of the compensation capacitor Cc; eleventh transistor M _c1 The drains of the (a) are respectively coupled to the tenth transistor M _c2 Source of eleventh transistor M _c1 Source of twelfth (a)Transistor M _c3 The source electrodes of the first and second transistors are respectively coupled to a tenth transistor M _c2 Drain of twelfth transistor M _c3 A drain electrode of (2); second first current source I ₁₂ The other end of the second current source I ₂₂ The other ends of the two are coupled with the grounding end; sixth transistor M _s1 Is controlled by a first clock signal clk _high Control, seventh transistor M _s2 Is controlled by a second clock signal clk _low Control, eighth transistor M _s4 Is controlled by a first clock signal clk _high The ninth transistor M _s3 Is controlled by a second clock signal clk _low Is controlled by the opposite signal of the tenth transistor M _c2 Is controlled by a third clock signal clk _clear Control, eleventh transistor M _c1 Gate of twelfth transistor M _c3 Are all clocked by the third clock signal clk _clear Is controlled by the opposite signal of (a); the other end of the compensation capacitor Cc is also coupled with the output signal V of the voltage outer ring _EAO One end of the compensation capacitor Cc outputs a compensated outer ring output signal V _EAO,ripple . Further, the signal compensation circuit 123 further includes a clock signal generating circuit 1231 for generating all the above-mentioned clock signals, specifically the first clock signal clk _high The second clock signal clk is obtained according to the gate signal HG of the upper tube MD1 of the voltage converter _low The third clock signal clk is obtained according to the gate signal LG of the lower tube MD2 of the voltage converter _clear The gate signal HG of the upper tube MD1 and the gate signal LG of the lower tube MD2 are obtained. As shown in fig. 5, the clock signal generating circuit 1231 includes first to seventh inverters N7, first to third transmission gates, a first one-shot circuit 12311, a second one-shot circuit 12312, and a flip-flop 12313, wherein an input end of the first inverter N1 receives the gate signal HG of the upper tube MD1, an output end of the first inverter N1 is coupled to an input end of the second inverter N2, an output end of the second inverter N2 is respectively coupled to an input end of the third inverter N3 and an input end of the first transmission gate TG1, and an output end of the third inverter N3 outputs the first clock signal clk _high Is the opposite signal of (2)The output end of the first transmission gate TG1 outputs a first clock signal clk _high The method comprises the steps of carrying out a first treatment on the surface of the The input end of the fourth inverter N4 receives the gate signal LG of the down tube MD2, the output end of the fourth inverter N4 is coupled to the input end of the fifth inverter N5, the output end of the fifth inverter N5 is respectively coupled to the input end of the sixth inverter N6 and the input end of the second transmission gate TG2, and the output end of the sixth inverter N6 outputs the second clock signal clk _low Opposite signal +.>The output end of the second transmission gate TG2 outputs the second clock signal clk _low The method comprises the steps of carrying out a first treatment on the surface of the The input terminal of the first one-shot circuit 12311 receives the output signal HG_P of the second inverter N2, the output terminal of the first one-shot circuit 12311 is coupled to one input terminal of the flip-flop 12313, the input terminal of the second one-shot circuit 12312 receives the output signal LG_N of the fourth inverter N4, the output terminal of the second one-shot circuit 12312 is coupled to the other input terminal of the flip-flop 12313, the output terminal of the flip-flop 12313 is respectively coupled to the input terminal of the third transmission gate and the input terminal of the seventh inverter N7, and the output terminal of the third transmission gate outputs the third clock signal clk _clear The output end of the seventh inverter N7 outputs the third clock signal clk _clear Opposite signal +.>

The signal compensation circuit 123 generates a dual ramp signal and outputs it with the voltage outer loop output signal V _EAO And a superimposed circuit. Circuit principle analysis is performed in conjunction with fig. 4 to 6, in which fig. 6 is also an exemplary circuit diagram of the signal compensation circuit 123, which is identical to the structure of fig. 4, and fig. 4 and 6 differ in that the flow direction of the current shown in fig. 4 is for the flow direction when the upper tube MD1 is on, and fig. 6 shows the flow direction of the current is for the flow direction when the upper tube MD1 is off. As shown in fig. 4 to 6, the left end of the compensation capacitor Cc responsible for generating the dual ramp signal and the voltage outer loop output signal V _EAO Connected, the right end generates a signal with double slopes superimposed, namely a compensated outer ring output signal V _EAO,ripple . When the upper tube MD1 is turned on, the first clock signal clk _high The signal is high, the second clock signal clk _low Is low, M _s1 、M _s3 Turn on, M _s2 、M _s4 Turn off, first current g _m1 ×(V _in -V _out ) Flow from left to right through C _c Discharging it to generate a downward slope, and at this time, a second current g proportional to the output voltage Vout _m1 ×V _out Automatic follow current; when the upper tube MD1 is turned off, the second clock signal clk _low Is high, the first clock signal clk _high Is low, M _s2 、M _s4 Turn on, M _s1 、M _s3 Turn off, a second current g proportional to the output voltage Vout _m1 ×V _out Flow from right to left through C _c Charging it to generate an upward slope, and at this time, a first current g proportional to the input-output voltage difference _m1 ×(V _in -V _out ) And (5) automatic follow current. It can be seen that during the generation of the double ramp, the switching action only changes the current flow direction, without switching it off; current g _m1 ×(V _in -V _out ) Or current g _m1 ×V _out Either through the compensation capacitor Cc or automatically, thereby saving the setup time and the resulting electronic interference when switching on the process again after switching off the current source. In addition, no excess charge flows into or out of V during the whole process _EAO Nor does there flow excess charge into or out of V _EAO，ripple The interference of the dual ramp compensation circuit 120 to the front and back stage circuits is greatly reduced. M in parallel with compensation capacitor Cc _c2 Responsible for zeroing the ramp. Due to M _c2 A gate control signal of (a) a third clock signal clk _clear Will be to C _c The two ends generate interference, so in order to avoid the interference, the two ends are provided with a plurality of channels _c2 M is added into the left end and the right end _c1 、M _c3 ，M _c1 、M _c3 Is a dummy switch (dummy), the control signal of the grid electrode and M _c2 In this way, clock feedthrough and charge injection effects on the ramp generated during switching are effectively reduced.

In addition, as shown in fig. 7-8, the generation of the dual ramp signal and the reset key waveform thereof corresponding to the ACOT control circuit of the present disclosure are shown in different modes in steady state, wherein fig. 7 corresponds to a continuous conduction mode (Continuous Conduction Mode, CCM), fig. 8 corresponds to a discontinuous conduction mode (Discontinuous Conduction Mode, DCM), HG in fig. 7 and 8 represents the gate signal of the upper tube MD1, LG represents the gate signal of the lower tube MD2, I _o Representing load current, I _L Representing inductor current, it can be seen from fig. 7 that when the voltage converter is in CCM mode of operation, the circuit generating the dual ramp signal resets within the dead time of the down tube MD2 turning off to the up tube MD1 turning on; when the voltage converter is in the DCM working mode, the circuit generating the double-slope signal is always in a reset state when both the upper tube MD1 and the lower tube MD2 are kept off. Through reasonable utilization of dead time, the generated double slopes can be aligned with the on time and the off time of the upper tube MD1 strictly, namely, once the upper tube MD1 is opened, the compensated outer ring outputs a signal V _EAO,ripple The horse descends from 0; once the down tube MD2 is opened, the compensated outer ring outputs a signal V _EAO,ripple The vertical horse rises from the hold value.

In addition, as is apparent from the above description, when the upper tube MD1 is in the off state, the slope S of the upward slope is generated _e The method comprises the following steps:

wherein Cc is the capacitance of the compensation capacitor Cc;

inductor current falling slope S of voltage converter _f The method comprises the following steps:

wherein L is the inductance value of the inductor L;

therefore, the equivalent virtual resistance R brought by the internal double-slope compensation mode in the present disclosure _i The method comprises the following steps:

and the equivalent virtual resistance R caused by the injected ramp is also used for avoiding the problem of subharmonic oscillation of COT _i The following expression needs to be satisfied:

where Cout is the capacitance of the output capacitor Cout.

As can be seen from equation (1), the virtual resistance R due to the dual slope compensation in the present disclosure _i Only by the off-chip inductance (L), the on-chip compensation capacitance Cc and the internal circuit parameter (g _m1 ) And determining independently of the input/output duty cycle. Thus, by properly setting the internal circuit parameters, the combined (2) analysis can result in even an off-chip capacitance (i.e., output capacitance Cout) with a smaller R _ESR In the case of ceramic capacitors, the ramp produced can also meet the system stability conditions over a wide input-output range (e.g., constant output, large input variation).

Further, as shown in fig. 9, the error amplifying circuit 110 includes: error amplifier EA, third resistor R ₃ First capacitor C ₁ A second capacitor C ₂ Wherein the positive input end of the error amplifier EA is coupled to the reference voltage Vref, and the negative input end of the error amplifier EA is coupled to the feedback signal V _fb The output end of the error amplifier EA outputs a voltage outer loop output signal V _EAO The method comprises the steps of carrying out a first treatment on the surface of the First capacitor C ₁ One end of (C) a second capacitor C ₂ One end of the capacitor C is coupled to the output end of the error amplifier EA ₂ The other end of the capacitor is coupled to the ground terminal, the first capacitor C ₁ The other end of (a) is connected in series with a third resistor R ₃ The rear coupling is coupled to the ground terminal.

Further, in order to illustrate the beneficial effects of the ACOT control circuit in the embodiments of the present disclosure, a waveform comparison schematic diagram corresponding to the conventional ACOT control manner and the ACOT control circuit of the present disclosure when the load jumps is shown in fig. 10. In FIG. 10, the feedback signal V is shown as follows from top to bottom _fb And the present disclosureOuter loop output signal V after middle compensation _EAO,ripple "second PWM signal PWM2", "PWM signal PWM0 of conventional manner", "load current I" in this disclosure _o And inductor current I of the present disclosure _L And conventional inductor current I _L0 "waveform diagrams corresponding to the output voltage Vout of the present disclosure and the conventional output voltage Vout 0". It can be seen from fig. 10 that when the output voltage Vout is undervoltage due to load jump, comparing the two waveforms PWM2 and PWM0, the on-time is determined by the compensated outer loop output signal V in the present disclosure _EAO,ripple Is determined by the falling ramp of (2), the actual on-time is compared with the traditional preset on-time t _on Adaptively prolong, so that the inductance current I _L With a larger slope (than the conventional inductor current I _L0 Greater slope) follows the load current I _o Thereby having a faster transient response and a smaller output under-voltage value; after the steady state is entered, the output voltage Vout returns to a proper value, and the conduction time is again changed from the preset conduction time t _on And determines, thereby, relatively stabilizes the switching frequency.

In addition, it should be further noted that, in the embodiments of the present disclosure, the dual-slope compensation mode is an on-chip compensation, which can save chip area compared to the conventional ripple compensation scheme. The traditional ripple compensation scheme is to connect a low-pass filter composed of a resistor and a capacitor to two ends of an inductor L (off-chip inductor), collect information of inductance current ripple, and then superimpose the ripple on a feedback signal V through a high-pass filter formed by an AC coupling capacitor and a feedback resistor _fb And (3) upper part. This solution requires a large value of resistance, capacitance, and if these passive components are placed in the chip, it is disadvantageous for the miniaturization of the chip area. And the traditional ripple compensation scheme often depends on the reserved connection output voltage V of the chip _out Is not suitable for reserving only the feedback signal V _fb The pin case has no flexibility, but the dual ramp compensation scheme in the disclosed embodiment may also be adapted to reserve only the feedback signal V _fb The situation of the pins is more flexible.

Embodiments of the present disclosure also provide a chip including the ACOT control circuit applied to the voltage converter in the foregoing embodiments. The chip may be a DC-DC switching power supply chip.

In summary, the ACOT control circuit applied to the voltage converter in the embodiment of the disclosure realizes that the on time can be adaptively prolonged when the load jump of the voltage converter occurs, and has the effects of quicker transient response and smaller output undervoltage value.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus and methods according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

As used herein and in the appended claims, the singular forms of words include the plural and vice versa, unless the context clearly dictates otherwise. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the terms "comprising" and "including" are to be construed as being inclusive rather than exclusive. Likewise, the terms "comprising" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a set of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or broad.

Further aspects and scope of applicability will become apparent from the description provided herein. It should be understood that various aspects of the disclosure may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure.

While several embodiments of the present disclosure have been described in detail, it will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An ACOT control circuit for a voltage converter, the ACOT control circuit comprising: an error amplifying circuit, a double-slope compensating circuit, a pulse width modulation comparator and a conduction time control circuit,

the error amplifying circuit is configured to receive a feedback signal of the output voltage of the voltage converter and compare the feedback signal with a reference voltage to obtain a voltage outer loop output signal;

the dual-slope compensation circuit is configured to generate a dual-slope signal based on an input voltage and an output voltage of the voltage converter, and superimpose the dual-slope signal and the voltage outer-loop output signal to generate a compensated outer-loop output signal, wherein the slope of the dual-slope signal is related to the slope of an inductance current of the voltage converter;

the pulse width modulation comparator is configured to compare the compensated outer loop output signal with the feedback signal to obtain a first pulse width modulation signal;

the on-time control circuit is used for generating a second pulse width modulation signal for controlling the upper tube and the lower tube of the voltage converter, and is configured to switch on the upper tube of the voltage converter according to the first pulse width modulation signal and shield a preset on-time signal if the first pulse width modulation signal is still at a high level after a preset on-time is passed, and the switch of the upper tube is determined by the height of the first pulse width modulation signal.

2. The ACOT control circuit for a voltage converter according to claim 1, wherein the on-time control circuit comprises: a preset on-time control circuit, a shortest off-time control circuit, an OR gate and three NAND gates,

the preset on-time control circuit is configured to determine the preset on-time according to the input/output duty ratio of the voltage converter, and generate a first indication signal according to the second pulse width modulation signal and the preset on-time, wherein the first indication signal is used for indicating whether to enter the preset on-time or not;

the shortest turn-off time control circuit is configured to generate a second indicating signal according to the second pulse width modulation signal and the shortest turn-off time, wherein the second indicating signal is used for indicating whether the shortest turn-off time is reached;

the two input ends of the OR gate are respectively coupled with the first indication signal and the first pulse width modulation signal, the output end of the OR gate is coupled with one input end of a second NAND gate, the two input ends of the first NAND gate are respectively coupled with the second indication signal and the first pulse width modulation signal, and the output end of the first NAND gate is coupled with one input end of a third NAND gate;

The other input end of the second NAND gate is coupled with the output end of the third NAND gate, the output end of the second NAND gate is coupled with the other input end of the third NAND gate, and the output end of the third NAND gate is used as the output end of the on-time control circuit and outputs the second pulse width modulation signal.

3. The ACOT control circuit for a voltage converter of claim 1, wherein the dual ramp compensation circuit comprises: a current generating circuit, a signal compensating circuit,

wherein the current generation circuit is configured to generate a first current proportional to a voltage difference between the input voltage and the output voltage and a second current proportional to the output voltage according to the input voltage and the output voltage;

the signal compensation circuit is configured to generate the double-slope signal by charging and discharging a compensation capacitor according to the current generated by the current generation circuit, and superimpose the double-slope signal and the voltage outer ring output signal to generate the compensated outer ring output signal.

4. The ACOT control circuit for a voltage converter according to claim 3, wherein the current generating circuit comprises: a first current generating circuit, a second current generating circuit,

The first current generation circuit is configured to generate the first current by performing scaling and low-pass filtering on the input voltage and then performing difference between the input voltage and the second current;

the second current generation circuit is configured to generate the second current after scaling and low-pass filtering the output voltage.

5. The ACOT control circuit for a voltage converter according to claim 4, wherein the first current generating circuit comprises: the circuit comprises a first voltage dividing resistor pair, a first low-pass filter module, a first operational amplifier, first to third transistors and a first resistor, wherein the first voltage dividing resistor pair is coupled between the input voltage and a ground terminal; the first low-pass filter module is coupled between the middle node of the two divider resistors in the first divider resistor pair and the positive input end of the first operational amplifier; the negative input end of the first operational amplifier is respectively coupled with one end of the first resistor and the source electrode of the first transistor, and the output end of the first operational amplifier is coupled with the grid electrode of the first transistor; the drain electrode of the first transistor is respectively coupled with the drain electrode of the second transistor, the grid electrode of the second transistor and the grid electrode of the third transistor; the source electrode of the second transistor and the source electrode of the third transistor are both coupled with a power supply voltage, and the drain electrode of the third transistor is coupled with the second current generated by the second current generating circuit and outputs the first current; the other end of the first resistor is coupled with the grounding end;

The second current generation circuit includes: the second voltage division resistor pair, the second low-pass filter module, the second operational amplifier, the fourth transistor, the fifth transistor and the two second resistors, wherein the second voltage division resistor pair is coupled between the output voltage and the ground terminal; the second low-pass filter module is coupled between the middle node of the two divider resistors in the second divider resistor pair and the positive input end of the second operational amplifier; the negative input end of the second operational amplifier is respectively coupled with one end of the first second resistor, the source electrode of the fourth transistor, the source electrode of the fifth transistor and one end of the second resistor, and the output end of the second operational amplifier is respectively coupled with the grid electrode of the fourth transistor and the grid electrode of the fifth transistor; the drain electrode of the fourth transistor generates the second current and is coupled with the drain electrode of the third transistor in the first current generation circuit, and the drain electrode of the fifth transistor outputs the second current; the other ends of the two second resistors are coupled to the ground terminal.

6. The ACOT control circuit for a voltage converter according to claim 3, wherein the signal compensation circuit comprises: a compensation capacitor, two first current sources, two second current sources, and a sixth to twelfth transistors, wherein the current value of the first current sources is equal to the value of the first current, the current value of the second current sources is equal to the value of the second current,

One end of a first current source and one end of a first second current source are both coupled with a power supply voltage, the other end of the first current source is respectively coupled with the drain electrode of a sixth transistor and the source electrode of an eighth transistor, and the other end of the first second current source is respectively coupled with the drain electrode of the eighth transistor, one end of the compensation capacitor, the drain electrode of a ninth transistor and one end of a second first current source;

the source electrode of the sixth transistor is respectively coupled with the drain electrode of the seventh transistor and the other end of the compensation capacitor, and the source electrode of the seventh transistor is respectively coupled with one end of the second current source and the source electrode of the ninth transistor;

the source electrode of the tenth transistor is coupled with the other end of the compensation capacitor, and the drain electrode of the tenth transistor is coupled with one end of the compensation capacitor;

the drain electrode of the eleventh transistor is coupled with the source electrode of the tenth transistor and the source electrode of the eleventh transistor respectively, and the source electrode of the twelfth transistor is coupled with the drain electrode of the tenth transistor and the drain electrode of the twelfth transistor respectively;

the other end of the second first current source and the other end of the second current source are coupled with a grounding end;

The grid electrode of the sixth transistor is controlled by a first clock signal, the grid electrode of the seventh transistor is controlled by a second clock signal, the grid electrode of the eighth transistor is controlled by an opposite signal of the first clock signal, the grid electrode of the ninth transistor is controlled by an opposite signal of the second clock signal, the grid electrode of the tenth transistor is controlled by a third clock signal, and the grid electrodes of the eleventh transistor and the twelfth transistor are both controlled by an opposite signal of the third clock signal;

the other end of the compensation capacitor is further coupled with the voltage outer ring output signal, and one end of the compensation capacitor outputs the compensated outer ring output signal.

7. The ACOT control circuit for a voltage converter of claim 6, wherein the first clock signal is derived from a gate signal of an upper pipe of the voltage converter, the second clock signal is derived from a gate signal of a lower pipe of the voltage converter, and the third clock signal is derived from the gate signal of the upper pipe and the gate signal of the lower pipe.

8. The ACOT control circuit applied to a voltage converter according to claim 1, wherein the error amplifying circuit includes: an error amplifier, a third resistor, a first capacitor, a second capacitor,

The positive input end of the error amplifier is coupled with the reference voltage, the negative input end of the error amplifier is coupled with the feedback signal, and the output end of the error amplifier outputs the voltage outer ring output signal;

one end of the first capacitor and one end of the second capacitor are both coupled with the output end of the error amplifier, the other end of the second capacitor is coupled with the grounding end, and the other end of the first capacitor is coupled with the grounding end after being connected with the third resistor in series.

9. The ACOT control circuit for a voltage converter of claim 3, wherein a ratio of the first current to the output voltage is equal to a ratio of the second current to the voltage difference.

10. Chip characterized by comprising an ACOT control circuit according to any of claims 1 to 9 applied to a voltage converter.