CN116844966A - Preparation method of flip chip packaging structure and packaging structure - Google Patents

Preparation method of flip chip packaging structure and packaging structure Download PDF

Info

Publication number
CN116844966A
CN116844966A CN202310838622.0A CN202310838622A CN116844966A CN 116844966 A CN116844966 A CN 116844966A CN 202310838622 A CN202310838622 A CN 202310838622A CN 116844966 A CN116844966 A CN 116844966A
Authority
CN
China
Prior art keywords
chip
layer
metal layer
wafer
flip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310838622.0A
Other languages
Chinese (zh)
Inventor
华显刚
贺姝敏
杨斌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Fozhixin Microelectronics Technology Research Co ltd
Original Assignee
Guangdong Fozhixin Microelectronics Technology Research Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong Fozhixin Microelectronics Technology Research Co ltd filed Critical Guangdong Fozhixin Microelectronics Technology Research Co ltd
Priority to CN202310838622.0A priority Critical patent/CN116844966A/en
Publication of CN116844966A publication Critical patent/CN116844966A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The application relates to the technical field of semiconductors, and particularly discloses a preparation method of a flip chip packaging structure and the packaging structure, wherein the preparation method comprises the following steps: providing a wafer, and arranging a structural metal layer on the upper surface of the wafer based on chip distribution; dicing the wafer according to the chip distribution to obtain chip monomers; providing a carrier plate, and reversely fastening and fixing the chip monomer on the carrier plate based on the temporary bonding layer; the top surface of the plastic packaging carrier plate is higher than or equal to the top surface of the plastic packaging layer and higher than the back side of the chip monomer to obtain a plastic packaging body; manufacturing an electric connection structure on the plastic package body; the preparation method skips the laser drilling process and the process of covering the metal layer, omits the deviation of laser drilling, and improves the processing precision of the packaging structure, thereby improving the yield of products.

Description

Preparation method of flip chip packaging structure and packaging structure
Technical Field
The application relates to the technical field of semiconductors, in particular to a preparation method of a flip chip packaging structure and the packaging structure.
Background
When the fan-out type packaging structure is packaged in a face down mode, laser drilling is required to be conducted towards the front surface of the plastic packaging body after a plastic packaging layer is formed, and a metal layer is filled to lead out PAD of the chip; however, before filling the metal layer, the chip is reversely mounted on the carrier plate and has certain deviation, and the chip position drift is caused in the chip plastic packaging process, and meanwhile, the laser drilling is performed by taking the position of the carrier plate as a reference object and also has certain deviation; under the influence of the various deviation data, the laser drilling position is easy to deviate from the PAD position of the chip, so that the PAD cannot be led out smoothly by the metal layer, the problem of insufficient machining precision exists, and the product yield is influenced.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
The application aims to provide a preparation method of a flip chip packaging structure and the packaging structure, and the processing precision of the packaging structure, so that the yield of products is improved.
In a first aspect, the present application provides a method for preparing a flip chip package structure, the method for preparing the flip chip package structure comprising the steps of:
s1, providing a wafer, and arranging a structural metal layer on the upper surface of the wafer based on chip distribution;
s2, dicing the wafer according to the chip distribution to obtain chip monomers;
s3, providing a carrier plate, and reversely fastening and fixing the chip monomer on the carrier plate based on the temporary bonding layer;
s4, the top surface of the plastic package carrier plate is higher than or equal to the top surface of the plastic package layer on the back side of the chip monomer to obtain a plastic package body;
s5, manufacturing an electric connection structure on the plastic package body.
Compared with the traditional flip-chip packaging process, the preparation method of the flip-chip packaging structure of the application firstly takes the chip on the wafer as a processing reference to manufacture the structural metal layer, so that the structural metal layer can be accurately arranged on the chip and protect the PAD of the chip, and the chip monomer and the structural metal layer are packaged simultaneously after the chip monomer is flipped, so that the preparation method of the flip-chip packaging structure of the application skips the laser drilling process and the process of covering the metal layer after the traditional flip-chip packaging structure preparation method, omits the deviation of laser drilling, improves the processing precision of the packaging structure, and further improves the yield of products.
The preparation method of the flip chip packaging structure comprises the step of forming a structural metal layer, wherein the structural metal layer is a UBM layer or a tin-plated layer.
In this example, the UBM layer can connect to the PAD that protects and leads out of the chip; the tin-melting layer is formed by tin-melting treatment, has the characteristics of smoothness, flatness and compactness, and can uniformly cover the PAD of the chip so as to lead out the PAD.
The preparation method of the flip chip packaging structure, wherein when the structural metal layer is a UBM layer, the step of arranging the structural metal layer comprises the following steps:
s11, defining passivation patterns on the upper surface of the wafer based on chip distribution;
and S12, depositing the UBM layer on the upper surface of the wafer according to the passivation pattern.
The preparation method of the flip chip packaging structure, wherein the step of disposing the structural metal layer includes the steps of:
s10, a dielectric thickening layer surrounding the PAD is arranged on the upper surface of the wafer based on chip distribution.
In this example, the dielectric thickening layer is provided to cover the portion of the chip except the PAD to protect the chip, and an opening is formed at the PAD, so that the UBM layer is deposited based on the dielectric thickening layer, and the UBM layer is more compact in convergence and is mainly deposited in the opening, so that the electrical connection structure can be directly connected with the UBM deposited in the middle of the PAD, the routing range is shortened, the chip interval in the whole plastic package is smaller, and the number of chip monomers in the plastic package in each packaging process is increased, so that the production efficiency is improved.
The preparation method of the flip chip packaging structure comprises the step of forming a dielectric thickening layer into a PI protection layer with a plurality of surrounding holes for surrounding each PAD on the wafer.
The UBM layer comprises sinking metal structures, the quantity of the sinking metal structures is the same as that of PADs on the wafer, and the sinking bottoms of the sinking metal structures completely cover the corresponding PADs.
The preparation method of the flip-chip packaging structure comprises the step of inwards inclining and sinking the sinking metal structure body.
The preparation method of the flip chip packaging structure comprises the step that the structural metal layer covers PADs of all chips on a wafer.
The preparation method of the flip chip packaging structure comprises the following step S5:
s51, removing the carrier plate on the plastic package body;
s52, inversely detaching the plastic package body after the carrier plate, and sequentially performing the processes of manufacturing a rewiring layer, opening a window by ink and implanting balls.
In a second aspect, the present application further provides a package structure prepared by the method for preparing a flip chip package structure provided in the first aspect, where the package structure includes:
a plastic sealing layer;
the chip monomer is arranged in the plastic package layer, and the top surface of the chip monomer is provided with a structural metal layer;
and the electric connection structure is arranged on the plastic sealing layer and the structural metal layer.
The packaging process of the packaging structure of the application firstly takes the chip on the wafer as a processing reference to manufacture the structural metal layer, so that the structural metal layer can be accurately arranged on the chip and protect the PAD of the chip, and the chip monomer and the structural metal layer are packaged at the same time after the chip monomer is inverted, so that the packaging process skips the laser drilling procedure of the traditional inverted packaging structure preparation method and the process of covering the metal layer, thereby omitting the deviation of laser drilling and improving the processing precision of the packaging structure.
Compared with the traditional flip-chip packaging process, the preparation method firstly takes the chip on the wafer as a processing reference to manufacture the structural metal layer, so that the structural metal layer can be accurately arranged on the chip and protect the PAD of the chip, and the chip monomer and the structural metal layer are packaged at the same time after the chip monomer is flipped, so that the preparation method of the flip-chip packaging structure skips the laser drilling process and the process of covering the metal layer after the laser drilling deviation is omitted, the processing precision of the packaging structure is improved, and the yield of products is improved.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a flip chip package structure according to an embodiment of the present application.
Fig. 2 is a schematic process flow diagram of a method for manufacturing a flip chip package structure according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a package structure according to some embodiments of the present application.
Fig. 4 is a schematic structural diagram of a package structure according to other embodiments of the present application.
Reference numerals: 1. a plastic sealing layer; 2. a chip monomer; 3. a structural metal layer; 4. a dielectric thickening layer; 5. an ink layer; 6. a rewiring layer; 7. and a first ball planting.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The following disclosure provides many different embodiments, or examples, for implementing different features of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
The preparation process of the existing chip flip packaging structure comprises the steps of firstly reversely fastening and fixing a plurality of chip monomers on a carrier plate, carrying out plastic packaging treatment on the chip monomers to obtain a plastic package body, then dismantling the carrier plate on the plastic package body, arranging a new carrier plate on the other side, carrying out laser drilling and metal layer deposition treatment on the plastic package body by taking the new carrier plate as a reference, so as to lead PAD of the chip monomers in the plastic package body outwards based on a metal layer filled in a hole generated by laser drilling, and then manufacturing an electric connection structure on one side of the metal layer of the plastic package body to obtain a packaging structure which accords with expectations; in the preparation process of the packaging structure, certain position deviation exists in the operation of the chip monomer back-off on the carrier plate, certain processing deviation exists in the laser drilling process, the new carrier plate is used as a reference for the drilling process, holes in the packaging structure are easy to deviate from PAD of the chip monomer under the comprehensive effect of the various deviation factors, so that the metal layer deviates from the PAD and cannot lead the PAD outwards, and the yield of products is affected.
In a first aspect, referring to fig. 1 and 2, some embodiments of the present application provide a method for manufacturing a flip-chip package structure, the method for manufacturing the flip-chip package structure includes the following steps:
s1, providing a wafer, and arranging a structural metal layer on the upper surface of the wafer based on chip distribution;
s2, dicing the wafer according to the chip distribution to obtain chip monomers;
s3, providing a carrier plate, and reversely fastening and fixing the chip monomer on the carrier plate based on the temporary bonding layer;
s4, the top surface of the plastic package carrier plate is higher than or equal to the top surface of the plastic package layer on the back side of the chip monomer to obtain a plastic package body;
s5, manufacturing an electric connection structure on the plastic package body.
In particular, a wafer refers to a silicon wafer used for manufacturing a silicon semiconductor circuit, that is, a plurality of chips can be prepared based on wafer dicing, which is actually composed of a plurality of closely connected chips (i.e., dies), each of which has PADs (PADs) or bumps (bumps) for I/O connection, and the packaging process of the chips essentially designs a process of circuit-out connection of the PADs of the chips PAD for I/O connection.
More specifically, compared with the prior art, the preparation method of the embodiment of the application directly starts the first step of the packaging process on the wafer, and utilizes the step S1 to set the structural metal layer on the surface of the wafer, namely, corresponding setting structural metal layers are directly set on the chips at different positions by taking the chips on the wafer as reference, so that the accuracy of the manufacturing positions of the setting structural metal layers is ensured; it should be noted that, the PAD of each chip on the wafer is connected with a corresponding structural metal layer, so that the structural metal layer can be used as a contact point for electrical connection of the chip, so that the PAD of the corresponding chip can be led out based on the connection of the structural metal layer and a subsequent electrical connection structure; the PAD of the chip is generally made of aluminum or copper or aluminum-copper alloy, and is easy to be corroded by liquid medicine, so that the structural metal layer can protect the PAD of the chip.
More specifically, the dicing process in step S2 is a dicing process of the wafer, and the wafer can be diced into a plurality of die units according to the distribution (preset distribution) of the dies on the wafer, where each die unit includes a die, a plurality of PADs, and the structural metal layer fabricated based on step S1.
More specifically, one end of the chip with the PAD is a positive side, and one end away from the PAD is a back side, and step S3 is to fix the positive side (the structural metal layer of the chip monomer) of the chip monomer on the carrier plate after the chip monomer is inverted, so that the back side of the chip monomer faces upwards; in step S3, a plurality of chip monomers are fixed on a carrier plate, so as to realize batch production of packaged chips.
More specifically, the plastic packaging process can fix the relative positions of the plurality of chip monomers and is beneficial to manufacturing related electric connection structures by using one or more chips so as to obtain the packaged chips meeting the expected requirements; in addition, since the chip monomer is fixed on the carrier plate based on the structural metal layer, the plastic packaging treatment process can generate a groove-shaped structure surrounding the structural metal layer, thereby forming a deposition hole similar to the existing flip chip (face down) packaging structure based on laser drilling, and the structural metal layer is already covered in the operation structure, so that the packaging method of the embodiment of the application can skip the treatment process of metal layer deposition for the plastic packaging body after laser drilling to lead out PAD, and can directly utilize the step S5 to manufacture an electric connection structure on the structural metal layer; the process of fabricating the electrical connection structure in step S5 is a process of fabricating a related electrical connection circuit, which can be fabricated by using a conventional fabrication method of the electrical connection structure used for the flip-chip package structure, and therefore will not be described herein.
Compared with the traditional flip-chip packaging process, the preparation method of the flip-chip packaging structure of the embodiment of the application firstly takes the chip on the wafer as a processing reference to manufacture the structural metal layer, so that the structural metal layer can be accurately arranged on the chip and protect the PAD of the chip, and the chip monomer and the structural metal layer are packaged at the same time after the chip monomer is flipped, so that the preparation method of the flip-chip packaging structure of the embodiment of the application skips the laser drilling process of the traditional flip-chip packaging structure preparation method and the process of covering the metal layer later, omits the deviation of laser drilling, improves the processing precision of the packaging structure, and further improves the yield of products; in addition, the process of laser drilling and covering a metal layer can be omitted, and the production efficiency of the packaging structure can be effectively improved.
In some preferred embodiments, the structural metal layer is a UBM layer or a tin oxide layer.
Specifically, the UBM layer, namely the under bump metallization layer (under bump metalization), has the structural characteristics of a sink, can be connected to the PAD for protecting and leading out the chip, is formed by a deposition method, and can be realized by adopting a sputtering, electroless, plating mode.
More specifically, the tin-plated layer is formed by tin-plating treatment, has a specific property of smoothness, flatness and compactness, and can uniformly cover the PAD of the chip to lead out the PAD.
In some preferred embodiments, when the structural metal layer is a UBM layer, the step of disposing the structural metal layer includes:
s11, defining passivation patterns on the upper surface of the wafer based on chip distribution;
and S12, depositing a UBM layer on the upper surface of the wafer according to the passivation pattern.
Specifically, the passivation pattern is designed based on the chip distribution, so that the PAD of each chip on the whole wafer is correspondingly provided with a UBM layer.
In some preferred embodiments, the step of disposing the structural metal layer includes the step performed prior to S11:
s10, a dielectric thickening layer surrounding the PAD is arranged on the upper surface of the wafer based on chip distribution.
Specifically, the dielectric thickening layer is arranged to cover the part except the PAD in the chip to protect the chip, and an opening is formed at the PAD, so that the UBM layer is deposited based on the dielectric thickening layer, the UBM layer is converged more compactly and is mainly deposited in the opening, the electric connection structure can be directly connected with the UBM deposited in the middle of the PAD, the routing range is shortened, the chip interval in the whole plastic package body is smaller, the number of chip monomers in the plastic package body in each packaging treatment is increased, and the production efficiency is improved.
More specifically, the dielectric thickening layer is made of a synthetic resin film, and the synthetic resin film is one of an ABF film, a PI film and an ABF-like film.
In some preferred embodiments, the dielectric thickening layer is a PI protective layer with a plurality of enclosure holes to surround each PAD on the wafer.
In some preferred embodiments, a structural metal layer overlies the PADs of the individual chips on the wafer.
In some preferred embodiments, the UBM layer includes a submerged metal structure that is the same number of PADs on the wafer and whose submerged bottom completely covers the corresponding PADs.
Specifically, in the embodiment of the application, each PAD is provided with a corresponding UBM layer, so that all PADs can be led out based on the corresponding UBM layer without mutual interference, and the submerged bottom of the UBM layer completely covers the corresponding PAD, so that the PAD can be protected from corrosion and has a good contact end for led out.
In some preferred embodiments, the submerged metal structure is inclined inward to sink.
Specifically, the UBM layer that is inclined and sunk inwards has a sunk groove that gradually expands upwards, which is beneficial to the step S5 of manufacturing the electrical connection structure to connect with the bottom of the UBM layer to conduct with the PAD.
In some preferred embodiments, step S5 comprises:
s51, removing the carrier plate on the plastic package body;
s52, inversely detaching the plastic package body after the carrier plate, and sequentially performing the processes of manufacturing a rewiring layer, opening a window by ink and implanting balls.
Specifically, the front side of the chip monomer in the plastic package body after the carrier plate is removed and inverted is upwards arranged, namely, the structural metal layer based on the plastic package layer surrounding is positioned on the top surface of the plastic package body and exposed, so that the preparation method of the embodiment of the application can obtain the electric connection structure for leading out the PAD on the removed carrier plate through the processes of manufacturing the rewiring layer, ink windowing and ball planting.
More specifically, the chip monomer and the plastic sealing layer are connected to the carrier based on the temporary bonding layer, so that step S51 quickly removes the carrier by releasing the temporary bonding layer.
In a second aspect, referring to fig. 3, some embodiments of the present application further provide a package structure prepared by using the method for preparing a flip chip package structure provided in the first aspect, where the package structure includes:
a plastic layer 1;
the chip monomer 2 is arranged in the plastic sealing layer 1, and the top surface of the chip monomer is provided with a structural metal layer 3;
and the electric connection structure is arranged on the plastic sealing layer and the structural metal layer.
The electrical connection structure includes:
a rewiring layer 6 provided on the structural metal layer 3;
an ink layer 5 provided on the rewiring layer 6 and having a plurality of ink windows;
the first ball-planting device 7 is arranged on the ink layer 5 and is connected with the rewiring layer 6 through the ink window.
In the packaging process of the packaging structure, the chip on the wafer is used as the processing reference to manufacture the structural metal layer 3, so that the structural metal layer 3 can be accurately arranged on the chip and protect the PAD of the chip, and the chip monomer 2 and the structural metal layer 3 are packaged at the same time after the chip monomer 2 is inverted, so that the packaging process skips the laser drilling process of the existing inverted packaging structure preparation method and the process of covering the metal layer afterwards, the deviation of laser drilling is omitted, the processing precision of the packaging structure is improved, and the yield of products is improved.
More specifically, as shown in fig. 4, the package structure of the embodiment of the present application may further provide a dielectric thickening layer 4 to raise the edge of the structural metal layer 3.
In summary, the embodiment of the application provides a preparation method of a flip chip packaging structure and a packaging structure, wherein compared with the traditional flip chip packaging process, the preparation method firstly takes chips on a wafer as processing references to manufacture a structural metal layer, so that the structural metal layer can be accurately arranged on the chips and protect PADs of the chips, and the chip monomers and the structural metal layer are packaged at the same time after the chip monomers are flipped, so that the preparation method of the flip chip packaging structure skips the laser drilling process of the traditional flip chip packaging structure preparation method and the process of covering the metal layer, the deviation of laser drilling is omitted, the processing precision of the packaging structure is improved, and the yield of products is improved.
In the description of the present specification, reference to the terms "one embodiment," "certain embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
What has been described above is merely some embodiments of the present application. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit of the application.

Claims (10)

1. The preparation method of the flip chip packaging structure is characterized by comprising the following steps of:
s1, providing a wafer, and arranging a structural metal layer on the upper surface of the wafer based on chip distribution;
s2, dicing the wafer according to the chip distribution to obtain chip monomers;
s3, providing a carrier plate, and reversely fastening and fixing the chip monomer on the carrier plate based on the temporary bonding layer;
s4, the top surface of the plastic package carrier plate is higher than or equal to the top surface of the plastic package layer on the back side of the chip monomer to obtain a plastic package body;
s5, manufacturing an electric connection structure on the plastic package body.
2. The method for manufacturing a flip-chip package structure according to claim 1, wherein the structural metal layer is a UBM layer or a tin oxide layer.
3. The method of manufacturing a flip-chip package structure according to claim 2, wherein when the structural metal layer is a UBM layer, the step of disposing the structural metal layer includes:
s11, defining passivation patterns on the upper surface of the wafer based on chip distribution;
and S12, depositing the UBM layer on the upper surface of the wafer according to the passivation pattern.
4. The method of manufacturing a flip-chip package structure according to claim 3, wherein the step of disposing the structural metal layer includes the step of, prior to S11:
s10, a dielectric thickening layer surrounding the PAD is arranged on the upper surface of the wafer based on chip distribution.
5. The method of claim 4, wherein the dielectric thickening layer is a PI protective layer having a plurality of holes surrounding each PAD on the wafer.
6. The method of claim 3, wherein the UBM layer comprises a submerged metal structure having the same number of PADs as the PADs on the wafer, and the submerged bottom of the submerged metal structure completely covers the corresponding PADs.
7. The method of manufacturing a flip-chip package structure according to claim 6, wherein the sinking metal structure is inclined inward.
8. The method of claim 1, wherein the structural metal layer covers PADs of the individual chips on the wafer.
9. The method for manufacturing a flip-chip package structure according to claim 1, wherein step S5 includes:
s51, removing the carrier plate on the plastic package body;
s52, inversely detaching the plastic package body after the carrier plate, and sequentially performing the processes of manufacturing a rewiring layer, opening a window by ink and implanting balls.
10. A package structure prepared by the method for preparing a flip chip package structure according to any one of claims 1 to 9, wherein the package structure comprises:
a plastic sealing layer;
the chip monomer is arranged in the plastic package layer, and the top surface of the chip monomer is provided with a structural metal layer;
and the electric connection structure is arranged on the plastic sealing layer and the structural metal layer.
CN202310838622.0A 2023-07-10 2023-07-10 Preparation method of flip chip packaging structure and packaging structure Pending CN116844966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310838622.0A CN116844966A (en) 2023-07-10 2023-07-10 Preparation method of flip chip packaging structure and packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310838622.0A CN116844966A (en) 2023-07-10 2023-07-10 Preparation method of flip chip packaging structure and packaging structure

Publications (1)

Publication Number Publication Date
CN116844966A true CN116844966A (en) 2023-10-03

Family

ID=88168635

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310838622.0A Pending CN116844966A (en) 2023-07-10 2023-07-10 Preparation method of flip chip packaging structure and packaging structure

Country Status (1)

Country Link
CN (1) CN116844966A (en)

Similar Documents

Publication Publication Date Title
US11355474B2 (en) Semiconductor package and method manufacturing the same
US10971483B2 (en) Semiconductor structure and manufacturing method thereof
US10325834B2 (en) Semiconductor packages and methods of fabrication thereof
US9859229B2 (en) Package structure and method for forming the same
US20180211936A1 (en) Thin fan-out multi-chip stacked package structure and manufacturing method thereof
US11289401B2 (en) Semiconductor package
US11848265B2 (en) Semiconductor package with improved interposer structure
US20100301472A1 (en) Electronic component and manufacturing method thereof
CN101221936A (en) Wafer level package with die receiving through-hole and method of the same
US10818614B2 (en) Package structure
US20080258306A1 (en) Semiconductor Device and Method for Fabricating the Same
TWI730629B (en) Package structure and method for forming the same
CN116844966A (en) Preparation method of flip chip packaging structure and packaging structure
TW202125732A (en) Package structure and method of forming the same
US20240087983A1 (en) Semiconductor package and method of manufacturing the semiconductor package
US11948914B2 (en) Chip package structure with integrated device integrated beneath the semiconductor chip
US11935824B2 (en) Integrated circuit package module including a bonding system
CN220692002U (en) Semiconductor package
US20240178120A1 (en) Integrated fan-out package and manufacturing method thereof
KR20030002628A (en) Method for fabricating wafer level package
CN116844967A (en) Preparation method of chip packaging structure and packaging structure
CN115101482A (en) Semiconductor packaging structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination