CN116827331A

CN116827331A - Transmitting-side circuit

Info

Publication number: CN116827331A
Application number: CN202210287178.3A
Authority: CN
Inventors: 朱宏镇; 蔡千慧; 陈永泰
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2022-03-22
Filing date: 2022-03-22
Publication date: 2023-09-29

Abstract

The invention discloses a transmitting-end circuit. The transmitting end circuit is provided with a first transmitting node and a second transmitting node, and the transmitting end circuit comprises: the first resistor, the second resistor, the third resistor, the fourth resistor and the driving circuit. The driving circuit comprises a first transistor group, a second transistor group, a third transistor group and a fourth transistor group. The first resistor is coupled between the first output terminal and the first transmitting node. The second resistor is coupled between the second output terminal and the second transmitting node. The third resistor is coupled between the third output terminal and the first transmitting node. The fourth resistor is coupled between the fourth output terminal and the second transmitting node. The first, second, third and fourth transistor groups are respectively coupled between a first reference voltage and a second reference voltage and are respectively electrically connected with the first, second, third and fourth output ends.

Description

Transmitting-side circuit

Technical Field

The present invention relates to a transmitting-side circuit, and more particularly, to impedance matching of a transmitting-side circuit.

Background

Fig. 1 shows a conventional transmitter circuit. The transmitting-side circuit 120 amplifies an output signal of a digital-to-analog converter (DAC) 110 and then couples the amplified output signal to a load resistor RL through a transformer 130. The transmit-side circuit 120 includes a driving circuit 122, a switching resistor network 124, a switching resistor network 126, a resistor Rp1, a resistor Rp2, a resistor Rp3, a resistor Rp4, a feedback resistor Rf1, and a feedback resistor Rf2.MDIP and MDIN are the transmitting nodes of the transmitting-side circuit 120.

The characteristic impedance of the transmit-side circuit 120 (consisting of resistor Rp1, resistor Rp2, resistor Rp3, resistor Rp4, switched resistor network 124, and switched resistor network 126) must match the load resistor RL. However, because of process drift, the resistance values of the resistors Rp1, rp2, rp3, and Rp4 may not be the originally designed resistance values. The purpose of the switched resistor network 124 and the switched resistor network 126 is to correct the resistance values to achieve impedance matching.

Referring to fig. 2, fig. 2 is a circuit diagram of a switched resistor network. The switching resistor network 124 and the switching resistor network 126 may be exemplified by the switching resistor network 200. The switched resistor network 200 includes a resistor R0 and a plurality of resistor-switch units 210 (including resistor-switch units 210_1, …, and resistor-switch units 210_n, n being equal to or greater than 2). Taking the resistor-switch units 210—n as an example, each resistor-switch unit 210 includes 2 resistors (Ran and Rbn) and 2 transistors (MNn and MPn), and the 2 transistors form a transmission gate, and the transmission gate is controlled by the control signal ct_n and the control signal ctb_n. The equivalent resistance of the switch resistor network 200 can be adjusted by controlling whether the transmission gate is on or not, so as to achieve the purpose of correcting the resistance.

Because of the large signal swing on the switched resistor network 124 and the switched resistor network 126, the transistor of fig. 2 must be able to withstand high voltages. However, the conventional transmitter circuit 120 is not suitable for advanced processes because the transistors fabricated in advanced processes cannot withstand high voltages.

Disclosure of Invention

In view of the shortcomings of the prior art, an objective of the present invention is to provide a transmitting-side circuit to improve the shortcomings of the prior art.

One embodiment of the present invention provides a transmitting-side circuit. The transmitting end circuit is provided with a first transmitting node and a second transmitting node, and the transmitting end circuit comprises: the first resistor, the second resistor, the third resistor, the fourth resistor and the driving circuit. The driving circuit comprises a first transistor group, a second transistor group, a third transistor group and a fourth transistor group. The first resistor is coupled between the first output terminal and the first transmitting node. The second resistor is coupled between the second output terminal and the second transmitting node. The third resistor is coupled between the third output terminal and the first transmitting node. The fourth resistor is coupled between the fourth output terminal and the second transmitting node. The first transistor group is coupled between a first reference voltage and a second reference voltage and is electrically connected to the first output terminal. The second transistor group is coupled between the first reference voltage and the second reference voltage and is electrically connected to the second output terminal. The third transistor group is coupled between the first reference voltage and the second reference voltage and is electrically connected to the third output terminal. The fourth transistor group is coupled between the first reference voltage and the second reference voltage and is electrically connected to the fourth output terminal.

The transmitting end circuit achieves the aim of impedance matching by providing a plurality of transistor groups and a plurality of resistors. Compared with the prior art, the invention is suitable for advanced process because the characteristic impedance is not corrected by a mode of serially connecting resistors with a transmission gate.

The present invention is described in detail below with reference to the drawings, which illustrate examples and effects of the present invention.

Drawings

FIG. 1 shows a conventional transmitter circuit;

FIG. 2 is a circuit diagram of a conventional switched resistor network;

FIG. 3 is a functional block diagram of one embodiment of a transmitter circuit of the present invention;

FIG. 4 is a functional block diagram of one embodiment of a driving circuit;

FIG. 5 shows an internal circuit of a plurality of transistor groups;

FIG. 6 shows an internal circuit of a plurality of transistor groups;

fig. 7 shows an embodiment of a transistor group coupling resistor according to the present invention.

Detailed Description

The technical terms used in the following description are used to refer to the conventional terms in the art, and some terms are described or defined in the specification, and the explanation of the some terms is based on the description or definition of the specification.

The present disclosure includes a transmitting-side circuit. Since some of the components included in the transmitter circuit of the present invention may be known components alone, details of known components will be omitted from the following description without affecting the full disclosure and operability of the device.

In the following description, each transistor has a first terminal, a second terminal, and a control terminal. When the transistor is used as a switch, the first terminal and the second terminal of the transistor are two terminals of the switch, and the control terminal controls the switch to be conductive (the transistor is turned on) or non-conductive (the transistor is turned off). For a Metal-Oxide-semiconductor field effect transistor (MOSFET), the first terminal may be one of a source (source) and a drain (drain), the second terminal may be the other of the source and the drain, and the control terminal may be a gate (gate). For a bipolar junction transistor (bipolar junction transistor, BJT), the first terminal may be one of a collector (collector) and an emitter (emitter), the second terminal may be the other of the collector and the emitter, and the control terminal may be a base (base).

FIG. 3 is a functional block diagram of one embodiment of a transmitter circuit 300 according to the present invention. In an embodiment, the transmitter circuit 300 is, for example, an ethernet transmitter circuit. The transmitting-side circuit 300 includes a driving circuit 310, a resistor rp_0, a resistor rp_1, a resistor rp_m, a resistor rn_0, a resistor rn_1, a resistor rn_m, a feedback resistor rp_f, and a feedback resistor rn_f. The transmitting circuit 300 receives the input signal vip and the input signal vin through the input terminal N1 and the input terminal N2, and is coupled to the transformer 130 through the transmitting node MDIP and the transmitting node MDIN. The input signal vip and the input signal vin are output signals of the digital-to-analog converter 110.

The driving circuit 310 includes a plurality of output terminals: output terminal vop_0, output terminals vop_1, …, output terminal vop_m, output terminal von_0, output terminals von_1, …, and output terminal von_m (m.gtoreq.1). The resistor rp_0 is coupled or electrically connected between the output terminal vop_0 and the transmitting node MDIP; the resistor rp_1 is coupled or electrically connected between the output terminal vop_1 and the transmitting node MDIP; the resistor rp_m is coupled or electrically connected between the output terminal vop_m and the transmitting node MDIP; the resistor Rn_0 is coupled or electrically connected between the output terminal von_0 and the transmitting node MDIN; the resistor Rn_1 is coupled or electrically connected between the output terminal von_1 and the transmitting node MDIN; the resistor rn_m is coupled or electrically connected between the output terminal von_m and the transmitting node MDIN. The feedback resistor rp_f is coupled or electrically connected between the output terminal von_0 and the input terminal N1, and the feedback resistor rn_f is coupled or electrically connected between the output terminal von_0 and the input terminal N2.

The present invention controls the number of resistor strings/parallel connections (i.e., corrects the resistance value) by controlling the configuration of the driving circuit 310, thereby achieving impedance matching. The following describes how to control the configuration of the driving circuit 310 with reference to fig. 4 to 6.

Referring to fig. 4, fig. 4 is a functional block diagram of one embodiment of a driving circuit 310. The driving circuit 310 includes an amplifier circuit 311, a plurality of transistor groups 314 (including 314_0, 314_1, …, 314_m), and a plurality of transistor groups 316 (including 316_0, 316_1, …, 316_m). The amplifier circuit 311 includes an operational amplifier 312. The operational amplifier 312 receives the input signal vip and the input signal vin, and outputs a signal vop1_g, a signal vop2_g, a signal von1_g, and a signal von2_g. In an embodiment, the signals vop1_g and vop2_g are a set of differential signals. The signal von1_g and the signal von2_g are a set of differential signals. Each transistor group 314 receives the signals vop1_g and von1_g, and each transistor group 316 receives the signals vop2_g and von2_g. The transistor group 314_0, the transistor group 314_1, the transistor group 314_m, the transistor group 316_0, the transistor group 316_1, the transistor group 316_m are all coupled or electrically connected between a first reference voltage (e.g., the voltage source VDD) and a second reference voltage (e.g., the ground GND, VDD > GND), and are electrically connected to the output terminal vop_0, the output terminal vop_1, the output terminal vop_m, the output terminal von_0, the output terminal von_1, and the output terminal von_m, respectively; in other words, the output terminals vop_0, vop_1, vop_m, von_0, von_1 and von_m are the output terminals of the transistor group 314_0, 314_1, 314_m, 316_0, 316_1 and 316_m, respectively.

Each transistor group may be enabled (i.e., on) or disabled (i.e., off). When a transistor group is enabled, its corresponding resistance (i.e., the resistance coupled or electrically connected to the output of the transistor group) becomes part of the characteristic impedance of the transmitter circuit 300 (i.e., the resistance value of the resistance affects the characteristic impedance); when a certain transistor group is disabled, its corresponding resistance is not part of the characteristic impedance of the transmit-side circuit 300 (i.e., the resistance value of the resistance does not affect the characteristic impedance). For example, when the transistor group 314_1 is enabled, the resistor rp_1 participates in the correction of the resistance value (i.e., affects the impedance matching).

Since the transistor group 314_0 and the transistor group 316_0 are respectively coupled or electrically connected to the feedback resistor rp_f and the feedback resistor rn_f, the transistor group 314_0 and the transistor group 316_0 remain on.

In some embodiments, paired transistor groups (314_k and 316_k, where 1.ltoreq.k.ltoreq.m) are enabled together or disabled together. When the transistor group 314_k and the transistor group 316_k are enabled together, the output terminal vop_k and the output terminal von_k form a virtual ground (virtual ground). For example, referring to fig. 3 and 4, when the transistor group 314_0, the transistor group 316_0, the transistor group 314_1 and the transistor group 316_1 are all enabled, and the other transistor groups are all disabled, the characteristic impedance of the transmitting-side circuit 300 is equal to (rp_0+rn_0)// (rp_1+rn_1) (wherein '//' represents parallel).

In some embodiments (for purposes of example only and not limitation of the invention), the resistance value of resistor Rp_0 is equal to the resistance value of resistor Rn_0, the resistance value of resistor Rp_1 is equal to the resistance value of resistor Rn_1, …, and the resistance value of resistor Rp_m is equal to the resistance value of resistor Rn_m.

In some embodiments (which are intended to be illustrative and not limiting, the present invention), the resistance values of the resistors Rp_0 and Rn_0 are 2/32 kiloohms (kilo-ohm), and the resistance values of the resistors Rp_k and Rn_k are 2/2 ^k-1 Kiloohms (where 1.ltoreq.k.ltoreq.m).

Referring to fig. 5, fig. 5 shows the internal circuitry of the plurality of transistor groups 314. Each transistor group 314 includes 4 transistors and 2 switches. Taking the transistor group 314_0 as an example, the transistor group 314_0 includes a transistor MP_0, a transistor MN_0, a transistor MPC_0, a transistor MNC_0, a switch SWP_0, and a switch SWN_0. The source of the transistor MP_0 is coupled or electrically connected to the first reference voltage; the drain of the transistor MP_0 is coupled or electrically connected to the output terminal vop_0; the gate of the transistor MP_0 is coupled or electrically connected to the switch SWP_0. The source of the transistor mn_0 is coupled or electrically connected to the second reference voltage; the drain of the transistor mn_0 is coupled to or electrically connected to the output terminal vop_0; the gate of the transistor mn_0 is coupled to or electrically connected to the switch swn_0. The source of the transistor MPC_0 is coupled or electrically connected with the drain of the transistor MP_0; the drain of the transistor MPC_0 is coupled or electrically connected to the output terminal vop_0; the gate of transistor mpc_0 receives the voltage PMOS-biasP. The source of the transistor MNC_0 is coupled or electrically connected with the drain of the transistor MN_0; the drain of the transistor MNC_0 is coupled or electrically connected to the output terminal vop_0; the gate of transistor mnc_0 receives the voltage NMOS-biasN. Switch swp_0 is controlled by control signal powb_p_0. When the control signal powb_p_0 is at the first level, the gate of the transistor mp_0 receives the signal vop1_g (i.e., is coupled or electrically connected to the operational amplifier 312); when the control signal powb_p_0 is at the second level, the gate of the transistor mp_0 receives the first reference voltage (i.e., is coupled or electrically connected to the voltage source VDD). Switch swn_0 is controlled by control signal powbb_n_0. When the control signal powbb_n_0 is at the first level, the gate of the transistor mn_0 receives the signal von1_g (i.e., is coupled or electrically connected to the operational amplifier 312); when the control signal powbb_n_0 is at the second level, the gate of the transistor mn_0 receives a second reference voltage (e.g., ground GND).

When the gate of transistor MP_0 receives the signal vop1_g and the gate of transistor MN_0 receives the signal von1_g, transistor group 314_0 is enabled; when the gate of the transistor MP_0 receives the first reference voltage and the gate of the transistor MN_0 receives the second reference voltage, the transistor group 314_0 is disabled.

The transistors MPC_0 and MNC_0 have protection function to prevent the transistors MP_0 and MN_0 from being subjected to excessive voltage. The voltage PMOS-biasP is the bias voltage of transistor MPC_0, and the voltage NMOS-biasN is the bias voltage of transistor MNC_0. In some embodiments, the transistors mpc_0 and mnc_0 may be omitted if the transistors mp_0 and mn_0 are not subjected to excessive voltages.

The transistor group 314_1 includes a transistor MP_1, a transistor MN_1, a transistor MPC_1, a transistor MNC_1, a switch SWP_1, and a switch SWN_1. The switches swp_1 and swn_1 are controlled by the control signals powb_p_1 and powbb_n_1, respectively. The transistor group 314_m includes a transistor mp_m, a transistor mn_m, a transistor mpc_m, a transistor mnc_m, a switch swp_m, and a switch swn_m. The switch swp_m and the switch swn_m are controlled by the control signal powb_p_m and the control signal powbb_n_m, respectively. The structures of the transistor group 314_1 and the transistor group 314_m are the same as the transistor group 314_0, and thus will not be described again.

The structure of the transistor group 316 is the same as that of the transistor group 314, and a person skilled in the art can refer to fig. 5 to implement the transistor group 316, so that the description thereof is omitted.

Referring to fig. 6, fig. 6 shows the internal circuitry of the plurality of transistor groups 314. The implementation details of the switch of fig. 5 can be seen from fig. 6. The switch swp_0 includes a transistor mp_0_vo and a transistor mp_0_pwd. The switch swn_0 includes a transistor mn_0_vo and a transistor mn_0_pwd. The switch swp_1 includes a transistor mp_1_vo and a transistor mp_1_pwd. The switch swn_1 includes a transistor mn_1_vo and a transistor mn_1_pwd. The switch swp_m includes a transistor mp_m_vo and a transistor mp_m_pwd. The switch swn_m includes a transistor mn_m_vo and a transistor mn_m_pwd.

Take switch swp_0 as an example. The source of the transistor MP_0_vo is coupled or electrically connected with the gate of the transistor MP_0; the drain of the transistor mp_0_vo receives the signal vop1_g; the gate of the transistor mp_0_vo receives the control signal powb_p_0. The source of the transistor MP_0_PWD is coupled or electrically connected to the first reference voltage; the drain of the transistor MP_0_PWD is coupled or electrically connected to the gate of the transistor MP_0; the gate of the transistor mp_0_pwd receives the control signal powbb_p_0. The control signal powb_p_0 and the control signal powbb_p_0 are opposite signals. When the control signal powb_p_0 is high, the transistor mp_0_vo is turned off and the transistor mp_0_pwd is turned on (when the transistor mp_0 is turned off); when the control signal powb_p_0 is low, the transistor mp_0_vo is turned on and the transistor mp_0_pwd is turned off (the transistor mp_0 is turned on).

Those skilled in the art can know the implementation details of other switches from the above description about the switch swp_0, and therefore the description is omitted. The control signal powbb_n_0 and the control signal powb_n_0 are mutually inverted signals. The control signal powb_p_1 and the control signal powbb_p_1 are mutually inverted signals. The control signal powbb_n_1 and the control signal powb_n_1 are mutually inverted signals. The control signal powb_p_m and the control signal powbb_p_m are mutually inverted signals. The control signal powbb_n_m and the control signal powb_n_m are mutually inverted signals.

Fig. 6 is merely an example, and the implementation of the switch of fig. 5 is not limited to fig. 6.

Referring to fig. 7, fig. 7 shows an embodiment of a transistor group coupling resistor according to the present invention. The transistor group 314_k (or the transistor group 316_k, where 0.ltoreq.k.ltoreq.m) includes a plurality of unit transistor groups 710, each unit transistor group 710 is coupled or electrically connected to a unit resistor R_u, and the unit transistor groups 710 and the unit resistors R_u are connected in parallel.

In some embodiments (for purposes of example only and not limiting the invention), the transistor group 314_k and the transistor group 316_k each include 2 ^k A group 710 of unit transistors, and the resistors Rp_k and Rn_k (i.e., the resistors respectively coupled or electrically connected to the output terminals vop_k and von_k) each comprise 2 ^k And a unit resistor R _ u. The advantage of this design is that since each transistor group 314—k and 316—k is composed of the unit transistor group 710 and each resistor rp—k and rn—k is composed of the unit resistor r_u, the transistor groups 314—k, 316—k, rp—k and rn—k are proportional to the process (proportional to the number of the unit transistor group 710 or the unit resistor r_u included), which is beneficial to the correction (i.e., impedance matching) of the resistance value of the entire transmitting-side circuit 300.

Note that the dashed lines on the transistors in fig. 5 and 6 represent the bias of the base of the transistor; however, this is just one embodiment, and the present invention is not limited thereto. Other base bias schemes are also contemplated by the present invention.

It should be noted that the shapes, sizes and proportions of the components are merely illustrative for the purpose of those skilled in the art to understand the present invention, and are not intended to limit the present invention.

Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art may make various changes to the technical features of the present invention according to the explicit or implicit matters of the present invention, and all the changes may be within the scope of the present invention as defined by the claims.

Claims

1. A transmitter circuit having a first transmitter node and a second transmitter node, the transmitter circuit comprising:

the first resistor is coupled between the first output end and the first transmitting node;

the second resistor is coupled between the second output end and the second transmitting node;

the third resistor is coupled between the third output end and the first transmitting node;

a fourth resistor coupled between a fourth output terminal and the second transmitting node; and

a driving circuit comprising:

a first transistor group coupled between a first reference voltage and a second reference voltage and electrically connected to the first output terminal;

a second transistor group coupled between the first reference voltage and the second reference voltage and electrically connected to the second output terminal;

a third transistor group coupled between the first reference voltage and the second reference voltage and electrically connected to the third output terminal; and

and a fourth transistor group coupled between the first reference voltage and the second reference voltage and electrically connected to the fourth output terminal.

2. The transmitting-side circuit of claim 1, further comprising:

an operational amplifier outputting a first signal, a second signal, a third signal and a fourth signal;

the first transistor group and the third transistor group respectively receive the first signal and the second signal, and the second transistor group and the fourth transistor group respectively receive the third signal and the fourth signal.

3. The transmit side circuit of claim 2, wherein the first transistor group, the second transistor group, the third transistor group, and the fourth transistor group each comprise:

a first transistor having a first source, a first drain and a first gate, wherein the first source is coupled to the first reference voltage, the first drain is coupled to the first output terminal, the second output terminal, the third output terminal or the fourth output terminal, and the first gate receives the first signal, the third signal or the first reference voltage; and

the second transistor is provided with a second source electrode, a second drain electrode and a second grid electrode, wherein the second source electrode is coupled with the second reference voltage, the second drain electrode is coupled with the first output end, the second output end, the third output end or the fourth output end, and the second grid electrode receives the second signal, the fourth signal or the second reference voltage.

4. The transmit side circuit of claim 3, wherein the first transistor group, the second transistor group, the third transistor group, and the fourth transistor group each further comprise:

a first switch coupled to the first gate for coupling the first gate to the operational amplifier or the first reference voltage according to a first control signal; and

the second switch is coupled to the second gate for coupling the second gate to the operational amplifier or the second reference voltage according to a second control signal.

5. The transmit-side circuit of claim 4, wherein the first switch and the second switch each comprise:

a third transistor having a third source, a third drain and a third gate, wherein the third source is coupled to the first gate or the second gate, the third drain receives the first signal, the second signal, the third signal or the fourth signal, and the third gate receives the first control signal or the second control signal; and

the fourth transistor is provided with a fourth source electrode, a fourth drain electrode and a fourth grid electrode, wherein the fourth source electrode is coupled with the first reference voltage or the second reference voltage, the fourth drain electrode is coupled with the first grid electrode or the second grid electrode, and the fourth grid electrode receives an inversion signal of the first control signal or an inversion signal of the second control signal.

6. The transmit side circuit of claim 3, wherein the first transistor group, the second transistor group, the third transistor group, and the fourth transistor group each further comprise:

a third transistor having a third source, a third drain and a third gate, wherein the third source is coupled to the first drain, the third drain is coupled to the first output terminal, the second output terminal, the third output terminal or the fourth output terminal, and the third gate receives a first voltage; and

and a fourth transistor having a fourth source, a fourth drain and a fourth gate, wherein the fourth source is coupled to the second drain, the fourth drain is coupled to the first output terminal, the second output terminal, the third output terminal or the fourth output terminal, and the fourth gate receives a second voltage.

7. The transmitter circuit of claim 2 wherein the operational amplifier has a first input and a second input, the transmitter circuit further comprising:

the first feedback resistor is coupled between the first output end and the first input end; and

the second feedback resistor is coupled between the second output end and the second input end.

8. The transmit side circuit of claim 7, wherein the first transistor group and the second transistor group remain on.

9. The transmitting circuit of claim 1, wherein the first resistor is comprised of R unit resistors and the first transistor group is comprised of R unit transistor groups, R being a positive integer.

10. The transmitting circuit of claim 1, wherein the first resistor has a resistance equal to a resistance of the second resistor, and the third resistor has a resistance equal to a resistance of the fourth resistor.