CN116825033A - Shifting register, grid driving circuit and display device - Google Patents

Abstract

The disclosure provides a shift register, a gate driving circuit and a display device, which belong to the technical field of display, wherein the shift register is configured to provide a gate driving signal for a pixel driving circuit, and the shift register comprises: an input sub-circuit, an output sub-circuit, an operation sub-circuit, and a clock driving sub-circuit; wherein the input subcircuit is configured to receive an input signal and precharge the pull-up node through the input signal; the pull-up node is a connection node between the input sub-circuit and the output sub-circuit; an output sub-circuit configured to output a first clock signal input to the first clock signal terminal through the signal output terminal under control of a pull-up node potential; an operation sub-circuit configured to compare the acquired pixel voltage of the pixel driving circuit with a reference voltage to generate a first control signal; the clock driving sub-circuit is configured to input a first clock signal to the first clock signal terminal according to a first control signal.

Description

Shifting register, grid driving circuit and display device

Technical Field

The disclosure belongs to the technical field of display, and particularly relates to a shift register, a gate driving circuit and a display device.

Background

The grid driving circuit of the display device comprises a plurality of cascaded shift registers, and the shift registers sequentially output scanning signals. At present, the resolution requirement of a display device is higher and higher, and the load of a clock signal line is larger (the load comprises parasitic capacitance and parasitic resistance on a wiring), so that the clock signal is distorted in the transmission process, and the actual charging time of a pixel driving circuit is shortened, thereby causing brightness difference on a display panel and causing bad display panel.

Disclosure of Invention

The present disclosure is directed to at least one of the technical problems in the prior art, and provides a shift register, a gate driving circuit and a display device.

In a first aspect, an aspect of the present disclosure is a shift register configured to provide a gate driving signal to a pixel driving circuit, the shift register including:

an input sub-circuit, an output sub-circuit, an operation sub-circuit, and a clock driving sub-circuit; wherein,,

the input subcircuit is configured to receive an input signal and precharge a pull-up node through the input signal; the pull-up node is a connection node between the input sub-circuit and the output sub-circuit;

The output sub-circuit is configured to output a first clock signal input to a first clock signal end through a signal output end under the control of the potential of the pull-up node;

the operation sub-circuit is configured to compare the acquired pixel voltage of the pixel driving circuit with a reference voltage to generate a first control signal;

the clock driving sub-circuit is configured to input the first clock signal to the first clock signal terminal according to the first control signal.

In some embodiments, the reference voltage is a sawtooth voltage.

In some embodiments, the input subcircuit includes a first transistor and a second transistor;

the control electrode of the first transistor is connected with the second clock signal end, the first electrode of the first transistor is connected with the signal input end, the second electrode of the first transistor is connected with the first electrode of the second transistor, the control electrode of the second transistor is connected with the first voltage end, and the second electrode of the second transistor is connected with the pull-up node.

In some embodiments, the shift register further comprises a voltage holding sub-circuit;

the voltage holding sub-circuit is configured to store a second voltage under control of the first clock signal and output the second voltage to a second pole of the first transistor under control of a pull-down node potential.

In some embodiments, the voltage holding sub-circuit includes a seventh transistor and an eighth transistor;

the control electrode of the seventh transistor is connected with the first clock signal end, the first electrode of the seventh transistor is connected with the second electrode of the first transistor, and the second electrode of the seventh transistor is connected with the first electrode of the eighth transistor; the control electrode of the eighth transistor is connected with the pull-down node, and the second electrode of the eighth transistor is connected with the second voltage end.

In some embodiments, the output subcircuit includes a third transistor and a first capacitor;

the control electrode of the third transistor is connected with the pull-up node, the first electrode of the third transistor is connected with the first clock signal end, and the second electrode of the third transistor is connected with the signal output end; the first polar plate of the first capacitor is connected with the control electrode of the third transistor, and the second polar plate of the first capacitor is connected with the second pole of the third transistor.

In some embodiments, the shift register further includes a pull-down control subcircuit;

the pull-down control sub-circuit is configured to transmit the first voltage to the pull-down node under control of the second clock signal, and to transmit the second clock signal to the pull-down node under control of the pull-up node potential.

In some embodiments, the pull-down control subcircuit includes a fourth transistor and a fifth transistor;

the control electrode of the fourth transistor is connected with the second clock signal end, the first electrode of the fourth transistor is connected with the first voltage end, and the second electrode of the fourth transistor is connected with the pull-down node; the control electrode of the fifth transistor is connected with the input sub-circuit, the first electrode of the fifth transistor is connected with the second clock signal end, and the second electrode of the fifth transistor is connected with the pull-down node.

In some embodiments, the shift register further includes a pull-down subcircuit;

the pull-down subcircuit is configured to transmit a second voltage to the signal output terminal under control of the pull-down node potential.

In some embodiments, the pull-down subcircuit includes a sixth transistor and a second capacitor;

the control electrode of the sixth transistor is connected with the pull-down node, the first electrode of the sixth transistor is connected with the signal output end, and the second electrode of the sixth transistor is connected with the second voltage end; the first polar plate of the second capacitor is connected with the control electrode of the sixth transistor, and the second polar plate of the second capacitor is connected with the second pole of the sixth transistor.

In a second aspect, embodiments of the present disclosure further provide a gate driving circuit including a plurality of cascaded shift registers as in any one of the above embodiments; wherein,,

the signal input end of the first stage shift register is connected with the initial signal end;

the signal output end of the shift register of the stage is connected with the reset signal end of the shift register of the previous stage and the signal input end of the shift register of the next stage except the shift register of the first stage.

In a third aspect, embodiments of the present disclosure further provide a display device including the gate driving circuit described in the above embodiments.

Drawings

FIG. 1 is a schematic diagram of an exemplary display device;

FIG. 2 is a schematic diagram showing brightness differences between two ends of a display panel;

FIG. 3a is a schematic diagram illustrating the operation of a pixel driving circuit according to an embodiment of the disclosure;

FIG. 3b is a driving timing diagram of the pixel driving circuit shown in FIG. 3 a;

fig. 4a is a schematic structural diagram of a shift register according to an embodiment of the disclosure;

FIG. 4b is a timing diagram illustrating a driving operation of the shift register shown in FIG. 4 a;

FIG. 5 is a schematic diagram of the operating principle of the operational sub-circuits in an embodiment of the disclosure;

fig. 6 is a schematic diagram illustrating an operation principle of a clock driving sub-circuit according to an embodiment of the disclosure.

Wherein the reference numerals are as follows: 1. a shift register; 01. a pixel unit; 10. an input sub-circuit; 20. an output sub-circuit; 30. an operator circuit; 40. a clock driving sub-circuit; 50. a voltage holding sub-circuit; 60. a pull-down control subcircuit; 70. a pull-down sub-circuit; PU, pull-up node; PD, pull-down node; GSTV, signal input terminal; GCB, the first clock signal end; GCK, the second clock signal end; gout, signal output; u1, a first control signal; t11, a first reset transistor; t12, threshold compensation transistor; t13, driving transistor; t14, a data writing transistor; cst, storage capacitor; vcst, voltage of storage capacitor; vsw, sawtooth voltage; t15, a first light emitting control transistor; t16, a second light emission control transistor; t17, a second reset transistor; D. a light emitting device; gate, gate line; data, data lines; elvdd, first supply voltage terminal; vinit, reset power signal terminal; reset and Reset control signal terminals; an EM and light emission control end; elvss, second supply voltage terminal; t21, first transistor; t22, a second transistor; VGL, the first voltage end; VGH, the second voltage end; n1, a first node; n2, a second node; t27, seventh transistor; t28, eighth transistor; t23, third transistor; c1, a first capacitor; t24, fourth transistor; t25, fifth transistor; t26, sixth transistor; c2, a second capacitor.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, but not all embodiments. The components of the embodiments of the present disclosure, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the disclosure, as claimed, but is merely representative of selected embodiments of the disclosure. All other embodiments, which can be made by those skilled in the art based on the embodiments of this disclosure without making any inventive effort, are intended to be within the scope of this disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

Reference in the present disclosure to "a plurality of" or "a number" means two or more than two. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

Fig. 1 is a schematic view of an exemplary display device, and as shown in fig. 1, the display device includes a pixel unit 01 located in a display area, the pixel unit 01 includes a pixel driving circuit, and the display device further includes a gate driving circuit and a source driving circuit located in a peripheral area disposed around the display area. The grid driving circuit comprises a plurality of cascaded shift registers 1, wherein the plurality of shift registers 1 are connected with grid lines Gate, and scanning signals are sequentially input to each row of pixel driving circuits; the source driving circuit supplies Data signals to the pixel driving circuits of each column through the Data lines Data.

The clock signal line is used for inputting a clock signal to the shift register so as to control a scanning signal input to the pixel driving circuit, and further control the time of writing a data signal by the pixel driving circuit, namely, the actual charging time of the pixel driving circuit. Fig. 2 is a schematic diagram of brightness difference at two ends of a display panel, as shown in fig. 2, because the load of a clock signal line is larger (the load includes parasitic capacitance and parasitic resistance on a trace), the clock signal is distorted in the transmission process, and then the actual charging time of a pixel driving circuit is shortened, so that brightness difference occurs on the display panel, and the display panel is poor.

Specifically, the principle of the occurrence of the defect is as follows: as the resolution of the display panel is required to be higher and higher, the load on the clock signal line increases, which causes waveform distortion of the clock signal transmitted to the far end of the driving chip (Driver IC) of the display panel, so that the actual charging time of the pixel driving circuit is shortened, and the voltage written into the pixel driving circuit is lower than expected, and finally, the difference exists between the brightness of the far end of the Driver IC and the brightness of the near end of the Driver IC, namely, the display panel is poor.

The inventor finds that, in the prior art, for the problem of brightness difference at two ends of the display panel caused by RC delay, parasitic resistance and parasitic capacitance on the wiring are reduced mainly by optimizing the wiring material of the display panel, reducing the length of the wiring and the like, but these measures only can reduce bad phenomena, cannot completely eliminate brightness abnormality fundamentally, and also increase the production cost of panel factories and the difficulty of flexible circuit board (Flexible Printed Circuit, FPC) circuit Layout (Layout).

In view of this, the present disclosure provides a shift register whose clock signal can be adjusted according to the pixel voltage actually input to the pixel driving circuit, thereby adjusting the actual charging time of the pixel driving circuit, and finally improving the problem of display brightness difference of the display panel due to load distribution.

It should be noted that the shift register provided in the embodiments of the present disclosure may be applied to different pixel driving circuits. For example, the pixel driving circuit may be a 5T2C driving circuit, a 7T1C driving circuit, or the like, which is not particularly limited in the present disclosure. For convenience of description and understanding, in the embodiments of the present disclosure, a pixel driving circuit is taken as an example of a 7T1C (i.e., seven transistors and one capacitor structure) pixel driving circuit, and fig. 3a is a schematic diagram illustrating an operation principle of the pixel driving circuit in the embodiments of the present disclosure; fig. 3b is a driving timing diagram of the pixel driving circuit shown in fig. 3a, and as shown in fig. 3a and 3b, the pixel driving circuit includes a first reset transistor T11, a threshold compensation transistor T12, a driving transistor T13, a data writing transistor T14, a storage capacitor Cst, a first light emitting control transistor T15, a second light emitting control transistor T16, a second reset transistor T17, and a light emitting device D.

It should be noted that, in the embodiment of the present disclosure, the pixel voltage actually input to the pixel driving circuit is taken as an example of the pixel driving circuit shown in fig. 3a, and is the voltage Vcst of the storage capacitor.

It should be noted that, the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and the source and the drain of the transistors are symmetrical, so that there is no difference between the source and the drain. In the embodiments of the present disclosure and in the following description, to distinguish between the source and the drain of a transistor, one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a control pole. In addition, the transistors can be divided into N type and P type according to the characteristic distinction of the transistors, when the P type transistors are adopted, the first electrode is the source electrode of the P type transistors, the second electrode is the drain electrode of the P type transistors, and when the grid electrode inputs low level signals, the source electrode and the drain electrode are conducted; when the N-type transistor is adopted, the first electrode is the source electrode of the N-type transistor, the second electrode is the drain electrode of the N-type transistor, and when the grid electrode inputs a high-level signal, the source electrode and the drain electrode are conducted. In the embodiment of the disclosure, the first reset transistor T11, the threshold compensation transistor T12, the driving transistor T13, the data writing transistor T14, the first light emitting control transistor T15, the second light emitting control transistor T16, and the second reset transistor T17 are all specifically described by taking P-type transistors as examples.

Specifically, the second pole of the Data writing transistor T14 is electrically connected to the first pole of the driving transistor T13, the first pole of the Data writing transistor T14 is configured to be electrically connected to the Data line Data to receive the Data signal, and the control pole of the Data writing transistor T14 is configured to be electrically connected to the signal output terminal Gout to receive the first clock signal; the second polar plate of the storage capacitor Cst is electrically connected with the first power supply voltage end Elvdd, and the first polar plate of the storage capacitor Cst is electrically connected with the control electrode of the driving transistor T13; a first pole of the threshold compensation transistor T12 is electrically connected to a control pole of the driving transistor T13, a second pole of the threshold compensation transistor T12 is electrically connected to a second pole of the driving transistor T13, and a control pole of the threshold compensation transistor T12 is configured to be electrically connected to the signal output terminal Gout to receive the compensation control signal; a first pole of the first Reset transistor T11 is configured to be electrically connected to the Reset power supply signal terminal Vinit to receive a Reset signal, a second pole of the first Reset transistor T11 is electrically connected to the control pole of the driving transistor T13, and a control pole of the first Reset transistor T11 is configured to be electrically connected to the Reset control signal terminal Reset to receive a Reset control signal; a second electrode of the second Reset transistor T17 is configured to be electrically connected to the Reset power supply signal terminal Vinit to receive a Reset signal, a first electrode of the second Reset transistor T17 is electrically connected to the first electrode of the light emitting device D, and a control electrode of the second Reset transistor T17 is configured to be electrically connected to the Reset control signal terminal Reset to receive a Reset control signal; a first pole of the first light emitting control transistor T15 is electrically connected to the first power supply voltage terminal Elvdd, a second pole of the first light emitting control transistor T15 is electrically connected to a first pole of the driving transistor T13, and a control pole of the first light emitting control transistor T15 is configured to be electrically connected to the light emitting control terminal EM to receive a light emitting control signal; a first electrode of the second light emission control transistor T16 is electrically connected to a second electrode of the driving transistor T13, a second electrode of the second light emission control transistor T16 is electrically connected to a first electrode of the light emitting device D, and a control electrode of the second light emission control transistor T16 is configured to be electrically connected to the light emission control terminal EM to receive a light emission control signal; the second electrode of the light emitting device D is electrically connected to the second power supply voltage terminal Elvss.

It should be noted that, one of the first power voltage terminal Elvdd and the second power voltage terminal Elvss is a high voltage terminal, and the other is a low voltage terminal. For example, the first power supply voltage terminal Elvdd is a voltage source to output a constant first power supply voltage, which is a positive voltage; the second power voltage terminal Elvss may be a voltage source to output a constant second power voltage, which is a negative voltage. For example, in some embodiments, the second supply voltage terminal Elvss may be grounded.

The scan signal and the compensation control signal may be identical, i.e., the control electrode of the data writing transistor T14 and the control electrode of the threshold compensating transistor T12 may be electrically connected to the same signal line to receive the same signal (e.g., the scan signal, i.e., the first clock signal in the embodiment of the present disclosure), thereby reducing the number of signal lines. Of course, it is understood that the control electrode of the data writing transistor T14 and the control electrode of the threshold compensating transistor T12 may be electrically connected to different signal lines, respectively.

The scan signal and the compensation control signal may also be different, so that the control electrode of the data writing transistor T14 and the threshold compensation transistor T12 may be separately and individually controlled, increasing the flexibility of controlling the pixel circuit. In the embodiment of the present disclosure, the control electrode of the data writing transistor T14 and the control electrode of the threshold compensating transistor T12 are electrically connected to the signal output terminal Gout.

The control electrode of the first light emission control transistor T15 and the control electrode of the second light emission control transistor T16 may be electrically connected to the same signal line, for example, the light emission control terminal EM, to receive the same signal, thereby reducing the number of signal lines. Of course, it is understood that the control electrode of the first light emission control transistor T15 and the control electrode of the second light emission control transistor T16 may be electrically connected to different signal lines, respectively. In the embodiment of the present disclosure, the control electrodes of the first light emission control transistor T15 and the second light emission control transistor T16 are electrically connected to the light emission control terminal EM.

The control electrode of the first Reset transistor T11 and the control electrode of the second Reset transistor T17 may be electrically connected to the same signal line, for example, the Reset control signal terminal Reset, to receive the same signal, thereby reducing the number of signal lines. Of course, it is understood that the control electrode of the first reset transistor T11 and the control electrode of the second reset transistor T17 may be electrically connected to different signal lines, respectively. In the embodiment of the present disclosure, the control electrode of the first Reset transistor T11 and the control electrode of the second Reset transistor T17 are electrically connected to the Reset control signal terminal Reset.

The first pole of the first reset transistor T11 and the second pole of the second reset transistor T17 may be electrically connected to the same signal line, for example, the reset power signal terminal Vinit may be a dc reference voltage terminal to output a constant dc reference voltage. The reset power signal terminal Vinit may be a high voltage terminal or a low voltage terminal, as long as it can provide a reset signal to reset the control electrode of the driving transistor T13 and the first electrode of the light emitting element, which is not limited in the present disclosure. In the embodiment of the present disclosure, the reset power supply signal terminal Vinit is exemplified that the first pole of the first reset transistor T11 and the second pole of the second reset transistor T17 are electrically connected. In addition, the specific structure in the pixel driving circuit shown in fig. 3a in the embodiment of the disclosure may be set according to the actual application requirement, and the embodiment of the disclosure is not limited in detail.

As shown in fig. 3b, the operation of the pixel driving circuit is divided into: a reset phase t1, a data writing and threshold compensation phase t2 and a light emitting phase t3.

Reset phase (t 1): the Reset control signal end Reset writes a low-level signal, and the signal output end Gout and the light emitting control end EM write a high-level signal; the first reset transistor T11 and the second reset transistor T17 are turned on, and the control electrode of the driving transistor T13 is written with an initial voltage by the reset power signal terminal Vinit, in preparation for writing a data voltage for the next frame. The anode of the light emitting device D is written with an initialization voltage through the second reset transistor T17, so that the light emitting device D is no longer in a forward conduction state, and an internal electric field formed by directional movement of impurity ions in the light emitting device D gradually disappears, thereby restoring the characteristics of the light emitting device D.

Data writing and threshold compensation stage (t 2): the signal output end Gout is written into a low-level signal, and the Reset control signal end Reset and the first light emitting control end EM are written into a high-level signal; the data writing transistor T14 and the threshold compensating transistor T12 are turned on. The driving transistor T13 is connected to a diode structure by the threshold compensation transistor T12, and the Data voltage written on the Data line Data is written to the gate electrode of the driving transistor T13 through the Data writing transistor T14 and the threshold compensation transistor T12 until the driving transistor T13 is turned off, and the gate electrode voltage of the driving transistor T13 is stored in the storage capacitor Cst.

Light-emitting stage (t 3): the light emission control terminal EM writes a low level signal, the signal output terminal Gout and the Reset control signal terminal Reset write a high level signal, the first light emission control transistor T15 and the second light emission control transistor T16 are both turned on, the first pole of the driving transistor T13 is connected to the first power supply voltage terminal Elvdd, and the first pole voltage of the driving transistor T13 is instantaneously changed from the data voltage of the previous stage to the first power supply voltage. The light emitting device D emits light by the driving of the driving transistor T13, and at this time, the driving transistor T13 operates in a saturation region until a reset phase of the next frame.

Wherein, the expression of the light emitting current of the light emitting device D is as follows:

I _ds ＝β(V _Elvdd -V _Data ) ²

wherein,,

wherein I is _ds Representing the driving current of the light emitting device D; v (V) _Elvdd Representing a first supply voltage; v (V) _Data Representing the data voltage.

Beta is a parameter for the drive transistor T13,representing the channel width-to-length ratio of the thin film transistor; c (C) _ox Represents the dielectric constant; μ represents the equivalent mobility, i.e. the average drift velocity of the carriers under the action of a unit electric field.

As can be seen, the larger the data voltage, the smaller the driving current of the light emitting device D, and the lower the luminance of the light emitting device D. When the waveform of the clock signal transmitted to the far end of the Driver IC of the display panel is distorted, the actual charging time of the pixel driving circuit is shortened, so that the voltage written into the pixel driving circuit is lower than expected, and finally the brightness of the far end of the Driver IC is higher than the brightness of the near end of the Driver IC, namely the display panel is poor.

The shift register provided by the embodiments of the present disclosure is specifically described below with reference to the accompanying drawings.

In a first aspect, a technical solution adopted to solve the technical problem of the present disclosure is a shift register, fig. 4a is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure, and as shown in fig. 4a, the shift register is configured to provide a gate driving signal for a pixel driving circuit through a gate line, and the shift register includes: an input sub-circuit 10, an output sub-circuit 20, an operation sub-circuit 30, and a clock driving sub-circuit 40.

Specifically, the input subcircuit 10 is connected with the signal input end GSTV and the pull-up node PU; the pull-up node PU is a connection node between the input sub-circuit 10 and the output sub-circuit 20. The output sub-circuit 20 is connected to the first clock signal terminal GCB, the pull-up node PU and the signal output terminal Gout.

The input sub-circuit 10 is configured to receive an input signal input from the signal input terminal GSTV and precharge the pull-up node PU through the input signal; the output sub-circuit 20 is configured to output the first clock signal input to the first clock signal terminal GCB through the signal output terminal Gout under the control of the potential of the pull-up node PU; the operation sub-circuit 30 is configured to compare the acquired pixel voltage of the pixel driving circuit with a reference voltage to generate a first control signal U1; the clock driving sub-circuit 40 is configured to input a first clock signal to the first clock signal terminal GCB according to the first control signal U1.

Fig. 5 is a schematic diagram of an operating principle of an operational sub-circuit in an embodiment of the present disclosure, as shown in fig. 4a and fig. 5, a pixel voltage of a pixel driving circuit in the embodiment of the present disclosure is actually a voltage Vcst of a storage capacitor in the pixel driving circuit, a reference voltage in the embodiment of the present disclosure is actually a sawtooth voltage Vsw input by an oscillator, and by comparing the voltage Vcst of the storage capacitor in the pixel driving circuit with the sawtooth voltage Vsw input by the oscillator, a first control signal U1 with a duty ratio that varies with the voltage Vcst of the storage capacitor can be output.

Further, in some embodiments, the operator circuit 30 may be a PWM regulator. The non-inverting input terminal of the PWM regulator is connected to the oscillator, the inverting input terminal of the PWM regulator is connected to the first plate of the storage capacitor Cst of the pixel driving circuit, and the output terminal of the PWM regulator is connected to the clock driving sub-circuit 40. In the embodiment of the disclosure, the non-inverting input terminal of the PWM regulator inputs the sawtooth voltage Vsw generated by the oscillator, the inverting input terminal of the PWM regulator inputs the voltage Vcst of the storage capacitor of the pixel driving circuit, and the PWM regulator compares the sawtooth voltage Vsw with the voltage Vcst of the storage capacitor and outputs the first control signal U1 having a certain duty cycle to realize the final change of the clock signal input to the output sub-circuit 20.

Specifically, as shown in fig. 5, the saw-tooth voltage Vsw generated by the oscillator is input to the non-inverting input terminal of the PWM regulator, the voltage Vcst of the storage capacitor of the pixel driving circuit is input to the inverting input terminal of the PWM regulator, the saw-tooth voltage Vsw is compared with the voltage Vcst of the storage capacitor by the PWM regulator, when the saw-tooth voltage Vsw input to the non-inverting input terminal of the PWM regulator is greater than the voltage Vcst of the storage capacitor input to the inverting input terminal of the PWM regulator, the output terminal of the PWM regulator outputs a high level, otherwise the output terminal of the PWM regulator outputs a low level. In this process, the period of the first control signal U1 does not change, and when the slope of the sawtooth voltage Vsw generated by the oscillator changes, the duty ratio of the first control signal U1 follows the change, depending on the use scenario and setting. In this way, the first control signal U1 having a certain duty cycle is outputted to effect a final change of the first clock signal inputted to the output sub-circuit 20. The specific parameters of the sawtooth wave signals are not particularly limited in the disclosure.

Fig. 6 is a schematic diagram of the working principle of the clock driving sub-circuit in the embodiment of the disclosure, as shown in fig. 4a and fig. 6, since the driving capability of the first control signal U1 outputted by the operation sub-circuit 30 is weak, the clock driving sub-circuit 40 needs to be configured to convert the first control signal U1 into a first clock signal with a stronger driving capability. In the embodiment of the disclosure, the clock driving sub-circuit 40 may pull the high level voltage of the first control signal U1 up to VGH, and pull the low level voltage of the first control signal U1 down to VGL. For example, the first clock signal is a group of pulse wave signals, the high level voltage of which is VGH, and the low level voltage of which is VGL. The specific values of the high-level voltage VGH and the low-level voltage VGL are not particularly limited in the present disclosure, and may be changed according to actual products.

In the embodiment of the disclosure, by setting the operation sub-circuit 30 to compare the voltage Vcst of the storage capacitor in the pixel driving circuit with the sawtooth voltage Vsw input by the oscillator, and adjusting the duty ratio of the first clock signal finally input to the output sub-circuit 20 in real time according to the comparison result, the actual charging time of the corresponding pixel driving circuit can be increased or decreased, and finally the problem of display brightness difference due to load distribution in the display panel can be improved.

In some embodiments, as shown in fig. 4a, the input sub-circuit 10 includes a first transistor T21 and a second transistor T22. The control electrode of the first transistor T21 is connected to the second clock signal terminal GCK, the first electrode of the first transistor T21 is connected to the signal input terminal GSTV, the second electrode of the first transistor T21 is connected to the first electrode of the second transistor T22, the control electrode of the second transistor T22 is connected to the first voltage terminal VGL, and the second electrode of the second transistor T22 is connected to the pull-up node PU.

In some embodiments, as shown in fig. 4a, the shift register further includes a voltage holding sub-circuit 50. The voltage holding sub-circuit 50 is configured to store a second voltage under control of the first clock signal, and output the second voltage to the second pole of the first transistor T21 under control of the potential of the pull-down node PD.

In some embodiments, as shown in fig. 4a, the voltage holding sub-circuit 50 includes a seventh transistor T27 and an eighth transistor T28. The control electrode of the seventh transistor T27 is connected with the first clock signal end GCB, the first electrode of the seventh transistor T27 is connected with the second electrode of the first transistor T21, and the second electrode of the seventh transistor T27 is connected with the first electrode of the eighth transistor T28; the control electrode of the eighth transistor T28 is connected to the pull-down node PD, and the second electrode of the eighth transistor T28 is connected to the second voltage terminal VGH.

In some embodiments, as shown in fig. 4a, the output sub-circuit 20 includes a third transistor T23 and a first capacitance C1. The control electrode of the third transistor T23 is connected to the pull-up node PU, the first electrode of the third transistor T23 is connected to the first clock signal terminal GCB, and the second electrode of the third transistor T23 is connected to the signal output terminal Gout; the first polar plate of the first capacitor C1 is connected to the control electrode of the third transistor T23, and the second polar plate of the first capacitor C1 is connected to the second polar of the third transistor T23.

In some embodiments, as shown in FIG. 4a, the shift register further includes a pull-down control sub-circuit 60. The pull-down control sub-circuit 60 is configured to transmit the first voltage to the pull-down node PD under control of the second clock signal, which is transmitted to the pull-down node PD under control of the pull-up node PU potential.

In some embodiments, as shown in fig. 4a, the pull-down control subcircuit 60 includes a fourth transistor T24 and a fifth transistor T25. The control electrode of the fourth transistor T24 is connected with the second clock signal end GCK, the first electrode of the fourth transistor T24 is connected with the first voltage end VGL, and the second electrode of the fourth transistor T24 is connected with the pull-down node PD; the control electrode of the fifth transistor T25 is connected to the input sub-circuit 10, the first electrode of the fifth transistor T25 is connected to the second clock signal terminal GCK, and the second electrode of the fifth transistor T25 is connected to the pull-down node PD.

In some embodiments, as shown in FIG. 4a, the shift register further includes a pull-down subcircuit 70. The pull-down sub-circuit 70 is configured to transmit the second voltage to the signal output terminal Gout under the control of the potential of the pull-down node PD.

In some embodiments, as shown in fig. 4a, the pull-down subcircuit 70 includes a sixth transistor T26 and a second capacitor C2. The control electrode of the sixth transistor T26 is connected to the pull-down node PD, the first electrode of the sixth transistor T26 is connected to the signal output terminal Gout, and the second electrode of the sixth transistor T26 is connected to the second voltage terminal VGH; the first electrode plate of the second capacitor C2 is connected to the control electrode of the sixth transistor T26, and the second electrode plate of the second capacitor C2 is connected to the second electrode of the sixth transistor T26.

It should be noted that, in the embodiment of the disclosure, the frequencies of the output signals of the first clock signal terminal GCB and the second clock signal terminal GCK are the same, and the phases are opposite. In the shift register, the first transistor T21, the second transistor T22, the third transistor T23, the fourth transistor T24, the fifth transistor T25, the sixth transistor T26, the seventh transistor T27, and the eighth transistor T28 are P-type transistors. The first voltage terminal VGL outputs a constant low level, and the second voltage terminal VGH outputs a constant high level, for example.

A detailed description will be given below of a complete shift register as shown in fig. 4 a. In the disclosed embodiment, the shift register includes an input sub-circuit 10, an output sub-circuit 20, an operation sub-circuit 30, a clock driving sub-circuit 40, a voltage holding sub-circuit 50, a pull-down control sub-circuit 60, and a pull-down sub-circuit 70.

Specifically, the input sub-circuit 10 includes a first transistor T21 and a second transistor T22; the output sub-circuit 20 includes a third transistor T23 and a first capacitor C1; the pull-down control subcircuit 60 includes a fourth transistor T24 and a fifth transistor T25; the pull-down subcircuit 70 includes a sixth transistor T26 and a second capacitor C2; the voltage holding sub-circuit 50 includes a seventh transistor T27 and an eighth transistor T28.

Specifically, the control electrode of the first transistor T21, the control electrode of the fourth transistor T24 and the first electrode of the fifth transistor T25 are all connected to the second clock signal terminal GCK, the first electrode of the first transistor T21 is connected to the signal input terminal GSTV, the second electrode of the first transistor T21, the first electrode of the second transistor T22, the control electrode of the fifth transistor T25 and the first electrode of the seventh transistor T27 are all connected to the second node N2, the control electrode of the second transistor T22 and the first electrode of the fourth transistor T24 are all connected to the first voltage terminal VGL, the control electrode of the second transistor T22, the control electrode of the third transistor T23 and the first electrode of the first capacitor C1 are all connected to the pull-up node PU, the first electrode of the third transistor T23 and the control electrode of the seventh transistor T27 are all connected to the first clock signal terminal GCB, the second electrode of the second transistor T23, the second electrode of the second capacitor C1 and the first electrode of the fourth transistor T27 are all connected to the second voltage terminal VGL, the second electrode of the fourth transistor T26 is connected to the second electrode of the fifth transistor T28, and the fourth electrode of the fourth transistor T26 is connected to the fifth electrode of the fourth transistor T28, and the fifth electrode of the fourth transistor T28 is all connected to the fifth electrode of the fourth transistor T28 is connected to the fourth electrode of the fourth electrode 26.

Fig. 4b is a driving timing diagram of the shift register shown in fig. 4a, as shown in fig. 4a and 4b, in the first stage T1, gstv=1; gck=0; gcb=1. Where "0" indicates a low level and "1" indicates a high level, and the description thereof will be omitted. In addition, the first voltage terminal VGL outputs a low level, and the second voltage terminal VGH outputs a high level.

At this time, the signal input terminal GSTV outputs a high level, the second clock signal terminal GCK outputs a low level, and the first clock signal terminal GCB outputs a high level. The first transistor T21, the second transistor T22, the fourth transistor T24, the sixth transistor T26, and the eighth transistor T28 are all turned on, and the third transistor T23, the fifth transistor T25, and the seventh transistor T27 are all turned off.

Specifically, the second clock signal terminal GCK outputs a low level, and the first transistor T21 and the fourth transistor T24 are turned on. The first voltage terminal VGL outputs a low level, and the second transistor T22 is turned on. The high level output from the signal input terminal GSTV is transmitted to the second node N2 through the first transistor T21 and to the pull-up node PU through the second transistor T22. The low level output from the first voltage terminal VGL is transmitted to the gate of the eighth transistor T28 through the fourth transistor T24, and the pull-down node PD, both the eighth transistor T28 and the sixth transistor T26 are turned on, and the high level output from the second voltage terminal VGH is output to the signal output terminal Gout.

In the second phase T2, gstv=1; gck=1; gcb=0.

At this time, the signal input terminal GSTV outputs a high level, the second clock signal terminal GCK outputs a high level, and the first clock signal terminal GCB outputs a low level. The second transistor T22, the sixth transistor T26, the seventh transistor T27, and the eighth transistor T28 are all turned on, and the first transistor T21, the fourth transistor T24, the third transistor T23, and the fifth transistor T25 are all turned off.

Specifically, the first clock signal terminal GCB outputs a low level, and the seventh transistor T27 is turned on. The first voltage terminal VGL outputs a low level, and the second transistor T22 is turned on. Under the control of the pull-down node PD, the sixth transistor T26 and the eighth transistor T28 are turned on, and the high level output from the second voltage terminal VGH is output to the signal output terminal Gout.

In the third phase T3, gstv=0; gck=0; gcb=1. At this time, the second clock signal terminal GCK outputs a low level, and the first transistor T21 and the fourth transistor T24 are turned on. The low level output from the signal input terminal GSTV is transmitted to the second node N2 through the first transistor T21, and then transmitted to the pull-up node PU through the turned-on second transistor T22. The fifth transistor T25 is turned on under the control of the second node N2. The low level output from the first voltage terminal VGL is transferred to the pull-down node PD through the fourth transistor T24, and the low level output from the second clock signal terminal GCK is transferred to the pull-down node PD through the fifth transistor T25.

Specifically, after the eighth transistor T28 is turned on and the seventh transistor T27 is turned off and the high level output by the second voltage terminal VGH passes through the eighth transistor T28, the parasitic capacitance GS formed by the gate and the source (or the drain) of the seventh transistor T27 and the parasitic capacitance GD formed by the gate and the drain (or the source) of the eighth transistor T28 may be stored, that is, the high level output by the second voltage terminal VGH is stored at the first node N1.

The third transistor T23 is turned on under the control of the pull-up node PU, and transmits the high level output from the first clock signal terminal GCB to the signal output terminal Gout. The sixth transistor T26 is turned on under the control of the pull-down node PD, and transmits the high level output from the second voltage terminal VGH to the signal output terminal Gout.

In the fourth phase T4, gstv=1; gck=1; gcb=0.

At this time, the second clock signal terminal GCK outputs a high level, and the first transistor T21 and the fourth transistor T24 are turned off. Under the bootstrap action of the first capacitor C1, the pull-up node PU remains low. At this time, the third transistor T23 maintains an on state and outputs a low level of the first clock signal terminal GCB to the signal output terminal Gout. Under the control of the pull-up node PU, the fifth transistor T25 is turned on, and transmits the high level output from the second clock signal terminal GCK to the pull-down node PD. At this time, the eighth transistor T28 and the sixth transistor T26 are turned off.

In the fifth phase T5, gstv=1; gck=0; gcb=1.

At this time, under the control of the low level output from the second clock signal terminal GCK, the first transistor T21 and the fourth transistor T24 are turned on, the high level output from the signal input terminal GSTV is transmitted to the pull-up node PU, and the third transistor T23 and the fifth transistor T25 are turned off.

The low level of the first voltage terminal VGL is transmitted to the pull-down node PD through the fourth transistor T24, the sixth transistor T26 is turned on, and the eighth transistor T28 is turned on. The high level of the second voltage terminal VGH is transmitted to the signal output terminal Gout through the sixth transistor T26 and stored to the first node N1 through the eighth transistor T28. Under control of the first clock signal terminal GCB, the seventh transistor T27 is turned off.

In the sixth phase T6, gstv=1; gck=1; gcb=0.

At this time, the first transistor T21 and the fourth transistor T24 are turned off under the control of the high level output from the second clock signal terminal GCK. The pull-down node PD maintains the low level of the previous stage by the discharging action of the second capacitor C2. At this time, the sixth transistor T26 and the eighth transistor T28 are turned on. Under the low level control of the first clock signal terminal GCB, the seventh transistor T27 is turned on, the high level at the first node N1 is transmitted to the second node N2 and the pull-up node PU, and the third transistor T23 and the fifth transistor T25 are turned off. The high level of the second voltage terminal VGH is transmitted to the signal output terminal Gout through the sixth transistor T26, and the signal output terminal Gout maintains the high level output.

In the embodiment of the present disclosure, the active level input to the pixel driving circuit as shown in fig. 3a is a low level. In the fourth stage T4, the low level of the first clock signal terminal GCB is output to the signal output terminal Gout, so that the Data voltage written on the Data line Data of the pixel driving circuit shown in fig. 3a is written to the gate electrode of the driving transistor T13 through the Data writing transistor T14 and the threshold compensating transistor T12 until the driving transistor T13 is turned off, and the gate electrode voltage of the driving transistor T13 is stored in the storage capacitor Cst.

In some embodiments, when the voltage Vcst of the storage capacitor is low, the display brightness of the display panel at the position is higher in actual use, and by changing the first clock signal output by the signal output terminal Gout, the duration of the low level of the first clock signal can be increased, so that the charging time of the pixel is increased, that is, the voltage Vcst of the storage capacitor is increased, and further, the brightness of the display panel is reduced, and finally, the technical effect of improving the local brightness on the display panel is achieved.

In some embodiments, when the voltage Vcst of the storage capacitor is higher, the display brightness of the display panel at the position is darker in actual use, and by changing the first clock signal output by the signal output terminal Gout, the duration of the low level of the first clock signal can be reduced, so that the charging time of the pixel is reduced, that is, the voltage Vcst of the storage capacitor is reduced, and further, the brightness of the display panel is increased, and finally, the technical effect of improving the local darkness on the display panel is achieved.

It should be noted that, in the embodiment of the present disclosure, the transistors in the shift register and the transistors in the pixel driving circuit are both illustrated by taking P-type transistors as examples, when the transistors in the shift register and the transistors in the pixel driving circuit adopt N-type transistors, part of the control signals need to be turned over, and the positions of the first voltage terminal VGL and the second voltage terminal VGH are exchanged, but the working process of the shift register is the same and is not repeated here.

In a second aspect, embodiments of the present disclosure also provide a gate driving circuit including a plurality of cascaded shift registers as in any one of the above embodiments. The signal input end GSTV of the first stage shift register is connected with the initial signal end, and when the initial signal end inputs an initial signal, the shift register starts to work; the signal output terminal Gout of the shift register of the present stage is connected to the reset signal terminal of the shift register of the previous stage and the signal input terminal GSTV of the shift register of the next stage, except for the shift register of the first stage. The gate driving circuit in the embodiments of the present disclosure has the same technical effects as the shift register provided in the above embodiments, and will not be described herein.

In a third aspect, embodiments of the present disclosure also provide a display device including the gate driving circuit in the above embodiments. The gate driving circuit in the display device provided by the embodiments of the present disclosure has the same technical effects as the shift register provided by the above embodiments, and since the structure and the beneficial effects of the shift register have been described in detail in the above embodiments, the details are not repeated here.

In the embodiment of the present disclosure, the display device may be an organic light emitting diode display device or a liquid crystal display device, which is not particularly limited in this disclosure. For example, the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

It is to be understood that the above embodiments are merely exemplary embodiments employed to illustrate the principles of the present disclosure, however, the present disclosure is not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the disclosure, and are also considered to be within the scope of the disclosure.

Claims (12)

1. A shift register configured to supply a gate drive signal to a pixel drive circuit, the shift register comprising:

an input sub-circuit, an output sub-circuit, an operation sub-circuit, and a clock driving sub-circuit; wherein,,

the input subcircuit is configured to receive an input signal and precharge a pull-up node through the input signal; the pull-up node is a connection node between the input sub-circuit and the output sub-circuit;

the output sub-circuit is configured to output a first clock signal input to a first clock signal end through a signal output end under the control of the potential of the pull-up node;

the operation sub-circuit is configured to compare the acquired pixel voltage of the pixel driving circuit with a reference voltage to generate a first control signal;

the clock driving sub-circuit is configured to input the first clock signal to the first clock signal terminal according to the first control signal.

2. The shift register of claim 1, wherein the reference voltage is a sawtooth voltage.

3. The shift register of claim 1, wherein the input subcircuit comprises a first transistor and a second transistor;

The control electrode of the first transistor is connected with the second clock signal end, the first electrode of the first transistor is connected with the signal input end, the second electrode of the first transistor is connected with the first electrode of the second transistor, the control electrode of the second transistor is connected with the first voltage end, and the second electrode of the second transistor is connected with the pull-up node.

4. A shift register as claimed in claim 3, further comprising a voltage holding sub-circuit;

the voltage holding sub-circuit is configured to store a second voltage under control of the first clock signal and output the second voltage to a second pole of the first transistor under control of a pull-down node potential.

5. The shift register of claim 4, wherein the voltage holding sub-circuit comprises a seventh transistor and an eighth transistor;

the control electrode of the seventh transistor is connected with the first clock signal end, the first electrode of the seventh transistor is connected with the second electrode of the first transistor, and the second electrode of the seventh transistor is connected with the first electrode of the eighth transistor; the control electrode of the eighth transistor is connected with the pull-down node, and the second electrode of the eighth transistor is connected with the second voltage end.

6. The shift register of claim 1, wherein the output sub-circuit comprises a third transistor and a first capacitance;

the control electrode of the third transistor is connected with the pull-up node, the first electrode of the third transistor is connected with the first clock signal end, and the second electrode of the third transistor is connected with the signal output end; the first polar plate of the first capacitor is connected with the control electrode of the third transistor, and the second polar plate of the first capacitor is connected with the second pole of the third transistor.

7. The shift register of claim 1, further comprising a pull-down control sub-circuit;

the pull-down control sub-circuit is configured to transmit the first voltage to the pull-down node under control of the second clock signal, and to transmit the second clock signal to the pull-down node under control of the pull-up node potential.

8. The shift register of claim 7, wherein the pull-down control sub-circuit comprises a fourth transistor and a fifth transistor;

the control electrode of the fourth transistor is connected with the second clock signal end, the first electrode of the fourth transistor is connected with the first voltage end, and the second electrode of the fourth transistor is connected with the pull-down node; the control electrode of the fifth transistor is connected with the input sub-circuit, the first electrode of the fifth transistor is connected with the second clock signal end, and the second electrode of the fifth transistor is connected with the pull-down node.

9. The shift register of claim 1, further comprising a pull-down subcircuit;

the pull-down subcircuit is configured to transmit a second voltage to the signal output terminal under control of the pull-down node potential.

10. The shift register of claim 9, wherein the pull-down sub-circuit comprises a sixth transistor and a second capacitor;

the control electrode of the sixth transistor is connected with the pull-down node, the first electrode of the sixth transistor is connected with the signal output end, and the second electrode of the sixth transistor is connected with the second voltage end; the first polar plate of the second capacitor is connected with the control electrode of the sixth transistor, and the second polar plate of the second capacitor is connected with the second pole of the sixth transistor.

11. A gate drive circuit comprising a plurality of cascaded shift registers according to any one of claims 1-10; wherein,,

the signal input end of the first stage shift register is connected with the initial signal end;

the signal output end of the shift register of the stage is connected with the reset signal end of the shift register of the previous stage and the signal input end of the shift register of the next stage except the shift register of the first stage.

12. A display device comprising the gate driving circuit according to claim 11.