CN116821893B - Code execution method, device, electronic equipment and storage medium - Google Patents
Code execution method, device, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN116821893B CN116821893B CN202311115838.0A CN202311115838A CN116821893B CN 116821893 B CN116821893 B CN 116821893B CN 202311115838 A CN202311115838 A CN 202311115838A CN 116821893 B CN116821893 B CN 116821893B
- Authority
- CN
- China
- Prior art keywords
- ith
- thread
- code
- executed
- context
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 51
- 230000002159 abnormal effect Effects 0.000 claims description 11
- 230000008569 process Effects 0.000 abstract description 11
- 238000004590 computer program Methods 0.000 description 10
- 238000004891 communication Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012356 Product development Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010801 machine learning Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001953 sensory effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Storage Device Security (AREA)
Abstract
The embodiment of the disclosure provides a code execution method, a code execution device, an electronic device and a storage medium. The method is applied to the technical field of computer security, and comprises the steps that a 1 st thread generated by an operating system executes a code to be executed; if the 1 st thread is executed to the 1 st preset position, stopping executing, and storing the 1 st context environment into a 1 st memory space, wherein the 1 st memory space is obtained by the 1 st thread from the heap memory; and executing the ith thread from the ith-1 preset position of the code to be executed according to the ith-1 context environment, stopping executing if the ith thread is executed to the ith preset position, and storing the ith context environment into the ith memory space. In this way, sequential execution of the code to be executed by using a plurality of different threads can be realized, leakage of memory features in the process of executing the code is reduced, and the safety of code execution is improved.
Description
Technical Field
The present disclosure relates to the field of computer security technologies, and in particular, to a code execution method, a code execution device, an electronic device, and a storage medium.
Background
The safety of code execution has important significance for software development enterprises, and the safety of code execution is the guarantee of development life for the development enterprises from early product development and later product operation. In the early product research and development stage, the code execution safety is protected, so that the code of an enterprise can be prevented from being leaked, the legal rights and interests of the enterprise are protected, and the research results of the enterprise are guaranteed; in the later product operation stage, the safety protection of code execution plays a key role in guaranteeing the advantages of enterprises in industry and preventing confidential data from leaking out to impact products.
In the aspect of improving the code execution safety, an anti-debugging mode is adopted, but compatibility problems are easy to occur in different windows versions, so that the code execution safety is lower.
Therefore, there is a need for a code execution method, apparatus, electronic device, and storage medium with higher security.
Disclosure of Invention
The present disclosure provides a code execution method, apparatus, electronic device, and storage medium.
According to a first aspect of the present disclosure, a code execution method is provided. The method comprises the following steps:
executing the code to be executed by a 1 st thread generated by an operating system;
if the 1 st thread is executed to the 1 st preset position, stopping executing, and storing the 1 st context environment into a 1 st memory space, wherein the 1 st memory space is obtained by the 1 st thread from a heap memory;
executing an ith thread from an ith-1 preset position of the code to be executed according to an ith-1 context environment, stopping executing if the ith thread is executed to the ith preset position, and storing the ith context environment into an ith memory space; the ith thread is applied from a thread pool of an operating system by the ith-1 thread, i is a positive integer greater than 1, and the initial value of i is 2.
Further, if the ith thread executes to the ith preset position, stopping execution, and storing the ith context to the ith memory space, so that the (i+1) th thread executes the code to be executed according to the ith context, including:
and registering a timer by the ith thread so that the (i+1) th thread executes the code to be executed after a preset time according to the ith context.
Further, if the ith thread executes to the ith preset position, stopping execution, and storing the ith context to the ith memory space, so that the (i+1) th thread executes the code to be executed according to the ith context, and further comprising:
the ith thread covers the ith-1 context environment into the own context environment, and executes the code to be executed according to the ith-1 context environment.
Further, after the executing the code to be executed according to the i-1 th context, the method includes:
judging whether the ith thread completely covers the ith-1 context environment into the own context environment or not;
if yes, the ith thread releases the ith-1 memory space.
Further, if the ith thread executes to the ith preset position, stopping execution, and storing the ith context to the ith memory space, so that the (i+1) th thread executes the code to be executed according to the ith context, and further comprising:
judging whether i+1 is a threshold value or not;
if yes, stopping executing the code to be executed.
Further, if the ith thread is executed to the ith preset position, stopping the execution, including:
and inserting an abnormal instruction into the ith preset position by the ith thread, so that the ith thread stores the ith context environment into the ith memory space after triggering the abnormal instruction.
Further, the contextual environment includes at least one of:
program counter state, register value, heap memory space state table, and heap memory space state table.
According to a second aspect of the present disclosure, a code execution apparatus is provided. The device comprises:
the first execution module is used for executing the code to be executed by the 1 st thread generated by the operating system;
the storage module is used for stopping execution if the 1 st thread is executed to the 1 st preset position, and storing the 1 st context environment into a 1 st memory space, wherein the 1 st memory space is obtained by the 1 st thread from a heap memory;
the second execution module is used for executing the ith thread from the ith-1 preset position of the code to be executed according to the ith-1 context environment, stopping execution if the ith thread is executed to the ith preset position, and storing the ith context environment into the ith memory space; the ith thread is applied from a thread pool of an operating system by the ith-1 thread, i is a positive integer greater than 1, and the initial value of i is 2.
According to a third aspect of the present disclosure, an electronic device is provided. The electronic device includes: the computer program comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes a code execution method when executing the program.
According to a fourth aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a code execution method.
Executing a code to be executed according to an i-1 context through an i-1 thread, wherein the i-1 thread is applied for from a thread pool of an operating system, i is a positive integer greater than 1, and the initial value of i is 2; if the ith thread executes to the ith preset position, stopping execution, and storing the ith context environment into an ith memory space so that the (i+1) th thread executes the code to be executed according to the ith context environment, wherein the ith memory space is applied for by the ith thread from a heap memory, the sequential execution of the code to be executed by using a plurality of different threads is realized, the leakage of memory characteristics in the code executing process is reduced, and the code executing safety is improved.
It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. In the drawings, wherein like or similar reference numerals denote like or similar elements, in which:
FIG. 1 illustrates a flow chart of a method of code execution according to an embodiment of the present disclosure;
FIG. 2 illustrates a flow chart of a method of code execution according to another embodiment of the present disclosure;
FIG. 3 illustrates a block diagram of a code execution apparatus according to an embodiment of the present disclosure;
fig. 4 illustrates a block diagram of an exemplary electronic device capable of implementing embodiments of the present disclosure.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments in this disclosure without inventive faculty, are intended to be within the scope of this disclosure.
In addition, the term "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
Fig. 1 shows a flowchart of a code execution method 100 according to an embodiment of the present disclosure, the method comprising:
s101, executing the code to be executed by the 1 st thread generated by the operating system.
In some embodiments, the code to be executed may be a digital code, a character code, or a hybrid code.
In some embodiments, the operating system may be a desktop operating system, a mobile phone operating system, a server operating system, an embedded operating system, or the like.
S102, stopping execution if the 1 st thread is executed to the 1 st preset position, and storing the 1 st context environment into a 1 st memory space, wherein the 1 st memory space is obtained by the 1 st thread from a heap memory.
In some embodiments, the context may be a counter state, a register value, a heap memory space state table, a stack memory space state table, or a combination thereof.
In some embodiments, if the 1 st thread executes to the i preset position, stopping the execution, including: and inserting an abnormal instruction into the 1 st preset position by the 1 st thread so that the i-th thread stores the 1 st context environment into the 1 st memory space after triggering the abnormal instruction.
In some embodiments, the exception instruction may be an abort instruction, an interrupt instruction, or a reset instruction.
In some embodiments, the 1 st thread may insert an exception instruction at a 1 st preset location when starting to execute the code to be executed; the 1 st thread can insert an abnormal instruction at a 1 st preset position after executing the code to be executed for a period of time; the 1 st thread may insert an abnormal instruction at a 1 st preset position according to the execution completion of the 1 st thread, for example, the 1 st thread inserts an abnormal instruction at the 1 st preset position when executing to an intermediate position from the execution position of the code to be executed to the 1 st preset position.
S103, executing an ith thread from an ith-1 preset position of the code to be executed according to an ith-1 context environment, stopping execution if the ith thread is executed to the ith preset position, and storing the ith context environment into an ith memory space; the ith thread is applied from a thread pool of an operating system by the ith-1 thread, i is a positive integer greater than 1, and the initial value of i is 2.
In some embodiments, the thread pool of the operating system may be a thread pool of a windows system, and a number of threads are stored in the thread pool of the windows system.
In some embodiments, in the process that the ith thread executes the code to be executed according to the ith-1 context, the ith thread may encrypt some executed or all consistent codes in the code to be executed, and the (i+1) th thread needs to decrypt the encrypted code portion before executing the code to be executed when executing the code to be executed.
In some embodiments, if the ith thread executes to the ith preset position, stopping execution, and storing an ith context to an ith memory space, so that the (i+1) th thread executes the code to be executed according to the ith context, including: and registering a timer by the ith thread so that the (i+1) th thread executes the code to be executed after a preset time according to the ith context. For example, the 2 nd thread registers a timer, and the interval time of the timer is set to 2 seconds, then after 2 seconds after the 2 nd thread registers the timer, the 3 rd thread starts executing the code to be executed.
According to the embodiment of the disclosure, the i+1th thread executing code and the i thread executing code are separated by the timer, so that the partition of the code to be executed in time is realized, the memory characteristics generated by the code to be executed in the execution process are reduced, and the safety in the code execution process is further improved.
In some embodiments, if the ith thread executes to the ith preset location, stopping execution, and storing the ith context in the ith memory space, and further comprising: the ith thread covers the ith-1 context environment into the own context environment, and executes the code to be executed according to the ith-1 context environment. For example, overlaying the ith thread with the ith-1 context into its own context may be accomplished by employing a defined user context overlay.
According to the embodiment of the disclosure, the i+1th thread is implemented to execute the code to be executed completely according to the i-th context environment by covering the i-1 th context environment into the own context environment, so that the influence of the i+1th thread's own context environment on the process of executing the code is avoided, and the accuracy of executing the code to be executed is improved.
In some embodiments, after said executing said code to be executed according to said i-1 th context, comprising: judging whether the ith thread completely covers the ith-1 context environment into the own context environment or not; if yes, the ith thread releases the ith-1 memory space.
According to the embodiment of the disclosure, by judging whether the ith thread completely covers the ith-1 context environment into the own context environment, the determination of the coverage degree of the context environment is realized, execution errors or execution code suspension caused by incomplete coverage of the context environment are avoided, and the stability of the execution process of the code to be executed is improved.
In some embodiments, after the executing the code to be executed according to the i-1 th context environment, further comprising: the ith thread calculates the coverage rate of covering the ith-1 context environment to the own context environment in unit time, and compares the calculated actual coverage rate F with a preset coverage rate F0, wherein if F is more than 0 and less than F0, the ith thread increases the preset time of the timer registered by the ith thread; if F0 is less than or equal to F is less than or equal to 1, the ith thread reduces the preset time of the timer registered by the ith thread.
In some embodiments, if the ith thread executes to the ith preset location, stopping execution, and storing the ith context in the ith memory space, and further comprising: judging whether i+1 is a threshold value or not; if yes, stopping executing the code to be executed. For example, the threshold may be set to 5, at which time the entire operation performed by the code to be executed is stopped when the 4 th thread ends the execution of the code to be executed according to the 3 rd context.
According to the embodiment of the disclosure, whether the i+1 is the threshold value is judged, so that the total number of threads is controlled, the progress of executing the code to be executed is controlled, and the flexibility of executing the code to be executed is improved.
In some embodiments, if the ith thread is executed to the ith preset position, stopping the execution, including: and inserting an abnormal instruction into the ith preset position by the ith thread, so that the ith thread stores the ith context environment into the ith memory space after triggering the abnormal instruction.
In some embodiments, the exception instruction may be an abort instruction, an interrupt instruction, or a reset instruction.
Executing a code to be executed according to an i-1 context through an i-1 thread, wherein the i-1 thread is applied for from a thread pool of an operating system, i is a positive integer greater than 1, and the initial value of i is 2; if the ith thread executes to the ith preset position, stopping execution, and storing the ith context environment into an ith memory space, wherein the ith memory space is obtained by applying for the ith thread from a heap memory, so that sequential execution of codes to be executed is realized by using a plurality of different threads, leakage of memory characteristics in the process of executing the codes is reduced, and the code execution safety is improved.
Fig. 2 shows a flowchart of a code execution method according to another embodiment of the present disclosure. The flow chart includes: the operating system generates a 1 st thread; executing the code to be executed by the 1 st thread; judging whether the 1 st thread is executed to a 1 st preset position or not; if not, the 1 st thread executes the code to be executed; if yes, stopping executing the 1 st thread, and storing the 1 st context environment into the 1 st memory space; executing the code to be executed by the ith thread according to the ith-1 context, wherein i is a positive integer greater than 1 and the initial value of i is 2; judging whether the ith thread is executed to an ith preset position or not; if not, the ith thread executes the code to be executed; if yes, stopping executing the ith thread, and storing the ith context environment into an ith memory space; in the process of circularly executing the code to be executed, judging whether i+1 reaches a threshold value or not; if yes, stopping executing the code to be executed and ending the whole process.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present disclosure is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present disclosure. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all alternative embodiments, and that the acts and modules referred to are not necessarily required by the present disclosure.
The foregoing is a description of embodiments of the method, and the following further describes embodiments of the present disclosure through examples of apparatus.
Fig. 3 shows a block diagram of a code execution apparatus 300 according to an embodiment of the present disclosure, the apparatus 300 comprising:
a first execution module 301, configured to execute a code to be executed by a 1 st thread generated by an operating system;
the storage module 302 is configured to stop execution if the 1 st thread executes to a 1 st preset position, and store a 1 st context to a 1 st memory space, where the 1 st memory space is obtained by the 1 st thread from a heap memory;
the second execution module 303 is configured to execute the ith thread from the ith-1 preset position of the code to be executed according to the ith-1 context, stop execution if the ith thread is executed to the ith preset position, and store the ith context into the ith memory space; the ith thread is applied from a thread pool of an operating system by the ith-1 thread, i is a positive integer greater than 1, and the initial value of i is 2.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the described modules may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again.
In the technical scheme of the disclosure, the acquisition, storage, application and the like of the related user personal information all conform to the regulations of related laws and regulations, and the public sequence is not violated.
According to embodiments of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.
Fig. 4 shows a schematic block diagram of an electronic device 400 that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
The electronic device 400 includes a computing unit 401 that can perform various suitable actions and processes according to a computer program stored in a ROM402 or a computer program loaded from a storage unit 408 into a RAM 403. In the RAM403, various programs and data required for the operation of the electronic device 400 may also be stored. The computing unit 401, ROM402, and RAM403 are connected to each other by a bus 404. An I/O interface 405 is also connected to bus 404.
Various components in electronic device 400 are connected to I/O interface 405, including: an input unit 406 such as a keyboard, a mouse, etc.; an output unit 407 such as various types of displays, speakers, and the like; a storage unit 408, such as a magnetic disk, optical disk, etc.; and a communication unit 409 such as a network card, modem, wireless communication transceiver, etc. The communication unit 409 allows the electronic device 400 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
The computing unit 401 may be a variety of general purpose and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 401 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 401 performs the respective methods and processes described above, for example, a code execution method. For example, in some embodiments, the code execution method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 408. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 400 via the ROM402 and/or the communication unit 409. When a computer program is loaded into RAM403 and executed by computing unit 401, one or more steps of the code-executing method described above may be performed. Alternatively, in other embodiments, the computing unit 401 may be configured to perform the code execution method by any other suitable means (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems-on-chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a readable storage medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The readable storage medium may be a machine-readable signal medium or a machine-readable storage medium. The readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: display means for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.
It should be appreciated that various forms of the flows described above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the technical solutions of the present disclosure are achieved, and are not limited herein.
The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (9)
1. A method of code execution, comprising:
executing the code to be executed by a 1 st thread generated by an operating system;
if the 1 st thread is executed to the 1 st preset position, stopping executing, and storing the 1 st context environment into a 1 st memory space, wherein the 1 st memory space is obtained by the 1 st thread from a heap memory;
executing an ith thread from an ith-1 preset position of the code to be executed according to an ith-1 context environment, stopping executing if the ith thread is executed to the ith preset position, and storing the ith context environment into an ith memory space; the ith thread registers a timer so that the (i+1) th thread executes the code to be executed after a preset time according to the ith context; the ith thread is applied from a thread pool of an operating system by the ith-1 thread, i is a positive integer greater than 1, and the initial value of i is 2.
2. The code execution method according to claim 1, wherein if the ith thread is executed to an ith preset location, stopping the execution and storing an ith context in an ith memory space, further comprising:
the ith thread covers the ith-1 context environment into the own context environment, and executes the code to be executed according to the ith-1 context environment.
3. The code execution method according to claim 2, characterized by comprising, after said executing the code to be executed according to the i-1 th context,:
judging whether the ith thread completely covers the ith-1 context environment into the own context environment or not;
if yes, the ith thread releases the ith-1 memory space.
4. The code execution method according to claim 1, wherein if the ith thread is executed to an ith preset location, stopping the execution and storing an ith context in an ith memory space, further comprising:
judging whether i+1 is a threshold value or not;
if yes, stopping executing the code to be executed.
5. The code execution method according to claim 1, wherein stopping execution if the ith thread is executed to an ith preset position, comprises:
and inserting an abnormal instruction into the ith preset position by the ith thread, so that the ith thread stores the ith context environment into the ith memory space after triggering the abnormal instruction.
6. The code execution method according to claim 1, wherein the context environment comprises at least one of:
program counter state, register value, heap memory space state table, and heap memory space state table.
7. A code execution apparatus, comprising:
the first execution module is used for executing the code to be executed by the 1 st thread generated by the operating system;
the storage module is used for stopping execution if the 1 st thread is executed to the 1 st preset position, and storing the 1 st context environment into a 1 st memory space, wherein the 1 st memory space is obtained by the 1 st thread from a heap memory;
the second execution module is used for executing the ith thread from the ith-1 preset position of the code to be executed according to the ith-1 context environment, stopping execution if the ith thread is executed to the ith preset position, and storing the ith context environment into the ith memory space; the ith thread registers a timer so that the (i+1) th thread executes the code to be executed after a preset time according to the ith context; the ith thread is applied from a thread pool of an operating system by the ith-1 thread, i is a positive integer greater than 1, and the initial value of i is 2.
8. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.
9. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1-6.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202311115838.0A CN116821893B (en) | 2023-08-31 | 2023-08-31 | Code execution method, device, electronic equipment and storage medium |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202311115838.0A CN116821893B (en) | 2023-08-31 | 2023-08-31 | Code execution method, device, electronic equipment and storage medium |
Publications (2)
Publication Number | Publication Date |
---|---|
CN116821893A CN116821893A (en) | 2023-09-29 |
CN116821893B true CN116821893B (en) | 2023-11-28 |
Family
ID=88127932
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202311115838.0A Active CN116821893B (en) | 2023-08-31 | 2023-08-31 | Code execution method, device, electronic equipment and storage medium |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN116821893B (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103019806A (en) * | 2011-09-22 | 2013-04-03 | 北京新媒传信科技有限公司 | Asynchronous task processing method and device |
CN105700913A (en) * | 2015-12-30 | 2016-06-22 | 广东工业大学 | Method for creation and parallel operation of lightweight bare chip codes |
CN111506426A (en) * | 2020-04-17 | 2020-08-07 | 翱捷科技(深圳)有限公司 | Memory management method and device and electronic equipment |
CN112612615A (en) * | 2020-12-28 | 2021-04-06 | 中孚安全技术有限公司 | Data processing method and system based on multithreading memory allocation and context scheduling |
CN114372260A (en) * | 2022-03-22 | 2022-04-19 | 荣耀终端有限公司 | Multithreading processing method and electronic equipment |
CN115016894A (en) * | 2022-06-02 | 2022-09-06 | 北京东土军悦科技有限公司 | Thread memory access method, device, equipment and storage medium |
CN115981962A (en) * | 2022-12-30 | 2023-04-18 | 北京基调网络股份有限公司 | Thread pool monitoring method and device, electronic equipment and storage medium |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8108880B2 (en) * | 2007-03-07 | 2012-01-31 | International Business Machines Corporation | Method and system for enabling state save and debug operations for co-routines in an event-driven environment |
-
2023
- 2023-08-31 CN CN202311115838.0A patent/CN116821893B/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103019806A (en) * | 2011-09-22 | 2013-04-03 | 北京新媒传信科技有限公司 | Asynchronous task processing method and device |
CN105700913A (en) * | 2015-12-30 | 2016-06-22 | 广东工业大学 | Method for creation and parallel operation of lightweight bare chip codes |
CN111506426A (en) * | 2020-04-17 | 2020-08-07 | 翱捷科技(深圳)有限公司 | Memory management method and device and electronic equipment |
CN112612615A (en) * | 2020-12-28 | 2021-04-06 | 中孚安全技术有限公司 | Data processing method and system based on multithreading memory allocation and context scheduling |
CN114372260A (en) * | 2022-03-22 | 2022-04-19 | 荣耀终端有限公司 | Multithreading processing method and electronic equipment |
CN115016894A (en) * | 2022-06-02 | 2022-09-06 | 北京东土军悦科技有限公司 | Thread memory access method, device, equipment and storage medium |
CN115981962A (en) * | 2022-12-30 | 2023-04-18 | 北京基调网络股份有限公司 | Thread pool monitoring method and device, electronic equipment and storage medium |
Also Published As
Publication number | Publication date |
---|---|
CN116821893A (en) | 2023-09-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8442960B1 (en) | Systems and methods for process self-elevation | |
EP3185166A1 (en) | Trusted metric method and device | |
JP2019215847A (en) | Reducing buffer overflow | |
CN112835639B (en) | Hook realization method, device, equipment, medium and product | |
CN116821893B (en) | Code execution method, device, electronic equipment and storage medium | |
CN105556461A (en) | Techniques for pre-OS image rewriting to provide cross-architecture support, security introspection, and performance optimization | |
CN104424403A (en) | Information processing method and electronic device | |
CN114637988A (en) | Binary-oriented function level software randomization method | |
CN114139605A (en) | Distributed model training method, system, device and storage medium | |
CN113590287A (en) | Task processing method, device, equipment, storage medium and scheduling system | |
CN111159703B (en) | Virtual machine data leakage detection method and device | |
US20180165453A1 (en) | Malicious code deactivating apparatus and method of operating the same | |
CN114510291B (en) | Data calling method, device, electronic equipment and storage medium | |
CN114338111B (en) | Vulnerability plugging method, device, equipment and storage medium | |
CN116628688A (en) | High-risk function call detection method and device, electronic equipment and storage medium | |
CN110673977B (en) | Data recovery optimization method, device, equipment and medium | |
CN117251417A (en) | File copying method and device, electronic equipment and storage medium | |
CN111159704B (en) | Virtual memory data leakage detection method and device | |
CN110795164B (en) | Application packaging method and device and application running method and device | |
CN116820486A (en) | Bug positioning method, device and equipment of application program and storage medium | |
CN116149946A (en) | Data acquisition method and device, electronic equipment and storage medium | |
CN117332417A (en) | Lesu software detection method, apparatus, device and storage medium | |
CN116755725A (en) | Configuration rollback method, device and apparatus based on configuration file, and storage medium | |
CN117728999A (en) | Web access flow control method, device, equipment and storage medium | |
CN118036092A (en) | Software integrity protection method and system based on hardware-assisted virtualization |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |