CN116798880A - High-power chip packaging bonding method and chip packaging piece - Google Patents
High-power chip packaging bonding method and chip packaging piece Download PDFInfo
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- CN116798880A CN116798880A CN202311016586.6A CN202311016586A CN116798880A CN 116798880 A CN116798880 A CN 116798880A CN 202311016586 A CN202311016586 A CN 202311016586A CN 116798880 A CN116798880 A CN 116798880A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 77
- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 93
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 239000000654 additive Substances 0.000 claims abstract description 17
- 230000000996 additive effect Effects 0.000 claims abstract description 17
- 238000001704 evaporation Methods 0.000 claims abstract description 8
- 230000008020 evaporation Effects 0.000 claims abstract description 8
- 238000004544 sputter deposition Methods 0.000 claims abstract description 8
- 238000009713 electroplating Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 35
- 239000000853 adhesive Substances 0.000 claims description 26
- 230000001070 adhesive effect Effects 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 17
- 239000003292 glue Substances 0.000 claims description 10
- 239000012790 adhesive layer Substances 0.000 claims description 8
- 238000001035 drying Methods 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims description 6
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000007772 electroless plating Methods 0.000 claims description 3
- 238000005240 physical vapour deposition Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 abstract description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052802 copper Inorganic materials 0.000 abstract description 7
- 239000010949 copper Substances 0.000 abstract description 7
- 230000017525 heat dissipation Effects 0.000 abstract description 7
- 238000000151 deposition Methods 0.000 abstract description 5
- 230000008021 deposition Effects 0.000 abstract description 5
- 239000000126 substance Substances 0.000 abstract description 5
- 230000007547 defect Effects 0.000 abstract description 4
- 238000007747 plating Methods 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 12
- 239000000919 ceramic Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920000728 polyester Polymers 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000000741 silica gel Substances 0.000 description 2
- 229910002027 silica gel Inorganic materials 0.000 description 2
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000005062 Polybutadiene Substances 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- WAKMOVBCOYGSDK-UHFFFAOYSA-N phenol;triazine Chemical compound C1=CN=NN=C1.OC1=CC=CC=C1 WAKMOVBCOYGSDK-UHFFFAOYSA-N 0.000 description 1
- 229920002857 polybutadiene Polymers 0.000 description 1
- 229920013716 polyethylene resin Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Abstract
Compared with the prior art of chip packaging, which has the problems of welding surface hollowness, virtual welding, false welding, low heat dissipation performance and the like, the application provides a solution for combining and growing a chip electrode and a substrate metal layer together at normal temperature, and particularly comprises the following steps: fixing the chip and the packaging substrate; the electrodes of the chip face the packaging substrate and correspond to the positions of the through holes; growing a metal layer in the through hole in an additive manufacturing mode, and electrically connecting the grown metal layer with the electrode; and encapsulating and packaging the surfaces of the chip and the packaging substrate. The application is operated at normal temperature, and the damage of high temperature and high pressure to the chip is completely avoided; by adopting one or the methods of evaporation, sputtering, copper deposition, electroplating or chemical plating, the chip electrode and the substrate metal layer are combined and grown together at normal temperature, so that the defects of hollowness, cold joint and the like are avoided, the surface contact is good, and the heat dissipation performance of the chip is greatly improved.
Description
Technical Field
The application relates to the field of chip packaging, in particular to a high-power chip packaging bonding method and a chip packaging piece.
Background
High-power chips refer to integrated circuit chips capable of processing high-power signals and are commonly used in control circuits for driving high-power loads such as motors and Light Emitting Diodes (LEDs). Unlike conventional low-power integrated circuits, power chips are required to withstand extreme environments such as high currents, high voltages, and high temperatures, while having high efficiency and reliability. Common power chips include power amplifiers, power switches, motor controllers, and the like.
At present, the packaging of the high-power chip mostly adopts methods such as solder paste welding, eutectic welding, hot-press welding, ultrasonic bonding wires and the like to realize the electrical connection of the chip and the packaging substrate. The methods have defects such as void ratio of a welding surface, false welding and the like; meanwhile, the processes all need high-temperature welding or larger pressure, and have potential damage to the chip; and the heat dissipation performance of these processes is hardly improved.
Disclosure of Invention
In view of the foregoing, the present application has been made to provide a method of high power chip package bonding and a chip package that overcomes the foregoing or at least partially solves the foregoing problems, including:
a method for packaging and bonding a high-power chip, for packaging the chip with a package substrate, wherein the package substrate is provided with a through hole, the package substrate comprises a metal layer, and the method comprises:
fixing the chip and the packaging substrate; the electrodes of the chip face the packaging substrate and correspond to the positions of the through holes;
growing the metal layer in the through hole in an additive manufacturing mode, and enabling the grown metal layer to be electrically connected with the electrode;
and encapsulating the surfaces of the chip and the packaging substrate.
Further, the step of growing the metal layer in the through hole by an additive manufacturing method and electrically connecting the grown metal layer with the electrode comprises the following steps:
growing the metal layer to a first designated height from the direction of the electrode in the through hole by an additive manufacturing mode;
and filling the electric connection surface formed by the through holes with an adhesive material to a second designated height.
Further, the first designated height is lower than the height of the through hole, and the second designated height is level with the surface of the package substrate.
Further, the method further comprises the following steps:
preparing a target area fixed with the chip on the surface of the packaging substrate;
and preparing the through holes at the positions where the packaging substrate is connected with the electrodes of the chip.
Further, the step of fixing the chip to the package substrate includes:
and aligning the electrode of the chip with the through hole, and fixing the chip with the packaging substrate through the target area.
Further, the step of fixing the chip and the package substrate through the target area includes:
coating an adhesive material on the target area where the chip and the packaging substrate need to be fixed;
and drying the bonding material to form a bonding layer.
Further, the step of encapsulating the chip and the surface of the encapsulation substrate includes:
coating packaging glue on the surfaces of the chip and the packaging substrate;
and drying the packaging adhesive to form a packaging adhesive layer.
Further, the packaging adhesive is subjected to drying treatment at 60-160 ℃.
Further, the additive manufacturing mode comprises one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating and electroless plating.
The chip packaging piece is prepared according to the high-power chip packaging bonding method.
The application has the following advantages:
in the embodiment of the application, compared with the prior chip packaging technology which has the problems of welding surface voids, virtual welding, false welding, low heat dissipation performance and the like, the application provides a solution for combining and growing a chip electrode and a substrate metal layer together at normal temperature, and specifically comprises the following steps: fixing the chip and the packaging substrate; the electrodes of the chip face the packaging substrate and correspond to the positions of the through holes; growing the metal layer in the through hole in an additive manufacturing mode, and enabling the grown metal layer to be electrically connected with the electrode; and encapsulating the surfaces of the chip and the packaging substrate. The application is operated at normal temperature, and the damage of high temperature and high pressure to the chip is completely avoided; by adopting one or the methods of evaporation, sputtering, copper deposition, electroplating or chemical plating, the chip electrode and the substrate metal layer are combined and grown together at normal temperature, so that the defects of hollowness, cold joint and the like are avoided, the surface contact is good, and the heat dissipation performance of the chip is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the following brief description will be given of the drawings required for the description of the present application, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a flow chart of steps of a method for bonding a high power chip package according to an embodiment of the present application;
fig. 2 is a schematic diagram illustrating steps of a method for bonding a high-power chip package according to an embodiment of the application.
In the figure, 1, a package substrate; 11. a target area; 12. a through hole; 2. and a chip.
Detailed Description
The application will be described in further detail with reference to the drawings and the detailed description, in order to make the objects, features and advantages of the application more comprehensible. It will be apparent that the described embodiments are some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that, in the method for packaging and bonding a high-power chip according to the embodiment of the present application, the chip 2 and the package substrate 1 are packaged, the package substrate 1 is provided with a through hole 12, and the package substrate 1 includes a metal layer.
In general, a ceramic substrate is used for high-power chip package, and the ceramic substrate 1 is that copper foil is directly bonded to alumina (Al 2 O 3 ) Or a special process plate on the surface (single or double sided) of an aluminum nitride (AlN) ceramic substrate. The ultrathin composite substrate has excellent electrical insulation performance, high heat conduction property, excellent soldering property and high adhesion strength, can etch various patterns like a PCB, and has great current carrying capacity. Therefore, ceramic substrates have become a base material for high-power electronic circuit structure technology and interconnection technology.
Referring to fig. 1, a method for bonding a high-power chip package according to an embodiment of the present application is shown;
the method comprises the following steps:
s110, fixing the chip 2 and the packaging substrate 1; wherein the electrodes of the chip 2 face the package substrate 1 and correspond to the positions of the through holes 12;
s120, growing the metal layer in the through hole 12 by an additive manufacturing mode, and electrically connecting the grown metal layer with the electrode;
s130, encapsulating the surfaces of the chip 2 and the encapsulation substrate 1.
In the embodiment of the application, compared with the prior chip packaging technology which has the problems of welding surface voids, virtual welding, false welding, low heat dissipation performance and the like, the application provides a solution for combining and growing a chip electrode and a substrate metal layer together at normal temperature, and specifically comprises the following steps: fixing the chip 2 and the packaging substrate 1; wherein the electrodes of the chip 2 face the package substrate 1 and correspond to the positions of the through holes 12; growing the metal layer in the through hole 12 by an additive manufacturing mode, and enabling the grown metal layer to form electric connection with the electrode; and encapsulating the surfaces of the chip 2 and the encapsulation substrate 1 by glue. The application is operated at normal temperature, and the damage of high temperature and high pressure to the chip is completely avoided; by adopting one or the methods of evaporation, sputtering, copper deposition, electroplating or chemical plating, the chip electrode and the substrate metal layer are combined and grown together at normal temperature, so that the defects of hollowness, cold joint and the like are avoided, the surface contact is good, and the heat dissipation performance of the chip is greatly improved.
Next, a method of high power chip package bonding in the present exemplary embodiment will be further described.
In an embodiment of the present application, the method further includes:
s101, preparing a target area 11 fixed with the chip 2 on the surface of the packaging substrate 1;
s102, preparing the through hole 12 at the position where the packaging substrate 1 is connected with the electrode of the chip 2.
In an embodiment of the present application, the specific process of "preparing the target area 11 fixed to the chip 12 on the surface of the package substrate 1" in step S101 may be further described in conjunction with the following description.
As an example, two electrodes are arranged on the same side of the high-power chip, the packaging substrate 1 is manufactured according to the circuit design requirement, and a target area 11 for fixing the packaging substrate 1 and the high-power chip is manufactured; wherein the target area 11 is an area of the package substrate 1 corresponding to between two electrodes of the chip 2.
In an embodiment of the present application, the specific process of "preparing the through hole 12 at the position where the package substrate 1 is connected to the electrode of the chip 2" described in step S102 may be further described in connection with the following description.
At the position where the package substrate 1 and the high power chip 2 are connected to each other by the electrode, the through holes 12 are formed, and the number of the through holes 12 is two.
As an example, a first target area inside the package substrate 1 is etched away; wherein the first target area is a longitudinally extending columnar structure corresponding to the electrode of the chip 2. Specifically, the etching window is formed by coating a photosensitive material and exposing and developing, so that the first target area is conveniently etched and removed.
Fixing the chip 2 to the package substrate 1 as described in the step S110; wherein the electrodes of the chip 2 face the package substrate 1 and correspond to the positions of the through holes 12.
In an embodiment of the present application, the specific process of "fixing the chip 2 to the package substrate 1" in step S110 may be further described in conjunction with the following description.
As described in the following steps, the electrodes of the chip 2 are aligned with the through holes 12, and the chip 2 is fixed to the package substrate 1 through the target region.
In an embodiment of the present application, a specific process of "fixing the chip 2 to the package substrate 1 through the target area 11" may be further described in conjunction with the following description.
As described in the following steps, an adhesive material is coated on the target area 11 where the chip 3 and the package substrate 1 need to be fixed;
the adhesive material is subjected to a baking treatment to form an adhesive layer, as described in the following steps.
As an example, an adhesive material is applied to the target area 11, the electrodes of the chip 2 are aligned with the through holes 12, and the adhesive material is baked, and the formed adhesive layer connects and fixes the chip 2 and the package substrate 1. Specifically, the bonding material is subjected to drying treatment at 60-160 ℃ to form the bonding layer. Specifically, the adhesive material may be an insulating adhesive, and the insulating adhesive includes one or more of polyester, epoxy, polyurethane, polybutadiene acid, organosilicon, polyester imine and polyimide.
Besides the insulating glue, the chip and the packaging substrate can be fixed by other methods, so that the purpose of fixation can be achieved.
The metal layer is grown in the via 12 by additive manufacturing and electrically connected to the electrode as described in step S120.
In one embodiment of the present application, the specific process of growing the metal layer in the via 12 by additive manufacturing and electrically connecting the grown metal layer with the electrode in step S120 may be further described in conjunction with the following description.
Growing the metal layer within the via 12 from the direction of the electrode to a first specified height by additive manufacturing, as described below;
as described in the following steps, the electrical connection surfaces formed by the vias 12 are filled with an adhesive material to a second specified height.
The first specified height is lower than the height of the through hole 12, and the second specified height is level with the surface of the package substrate 1. The additive manufacturing mode comprises one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating and electroless plating.
As an example, a selective growth method, such as evaporation, sputtering, copper deposition, electrical or chemical methods, is used, and the metal layer of the package substrate 1 is grown to a first specified height along the through hole 12 from the electrode by using an additive manufacturing method, so that the metal copper filled in the through hole 12 forms a good electrical connection with the electrode of the high-power chip, and also forms a good electrical connection with the circuit layer of the package substrate 1.
After the metal layer of the package substrate 1 grows to a first designated height along the inner wall of the through hole, the through hole 12 is filled to a second designated height by adopting an adhesive material, and the through hole 12 of the package substrate 1 is filled and leveled.
In one embodiment, the first specified height is half the height of the via 12.
As described in step S130, the surfaces of the chip 2 and the package substrate 1 are encapsulated by glue.
In an embodiment of the present application, the specific process of "encapsulating the chip 2 and the surface of the package substrate 1" in step S130 may be further described in conjunction with the following description.
Coating packaging glue on the surfaces of the chip 2 and the packaging substrate 1 as follows;
and drying the packaging adhesive to form a packaging adhesive layer as described in the following steps.
As an example, a surface of the package substrate 1 and the chip 2 connected thereto is coated with a packaging adhesive such that the top of the packaging adhesive is over the top of the chip 2. And drying the packaging adhesive to form a packaging adhesive layer, thereby obtaining the chip packaging piece. Specifically, the packaging glue is dried at the temperature of 60-160 ℃ to form the packaging glue layer, and the chip packaging piece is obtained. Specifically, the material of the encapsulation adhesive layer is conductive adhesive, such as epoxy resin mixed with metal powder, silica gel mixed with metal powder or mixed adhesive mixed with metal powder, which has better conductive performance. The encapsulation adhesive comprises one or more of epoxy resin, silica gel, polyimide (PI) resin, polyethylene (PE) resin and phenol triazine (PT Phenolic Triazine) resin. The packaging adhesive layer formed after the packaging adhesive is cured has good insulation and sealing performance, and can provide protection and prevent the product from being wetted. Cutting the encapsulated packaging piece to form the high-power device.
In one embodiment, referring to FIG. 2, there is shown:
1. the package substrate 1 is manufactured according to the circuit design requirement, and ceramic substrates are generally adopted for high-power chip package.
2. And manufacturing a through hole at the electrode connection position of the packaging substrate 1 and the high-power chip 2.
3. The high power chip 2 is placed over the through hole by using an insulating adhesive or other methods, so that it is connected with the package substrate 1.
4. The package substrate 1 connected with the high-power chip is turned over, so that the bottom of the package substrate 1 is upward.
5. The metal copper filled in the through hole 12 is well electrically connected with the electrode of the high-power chip 2 by adopting a selective growth method such as evaporation, sputtering, copper deposition, electrical property or chemical property, and the like, and is well electrically connected with the circuit layer of the packaging substrate 1.
6. And filling the bottom of the packaging substrate 1 with insulating glue to be flat.
7. And turning over the packaging substrate 1 and the connected high-power chip 2 together, and then encapsulating and cutting the surface packaging adhesive to form the high-power device.
The application also provides a chip package which is prepared according to the high-power chip package bonding method.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The above description of the method for bonding the high-power chip package and the chip package provided by the application applies specific examples to illustrate the principle and the implementation of the application, and the above examples are only used for helping to understand the method and the core idea of the application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. A method for packaging and bonding a high-power chip, which is used for packaging the chip and a packaging substrate, and is characterized in that the packaging substrate is provided with a through hole, the packaging substrate comprises a metal layer, and the method comprises the following steps:
fixing the chip and the packaging substrate; the electrodes of the chip face the packaging substrate and correspond to the positions of the through holes;
growing the metal layer in the through hole in an additive manufacturing mode, and enabling the grown metal layer to be electrically connected with the electrode;
and encapsulating the surfaces of the chip and the packaging substrate.
2. The method of claim 1, wherein the step of growing the metal layer within the via by additive manufacturing and electrically connecting the grown metal layer to the electrode comprises:
growing the metal layer to a first designated height from the direction of the electrode in the through hole by an additive manufacturing mode;
and filling the electric connection surface formed by the through holes with an adhesive material to a second designated height.
3. The method of claim 2, wherein the first specified height is lower than a height of the through hole, and the second specified height is level with a surface of the package substrate.
4. The method as recited in claim 1, further comprising:
preparing a target area fixed with the chip on the surface of the packaging substrate;
and preparing the through holes at the positions where the packaging substrate is connected with the electrodes of the chip.
5. The method of claim 4, wherein the step of securing the chip to the package substrate comprises:
and aligning the electrode of the chip with the through hole, and fixing the chip with the packaging substrate through the target area.
6. The method of claim 5, wherein the step of securing the chip to the package substrate through the target area comprises:
coating an adhesive material on the target area where the chip and the packaging substrate need to be fixed;
and drying the bonding material to form a bonding layer.
7. The method of claim 1, wherein the encapsulating the chip and the surface of the package substrate comprises:
coating packaging glue on the surfaces of the chip and the packaging substrate;
and drying the packaging adhesive to form a packaging adhesive layer.
8. The method of claim 7, wherein the encapsulation glue is baked at 60-160 ℃.
9. The method of claim 1, wherein the additive manufacturing means comprises one or more of chemical vapor deposition, physical vapor deposition, atomic layer deposition, sputtering, evaporation, electroplating, and electroless plating.
10. A chip package prepared by the method of bonding a high power chip package according to any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311016586.6A CN116798880A (en) | 2023-08-11 | 2023-08-11 | High-power chip packaging bonding method and chip packaging piece |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311016586.6A CN116798880A (en) | 2023-08-11 | 2023-08-11 | High-power chip packaging bonding method and chip packaging piece |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116798880A true CN116798880A (en) | 2023-09-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311016586.6A Pending CN116798880A (en) | 2023-08-11 | 2023-08-11 | High-power chip packaging bonding method and chip packaging piece |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116798880A (en) |
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2023
- 2023-08-11 CN CN202311016586.6A patent/CN116798880A/en active Pending
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