CN116794946A - Photomask and photolithography method - Google Patents

Abstract

The application provides a photomask and a photoetching method, wherein the photomask comprises the following components: the device comprises a substrate and a plurality of alignment mark patterns positioned on the substrate, wherein at least two alignment mark patterns are different, and part of the alignment mark patterns can be shielded. Therefore, when aiming at different products, different alignment mark patterns on the same photomask can be used, and the rest alignment mark patterns are shielded, so that a plurality of products can share one photomask comprising a plurality of alignment mark patterns, and the manufacturing cost is reduced.

Description

Photomask and photolithography method

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to a photomask and a photolithography method.

Background

Photolithography is a technique for performing precise, minute, and complex patterning of thin film surfaces, and is a particularly important fabrication technique in the semiconductor manufacturing industry. Photolithography is a relatively complex process that involves the use of a mask (also known as a reticle). The photomask generally includes a substrate, and a structure pattern and an alignment mark pattern on the substrate, wherein the structure pattern is used for forming a device structure, and the alignment mark pattern is used for precise alignment between film layers.

In some semiconductor processes, in order to ensure accurate alignment of a subsequent layer (layer), a Zero Mark (Zero Mark), i.e., a first layer alignment Mark, is often required to be manufactured on a wafer, and an alignment Mark pattern may be transferred onto the wafer by performing a photolithography process on a photomask to form the alignment Mark. The zero layer marks tend to be different for different products, which requires a separate set of corresponding alignment mark patterns for each product, resulting in increased manufacturing costs.

Disclosure of Invention

The application aims to provide a photomask and a photoetching method, which are used for solving the problem that in the prior art, a set of corresponding alignment mark patterns are required to be designed for each product independently, so that the manufacturing cost is increased.

In order to solve the above technical problems, the present application provides a photomask, which includes: the device comprises a substrate and a plurality of alignment mark patterns positioned on the substrate, wherein at least two alignment mark patterns are different, and part of the alignment mark patterns can be shielded.

Optionally, in the photomask, the at least two alignment mark patterns are different and include: the marking shapes and/or the marking layers of at least two alignment mark patterns are different.

Optionally, in the mask, the substrate includes a device mask region and a dicing street mask region, and each of the alignment mark patterns is located on the dicing street mask region.

Optionally, in the mask, the substrate includes a device mask region and a scribe line mask region, and each of the alignment mark patterns is located on the scribe line mask region and/or the device mask region.

Optionally, in the photomask, the photomask further includes a detection mark pattern, which is used for detecting the offset between two adjacent photomasks when the photomasks are spliced for use, and the detection mark pattern is located at the edge position of the substrate.

Optionally, in the photomask, at least one side edge of the detection mark pattern coincides with at least one side edge of the substrate.

Optionally, in the mask, the mask includes a plurality of the detection mark patterns.

Optionally, in the photomask, the photomask includes two detection mark patterns, the shape of the substrate is rectangular, and the two detection mark patterns are respectively located on a pair of opposite corners of the substrate.

The application also provides a lithographic method comprising:

providing a photomask as described above;

shielding part of the alignment mark patterns on the photomask and exposing at least one alignment mark pattern; the method comprises the steps of,

and executing a photoetching process on the wafer by using the photomask.

Optionally, in the lithographic method, providing a photomask as described above includes: providing at least two reticles as described above, and stitching together each of the reticles to form a stitched reticle; performing a photolithography process on a wafer using the reticle includes: and executing a photoetching process on the wafer by using the spliced photomask.

In the photomask and the photoetching method provided by the application, a plurality of alignment mark patterns are formed on the substrate, wherein at least two alignment mark patterns are different, and part of the alignment mark patterns can be shielded, so that when aiming at different products, different alignment mark patterns on the same photomask can be used, and the rest of alignment mark patterns are shielded, so that a photomask comprising a plurality of alignment mark patterns can be shared by a plurality of products, and the manufacturing cost is reduced.

Drawings

FIG. 1 is a schematic diagram of a photomask according to an embodiment of the present application.

FIG. 2 is a schematic diagram of a photolithography process performed using the mask shown in FIG. 1 according to an embodiment of the present application.

FIG. 3 is a schematic diagram of another embodiment of a photomask.

FIG. 4 is a schematic diagram of a photolithography process performed using the mask shown in FIG. 3 according to an embodiment of the present application.

FIG. 5 is another schematic diagram of a photolithography process performed using the reticle shown in FIG. 3 according to an embodiment of the present application.

Wherein reference numerals are as follows:

100. 100a, 100 b-masks; 101. 102-splicing the photomask; 110-a substrate; 111-device mask area; 112-dicing street mask area; 120. 120a, 120b, 120c, 120d, 120 e-alignment mark patterns; 130-structural pattern; 140. 140a, 140 b-detection of the pattern of marks.

Detailed Description

The photomask and the photolithography method according to the present application will be described in further detail with reference to the accompanying drawings and embodiments. Advantages and features of the application will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the application.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless defined otherwise in the present document, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present application belongs. The terms first, second and the like in the description and in the claims, are not used for any order, quantity or importance, but are used for distinguishing between different elements. Likewise, the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "plurality" means two or more. Unless otherwise indicated, the terms "front," "rear," "lower," and/or "upper" and the like are merely for convenience of description and are not limited to one location or one spatial orientation. The word "comprising" or "comprises", and the like, means that elements or items appearing before "comprising" or "comprising" are encompassed by the element or item recited after "comprising" or "comprising" and equivalents thereof, and that other elements or items are not excluded. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

The core idea of the present application is to provide a photomask and a photolithography method, wherein the photomask comprises: the device comprises a substrate and a plurality of alignment mark patterns positioned on the substrate, wherein at least two alignment mark patterns are different, and part of the alignment mark patterns can be shielded. Therefore, when aiming at different products, different alignment mark patterns on the same photomask can be used, and the rest alignment mark patterns are shielded, so that a plurality of products can share one photomask comprising a plurality of alignment mark patterns, and the manufacturing cost is reduced.

Specifically, please refer to fig. 1, which is a schematic diagram illustrating a structure of a photomask according to an embodiment of the present application. As shown in fig. 1, the mask 100 includes: a substrate 110 and a plurality of alignment mark patterns 120 on the substrate 110, wherein at least two of the alignment mark patterns 120 are different, and a portion of the alignment mark patterns 120 can be blocked. In the embodiment of the present application, the alignment Mark pattern 120 is mainly used to form a Zero Mark (Zero Mark) on an underlying semiconductor substrate, and is used as a position reference standard of various devices formed on the underlying semiconductor substrate, the Zero Mark is formed by forming an opening and filling the opening with a filler, wherein the optical parameters of the filler are known, so that the relative positions of various device structures can be determined by refraction, reflection, etc. of light, and in some semiconductor manufacturing processes, an opening is usually formed in the underlying semiconductor substrate, and then an insulating material is filled and planarized to form the Zero Mark.

The material of the substrate 110 may include, but is not limited to, glass, ceramic, resin, semiconductor material, etc. The substrate 110 includes a device mask region 111 for corresponding device regions on the wafer and a scribe line mask region 112 for corresponding scribe lines on the wafer. In the embodiment of the present application, the device mask region 111 is square, the scribe line mask region 112 surrounds the device mask region 111, where the scribe line mask region 112 is square and ring-shaped, and the substrate 110 is correspondingly square, and of course, in other embodiments, the shapes of the device mask region 111 and the scribe line mask region 112 may be arbitrarily set.

With continued reference to fig. 1, five alignment mark patterns 120 are schematically illustrated, here alignment mark pattern 120a, alignment mark pattern 120b, alignment mark pattern 120c, alignment mark pattern 120d, and alignment mark pattern 120e, respectively. In the embodiment of the present application, five of the alignment mark patterns 120 are located in the scribe line mask region 112. In other embodiments of the present application, the plurality of alignment mark patterns 120 may be partially located in the scribe line mask region 112 and partially located in the device mask region 111 according to design requirements. Preferably, a plurality of the alignment mark patterns 120 are scattered in the scribe line mask region 112, and each of the alignment mark patterns 120 has a space therebetween. Different alignment mark patterns on the same substrate are used for zero layer marks of different products, for example, the alignment mark pattern 120a is used for zero layer marks of a logic chip, and by shielding other alignment mark patterns (the alignment mark pattern 120b, the alignment mark pattern 120c, the alignment mark pattern 120d and the alignment mark pattern 120 e) except the alignment mark pattern 120a on the substrate, the zero layer marks of the logic chip are formed on the first bottom layer semiconductor substrate and used as a position reference standard for forming the logic chip on the first bottom layer semiconductor substrate; the alignment mark pattern 120b is used for zero layer marking of the memory chip, and the zero layer marking of the memory chip is formed on the second bottom semiconductor substrate by shielding other alignment mark patterns (the alignment mark pattern 120a, the alignment mark pattern 120c, the alignment mark pattern 120d and the alignment mark pattern 120 e) except the alignment mark pattern 120b on the substrate, so as to be used as a position reference standard for forming the memory chip on the second bottom semiconductor substrate.

Further, the marking shapes and/or the marking layers of at least two of the alignment mark patterns 120 are different, and the marking shapes and/or the marking layers of the alignment mark patterns 120 are not particularly limited. The number of marking layers refers to the number of layers of the device layer corresponding to the zero layer marking formed on the underlying semiconductor substrate by using the same alignment mark pattern, for example, the device layer formed on the underlying semiconductor substrate may include, but is not limited to, zero layer marking of any one layer/any two layers/any three layers/any four layers in the first device layer, the second device layer, the third device layer, and the fourth device layer, the device layer may be a single layer or a composite layer of at least two layers, the arrangement manner of products corresponding to different device layers may be the same or different, and the same alignment mark pattern 120 (for example, the alignment mark pattern 120 a/the alignment mark pattern 120 b/the alignment mark pattern 120 c/the alignment mark pattern 120 d/the alignment mark pattern 120 e) may be used for the zero layer marking of any one layer/any two layers/any three layers/any four layers in the underlying semiconductor substrate, so that the same alignment mark pattern 120 (for example, the alignment mark pattern 120 a/the alignment mark pattern 120 b/the alignment mark pattern 120 c/the alignment mark pattern 120d may be the number of layers 1/the layer 2.

For example, the number of mark layers of the alignment mark pattern 120a and the alignment mark pattern 120b is the same and the mark shape is different. Specifically, for example, the alignment mark patterns 120a and 120b may each include square mark patterns, but the sizes of the two are different, so that the mark shapes of the two are different. As another example, the alignment mark pattern 120a includes a square mark pattern and the alignment mark pattern 120b includes a circular mark pattern such that the mark shapes of the two are different. The number of marking layers of the alignment mark pattern 120a and the alignment mark pattern 120b is one, that is, the alignment mark pattern 120a and the mark pattern 120b are only used for forming alignment of one device layer, so that the number of marking layers of the two is the same.

As another example, the number of marking layers of the alignment mark pattern 120c and the alignment mark pattern 120d may be different, and the marking shapes may be completely different, or partially the same and partially different. Specifically, for example, the number of the marking layers of the alignment marking pattern 120c is two, so as to form alignment of the subsequent two device layers; the number of marking layers of the alignment marking pattern 120d is one, and is only used for forming alignment of a subsequent device layer, so that the number of marking layers of the alignment marking pattern and the device layer is different. Further, for example, the alignment mark pattern 120c may include two square mark patterns having different sizes; the alignment mark pattern 120d may include one square mark pattern, and the square mark pattern of the alignment mark pattern 120d and one square mark pattern of the alignment mark pattern 120c have the same size, i.e., the mark shapes of both mark patterns are partially the same. As another example, the alignment mark pattern 120c may include two square mark patterns having different sizes; the alignment mark pattern 120d may include a circular mark pattern, i.e., the mark shapes of the two are completely different.

In an embodiment of the present application, the mask 100 further includes a structural pattern 130 disposed on the substrate 110, and the structural pattern 130 is disposed on the device mask region 111. For forming a device structure.

Further, please refer to fig. 2, which is a schematic diagram illustrating a photolithography process performed by using the mask shown in fig. 1 according to an embodiment of the present application. As shown in fig. 2, after the mask 100 is provided, a portion of the alignment mark patterns 120 on the mask 100 are then masked and at least one of the alignment mark patterns 120 is exposed. Preferably, the mask 100 is used to block part of the alignment mark pattern 120. In the embodiment of the present application, the alignment mark pattern 120a, the alignment mark pattern 120b, the alignment mark pattern 120c, and the alignment mark pattern 120e on the photomask 100 are blocked, and the alignment mark pattern 120d is exposed.

Further, a part or all of the device mask region 111 and the pattern structure 130 thereon may be exposed, or all of the device mask region 111 and the pattern structure 130 thereon may be masked according to photolithography requirements, which is not limited in the present application.

Then, a photolithography process is performed on a wafer (not shown in fig. 2) using the mask 100. Here, alignment marks are formed on the wafer mainly using the exposed alignment mark patterns 120. After exposure of one exposure area is completed, the next exposure area may be then exposed by using the exposed alignment mark pattern 120, and the alignment mark may be continuously formed on the wafer until the photolithography of the whole wafer is completed. Six exposure areas are schematically shown in fig. 2.

In an embodiment of the present application, for a different product, it may further include: the exposed alignment marks 120 are changed, for example, the alignment mark pattern 120a, the alignment mark pattern 120c, the alignment mark pattern 120d, and the alignment mark pattern 120e on the mask 100 are blocked, and the alignment mark pattern 120b is exposed. The photolithography process may then continue with the mask 100 on another product wafer, for example, to form a zero level mark on the wafer.

Therefore, a plurality of different products can be prepared by using the same photomask, thereby reducing the manufacturing cost.

In an embodiment of the present application, further, a plurality of the masks 100 may be spliced to expand the exposure area of one exposure. Referring to fig. 3, preferably, the photomask 100 further includes a detection mark pattern 140 for detecting a shift between two adjacent photomasks 100 when the photomasks 100 are spliced, where the detection mark pattern 140 is located at an edge position of the substrate 110. The detection mark pattern 140 is located in the scribe line mask region 112.

Preferably, at least one side of the detection mark pattern 140 coincides with at least one side of the substrate 110. Referring to fig. 3, in the embodiment of the present application, the detection mark pattern 140 includes a square mark pattern, two sides of the detection mark pattern 140 are respectively overlapped with two sides of the substrate 110, where the detection mark pattern 140 is located at a corner of the substrate 110. In other embodiments of the present application, the detection mark pattern 140 may be located at a side portion of the substrate 110, for example.

In an embodiment of the present application, the mask 100 may include one or more of the detection mark patterns 140. For example, the mask 100 may include one of the detection mark patterns 140, and the one detection mark pattern 140 may be located at a side portion or a corner portion of the substrate 110. As another example, the mask 100 may include a plurality of the detection mark patterns 140, one of which may be located at a side portion of the substrate 110 and the other of which may be located at a corner portion of the substrate 110. Preferably, the plurality of detection mark patterns 140 are respectively located at different side edge portions and/or different corner portions of the substrate 110. For example, the mask 100 includes four detection mark patterns 140, and the four detection mark patterns 140 are respectively located at four corners of the substrate 110.

Referring to fig. 3, in the embodiment of the application, the mask 100 includes two detection mark patterns 140, namely a detection mark pattern 140a and a detection mark pattern 140b. Two of the detection mark patterns 140 are respectively located on a pair of opposite corners of the substrate 110. In the mask 100 shown in fig. 3, the detection mark pattern 140a and the detection mark pattern 140b are located at the upper left corner and the lower right corner of the substrate 110, respectively. Thus, the inspection mark patterns 140 can be made smaller, and the offset inspection can be performed by using the inspection mark patterns 140 and the masks 100 adjacently spliced on four sides.

Next, please refer to fig. 4, which is a schematic diagram illustrating a photolithography process performed by using the mask shown in fig. 3 according to an embodiment of the present application. As shown in fig. 4, in an embodiment of the present application, two masks 100 are schematically shown to be spliced to perform a photolithography process, mask 100a and mask 100b, respectively. Specifically, the mask 100a and the mask 100b are spliced together along the X direction to form the spliced mask 101, that is, in the embodiment of the present application, the length of the spliced mask 101 in the X direction is the sum of the lengths of the mask 100a and the mask 100b in the X direction, and the length of the spliced mask 101 in the Y direction is the same as the length of the mask 100a or the mask 100b in the Y direction.

Next, a part of the alignment mark pattern 120 on the splice mask 101 is blocked, and in this embodiment, the alignment mark pattern 120b, the alignment mark pattern 120c, the alignment mark pattern 120d, and the alignment mark pattern 120e on the splice mask 101 are blocked by using a light blocking function of the photolithography device, so that the alignment mark pattern 120a is exposed. Here, the detection mark pattern 140a is also masked, and the detection mark pattern 140b is exposed. In the embodiment of the present application, the splice mask 101 is used to form a zero layer mark, so that the device mask region 111 is also masked.

Further, a photolithography process is performed on a wafer (not shown in fig. 4) using the splice mask 101. Here, alignment marks are formed on the wafer using the exposed alignment mark pattern 120a. After exposure of one exposure area is completed, the next exposure area may be then exposed by using the exposed alignment mark pattern 120a, and the alignment mark may be continuously formed on the wafer until the photolithography of the whole wafer is completed. Wherein four exposure areas are schematically shown in fig. 4.

In the embodiment of the present application, a detection mark (not shown in the figure) may be formed on the wafer by the detection mark pattern 140b, and the offset between adjacent spliced photomasks 100 may be obtained by measuring the shape and size of the detection mark, so as to adjust accordingly, thereby further improving the exposure accuracy.

In an embodiment of the present application, the method may further include: the stitching method and/or the exposed alignment marks 120 are changed to form another stitching mask, as shown in fig. 5, to form a stitching mask 102, and then a photolithography process may be performed on wafers of another product using the stitching mask 102.

As shown in fig. 5, the mask 100a and the mask 100b are spliced together along the Y direction to form the spliced mask 102, that is, the length of the spliced mask 102 in the Y direction is the sum of the lengths of the mask 100a and the mask 100b in the Y direction, and the length of the spliced mask 102 in the X direction is the same as the length of the mask 100a or the mask 100b in the X direction.

Next, a portion of the alignment mark pattern 120 on the splice mask 102 is masked, and in this embodiment, the alignment mark pattern 120a, the alignment mark pattern 120c, the alignment mark pattern 120d, and the alignment mark pattern 120e on the splice mask 102 are masked by using a mask function of the photolithography device, so that the alignment mark pattern 120b is exposed.

Further, a photolithography process is performed on a wafer (not shown in fig. 5) using the splice mask 102. Here, alignment marks are formed on the wafer using the exposed alignment mark patterns 120b. After exposure of one exposure area is completed, the next exposure area may be then exposed by using the exposed alignment mark pattern 120b, and the alignment mark may be continuously formed on the wafer until the photolithography of the whole wafer is completed. Wherein four exposure areas are schematically shown in fig. 5.

Furthermore, in other implementations of the application, various combinations of the claims and the embodiments described above can be made to form different embodiments, the application is not to be enumerated, and one of ordinary skill in the art can make many variations based on the disclosure without undue burden.

The above description is only illustrative of the preferred embodiments of the present application and is not intended to limit the scope of the present application, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (10)

1. A photomask, the photomask comprising: the device comprises a substrate and a plurality of alignment mark patterns positioned on the substrate, wherein at least two alignment mark patterns are different, and part of the alignment mark patterns can be shielded.

2. The photomask of claim 1 wherein the at least two alignment mark patterns are different comprising: the marking shapes and/or the marking layers of at least two alignment mark patterns are different.

3. The mask of claim 1 wherein the substrate includes a device mask region and a dicing street mask region, each of the alignment mark patterns being located on the dicing street mask region.

4. The mask of claim 1, wherein the substrate comprises a device mask region and a dicing street mask region, each of the alignment mark patterns being located on the dicing street mask region and/or on the device mask region.

5. The mask of any one of claims 1 to 4, further comprising a detection mark pattern for detecting a shift between two adjacent masks when a plurality of masks are used in a spliced manner, the detection mark pattern being located at an edge position of the substrate.

6. The mask of claim 5 wherein at least one side of the detection mark pattern coincides with at least one side of the substrate.

7. The mask of claim 5 wherein said mask includes a plurality of said detection mark patterns.

8. The mask of claim 7 wherein said mask includes two of said detection mark patterns, said substrate being rectangular in shape, and two of said detection mark patterns being located on a pair of opposite corners of said substrate, respectively.

9. A lithographic method, the lithographic method comprising:

providing a photomask according to any of claims 1 to 8;

shielding part of the alignment mark patterns on the photomask and exposing at least one alignment mark pattern; the method comprises the steps of,

and executing a photoetching process on the wafer by using the photomask.

10. The lithographic method of claim 9, wherein providing a mask as claimed in any one of claims 1 to 8 comprises: providing at least two masks according to any one of claims 1 to 8, and stitching together each of the masks to form a stitched mask; performing a photolithography process on a wafer using the reticle includes: and executing a photoetching process on the wafer by using the spliced photomask.