CN116794470A

CN116794470A - New semiconductor parameter test hardware architecture system

Info

Publication number: CN116794470A
Application number: CN202211559313.1A
Authority: CN
Inventors: 柯伟
Original assignee: Haining Liwan Integrated Circuit Co ltd
Current assignee: Haining Liwan Integrated Circuit Co ltd
Priority date: 2022-12-06
Filing date: 2022-12-06
Publication date: 2023-09-22

Abstract

The application discloses a novel semiconductor parameter test hardware architecture system which comprises a test module and a switch matrix, wherein the test module comprises a source measurement unit (SUM), a digital multimeter, a capacitance measurement unit and a pulse generator unit (the test module comprises but is not limited to the test unit), and a spring pin (pogo pin) test wire is connected to the switch matrix.

Description

New semiconductor parameter test hardware architecture system

Technical Field

The present application relates to a new semiconductor parameter testing hardware architecture system, and more particularly, to a new semiconductor parameter testing hardware architecture system.

Background

With the development of semiconductor manufacturing technology, the integration level of semiconductor devices is continuously improved. In the field of wafer-level semiconductor parameter testing, the demand of automated test equipment is continuously increasing. In order to realize the Kelvin test function required in the semiconductor test, the switch matrix of the conventional semiconductor parameter test system has a relatively large demand for the switch matrix. With 8 input ports and 24 output ports, for example, kelvin test is needed, the conventional switch matrix is required to be 8 x 48. As shown in fig. 1. The traditional testing system has higher use cost and is unfavorable for the development of enterprises.

Disclosure of Invention

In order to solve some or some technical problems in the prior art, one of the purposes of the present application is to provide a new semiconductor parameter testing hardware architecture system, which can reduce the use cost of enterprises.

In order to solve the above existing technical problems, one of the purposes of the present application is achieved by adopting the following technical scheme:

a new semiconductor parametric test hardware architecture system includes a test module including a source measurement unit (SUM), a digital multimeter, a capacitance measurement unit, and a pulser unit (test module including, but not limited to, the above test units), and a switch matrix to which spring pin (pogo pin) test wires are connected.

Further, a traditional single switch matrix is split into two independent switch matrices according to an input port, two wires of a test wire connected with a spring needle are respectively connected to corresponding ports of the two switch matrices, the Force end of the SUM is connected to the input end of a first switch matrix, and the sense end of the SMU is connected to the input end of a second switch matrix.

Compared with the prior art, the application has the beneficial effects that:

through reasonable combination of switch matrixes and a new wire structure, the scale of the switch matrixes of the traditional semiconductor parameter testing system can be halved, the Kelvin testing function necessary in semiconductor testing is realized, and the use cost of the testing system is obviously reduced.

Drawings

FIG. 1 is a schematic diagram of a conventional switch matrix system according to the present application;

FIG. 2 is a schematic diagram of a novel switch matrix system of the present application;

Detailed Description

The present application will be further described with reference to the accompanying drawings and detailed description, wherein it is to be understood that, on the premise of no conflict, the following embodiments or technical features may be arbitrarily combined to form new embodiments.

In the description of the present application, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

The terms "first," "second," and the like in this specification are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means a relationship in which the associated object is a new semiconductor parameter test hardware architecture system or.

Example 1

As shown in fig. 1-2, a new semiconductor parameter testing hardware architecture system includes a testing module including a source measurement unit (SUM), a digital multimeter, a capacitance measurement unit, and a pulse generator unit (the testing module includes, but is not limited to, the above testing unit), and a switch matrix to which a pogo pin (pogo pin) testing wire is connected.

The traditional single switch matrix is split into two independent switch matrices according to an input port, two wires of a test wire connected with a spring needle are respectively connected to corresponding ports of the two switch matrices, the Force end of the SUM is connected to the input end of the first switch matrix, and the sense end of the SMU is connected to the input end of the second switch matrix. SMU 1F represents the force port of SMU1 and SMU 1S represents the sense port of SMU 1.

In summary, through reasonable combination of switch matrixes and a new wire structure, the switch matrix scale of the traditional semiconductor parameter testing system can be halved, thereby realizing the Kelvin testing function necessary in semiconductor testing and remarkably reducing the cost of the testing system.

The above embodiments are only preferred embodiments of the present application, and the scope of the present application is not limited thereto, but any insubstantial changes and substitutions made by those skilled in the art on the basis of the present application are intended to be within the scope of the present application as claimed.

Claims

1. A new semiconductor parametric test hardware architecture system, characterized by: the system comprises a test module and a switch matrix, wherein the test module comprises a source measurement unit (SUM), a digital universal meter, a capacitance measurement unit and a pulse generator unit (the test module comprises but is not limited to the test unit), and a spring needle (pogo pin) test wire is connected to the switch matrix.

2. The new semiconductor parametric test hardware architecture system of claim 1, wherein: the traditional single switch matrix is split into two independent switch matrices according to an input port, two wires of a test wire connected with a spring needle are respectively connected to corresponding ports of the two switch matrices, the Force end of the SUM is connected to the input end of the first switch matrix, and the sense end of the SMU is connected to the input end of the second switch matrix.