CN116781065B

CN116781065B - High-speed asynchronous dual-mode prescaler, control method thereof and electronic equipment

Info

Publication number: CN116781065B
Application number: CN202311061943.0A
Authority: CN
Inventors: 张文通
Original assignee: Core Tide Zhuhai Technology Co ltd
Current assignee: Core Tide Zhuhai Technology Co ltd
Priority date: 2023-08-23
Filing date: 2023-08-23
Publication date: 2023-12-12
Anticipated expiration: 2043-08-23
Also published as: CN116781065A

Abstract

The invention provides a high-speed asynchronous dual-mode prescaler, a control method thereof and electronic equipment, wherein the frequency divider comprises a first trigger, a control signal input end of the first trigger receives a signal output by a first AND gate; the control signal input end of the second trigger receives signals output by the second AND gate, and the second AND gate receives the signals output by the first trigger and the second trigger; a third trigger, the signal input end of which receives the output signal of itself; the first trigger and the second trigger both receive a reference clock signal, and the clock signal input end of the third trigger receives a signal output by the second trigger; the first AND gate receives signals output by the second trigger and the third trigger and receives a frequency division ratio control signal. The invention also provides a control method of the high-speed asynchronous dual-mode prescaler. The electronic device has the high-speed asynchronous dual-mode prescaler described above. The invention has the advantages of fewer electronic devices, reduced circuit area and lower requirement on power supply voltage.

Description

High-speed asynchronous dual-mode prescaler, control method thereof and electronic equipment

Technical Field

The invention relates to the technical field of electronic frequency division, in particular to a high-speed asynchronous dual-mode prescaler for realizing four frequency division or five frequency division, a control method of the dual-mode frequency divider and electronic equipment with the dual-mode frequency divider.

Background

With the development of electronic technology, electronic devices have increasingly higher requirements for operating frequencies. Since the power consumption of an electronic device is related to the operating frequency, the higher the operating frequency, the greater the power consumption of the electronic device, and therefore, the electronic device generally enters a low-frequency operating state when fewer instructions are executed, that is, the operating frequency of the electronic device is not fixed but varies. For this purpose, the electronic device is generally provided with a frequency divider that receives the reference clock signal and divides the reference clock signal so as to obtain a divided frequency that is different from the frequency of the reference clock signal.

Some existing frequency dividers have fixed frequency division, for example, a frequency divider can only divide by a set frequency division ratio, such as divide by two or divide by three. However, since the operating frequency of the electronic device varies greatly, it is generally necessary to use clock signals of a plurality of different frequencies, and it is necessary to provide a plurality of frequency dividers to obtain clock signals of a plurality of different frequency dividers, which increases the hardware circuits of the electronic device, resulting in an increase in the production cost of the electronic device.

For this reason, some existing electronic devices use a dual-mode frequency divider, where the dual-mode frequency divider is capable of receiving a division ratio control signal and outputting two different division frequencies under the control of the division ratio control signal, that is, one frequency divider may generate two different division frequencies, so as to reduce the number of frequency dividers used by the electronic device.

For example, the patent application CN101478307a discloses a dual-mode 4/4.5 prescaler, which is provided with four D flip-flops, two latches and two signal selectors, and a plurality of and gates are required, so that more electronic devices are used and the electronic area is larger. In addition, the prescaler has larger power consumption due to more electronic devices, and also needs to work under higher voltage, which puts higher demands on the power supply of the electronic devices.

Disclosure of Invention

It is a first object of the invention to provide a high-speed asynchronous dual-mode prescaler that is simple in structure and low in power consumption.

It is a second object of the present invention to provide an electronic device having a high-speed asynchronous dual-mode prescaler as described above.

A third object of the present invention is to provide a control method of the high-speed asynchronous dual-mode prescaler.

In order to achieve the first object of the present invention, the high-speed asynchronous dual-mode prescaler provided by the present invention includes a first trigger, a control signal input terminal of which receives a signal output by a first and gate; the control signal input end of the second trigger receives signals output by the second AND gate, and the second AND gate receives the signals output by the first trigger and the second trigger; a third trigger, the signal input end of which receives the output signal of itself; the first trigger and the second trigger both receive a reference clock signal, and the clock signal input end of the third trigger receives a signal output by the second trigger; the first AND gate receives signals output by the second trigger and the third trigger and receives a frequency division ratio control signal.

The above scheme shows that the high-speed asynchronous dual-mode prescaler is only provided with three triggers, wherein the first trigger and the second trigger both receive the reference clock signal, and the third trigger receives the signal output by the second trigger as the clock signal. When the frequency division ratio control signal is a low-level signal, the high-speed asynchronous dual-mode prescaler realizes four frequency division, and when the frequency division ratio control signal is a high-level signal, the high-speed asynchronous dual-mode prescaler realizes five frequency division, so that the dual-mode frequency division function is realized.

In a preferred embodiment, the second and gate receives signals output from the inverted signal output terminal of the first flip-flop and the inverted signal output terminal of the second flip-flop.

Therefore, the second AND gate calculates through signals of the reverse signal output ends of the first trigger and the second trigger, and a control signal output to the second trigger is obtained, so that the high-speed asynchronous dual-mode prescaler operates according to set logic.

In a further scheme, the clock signal input end of the third trigger receives the signal output by the homodromous signal output end of the second trigger.

In a further scheme, the signal input end of the third trigger receives the signal output by the reverse signal end of the third trigger.

In a further scheme, the first AND gate receives the inverted signal of the inverted signal output end of the second trigger, the signal output by the inverted signal output end of the third trigger, and the frequency division ratio control signal.

In a further scheme, an inverter is connected between the inverted signal output end of the second trigger and the input end of the first AND gate.

Alternatively, the first and gate receives the signal output by the inverted output end of the second trigger, the inverted signal from the inverted signal output end of the third trigger, and the frequency division ratio control signal.

In a further scheme, the first trigger, the second trigger and the third trigger are all D triggers.

In a further scheme, the first trigger, the second trigger and the third trigger are all formed by using MOS tubes.

Therefore, the invention is based on the E-TSPC structure, adopts a plurality of MOS tubes to realize the first trigger, the second trigger and the third trigger, can realize the high-speed asynchronous dual-mode prescaler by using the least MOS tubes, is beneficial to reducing the circuit area of the high-speed asynchronous dual-mode prescaler, has low power consumption and can operate under lower power supply voltage.

In order to achieve the second object of the present invention, an electronic device provided by the present invention is provided with the above-mentioned high-speed asynchronous dual-mode prescaler.

In order to achieve the third object of the present invention, the present invention provides a control method of the above-mentioned high-speed asynchronous dual-mode prescaler, comprising: setting the frequency division ratio control signal to a low level signal when the reference clock signal is divided by four; when the reference clock signal is divided by five, the division ratio control signal is set to a high level signal.

According to the scheme, the electronic equipment can change the frequency division frequency of the clock chip output by the high-speed asynchronous dual-mode prescaler by changing the level of the frequency division ratio control signal according to the requirement of the actually required clock signal frequency. Thus, the operation of adjusting the frequency of the high-speed asynchronous dual-mode prescaler is very simple, and only the level of the frequency division ratio control signal needs to be changed.

Drawings

Fig. 1 is a logic diagram of a first embodiment of a high-speed asynchronous dual mode prescaler of the present invention.

Fig. 2 is a waveform diagram of a first embodiment of a high-speed asynchronous dual-mode prescaler of the present invention.

Fig. 3 is a state transition diagram of a first embodiment of a high speed asynchronous dual mode prescaler of the present invention for divide-by-four.

Fig. 4 is a waveform diagram of a first embodiment of the high-speed asynchronous dual mode prescaler of the present invention for five frequency division.

Fig. 5 is a state jump diagram of a first embodiment of the high speed asynchronous dual mode prescaler of the present invention for divide-by-five.

Fig. 6 is an electrical schematic of a first embodiment of the high-speed asynchronous dual mode prescaler of the present invention.

Fig. 7 is a logic diagram of a second embodiment of the high speed asynchronous dual mode prescaler of the present invention.

The invention is further described below with reference to the drawings and examples.

Detailed Description

The high-speed asynchronous dual-mode prescaler is used for performing four-frequency division or five-frequency division on an input reference clock signal, only three D triggers are arranged in the high-speed asynchronous dual-mode prescaler, the number of used triggers is small, and a plurality of D triggers are all realized by using MOS (metal oxide semiconductor) tubes, so that the number of electronic devices used by the high-speed asynchronous dual-mode prescaler is small, the circuit area can be reduced, and the power consumption of the high-speed asynchronous dual-mode prescaler is reduced.

First embodiment:

referring to fig. 1, the high-speed asynchronous dual-mode frequency division of the present embodiment is provided with three flip-flops, namely, a first flip-flop DFF1, a second flip-flop DFF2 and a third flip-flop DFF3, and two and gates, namely, a first and a second and gates N1 and N2, respectively, and a not gate N3. The first flip-flop DFF1, the second flip-flop DFF2, and the third flip-flop DFF3 are D flip-flops.

The first flip-flop DFF1 and the second flip-flop DFF2 both receive the reference clock signal Fin, the third flip-flop DFF3 receives the signal output by the second flip-flop DFF2 as a clock signal, that is, the clock signal input terminal CLK3 of the third flip-flop DFF3 is connected to the unidirectional signal output terminal Q2 of the second flip-flop DFF2, that is, the signal output by the unidirectional signal output terminal Q2 of the second flip-flop DFF2 is used as a clock signal.

As can be seen from fig. 1, the control signal input terminal D1 of the first flip-flop DFF1 receives the signal output by the first and gate N1, and the first and gate N1 receives three signals, which are the inverted signal output by the inverted signal output terminal QN2 of the second flip-flop DFF2, the inverted signal output by the inverted signal output terminal QN3 of the third flip-flop DFF3, and the frequency division ratio control signal Mc, respectively. The frequency division ratio control signal Mc may be output by a controller of the electronic device, and is used to control the frequency of the clock signal of the high-speed asynchronous dual-mode frequency division output.

In order to invert the signal output by the inverted signal output terminal QN2 of the second flip-flop DFF2, a not gate N3 is provided between the inverted signal output terminal QN2 of the second flip-flop DFF2 and the input terminal of the first and gate N1, and the not gate N3 inverts the signal output by the inverted signal output terminal QN2 of the second flip-flop DFF 2.

The control signal input terminal D2 of the second flip-flop DFF2 receives the signal output by the second and gate N2, and the second and gate N2 receives the signals output by the first flip-flop DFF1 and the second flip-flop DFF2, specifically, the signal output terminal QN1 of the first flip-flop DFF1 and the signal output terminal QN2 of the second flip-flop DFF 2.

The control signal input terminal D3 of the third flip-flop DFF3 receives a signal output by itself, specifically, a signal output by the inverted signal output terminal QN3 of the third flip-flop DFF3.

In this embodiment, the state jump of the frequency-dividing signal is implemented according to the signals output by the reverse signal output ends QN1, QN2, QN3 of the three flip-flops. Specifically, when the frequency division ratio control signal Mc is at a low level, it is assumed that in the initial state, signals output by the inverted signal output terminals QN1, QN2, QN3 of the three flip-flops are all at a high level, that is, signals output by QN1, QN2, QN3 at this time are characterized as 111.

As shown in fig. 2, since the frequency division ratio control signal Mc is at a low level, the output of the first and gate N1 is constantly at a low level, that is, the control signal input terminal D1 of the first flip-flop DFF1 is constantly at a low level, and thus the inverted signal output terminal QN1 of the first flip-flop DFF1 is constantly at a high level.

Before the first rising edge of the reference clock signal Fin arrives, the inverted signal output terminal QN1 of the first flip-flop DFF1 outputs a high level signal, and the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a high level signal, so the second and gate N2 outputs a high level signal, and when the first rising edge of the reference clock signal Fin arrives, the control signal input terminal D2 of the second flip-flop DFF2 is high, so the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a low level signal. At this time, the level of the unidirectional signal output terminal Q2 of the second flip-flop DFF2 changes from a low level to a high level, forming a rising edge.

The clock signal input terminal CLK3 of the third flip-flop DFF3 receives the signal output from the unidirectional signal output terminal Q2 of the second flip-flop DFF2, that is, the signal output from the unidirectional signal output terminal Q2 of the second flip-flop DFF2 is used as the clock signal. Since the same-direction signal output terminal Q2 of the second flip-flop DFF2 forms a rising edge when the first rising edge of the reference clock signal Fin arrives, and the control signal input terminal D3 of the third flip-flop DFF3 receives the high-level signal output from the reverse signal output terminal QN3 thereof when the rising edge arrives, the reverse signal output terminal QN3 of the third flip-flop DFF3 will become a low-level signal the more. It can be seen that, at this time, the inverted signal output terminals QN1, QN2, QN3 of the three flip-flops output a high level signal, a low level signal, and a low level signal, respectively, and the binary number is represented as 100.

Before the second rising edge of the reference clock signal Fin arrives, the inverted signal output terminal QN1 of the first flip-flop DFF1 outputs a high level signal, and the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a low level signal, so the second and gate N2 outputs a low level signal, and when the second rising edge of the reference clock signal Fin arrives, the control signal input terminal D2 of the second flip-flop DFF2 is low, so the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a high level signal. At this time, the level of the unidirectional signal output terminal Q2 of the second flip-flop DFF2 changes from the high level to the low level, forming a falling edge.

The third flip-flop DFF3 does not change the output level when the clock signal input terminal CLK3 thereof is a falling edge, and thus the inverted signal output terminal QN3 of the third flip-flop DFF3 is still a low level signal. It can be seen that at this time, the inverted signal output terminals QN1, QN2, QN3 of the three flip-flops output a high level signal, and a low level signal, respectively, and the binary number is denoted by 110.

Before the third rising edge of the reference clock signal Fin arrives, the inverted signal output terminal QN1 of the first flip-flop DFF1 outputs a high level signal, the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a high level signal, and thus the second and gate N2 outputs a high level signal, and when the third rising edge of the reference clock signal Fin arrives, the control signal input terminal D2 of the second flip-flop DFF2 is high, and thus the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a low level signal. At this time, the level of the unidirectional signal output terminal Q2 of the second flip-flop DFF2 changes from a low level to a high level, forming a rising edge.

Before the rising edge arrives, the inverted signal output terminal QN3 of the third flip-flop DFF3 is a low level signal, and therefore, the inverted signal output terminal QN3 of the third flip-flop DFF3 becomes a high level signal as the rising edge arrives. It can be seen that at this time, the inverted signal output terminals QN1, QN2, QN3 of the three flip-flops output a high level signal, a low level signal, and a high level signal, respectively, and the binary number is represented as 101.

Before the fourth rising edge of the reference clock signal Fin arrives, the inverted signal output terminal QN1 of the first flip-flop DFF1 outputs a high level signal, and the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a low level signal, so the second and gate N2 outputs a low level signal, and when the fourth rising edge of the reference clock signal Fin arrives, the control signal input terminal D2 of the second flip-flop DFF2 is low, so the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a high level signal. At this time, the level of the unidirectional signal output terminal Q2 of the second flip-flop DFF2 changes from the high level to the low level, forming a falling edge.

The third flip-flop DFF3 does not change the output level when the clock signal input terminal CLK3 thereof is a falling edge, and thus the inverted signal output terminal QN3 of the third flip-flop DFF3 is still a high level signal. It can be seen that at this time, the inverted signal output terminals QN1, QN2, QN3 of the three flip-flops output a high level signal, respectively, and the binary number is represented as 111, that is, returns to the initial state. The state of the three flip-flops is cyclically changed as described above when the fifth rising edge of the reference clock signal Fin arrives. Thus, at four clock cycles of the reference clock signal Fin, the state changes of the inverted signal output terminals QN1, QN2, QN3 of the three flip-flops are 111, 100, 110, 101 in order, and the state changes are as shown in fig. 3. It can be seen that the high-speed asynchronous dual-mode prescaler achieves the function of four frequency divisions when the frequency division ratio control signal Mc is at a low level.

When the frequency division ratio control signal Mc is at a high level, referring to fig. 2, it is assumed that in the initial state, the signals output by the inverted signal output ends QN1, QN2, QN3 of the three flip-flops are all at a high level, that is, the signals output by QN1, QN2, QN3 at this time are characterized as 111, and since the first and gate N1 receives the signal inverted by the inverted signal output end QN2 of the second flip-flop DFF2, the first and gate N1 outputs a low level signal.

Before the first rising edge of the reference clock signal Fin arrives, the control signal input terminal D1 of the first flip-flop DFF1 is a low level signal, the inverted signal output terminal QN1 thereof outputs a high level signal, and the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a high level signal, so the second and gate N2 outputs a high level signal, and when the first rising edge of the reference clock signal Fin arrives, the control signal input terminal D2 of the second flip-flop DFF2 is a high level, so the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a low level signal. At this time, the level of the unidirectional signal output terminal Q2 of the second flip-flop DFF2 changes from a low level to a high level, forming a rising edge.

The clock signal input terminal CLK3 of the third flip-flop DFF3 receives the signal output from the unidirectional signal output terminal Q2 of the second flip-flop DFF 2. Since the same-direction signal output terminal Q2 of the second flip-flop DFF2 forms a rising edge when the first rising edge of the reference clock signal Fin arrives, and the control signal input terminal D3 of the third flip-flop DFF3 receives the high-level signal output from the reverse signal output terminal QN3 thereof when the rising edge arrives, the reverse signal output terminal QN3 of the third flip-flop DFF3 will become a low-level signal the more. It can be seen that, at this time, the inverted signal output terminals QN1, QN2, QN3 of the three flip-flops output a high level signal, a low level signal, and a low level signal, respectively, and the binary number is represented as 100.

Before the second rising edge of the reference clock signal Fin arrives, the inverted signal output terminal QN3 of the third flip-flop DFF3 outputs the low level signal, so the first and gate N1 still outputs the low level signal, and the control signal input terminal D1 of the first flip-flop DFF1 is the low level signal, so the inverted signal output terminal QN1 thereof outputs the high level signal. The inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a low level signal, so the second and gate N2 outputs a low level signal, and the control signal input terminal D2 of the second flip-flop DFF2 is low level when the second rising edge of the reference clock signal Fin arrives, so the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a high level signal. At this time, the level of the unidirectional signal output terminal Q2 of the second flip-flop DFF2 changes from the high level to the low level, forming a falling edge.

Before the third rising edge of the reference clock signal Fin arrives, the inverted signal output terminal QN3 of the third flip-flop DFF3 outputs the low level signal, so the first and gate N1 still outputs the low level signal, and the control signal input terminal D1 of the first flip-flop DFF1 is the low level signal, so the inverted signal output terminal QN1 thereof outputs the high level signal. The inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a high signal, so the second and gate N2 outputs a high signal, and the control signal input terminal D2 of the second flip-flop DFF2 is high when the third rising edge of the reference clock signal Fin arrives, so the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a low signal. At this time, the level of the unidirectional signal output terminal Q2 of the second flip-flop DFF2 changes from a low level to a high level, forming a rising edge.

Before the fourth rising edge of the reference clock signal Fin arrives, the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a low level signal, and the inverted signal output terminal QN3 of the third flip-flop DFF3 outputs a high level signal, and the frequency division ratio control signal Mc is added to the high level signal, so that the first and gate N1 outputs a high level signal, and the control signal input terminal D1 of the first flip-flop DFF1 is a high level signal, and thus the inverted signal output terminal QN1 of the first flip-flop DFF1 outputs a low level signal when the fourth rising edge of the reference clock signal Fin arrives.

And the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a low level signal, so the second and gate N2 outputs a low level signal, and the control signal input terminal D2 of the second flip-flop DFF2 is low level when the fourth rising edge of the reference clock signal Fin arrives, so the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a high level signal. At this time, the level of the unidirectional signal output terminal Q2 of the second flip-flop DFF2 changes from the high level to the low level, forming a falling edge.

The third flip-flop DFF3 does not change the output level when the clock signal input terminal CLK3 thereof is a falling edge, and thus the inverted signal output terminal QN3 of the third flip-flop DFF3 is still a high level signal. It can be seen that, at this time, the inverted signal output terminals QN1, QN2, QN3 of the three flip-flops output a low level signal, a high level signal, and a high level signal, respectively, and the binary number is characterized as 011.

Before the fifth rising edge of the reference clock signal Fin arrives, the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs the high level signal, and the inverted signal is the low level signal, so the first and gate N1 outputs the low level signal, and the control signal input terminal D1 of the first flip-flop DFF1 is the low level signal, so the inverted signal output terminal QN1 of the first flip-flop DFF1 outputs the high level signal when the fifth rising edge of the reference clock signal Fin arrives.

Before the fifth rising edge of the reference clock signal Fin arrives, the inverted signal output terminal QN1 of the first flip-flop DFF1 outputs a low level signal, so the second and gate N2 outputs a low level signal, and when the fifth rising edge of the reference clock signal Fin arrives, the control signal input terminal D2 of the second flip-flop DFF2 is low, so the inverted signal output terminal QN2 of the second flip-flop DFF2 outputs a high level signal. At this time, the level of the unidirectional signal output terminal Q2 of the second flip-flop DFF2 is kept at the low level.

Therefore, the third flip-flop DFF3 does not change state when the fifth rising edge of the reference clock signal Fin arrives, and the inverted signal output terminal QN3 thereof is still a high level signal. It can be seen that at this time, the inverted signal output terminals QN1, QN2, QN3 of the three flip-flops output a high level signal, respectively, and the binary number is represented as 111, that is, returns to the initial state.

The state of the three flip-flops is cyclically changed as described above when the sixth rising edge of the reference clock signal Fin arrives. Thus, at five clock cycles of the reference clock signal Fin, the state changes of the inverted signal output terminals QN1, QN2, QN3 of the three flip-flops are sequentially 111, 100, 110, 101, 011, as shown in fig. 5. It can be seen that the high-speed asynchronous dual-mode prescaler achieves the function of five division when the division ratio control signal Mc is at a high level.

In order to set the circuit area of the high-speed asynchronous dual-mode prescaler to be minimum, the embodiment adopts an E-TSPC structure to design three triggers, namely, a first trigger DFF1, a second trigger DFF2 and a third trigger DFF3 are all realized by MOS tubes. Further, the first and gate N1, the second and gate N2, and the not gate N3 in this embodiment are all implemented by using MOS transistors.

A circuit diagram of the high-speed asynchronous dual-mode prescaler adopting the E-TSPC structural design is shown in FIG. 6, wherein MOS tubes M5, M6, M7, M8, M9 and M11 form a first trigger DFF1, MOS tubes M12, M13, M14, M15, M16 and M17 form a second trigger DFF2, and MOS tubes M18, M19, M20, M21, M22, M23, M24, M25 and M26 form a third trigger DFF3. In addition, MOS transistors M1, M2, M3, M4 constitute a first and gate N1 and a not gate N3, and MOS transistors M9, M10, and M11 also constitute a second and gate N2.

As can be seen from fig. 6, MOS transistors M1, M5, M7, M11, M12, M14, M16, M18, M19, M21, M24 are P-type MOS transistors, and MOS transistors M2, M3, M4, M6, M8, M9, M10, M13, M15, M17, M20, M22, M23, M25, M26 are N-type MOS transistors. The MOS transistors M1, M5, M8, M11, M12, and M15 receive the reference clock signal Fin, the MOS transistor M4 receives the frequency division ratio control signal Mc, the drains of the MOS transistors M9 and M10 output the signal of the inverted signal output terminal QN1 of the first flip-flop DFF1, and the output signal is received by the gate of the MOS transistor M13. The drains of the MOS transistors M15 and M14 output the signal of the inverted signal output terminal QN2 of the second flip-flop DFF2, and the drains of the MOS transistors M17 and M16 output the signal of the homodromous signal output terminal Q2 of the second flip-flop DFF2, and the drains of the MOS transistors M24 and M25 output the output signal Qout of the high-speed asynchronous dual-mode prescaler. In addition, the drain electrode of the MOS transistor M21, the drain electrode of the MOS transistor M22, the gate electrode of the MOS transistor M24, and the gate electrode of the MOS transistor M26 are connected to each other.

Because three triggers, two AND gates and NOT gates of the high-speed asynchronous dual-mode prescaler are all realized by using MOS (metal oxide semiconductor) tubes, and the first trigger DFF1 and the second AND gate N2 share a part of the MOS tubes, the MOS tubes used by the whole high-speed asynchronous dual-mode prescaler are very few, on one hand, the circuit area of the high-speed asynchronous dual-mode prescaler can be reduced, and on the other hand, the whole circuit is formed by using the MOS tubes, so that the circuit has lower power consumption and can operate under lower power supply voltage, and the requirement on the power supply voltage is lower.

In this embodiment, signals received by the control signal input ends of the respective flip-flops are formed by the control signal input ends of the respective flip-flops or the reverse signal output ends of the other flip-flops, and signals output by the reverse signal output ends of the respective flip-flops are output as output signals of the high-speed asynchronous dual-mode prescaler, so that the number of connection nodes of the whole circuit is small, and the area of the circuit is reduced.

The high-speed asynchronous dual-mode prescaler can be arranged on an electronic device, for example, the electronic device is provided with a controller, the controller determines that four frequency division or five frequency division is needed according to actual use requirements, if the reference clock signal needs to be subjected to four frequency division, the frequency division ratio control signal Mc is set to be a low-level signal, and if the reference clock signal needs to be subjected to five frequency division, the frequency division ratio control signal Mc is set to be a high-level signal. In this way, the change of the frequency division frequency can be conveniently realized.

Second embodiment:

referring to fig. 7, the high-speed asynchronous double-modulus divider of the present embodiment is provided with three flip-flops, namely, a first flip-flop DFF7, a second flip-flop DFF8 and a third flip-flop DFF9, and further provided with two and gates, namely, a first and gate N6, a second and gate N7, and further provided with two not gates, namely, a first not gate N8 and a second not gate N9. The first flip-flop DFF1, the second flip-flop DFF2, and the third flip-flop DFF3 are all D flip-flops.

As can be seen from fig. 7, the first flip-flop DFF7 and the second flip-flop DFF8 each receive the reference clock signal Fin, and the third flip-flop DFF9 receives the signal output from the second flip-flop DFF8 as a clock signal, that is, the clock signal input terminal CLK9 of the third flip-flop DFF9 is connected to the unidirectional signal output terminal Q8 of the second flip-flop DFF 8.

The control signal input end D7 of the first flip-flop DFF7 receives the signal output by the first and gate N6, and the first and gate N6 receives three signals, which are the inverted signal of the signal output by the inverted signal output end QN8 of the second flip-flop DFF8, the inverted signal of the signal output by the homodromous signal output end Q9 of the third flip-flop DFF9, and the frequency division ratio control signal Mc.

For this purpose, a first not gate N8 is disposed between the inverted signal output terminal QN8 of the second flip-flop DFF8 and the input terminal of the first and gate N6, and a second not gate N9 is disposed between the homodromous signal output terminal Q9 of the third flip-flop DFF9 and the input terminal of the first and gate N6.

The control signal input terminal D8 of the second flip-flop DFF8 receives the signal output from the second and gate N7, and the second and gate N7 receives the signal output from the inverted signal output terminal QN7 of the first flip-flop DFF7 and the inverted signal output terminal QN8 of the second flip-flop DFF 8.

The control signal input end D9 of the third flip-flop DFF9 receives the signal output by itself, specifically, the signal after the inversion of the homodromous signal output end Q9 of the third flip-flop DFF 9.

Similarly, the present embodiment implements state skipping of the frequency-divided signal according to signals output from the inverted signal output terminals QN7, QN8, QN9 of the three flip-flops. Specifically, when the frequency division ratio control signal Mc is at a low level, four frequency division is realized, and state transitions of the reverse signal output ends QN7, QN8, QN9 of the three flip-flops are the same as those of the first embodiment; when the frequency division ratio control signal Mc is at a high level, five frequency divisions are implemented, and state jumps of the reverse signal output ends QN7, QN8, QN9 of the three flip-flops are the same as those of the first embodiment, and will not be described again.

In addition, the embodiment may also adopt an E-TSPC structure to design three flip-flops and two and gates, that is, the first flip-flop DFF7, the second flip-flop DFF8, the third flip-flop DFF9, the first and gate N6, the second and gate N7, the first not gate N8, and the second not gate N9 are all implemented by using MOS transistors.

Finally, it should be emphasized that the invention is not limited to the above-described embodiments, for example variations in the timing value of a fixed time, or variations in the internal structure of a floating timer, etc., which are intended to be included within the scope of the claims of the invention.

Claims

1. A high-speed asynchronous dual-mode prescaler comprising:

the control signal input end of the first trigger receives a signal output by the first AND gate;

the control signal input end of the second trigger receives signals output by a second AND gate, and the second AND gate receives the signals output by the first trigger and the second trigger;

the signal input end of the third trigger receives an output signal of the third trigger;

the first trigger and the second trigger both receive a reference clock signal, and the clock signal input end of the third trigger receives a signal output by the second trigger;

the first AND gate receives signals output by the second trigger and the third trigger and receives a frequency division ratio control signal.

2. The high-speed asynchronous dual mode prescaler of claim 1, wherein:

the second AND gate receives signals output by the reverse signal output end of the first trigger and the reverse signal output end of the second trigger.

3. The high-speed asynchronous dual mode prescaler of claim 1, wherein:

the clock signal input end of the third trigger receives the signal output by the homodromous signal output end of the second trigger.

4. The high-speed asynchronous dual mode prescaler of claim 1, wherein:

the signal input end of the third trigger receives the signal output by the reverse signal end of the third trigger.

5. The high-speed asynchronous dual mode prescaler of claim 1, wherein:

the first AND gate receives the inverted signal of the inverted signal output end of the second trigger, the signal output by the inverted signal output end of the third trigger, and the frequency division ratio control signal.

6. The high-speed asynchronous dual mode prescaler of claim 5, wherein:

an inverter is connected between the inverted signal output end of the second trigger and the input end of the first AND gate.

7. The high-speed asynchronous dual mode prescaler of claim 1, wherein:

the first AND gate receives the inverted signal of the inverted output end of the second trigger, the inverted signal of the same-direction signal output end of the third trigger, and the frequency division ratio control signal.

8. The high-speed asynchronous dual mode prescaler according to any of claims 1 to 7, wherein:

the first trigger, the second trigger and the third trigger are all composed of MOS tubes.

9. Electronic device, characterized in that a high-speed asynchronous dual-mode prescaler according to any of claims 1 to 8 is provided.

10. The control method of a high-speed asynchronous dual-mode prescaler according to any one of claims 1 to 8, comprising:

setting the frequency division ratio control signal to a low level signal when the reference clock signal is divided by four;

when the reference clock signal is divided by five, the frequency division ratio control signal is set to a high level signal.