CN116779648A - Schottky diode layout structure and manufacturing method thereof - Google Patents
Schottky diode layout structure and manufacturing method thereof Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 81
- 239000002184 metal Substances 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000005530 etching Methods 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000005468 ion implantation Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 210000001503 joint Anatomy 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000002513 implantation Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- -1 aluminum ions Chemical class 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 10
- 229910010271 silicon carbide Inorganic materials 0.000 description 10
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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Abstract
The application provides a schottky diode layout structure and a manufacturing method thereof, wherein the schottky diode layout structure comprises the following components: a first conductivity type substrate; a first conductive type epitaxial layer disposed on one side of the first conductive type substrate; the polygonal micro-grooves are arranged on one side, away from the first conductive type substrate, of the first conductive type epitaxial layer, the side walls of the polygonal micro-grooves are inclined planes, a platform area is reserved between adjacent edges of two adjacent polygonal micro-grooves, and a second conductive type metal area is arranged on the bottom surface of each polygonal micro-groove and the platform area; a first metal layer covering the polygonal micro-grooves and the second conductive-type metal region; the second metal layer is arranged on one side of the first conductive type substrate, which is away from the first conductive type epitaxial layer. The Schottky diode chip has smaller size, lower cost and higher manufacturing robustness.
Description
Technical Field
The application relates to the field of integrated circuit application, in particular to a schottky diode layout structure and a manufacturing method thereof.
Background
Compared with the traditional silicon material, the silicon carbide has the characteristics of wide band gap, high melting point, low dielectric constant, high breakdown field strength, high heat conductivity coefficient, high saturated electron drift speed and the like, and can be manufactured into devices to work under the scenes of higher temperature, closer distance, higher power level and the like.
However, the existing silicon carbide schottky diode (Schottky Barrier Diode, SBD) has the disadvantages of overlarge chip area, high cost, large PN junction area, overlarge junction capacitance, long turn-on and turn-off recovery time and increased power consumption.
Disclosure of Invention
In view of the problems in the prior art, the application provides a schottky diode layout structure and a manufacturing method thereof, which mainly solve the problem of low wafer utilization rate caused by large chip area of the conventional schottky diode.
In order to achieve the above and other objects, the present application adopts the following technical scheme.
The application provides a schottky diode layout structure, which comprises: a first conductivity type substrate; a first conductive type epitaxial layer disposed on one side of the first conductive type substrate; the polygonal micro-grooves are arranged on one side, away from the first conductive type substrate, of the first conductive type epitaxial layer, the side walls of the polygonal micro-grooves are inclined planes, a platform area is reserved between adjacent edges of two adjacent polygonal micro-grooves, and a second conductive type metal area is arranged on the bottom surface of each polygonal micro-groove and the platform area; a first metal layer covering the polygonal micro-groove and the second conductive type metal region to form schottky contact at a butt joint region of a side wall of the polygonal micro-groove and the mesa region; the second metal layer is arranged on one side of the first conductive type substrate, which is away from the first conductive type epitaxial layer.
In an embodiment of the present application, an opening section of the polygonal micro-groove is hexagonal.
In an embodiment of the present application, a butt joint position between the side wall of the polygonal micro-groove and the platform area is a cambered surface structure.
In an embodiment of the present application, the depth of the polygonal micro-groove is 1-1000nm.
In one embodiment of the application, the doping concentration of the first conductive type substrate is 1e19-1e21cm -3 The thickness is 100-500 mu m; the doping concentration of the first conductive type epitaxial layer is 5e15-2e16, and the thickness of the first conductive type epitaxial layer is 5-30 mu m; the junction depth of the second conductive type metal region is 0.6-1.8 μm, and the doping concentration is 1e16-5e18cm -3 。
The application also provides a manufacturing method of the schottky diode layout structure, which comprises the following steps: providing a first conductive type substrate; growing a first conductivity type epitaxial layer on the first conductivity type substrate; manufacturing a plurality of vertical groove areas on one side of the first conductive type epitaxial layer, which is away from the first conductive type substrate, wherein a platform area is reserved between adjacent sides of two adjacent vertical groove areas; respectively manufacturing a second conductive type metal region on the bottom surface of each vertical groove region and the platform region; etching the side wall of the vertical groove region to obtain a polygonal micro groove, wherein the side wall of the polygonal micro groove is an inclined plane; manufacturing a first metal layer, wherein the first metal layer covers the polygonal micro-groove and the second conductive type metal region so as to form Schottky contact at a butt joint region of the side wall of the polygonal micro-groove and the platform region; and manufacturing a second metal layer on one side of the first conductive type substrate away from the first conductive type epitaxial layer.
In an embodiment of the present application, the step of etching the sidewall of the vertical trench region to obtain the polygonal micro-trench includes: depositing silicon dioxide with the thickness of 0.1-10 mu m on one side of the first conductive type epitaxial layer away from the first conductive type substrate layer, and forming a vertical groove region by one-time etching; and performing secondary etching on the vertical groove region to form the polygonal micro groove with the inclined side wall.
In an embodiment of the present application, the step of forming the second conductive type metal region on the bottom surface of each of the vertical trench regions and the mesa region includes: depositing silicon dioxide on the surface of the vertical groove area; forming openings in the region where the vertical groove region is located and the platform region through photoetching; and implanting aluminum ions at the position of the opening by means of ion implantation to form the metal region of the second conductivity type.
In an embodiment of the present application, the step of fabricating the first metal layer includes: and depositing nickel or aluminum with the thickness of 1-10 mu m on one side of the first conductive type epitaxial layer, which is away from the first conductive type substrate, and annealing to form Schottky contact between the side wall of the polygonal micro-groove and the platform region, so as to obtain the first metal layer.
In one embodiment of the application, the implantation dosage of the aluminum ions is 1e12-1e16cm -2 The implantation energy is 400-1500KeV.
As described above, the schottky diode layout structure and the manufacturing method thereof provided by the application have the following beneficial effects.
The application can increase the utilization rate of the wafer area through the polygonal micro-groove design, and the side wall of the micro-groove is provided with the inclined plane, so that the Schottky contact area can be effectively increased, and the current density per unit area can be improved.
Drawings
Fig. 1 is a schematic cross-sectional view of a schottky diode according to an embodiment of the present application.
Fig. 2 is a flow chart of a method for fabricating a schottky diode layout structure according to an embodiment of the present application.
FIG. 3 is a schematic cross-sectional view of an embodiment of the present application after one etching.
Fig. 4 is a schematic cross-sectional view of an embodiment of the application after ion implantation.
FIG. 5 is a schematic cross-sectional view of a second etching process according to an embodiment of the application.
FIG. 6 is a schematic cross-sectional view of a deposited first metal layer and second metal layer according to an embodiment of the present application.
FIG. 7 is a schematic top view of an overall layout according to an embodiment of the present application.
Reference numerals illustrate:
1-first conductivity type substrate, 2-first conductivity type epitaxial layer, 3-polygonal micro-trench, 4-second conductivity type metal region, 5-mesa region, 6-second metal layer, 7-butt region.
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
Referring to fig. 1, the present application provides a schottky diode layout structure, which includes a first conductive type substrate 1, a first conductive type epitaxial layer 2, a plurality of polygonal micro-trenches 3, a second conductive type metal region 4, a first metal layer and a second metal layer 6. Wherein, the first conductivity type epitaxial layer 2 is disposed on one side of the first conductivity type substrate 1 layer, and the plurality of polygonal micro-trenches 3 are disposed on one side of the first conductivity type epitaxial layer 2 away from the first conductivity type substrate 1 layer. The side wall of each polygonal micro-groove 3 is an inclined plane. In the process of forming the polygonal micro-groove 3 structure, a platform area 5 is arranged between adjacent sides of any two adjacent polygonal micro-grooves 3, and the two polygonal micro-grooves 3 are separated by the platform area 5. In this way, the resulting mesa region 5 forms a polygonal envelope outside the polygonal micro-groove 3.The width of the land 5 (i.e., the distance between adjacent sides of the two adjacent polygonal micro grooves 3) may be set and adjusted according to actual production requirements, without limitation. A second conductivity type metal region 4 is provided at the bottom of each polygonal micro-groove 3, and the second conductivity type metal region 4 at the bottom of the polygonal micro-groove 3 extends from the bottom surface of the polygonal micro-groove 3 to the inside of the first conductivity type epitaxial layer 2. The mesa region 5 between each set of adjacent sides of two adjacent polygonal micro-trenches 3 may be provided with a second conductivity-type metal region 4, and the second conductivity-type metal region 4 may be formed by extending the surface of the mesa region 5 toward the inside of the first conductivity-type epitaxial layer 2. The second conductivity type metal region 4 may be obtained by ion implantation, and the implantation element may be Al ions. The junction depth of the second conductivity type metal region 4 is 0.6-1.8 μm, and the doping concentration is 1e16-5e18cm -3 。
In an embodiment, the depth of the polygonal micro-groove 3 may be set to 1-1000nm, the side wall of the polygonal micro-groove 3 is an inclined plane, the butt joint position of the side wall and the platform region 5 may be set to be an arc surface, and the arc surface structure may further increase the surface current density of the schottky contact region and improve the front current carrying capability.
In an embodiment, the opening section of the polygonal micro-groove 3 is hexagonal, the hexagonal structure design can increase the whole chip area, in addition, the micro-groove inclined plane design can enhance the manufacturing robustness of the hexagonal structure, even if the etching process is limited, the ideal hexagonal micro-groove is difficult to reach, the effect of high current density conduction can be achieved based on the inclined plane design, and the process complexity of device production can be effectively reduced. The Schottky diode with the same specification can enable the chip size to be smaller, the wafer utilization rate to be higher, and the production cost of the whole device to be reduced by adopting the scheme of the embodiment of the application.
In an embodiment, the first metal layer may be disposed outside each polygonal micro-groove 3 and the mesa region 5, and the surfaces of the polygonal micro-groove 3 and the mesa region 5 are covered by the first metal layer, so that the bottom surface of the polygonal micro-groove 3 contacts with the first metal layer, the second conductive type metal region 4 disposed at the bottom of the polygonal micro-groove 3 contacts with the first metal layer in ohmic contact, and the second conductive type metal region 4 disposed at the mesa region 5 contacts with the first metal layer in ohmic contact. The junction region 7 between the sidewall of the polygonal micro-trench 3 to the second conductivity type metal region 4 of the adjacent mesa region 5 forms a schottky contact with the first metal layer.
In an embodiment, the second metal layer 6 is arranged on the side of the first conductivity type substrate 1 facing away from the first conductivity type epitaxial layer 2, the second metal layer 6 being in ohmic contact with the first conductivity type substrate 1.
In an embodiment, the first conductivity type may be N-type and the second conductivity type may be P-type. Silicon carbide can be used as the substrate, and the doping concentration of the N-type substrate is 1e19-1e21cm -3 The thickness is 100-500 μm. The doping concentration of the N-type epitaxial layer is 5e15-2e16cm -3 The thickness is 5-30 μm. The second conductive type metal region 4 can be heavily doped to form a P+ region, the P+ region at the bottom of the polygonal micro-groove 3 and the P+ region of the adjacent platform region 5 are in ohmic contact with the first metal layer respectively, and the butt joint region 7 between the two P+ regions and the first metal layer form Schottky contact, so that an MPS structure is formed, corresponding conductivity modulation can be performed if instant heavy current is encountered, device failure is prevented, and anti-surge capability can be improved. In addition, each P+ region can form depletion layers which diffuse to two sides, so that the depletion layers formed by two adjacent P+ regions can be connected into a whole, reverse withstand voltage is enhanced, depletion capacity is stronger, and reverse leakage is effectively reduced.
Based on the Schottky diode layout structure, schottky contact is formed on the inclined surface of the side wall of the micro-groove structure through hexagonal micro-groove design, so that the Schottky contact area has smaller occupation ratio in the layout, smaller chip size and high wafer utilization rate, and the cost is effectively reduced; the Schottky contact area has smaller occupation ratio in the layout, and even if the etching of the micro-groove is incomplete, the reverse leakage performance of the device can be ensured by the communication of the depletion layer between the P+ areas, so that the robustness of the device is enhanced; the epitaxial layer can also adopt silicon carbide, ohmic contact of a P+ region is formed on the surface of the silicon carbide, an MPS structure can be formed based on ohmic contact and Schottky contact, and corresponding conductivity modulation can be performed when instantaneous heavy current is encountered, so that the device is prevented from being invalid.
Referring to fig. 2, fig. 2 is a flow chart illustrating a method for fabricating a schottky diode layout structure according to an embodiment of the application. The manufacturing method comprises the following steps:
in step S200, a first conductivity type substrate 1 is provided.
In an embodiment, silicon carbide may be used as the substrate, and the silicon carbide may be doped to obtain the first conductivity type substrate 1. Wherein the first conductivity type can be N type, the silicon carbide is doped with N type, and the doping concentration is 1e19-1e21cm -3 The thickness is 100-500um.
In step S210, a first conductivity-type epitaxial layer 2 is grown on the first conductivity-type substrate 1.
In one embodiment, a silicon carbide layer is epitaxially grown on a silicon carbide substrate as an epitaxial layer, the epitaxial layer is N-doped with a doping concentration of 5e15-2e16cm -3 The thickness is 5-30um.
In step S220, a plurality of vertical trench regions are formed on the side of the first conductivity-type epitaxial layer 2 facing away from the first conductivity-type substrate 1, and a mesa region 5 is left between adjacent sides of two adjacent vertical trench regions.
Referring to fig. 3, fig. 3 is a schematic cross-sectional view of an embodiment of the present application after one etching. In one embodiment, the vertical trench regions with sidewalls perpendicular to the first conductivity type epitaxial layer 2 may be formed by depositing an oxide layer and then photolithography and opening. Specifically, silicon dioxide can be deposited on the surface of the N-type epitaxial layer far away from the N-type substrate, and the deposition thickness is 0.1-10 mu m. And etching a polygonal vertical groove region on the surface of the N-type epitaxial layer by photoetching, wherein the etching depth is 1-1000nm.
In step S230, second conductivity type metal regions 4 are formed on the bottom surface of each vertical trench region and the mesa region 5, respectively.
Referring to fig. 4, fig. 4 is a schematic cross-sectional view of an ion implantation process according to an embodiment of the application. In one embodiment, the second conductivity type may be P-type. The silicon dioxide can be deposited again on the basis of one-time etching to obtain the vertical groove region, and the bottom surface of the vertical groove region and partial regions of the platform region 5 are exposed through photoetching and open holes, so that the positioning during ion implantation is facilitated. Can be used forAl particles are injected into the exposed open hole area with the injection dosage of 1e12-1e16cm -2 The implantation energy is 400-1500KeV, the junction depth is 0.6-1.8 μm, and the doping concentration is 1e16-5e18cm -3 P+ regions (i.e., second conductivity type metal regions 4) are formed in the vertical trench regions and the mesa regions 5, respectively.
And step S240, etching the side wall of the vertical groove region to obtain a polygonal micro groove, wherein the side wall of the polygonal micro groove is an inclined plane.
In one embodiment, the step of etching the sidewall of the vertical trench region to obtain the polygonal micro-trench includes: depositing silicon dioxide with the thickness of 0.1-10 mu m on one side of the first conductive type epitaxial layer 2 facing away from the first conductive type substrate, and forming a vertical groove region by one-time etching; and performing secondary etching in the vertical groove region to form a polygonal micro groove 3 with the side wall being an inclined plane.
Referring to fig. 5, fig. 5 is a schematic cross-sectional view of the second etching process according to an embodiment of the application. After the etching of the vertical trench region is completed, the second conductivity type metal region 4 is manufactured by ion implantation, and then the second etching is performed, so that the sidewall of the trench region forms an inclined plane of 1-90 degrees. Specifically, each side of the polygonal vertical groove region can be etched respectively in sequence, and taking a hexagonal micro groove as an example, after etching is finished in one direction, the rotation angle continues to etch until the etching is finished in six sides, and a sacrificial oxide layer is deposited by 1-500nm to prevent the device performance from being influenced by contact with air in the next production process. The sacrificial oxide layer may be removed after the next manufacturing process to obtain the structure shown in fig. 5.
In one embodiment, after ion implantation is completed, a carbon film may be deposited on the surface, the thickness of the carbon film may be controlled to be between 0.1 μm and 2 μm, an annealing operation may be performed at a temperature of 1000 ℃ to 2000 ℃ for 0.1 to 1 hour, and after annealing is completed, the carbon film may be removed to obtain a cross-sectional structure as shown in fig. 5.
In step S250, a first metal layer is formed to cover the polygonal micro-groove 3 and the second conductive type metal region 4 to form schottky contact at the abutting region of the sidewall of the polygonal micro-groove 3 and the mesa region 5.
Referring to fig. 6, fig. 6 is a schematic cross-sectional view of a first metal layer and a second metal layer deposited according to an embodiment of the application. In an embodiment, a first metal layer may be deposited on a side surface of the first conductive type epitaxial layer 2 facing away from the first conductive type substrate 1, and the polygonal micro-groove 3 and the second conductive type metal region 4 of the mesa region 5 on the surface of the first conductive type epitaxial layer 2 may be covered by the first metal layer. Specifically, nickel or aluminum may be deposited on the surface of the N-type epitaxial layer as a first metal layer to a thickness of 1-10 μm, and after annealing, the first metal layer forms ohmic contact with each of the second conductivity type metal regions 4. Meanwhile, between the second conductive type metal region 4 at the bottom of the polygonal micro-groove 3 and the second conductive type metal region 4 of the adjacent platform region 5, the first metal layer and the first conductive type epitaxial layer 2 form schottky contact, and an MPS structure can be formed based on the mixed structure arrangement of ohmic contact and schottky contact, so that corresponding conductivity modulation can be performed if instantaneous high current is encountered, and device failure is prevented. Meanwhile, the side wall of the polygonal micro-groove 3 structure is an inclined plane, so that schottky contact is formed in the side wall area, the schottky area can be increased, and the front current carrying capacity is enhanced. In addition, by adjusting the ion implantation of the bottom of the polygonal micro-groove 3 and the mesa region 5, reverse leakage can be reduced. The Schottky contact area has smaller occupation ratio in the layout, and if the etching is incomplete, the reverse leakage performance of the device is not affected, so that the robustness is higher. The angle of the side wall inclined plane determines the magnitude of the current density, and the high current density conduction can be realized by adjusting the angle of the side wall inclined plane.
In step S260, a second metal layer 6 is fabricated on the side of the first conductivity type substrate 1 facing away from the first conductivity type epitaxial layer 2.
In an embodiment, the second metal layer 6 may form an ohmic contact with the first conductive type substrate 1, and an external circuit is accessed through the first metal layer and the second metal layer 6.
Referring to fig. 7, fig. 7 is a schematic top view of an overall layout according to an embodiment of the application. A schematic cross-sectional structure of the schottky diode shown in fig. 1 can be obtained by cutting along a black straight line in fig. 7. The side wall of the polygonal micro groove 3 is etched into an inclined plane, so that the current density can be greatly increased, the conduction voltage drop of unit chip area is further reduced, the chip size is smaller, the wafer area utilization rate is higher, and the production cost of the whole device can be reduced; by adjusting the ion implantation of the bottom of the polygonal micro-groove 3 and the platform region 5, the reverse leakage current can be effectively reduced, and even if the etching result of the polygonal micro-groove 3 is not ideal, the high current density conduction can be realized; ohmic contact is formed in the second conductive type metal regions 4, ohmic contact is formed between the second conductive type metal regions 4, an MPS structure can be obtained, the surge resistance is stronger, and corresponding conductivity modulation can be performed if instantaneous large current is encountered, so that the device failure is prevented.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. A schottky diode layout structure comprising:
a first conductivity type substrate;
a first conductive type epitaxial layer disposed on one side of the first conductive type substrate;
the polygonal micro-grooves are arranged on one side, away from the first conductive type substrate, of the first conductive type epitaxial layer, the side walls of the polygonal micro-grooves are inclined planes, a platform area is reserved between adjacent edges of two adjacent polygonal micro-grooves, and a second conductive type metal area is arranged on the bottom surface of each polygonal micro-groove and the platform area;
a first metal layer covering the polygonal micro-groove and the second conductive type metal region to form schottky contact at a butt joint region of a side wall of the polygonal micro-groove and the mesa region;
the second metal layer is arranged on one side of the first conductive type substrate, which is away from the first conductive type epitaxial layer.
2. The schottky diode layout structure of claim 1 wherein said polygonal micro-trench has a hexagonal open cross-section.
3. The schottky diode layout structure of claim 1 wherein the location of the abutment of the sidewalls of the polygonal micro-trench with the mesa region is a cambered surface structure.
4. The schottky diode layout structure of claim 1 wherein said polygonal micro-grooves have a depth of 1-1000nm.
5. The schottky diode layout structure of claim 1 wherein said first conductivity type substrate has a doping concentration of 1e19-1e21cm -3 The thickness is 100-500 mu m; the doping concentration of the first conductive type epitaxial layer is 5e15-2e16, and the thickness of the first conductive type epitaxial layer is 5-30 mu m; the junction depth of the second conductive type metal region is 0.6-1.8 μm, and the doping concentration is 1e16-5e18cm -3 。
6. The manufacturing method of the Schottky diode layout structure is characterized by comprising the following steps of:
providing a first conductive type substrate;
growing a first conductivity type epitaxial layer on the first conductivity type substrate;
manufacturing a plurality of vertical groove areas on one side of the first conductive type epitaxial layer, which is away from the first conductive type substrate, wherein a platform area is reserved between adjacent sides of two adjacent vertical groove areas;
respectively manufacturing a second conductive type metal region on the bottom surface of each vertical groove region and the platform region;
etching the side wall of the vertical groove region to obtain a polygonal micro groove, wherein the side wall of the polygonal micro groove is an inclined plane;
manufacturing a first metal layer, wherein the first metal layer covers the polygonal micro-groove and the second conductive type metal region so as to form Schottky contact at a butt joint region of the side wall of the polygonal micro-groove and the platform region;
and manufacturing a second metal layer on one side of the first conductive type substrate away from the first conductive type epitaxial layer.
7. The method of fabricating a schottky diode layout structure according to claim 6, wherein the step of etching the sidewall of the vertical trench region to obtain a polygonal micro-trench comprises:
depositing silicon dioxide with the thickness of 0.1-10 mu m on one side of the first conductive type epitaxial layer away from the first conductive type substrate, and forming a vertical groove region by one-time etching;
and performing secondary etching on the vertical groove region to form the polygonal micro groove with the inclined side wall.
8. The method of fabricating a schottky diode layout structure as defined in claim 6, wherein the step of fabricating a second conductivity type metal region on the bottom surface of each of said vertical trench regions and said mesa region, respectively, comprises:
depositing silicon dioxide on the surface of the vertical groove area;
forming openings in the region where the vertical groove region is located and the platform region through photoetching;
and implanting aluminum ions at the position of the opening by means of ion implantation to form the metal region of the second conductivity type.
9. The method of fabricating a schottky diode layout structure as defined in claim 6, wherein the step of fabricating the first metal layer comprises:
and depositing nickel or aluminum with the thickness of 1-10 mu m on one side of the first conductive type epitaxial layer, which is away from the first conductive type substrate, and annealing to form Schottky contact between the side wall of the polygonal micro-groove and the platform region, so as to obtain the first metal layer.
10. The method for fabricating a schottky diode layout structure according to claim 8, wherein the implantation dose of aluminum ions is 1e12-1e16cm -2 The implantation energy is 400-1500KeV.
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