CN116779446A - Shielded gate MOS device and manufacturing method thereof - Google Patents

Shielded gate MOS device and manufacturing method thereof Download PDF

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Publication number
CN116779446A
CN116779446A CN202310946019.4A CN202310946019A CN116779446A CN 116779446 A CN116779446 A CN 116779446A CN 202310946019 A CN202310946019 A CN 202310946019A CN 116779446 A CN116779446 A CN 116779446A
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type
gate
substrate
shielding
implantation
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支立明
陈洪密
刘沙沙
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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Abstract

The application provides a shielding gate MOS device and a manufacturing method thereof, comprising the following steps: providing a substrate, wherein a plurality of grooves are formed in the substrate; performing first type ion inclined implantation in the substrate at two sides of the groove, and forming a first type implantation region in the substrate between adjacent grooves; performing second type ion inclined implantation on the substrates at the two sides of the grooves, and forming second type implantation areas in the substrate between the adjacent grooves, wherein the areas are close to the grooves at the two sides; and forming a shielding gate and a polysilicon gate which are spaced from bottom to top in the groove. According to the application, through performing twice ion tilt implantation on the substrates at two sides of the groove, a super junction structure of N column-P column-N column or P column-N column-P column is formed in the substrate, the PN column structure can further reduce the resistivity of the drift layer, and the super junction structure introduces a novel depletion region so as to expand the area of the epitaxial layer of the shielding gate MOS device which participates in conducting the substrate, and can use epitaxy with higher concentration so as to reduce the conducting resistance.

Description

Shielded gate MOS device and manufacturing method thereof
Technical Field
The application belongs to the technical field of integrated circuit manufacturing, and particularly relates to a shielding grid MOS device and a manufacturing method thereof.
Background
Split gate (Shielded Gate Trench, SGT, also known as shielded gate) field effect transistor (MOSFET) devices are more advantageous for flexible applications of semiconductor integrated circuits than conventional MOS devices due to their lower gate-to-drain capacitance, lower on-resistance, and higher withstand voltage performance. Specifically, in the split gate field effect transistor, the shielding gate is arranged below the polysilicon gate, so that the gate-drain capacitance can be greatly reduced, the electric field of the device is optimized, the breakdown voltage is improved, the drift region of the split gate field effect transistor also has higher impurity carrier concentration, and the on-resistance can be correspondingly reduced.
The SGT-MOSFET device has the advantages of small parasitic capacitance, high switching speed, low power loss and the like, and is a main stream power device in the current middle-low voltage application field. Compared with the common VD (Vertical Diffused, vertical diffusion) -MOSFET is introduced into the shielding grid, the shielding grid is used for assisting in depletion of carriers in the drift region, and the voltage withstand increasing effect is achieved. Currently, it becomes very difficult to reduce on-resistance by reducing the resistivity of the drift layer, subject to process conditions and silicon material performance limitations.
Disclosure of Invention
The application aims to provide a shielded gate MOS device and a manufacturing method thereof, wherein the method comprises the steps of sequentially executing twice ion inclined injection to substrates at two sides of a groove, and forming a super junction structure of a second type injection region, a first type injection region and a second type injection region in the substrate; the PN column structure can further reduce the resistivity of the drift layer, and the super junction structure introduces a novel depletion region so as to enlarge the area of an epitaxial layer on a substrate where an SGT device participates in conduction, and can use epitaxy with higher concentration so as to reduce the on resistance.
The application provides a manufacturing method of a shielding gate MOS device, which comprises the following steps:
providing a substrate, wherein a plurality of grooves are formed in the substrate;
performing first type ion inclined implantation in the substrates at two sides of the groove, and forming a first type implantation region in the substrate between adjacent grooves;
performing second-type ion inclined implantation on the substrates at two sides of the grooves, and forming second-type implantation areas in the areas, close to the grooves at two sides, of the substrates between the adjacent grooves; forming a second type injection region, a first type injection region and a super junction structure of the second type injection region in the substrate at two sides of the groove;
and forming a shielding gate and a polysilicon gate which are spaced from bottom to top in the groove.
Further, the first type ion implantation dose is greater than the second type ion implantation dose.
Further, the first type ion tilt implant dose range: 2X 10 19 Atoms/cm 2 ～9×10 21 Atoms/cm 2 。
Further, the second type ion tilt implant dose range: 2X 10 13 Atoms/cm 2 ～8×10 15 Atoms/cm 2 。
Further, the first type of ions are inclined to the implantation angle range: 20-75 degrees; the second type of ion inclined implantation angle range: 20-75 deg.
Further, an isolation layer is formed on the surface of the substrate at two sides of the groove, and the first type ion tilt implantation and the second type ion tilt implantation are respectively performed on the substrate at two sides of the groove by taking the isolation layer as a mask.
Further, forming a shielding gate and a polysilicon gate in the trench at intervals from bottom to top, which specifically comprises:
forming a shielding oxide layer, wherein the shielding oxide layer covers the bottom and the side wall surface of the lower part of the groove, the shielding oxide layer is provided with a first cavity area, and the shielding grid is formed in the first cavity area;
and forming a gate oxide layer, wherein the gate oxide layer covers the surfaces of the shielding gate and the shielding oxide layer and the side wall of the upper part of the groove, the gate oxide layer is provided with a second cavity area, and the polysilicon gate is formed in the second cavity area.
Further, after forming the shielding gate and the polysilicon gate, the method further includes:
implanting first type ions into the substrate at two sides of the groove to form a body region; and forming source regions on both sides of the body region by heavily doping the second type ions.
The application also provides a shielded gate MOS device, comprising:
a substrate in which a plurality of grooves are formed;
a shielding gate and a polysilicon gate which are spaced from bottom to top are formed in the groove;
a second type injection region, a first type injection region and a super junction structure of the second type injection region are formed in the substrate at two sides of the groove;
further, the shielded gate MOS device further includes:
a shielding oxide layer, wherein the shielding oxide layer is positioned in a gap between the shielding grid and the groove;
and the gate oxide layer is positioned between the shielding gate and the polysilicon gate and between the side wall of the polysilicon gate and the side wall of the groove.
Compared with the prior art, the application has the following beneficial effects:
the application provides a shielding gate MOS device and a manufacturing method thereof, comprising the following steps: providing a substrate, wherein a plurality of grooves are formed in the substrate; performing first type ion inclined implantation in the substrate at two sides of the groove, and forming a first type implantation region in the substrate between adjacent grooves; performing second type ion inclined implantation on the substrates at the two sides of the grooves, and forming second type implantation areas in the substrate between the adjacent grooves, wherein the areas are close to the grooves at the two sides; forming a second type injection region, a first type injection region and a super junction structure of the second type injection region in the substrate at two sides of the groove; and forming a shielding gate and a polysilicon gate which are spaced from bottom to top in the groove. Performing twice ion inclined injection on the substrates at two sides of the groove to form a super junction structure of a second type injection region, a first type injection region and a second type injection region in the substrate; the PN column structure can further reduce the resistivity of the drift layer, and the super junction structure introduces a novel depletion region so as to enlarge the area of an epitaxial layer on a shielding gate MOS device participating in conducting a substrate, and can use epitaxy with higher concentration so as to reduce the conducting resistance.
Drawings
Fig. 1 is a schematic flow chart of a manufacturing method of a shielded gate MOS device according to an embodiment of the present application.
Fig. 2 to 5 are schematic views illustrating steps of a method for manufacturing a shielded gate MOS device according to an embodiment of the present application.
Wherein, the reference numerals are as follows:
10-a substrate; 11-isolating layer; 12-first type implant regions; 13-second type implant regions; 14-shielding grids; 15-polysilicon gate; 16-shielding oxide layer; 17-gate oxide; 18-body region; 19-source region; 20-an interlayer dielectric layer; v-grooves; a-a first type ion tilt implantation angle; b-second type ions inclined at the implantation angle.
Detailed Description
The application is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present application will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to scale precisely, but rather are merely intended to facilitate a clear and concise description of embodiments of the present applications.
For ease of description, some embodiments of the application may use spatially relative terms such as "above" …, "" below "…," "top," "below," and the like to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like, herein below, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances.
The embodiment of the application provides a manufacturing method of a shielded gate MOS device, as shown in fig. 1, comprising the following steps:
step S1, providing a substrate, wherein a plurality of grooves are formed in the substrate;
s2, performing first type ion inclined implantation on the substrates at two sides of the groove, and forming a first type implantation region in the substrate between adjacent grooves;
s3, performing second-type ion inclined implantation on the substrates at two sides of the grooves, and forming second-type implantation areas in the areas, close to the grooves at two sides, of the substrates between the adjacent grooves; forming a second type injection region, a first type injection region and a super junction structure of the second type injection region in the substrate at two sides of the groove;
and S4, forming a shielding gate and a polysilicon gate in the groove at intervals from bottom to top.
The following describes in detail the steps of the method for manufacturing a shielded gate MOS device according to an embodiment of the present application with reference to fig. 2 to 5.
In step S1, as shown in fig. 2, a substrate 10 is provided, and a plurality of trenches V are formed in the substrate 10. Specifically, an isolation layer 11 is formed on the surface of the substrate, and the isolation layer and the substrate are etched to form a plurality of (2 or more) trenches V. The substrate 10 may be any suitable substrate material known to those skilled in the art, and may be a bare wafer, or a wafer processed through a series of processes, for example, a Shallow Trench Isolation (STI) may be formed therein. Illustratively, the substrate 10 includes, for example, a base and an epitaxial layer on the base surface, with the trenches V distributed in the epitaxial layer.
In step S2, as shown in fig. 3, a first type ion tilt implantation is performed on the substrate 10 on both sides of the trenches V, and first type implantation regions 12 are formed in the substrate 10 between adjacent trenches V.
It is also understood that the first is performed in the substrate 10 between adjacent trenches VThe type ions are implanted obliquely to form the first type implanted region 12. The dopant is introduced by a tilted implantation, during which the spacer 11 is used as a mask. The first type is illustratively a P-type. The first type of ion tilt implantation may include boron dopants and may be used with ion doses ranging from 2 x 10 19 Atoms/cm 2 To 9X 10 21 Atoms/cm 2 Is used for the implantation of (a). In one embodiment, the tilt implant is performed using an ion implantation device operating at energies ranging from 5keV to 60 keV. The tilt implantation may be performed at a temperature ranging from 50 c to 800 c. In another embodiment, the tilt implant is performed using a temperature ranging from 100 ℃ to 400 ℃. The first type ion inclined implantation angle A is a plane P parallel to the proceeding direction of the dopant 1 And a plane P perpendicular to the surface of the substrate 10 2 An acute angle formed when intersecting. The first type ion tilt implantation angle a ranges, for example, from 20 ° to 75 °.
In step S3, as shown in fig. 4, a second type ion tilt implantation is performed on the substrate on both sides of the trench V, and a second type implantation region 13 is formed in the substrate 10 between adjacent trenches V in a region near the trenches V on both sides. Forming a second type injection region 13, a first type injection region 12 and a super junction structure of the second type injection region 13 in the substrate at two sides of the groove V; the PN column structure can further reduce the resistivity of the drift layer, and the super junction structure introduces a novel depletion region so as to enlarge the area of an epitaxial layer on a shielding gate MOS device participating in conducting a substrate, and can use epitaxy with higher concentration so as to reduce the conducting resistance. The second type is illustratively an N-type, and the dopant is comprised of arsenic, phosphorus, germanium, xenon, argon, krypton, or combinations thereof. The second type of ion tilt implantation may employ ion doses ranging from 2 x 10 13 Atoms/cm 2 Up to 8X 10 15 Atoms/cm 2 Is used for the implantation of (a). The second type of ion inclined implantation angle B ranges, for example, from 20 ° to 75 °.
The first type ion implantation dose is greater than the second type ion implantation dose. Specifically, the first type implantation region 12 is formed in the substrate 10 between the adjacent trenches V, the second type implantation region 13 is located in the region, close to the two side trenches V, of the substrate 10 between the adjacent trenches by controlling the inclination implantation angle and the dose of the second type ions, the second type ions are not implanted in the middle region of the substrate 10 between the adjacent trenches, and the middle region of the substrate 10 between the adjacent trenches constitutes a first type column, such as a P column, for example, for the first type implantation region 12; the two sides of the first type column 12 constitute a second type column 13, for example an N column. After the second type ion tilt implantation, the isolation layer 11 is removed. The first type ion implantation and the second type ion implantation are both performed by using the isolation layer 11 as a mask, so that triangular non-implanted regions are formed on the upper portions of the substrates on both sides of the trench.
In step S4, as shown in fig. 5, a shielding gate 14 and a polysilicon gate 15 are formed in the trench V at intervals from bottom to top. Specifically, a shielding oxide layer 16 is formed, the shielding oxide layer 16 covers the bottom and the side wall surfaces of the trench V, the shielding oxide layer 16 has a first cavity region, and a shielding gate film layer is filled in the first cavity region. The shield oxide layer 16 may be formed by a suitable film forming process such as a thermal oxidation process or a Chemical Vapor Deposition (CVD) process or a process of thermal oxidation followed by chemical vapor deposition. The shield oxide layer 16 may be a single layer film or a stacked structure of multiple layers, depending on whether it is formed by a single film forming process or multiple film forming processes, is formed on the side walls and bottom surfaces of the trench and the surface of the substrate 10 at the periphery of the trench V. The material of the shielding oxide layer 16 may be a stacked material of oxide and nitride, oxide, nitride, or other suitable dielectric material.
The material of the shielding gate film layer may be a conductive material, for example, a polysilicon material or other suitable conductive material. The shielding gate film layer can be formed by polysilicon deposition and in-situ doping process, and N-type ion doped or P-type ion doped polysilicon is filled in the trench V, wherein the polysilicon is filled in the trench V, and the surface of the shielding oxide layer at the periphery of the trench V is also covered with polysilicon, wherein the N-type ion is at least one of phosphorus, arsenic, antimony, germanium and the like, and the P-type ion is boron or indium and the like. Removing a part of the thickness of the shielding gate film layer and removing a shielding oxide layer surrounding the removed part of the shielding gate film layer; the remaining thickness of the shield gate film constitutes the shield gate 14. In a specific implementation, the same thickness of the shielding gate film layer and the shielding oxide layer 16 may be removed, for example, by using the same etching process. Specifically, a dry etching manner can be adopted to remove a part of the thickness of the shielding gate film layer and the shielding oxide layer from top to bottom.
A gate oxide layer 17 is formed, the gate oxide layer 17 covers the surfaces of the shield gate 14 and the remaining shield oxide layer 16 and the sidewalls of the trench V above the shield gate 14, and the gate oxide layer 17 has a second cavity region in which the polysilicon gate 15 is formed. Polysilicon gate 15 may be formed by a suitable deposition process such as a chemical vapor deposition process to deposit polysilicon (polysilicon that may be doped with N-type ions or P-type ions) in the second cavity region of gate oxide 17. The deposited polysilicon is then top planarized by a chemical mechanical polishing process. Specifically, the material of the gate oxide layer 17 may be consistent with the material of the shield oxide layer 16 to improve the insulation effect. The material of the gate oxide 17 may also be inconsistent with the material of the shield oxide 16. The material of the shield oxide layer 16 is an oxide, for example, silicon oxide. By oxidizing the material of the substrate 10 to form the shielding oxide layer 16 by an oxidation process, the thickness of the shielding oxide layer 16 can be effectively controlled, a better insulating quality can be obtained, and the gate oxide layer 17 can be obtained in the same way.
The method for manufacturing the shielding gate MOS device can further comprise the following steps: implanting first type ions into the substrate on both sides of the trench to form a body region 18, the body region 18 being implanted with P-type ions, for example; and source regions 19 are formed on either side of body region 18 by heavily doping ions of a second type, such as implanting N-type ions, to form N-type heavily doped (N +) source regions 19. Source region 19 overlies a portion of body region 18.
Next, an interlayer dielectric layer 20 is formed over the substrate 10, and the interlayer dielectric layer 20 may be deposited by a chemical vapor deposition or the like process. The interlayer dielectric layer 20 and the like are etched by a contact hole process to form a plurality of contact holes penetrating the interlayer dielectric layer 20. And filling conductive materials in each contact hole to form corresponding contact plugs so as to lead out the electricity. For example, a contact hole may be formed above the source region 19, leading out the source region 19.
Illustratively, the source of the shielded gate MOS device is pulled through a plug in the contact hole above the source region 19, and the drain is pulled from the surface (i.e., the back) of the substrate 10 on the side away from the polysilicon gate 15, with the polysilicon gate 15 acting as the gate. The shielded gate MOS device includes a cell region and a termination region. In fig. 5, the shielding gate 14 and the polysilicon gate 15, which are spaced from bottom to top in the trench V, and the N pillar-P pillar-N pillar superjunction structures, for example, in the substrate on both sides of the trench V are located in the cell region of the shielding gate MOS device; the extraction structure of the polysilicon gate 15 is not shown in fig. 5, and the polysilicon gate 15 serves as a gate electrode that can be extracted through a contact hole of a termination region (not shown).
The embodiment also provides a shielded gate MOS device, as shown in fig. 5, including:
a substrate 10, in which a plurality of trenches V are formed in the substrate 10;
a shielding gate 14 and a polysilicon gate 15 which are spaced from bottom to top are formed in the groove V;
a super junction structure of the second type implant region 13, the first type implant region 12 and the second type implant region 13 is formed in the substrate on both sides of the trench V.
The shielded gate MOS device further includes: shield oxide layer 16, shield oxide layer 16 being located in the gap between shield gate 14 and trench V. Gate oxide layer 17 the gate oxide layer 17 is located between the shield gate 14 and the polysilicon gate 15 and between the sidewalls of the polysilicon gate 15 and the sidewalls of the trench V. The first type column is P-type, and the second type column is N-type; alternatively, the first type of column is N-type and the second type of column is P-type.
In summary, the present application provides a shielded gate MOS device and a method for manufacturing the same, including: providing a substrate, wherein a plurality of grooves are formed in the substrate; performing first type ion inclined implantation in the substrate at two sides of the groove, and forming a first type implantation region in the substrate between adjacent grooves; performing second type ion inclined implantation on the substrates at the two sides of the grooves, and forming second type implantation areas in the substrate between the adjacent grooves, wherein the areas are close to the grooves at the two sides; forming a second type injection region, a first type injection region and a super junction structure of the second type injection region in the substrate at two sides of the groove; and forming a shielding gate and a polysilicon gate which are spaced from bottom to top in the groove. Performing twice ion inclined injection on the substrates at two sides of the groove to form a super junction structure of a second type injection region, a first type injection region and a second type injection region in the substrate; the PN column structure can further reduce the resistivity of the drift layer, and the super junction structure introduces a novel depletion region so as to enlarge the area of the SGT device participating in conducting the epitaxial layer, and can use epitaxy with higher concentration so as to reduce the on resistance.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the method disclosed in the embodiment, the description is relatively simple since it corresponds to the device disclosed in the embodiment, and the relevant points refer to the description of the method section.
The foregoing description is only illustrative of the preferred embodiments of the present application, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present application using the method and technical content disclosed above without departing from the spirit and scope of the application, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present application fall within the scope of the technical solution of the present application.

Claims (10)

1. A method of manufacturing a shielded gate MOS device, comprising:
providing a substrate, wherein a plurality of grooves are formed in the substrate;
performing first type ion inclined implantation in the substrates at two sides of the groove, and forming a first type implantation region in the substrate between adjacent grooves;
performing second-type ion inclined implantation on the substrates at two sides of the grooves, and forming second-type implantation areas in the areas, close to the grooves at two sides, of the substrates between the adjacent grooves; forming a second type injection region, a first type injection region and a super junction structure of the second type injection region in the substrate at two sides of the groove;
and forming a shielding gate and a polysilicon gate which are spaced from bottom to top in the groove.
2. The method of manufacturing a shielded gate MOS device of claim 1, wherein the first type ion implantation dose is greater than the second type ion implantation dose.
3. The method of manufacturing a shielded gate MOS device of claim 2, wherein the first type of ion tilt implant dose range: 2X 10 19 Atoms/cm 2 ～9×10 21 Atoms/cm 2 。
4. The method of manufacturing a shielded gate MOS device of claim 2, wherein the second type of ion tilt implant dose ranges: 2X 10 13 Atoms/cm 2 ～8×10 15 Atoms/cm 2 。
5. The method of manufacturing a shielded gate MOS device of claim 1, wherein the first type of ions are implanted obliquely through a range of angles: 20-75 degrees; the second type of ion inclined implantation angle range: 20-75 deg.
6. The method of manufacturing a shielded gate MOS device according to any one of claims 1 to 5, wherein an isolation layer is formed on the substrate surfaces on both sides of the trench, and the first type ion tilt implantation and the second type ion tilt implantation are performed on the substrate on both sides of the trench with the isolation layer as a mask, respectively.
7. The method for manufacturing the shielded gate MOS device according to any one of claims 1 to 5, wherein the forming of the shielded gate and the polysilicon gate in the trench at intervals from bottom to top, comprises:
forming a shielding oxide layer, wherein the shielding oxide layer covers the bottom and the side wall surface of the lower part of the groove, the shielding oxide layer is provided with a first cavity area, and the shielding grid is formed in the first cavity area;
and forming a gate oxide layer, wherein the gate oxide layer covers the surfaces of the shielding gate and the shielding oxide layer and the side wall of the upper part of the groove, the gate oxide layer is provided with a second cavity area, and the polysilicon gate is formed in the second cavity area.
8. The method of manufacturing a shielded gate MOS device of claim 7, further comprising, after forming the polysilicon gate:
implanting first type ions into the substrate at two sides of the groove to form a body region; and forming source regions on both sides of the body region by heavily doping the second type ions.
9. A shielded gate MOS device, comprising:
a substrate in which a plurality of grooves are formed;
a shielding gate and a polysilicon gate which are spaced from bottom to top are formed in the groove;
and the substrate at two sides of the groove is provided with a super junction structure of a second type injection region, a first type injection region and a second type injection region.
10. The shielded gate MOS device of claim 9, further comprising:
a shielding oxide layer, wherein the shielding oxide layer is positioned in a gap between the shielding grid and the groove;
and the gate oxide layer is positioned between the shielding gate and the polysilicon gate and between the side wall of the polysilicon gate and the side wall of the groove.
CN202310946019.4A 2023-07-28 2023-07-28 Shielded gate MOS device and manufacturing method thereof Pending CN116779446A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117316992A (en) * 2023-11-29 2023-12-29 深圳基本半导体有限公司 Silicon carbide MOSFET device with double-gate structure and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117316992A (en) * 2023-11-29 2023-12-29 深圳基本半导体有限公司 Silicon carbide MOSFET device with double-gate structure and preparation method thereof

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