CN116778984A - Memory and sense amplifier thereof - Google Patents

Abstract

The invention provides a memory and a sense amplifier device thereof. The sense amplifying device comprises a differential amplifier, a first pre-charging circuit and a control voltage generator. The differential amplifier has a first input terminal and a second input terminal for receiving a data signal and a reference signal, respectively. The first precharge circuit is coupled to the first input terminal. The first pre-charging bed is based on the power voltage, and performs a pre-charging operation on the first input terminal according to the pre-charging start signal and the control voltage. The control voltage generator generates a control voltage according to a power supply voltage, wherein the control voltage is positively correlated with the power supply voltage.

Description

Memory and sense amplifier thereof

Technical Field

The invention relates to a memory and a sense amplifier device thereof.

Background

In the technical field of memories, a precharge circuit is often provided at an input terminal of a sense amplifier to precharge the input terminal of the sense amplifier in advance when a memory cell is read, so that a subsequent sensing operation of a data signal of the memory cell can be accelerated.

In the known art, the precharge circuit is often made to have a fixed precharge time. However, when the power supply voltage received by the sense amplifying device changes, the precharge circuit may boost the voltage at the input terminal of the sense amplifying device to a different extent during the fixed precharge time. For example, when the power supply voltage becomes high, the voltage at the input terminal of the sense amplifying device may be precharged to a relatively high voltage value; in contrast, when the power voltage becomes low, the voltage at the input terminal of the sense amplifying device can be precharged to a relatively low voltage value. The unstable state of the precharge operation can cause the phenomenon of sensing data errors when the memory is applied to power supply voltages of different magnitudes, or cause the reading speed to be different according to the magnitude of the power supply voltages.

Disclosure of Invention

According to an embodiment of the invention, a sense amplifying device includes a differential amplifier, a first pre-charge circuit, and a control voltage generator. The differential amplifier has a first input terminal and a second input terminal for receiving a data signal and a reference signal, respectively. The first precharge circuit is coupled to the first input terminal. The first pre-charging bed is based on the power voltage, and performs a pre-charging operation on the first input terminal according to the pre-charging start signal and the control voltage. The control voltage generator generates a control voltage according to a power supply voltage, wherein the control voltage is positively correlated with the power supply voltage.

According to an embodiment of the invention, the memory includes at least one memory cell and a sense amplifier. The sense amplifier is coupled to the memory cell. The sense amplifying device comprises a differential amplifier, a first pre-charging circuit and a control voltage generator. The differential amplifier has a first input terminal and a second input terminal for receiving a data signal and a reference signal, respectively. The first precharge circuit is coupled to the first input terminal. The first pre-charging bed is based on the power voltage, and performs a pre-charging operation on the first input terminal according to the pre-charging start signal and the control voltage. The control voltage generator generates a control voltage according to a power supply voltage, wherein the control voltage is positively correlated with the power supply voltage.

According to the above, the sense amplifying device of the present invention performs the precharge operation on the input terminals of the differential amplifier by controlling the voltage. The control voltage is positively correlated with the power supply voltage, so that the change of the power supply voltage can be compensated in the precharge operation of the first precharge circuit, and the precharge operation is not affected by the change of the power supply voltage. Thus, the overall action of the memory can be independent of the variation of the supply voltage.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a schematic diagram of a sense amplifier according to an embodiment of the invention;

FIG. 2 is a schematic diagram of an embodiment of a precharge circuit in a sense amplifying device according to an embodiment of the present invention;

FIG. 3 is a waveform diagram of the control voltage generator 200 according to the embodiment of FIG. 2;

FIG. 4 is a schematic diagram of a precharge circuit of a sense amplifier according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a memory according to an embodiment of the invention;

FIG. 6 is a schematic diagram of a memory according to another embodiment of the invention.

Description of the reference numerals

100: a sense amplifying device;

110. 511, 611: a differential amplifier;

120. 400, 512, 6121, 6122: a precharge circuit;

130. 200: controlling a voltage generator;

210: a constant current source;

310: a curve;

410. 420: a precharge sub-circuit;

500. 600: a memory;

513. 613: a data latch;

BL, RBL: a bit line;

CELL, CELLR: a storage unit;

DisC: a discharge control signal;

DL, RBL: a data line;

DO: sensing data;

IN1, IN2: an input end;

MPP0, MNN0, MP0 to MP5, MP01, MP11, MN2 to MN6, MND1, MND2, MPR2 to MPR6, MNR0 to MNR3: a transistor;

PC: a precharge enable signal;

PCSb, PCWb: pre-charging a promoter signal;

sout: outputting a signal;

VCC: a power supply voltage;

vpgp: controlling the voltage;

vra: a reference signal;

VREF, VSS: a reference voltage;

vsa: a data signal;

vthp: a turn-on voltage;

y, vsen, SET, SETN: a signal.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Referring to fig. 1, fig. 1 is a schematic diagram of a sense amplifying device according to an embodiment of the invention. The sense amplifying device 100 includes a differential amplifier 110, a pre-charge circuit 120, and a control voltage generator 130. The differential amplifier 110 has an input terminal IN1 and IN2. The input terminal IN1 of the differential amplifier 110 is coupled to the precharge circuit 120 and receives the data signal. The input IN2 of the differential amplifier 110 receives the reference signal Vra. IN this embodiment, the input terminal IN1 of the differential amplifier 110 can be coupled to a selected memory cell, wherein the selected memory cell is selected to perform a read operation. The selected memory cell can be used to provide the data signal Vsa to the input terminal IN1 of the differential amplifier 110. The precharge circuit 120 performs a precharge operation on the input terminal IN1 of the differential amplifier 110 before the data signal Vsa is supplied to the input terminal IN1 of the differential amplifier 110 during the read operation.

The differential amplifier 110 is used for comparing the magnitude of the data signal Vsa at the input terminal IN1 and the magnitude of the reference signal Vra at the input terminal IN2, and generating the output signal Sout by amplifying the difference between the data signal Vsa and the reference signal Vra.

IN the present embodiment, the precharge circuit 120 may perform the precharge operation on the input terminal IN1 according to the precharge enable signal PC and the control voltage Vpgp based on the power supply voltage VCC. The control voltage Vpgp is provided by the control voltage generator 130. Wherein, the control voltage generator 130 generates the control voltage Vpgp according to the power supply voltage VCC. In one embodiment, the control voltage Vpgp is positively correlated to the supply voltage VCC.

Further, the control voltage generator 130 may adjust the voltage value of the control voltage Vpgp according to the voltage value of the power supply voltage VCC. When the power supply voltage VCC is less than or equal to a reference value, the voltage value of the control voltage Vpgp may be maintained at a low voltage equal to approximately 0 volts. When the power supply voltage VCC is greater than the above-mentioned reference value, the control voltage Vpgp may be linearly increased in proportion to the power supply voltage VCC. In the present embodiment, when the power supply voltage VCC is greater than the above-described reference value, the amount of change in the control voltage Vpgp and the amount of change in the power supply voltage VCC may be equal.

As can be seen from the above description, when the power supply voltage VCC varies, the precharge circuit 120 can maintain the precharge capability of the input terminal IN1 according to the control voltage Vpgp which dynamically varies according to the variation of the power supply voltage VCC. IN this way, the precharge operation on the input terminal IN1 of the differential amplifier 110 is constant regardless of the variation of the power supply voltage VCC. The voltage at the input terminal IN1 of the differential amplifier 110 does not have a phenomenon of insufficient pre-charge or over-charge due to the variation of the power supply voltage VCC, so that the possibility of generating the erroneous output signal Sout of the differential amplifier 110 is reduced, and the data sensing speed of the sense amplifier 100 can be effectively maintained.

Referring to fig. 2, fig. 2 is a schematic diagram of an embodiment of a control voltage generator in a sense amplifying device according to an embodiment of the invention. The control voltage generator 200 includes a transistor MPP0 and a constant current source 210. A first terminal of the transistor MPP0 receives a supply voltage VCC; the control end of the transistor MPP0 receives the reference voltage VSS; the second terminal of the transistor MPP0 is coupled to the constant current source 210 and generates the control voltage Vpgp. The constant current source 210 is coupled between the second terminal of the transistor MPP0 and a reference ground, wherein the reference ground is used for receiving the reference voltage VSS. In this embodiment, the reference voltage VSS may be a ground voltage of 0 volts.

In the present embodiment, the constant current source 210 is constructed by a transistor MNN 0. The first terminal of the transistor MNN0 is coupled to the second terminal of the transistor MPP 0; the control terminal of the transistor MNN0 receives the reference voltage VREF; the second terminal of the transistor MNN0 receives the reference voltage VSS. Wherein, the reference voltage VREF may be greater than the reference voltage VSS. In this embodiment, the reference voltage VREF may be, for example, 1.1 v to 1.2 v.

The constant current source 210 is configured to draw a fixed current from the second terminal of the transistor MPP0 to the second terminal of the transistor MNN 0. When the power supply voltage VCC is not greater than the turn-on voltage (equivalent to the reference value) of the transistor MPP0, the transistor MPP0 is not turned on, and the control voltage Vpgp on the second terminal of the transistor MPP0 can be a very low voltage (e.g., 0 volt) by the pull-down action of the constant current source 210. The transistor MPP0 may be turned on when the power supply voltage VCC is greater than the turn-on voltage of the transistor MPP 0. At this time, a constant difference between the control voltage Vpgp and the power supply voltage VCC at the second terminal of the transistor MPP0 may be maintained.

Reference is now made to fig. 2 and 3 in synchronization, wherein fig. 3 is a waveform diagram illustrating an embodiment of the control voltage generator 200 according to the embodiment of fig. 2. Wherein the control voltage Vpgp is substantially equal to 0 volts when the supply voltage VCC is not greater than the turn-on voltage Vthp of the transistor MPP 0. When the power supply voltage VCC is greater than the turn-on voltage Vthp of the transistor MPP0, the control voltage Vpgp may linearly rise as the power supply voltage VCC rises. The slope of the variation curve 310 of the control voltage Vpgp and the power supply voltage VCC may be equal to 1.

Referring to fig. 4, fig. 4 is a schematic diagram of an embodiment of a precharge circuit of a sense amplifying device according to an embodiment of the invention. Precharge circuit 400 includes precharge sub-circuits 410 and 420. Precharge sub-circuit 410 includes transistors MP0 and MP01. The precharge sub-circuit 420 includes transistors MP1 and MP11. In the present embodiment, the first terminal of the transistor MP0 receives the power supply voltage VCC; the second terminal of the transistor MP0 is coupled to the first terminal of the transistor MP 01; the control terminal of the transistor MP0 receives the precharge promoter signal PCSb. The control terminal of the transistor MP01 receives the control voltage Vpgp; the second terminal of the transistor MP01 is coupled to the input terminal IN1 of the differential amplifier.

The first terminal of the transistor MP1 receives a power supply voltage VCC; the second terminal of the transistor MP1 is coupled to the first terminal of the transistor MP 11; the control terminal of the transistor MP1 receives the precharge promoter signal PCWb. The control terminal of the transistor MP11 receives the control voltage Vpgp; the second terminal of the transistor MP11 is coupled to the input terminal IN1 of the differential amplifier.

IN the present embodiment, the precharge sub-circuit 410 and the precharge sub-circuit 420 can respectively provide different driving capabilities to pull up the input terminal IN1 to the power supply voltage VCC for performing the precharge operation. The driving capability provided by the pre-charge sub-circuit 410 may be greater than the driving capability provided by the pre-charge sub-circuit 420.

When the precharge sub-circuit 410 performs the precharge operation, the transistor MP0 may be turned on according to the precharge promoter signal PCSb. Regardless of the variation of the power supply voltage VCC, when the power supply voltage VCC is greater than the reference value, the difference between the power supply voltage VCC and the control voltage Vpgp can be maintained to be constant based on the control voltage Vpgp varying with the variation of the power supply voltage VCC. Thus, the driving capability that the precharge sub-circuit 410 may provide is fixed.

Similarly, when the precharge sub-circuit 420 performs a precharge operation, the transistor MP1 may be turned on according to the precharge promoter signal PCWb. Regardless of the variation of the power supply voltage VCC, when the power supply voltage VCC is greater than the reference value, the difference between the power supply voltage VCC and the control voltage Vpgp can be maintained to be constant based on the control voltage Vpgp varying with the variation of the power supply voltage VCC. Thus, the driving capability that the precharge sub-circuit 420 may provide is also fixed.

Incidentally, in the present embodiment, the precharge sub-circuits 410 and 420 may perform the precharge operation simultaneously, or may perform the precharge operation in a time-sharing manner, without being limited thereto. In addition, when the power supply voltage VCC is lower than the above reference value, the sense amplifying device of the embodiment of the present invention is inactive.

Referring to fig. 5, fig. 5 is a schematic diagram of a memory according to an embodiment of the invention. The memory 500 comprises one or more memory CELLs CELL and a sense amplifying means 510. The sense amplifying device 510 includes a differential amplifier 511, a precharge circuit 512, and a data latch 513. The memory CELL may be a selected memory CELL, and the bit line BL is coupled to the data line DL through a switch configured by the transistor MN2, and is coupled to the input terminal IN1 of the differential amplifier 511 through a switch configured by the transistor MN 3. When the transistors MN2 and MN3 are turned on according to the signals Y and Vsen, respectively, the memory CELL provides the data signal Vsa to the input terminal IN1 of the differential amplifier 511 via the bit line BL and the data line DL. The memory CELL is controlled by a word line signal WL.

The precharge circuit 512 includes transistors MP0, MP1, MP01, and MP11. Transistors MP0, MP01 constitute a precharge sub-circuit, and transistors MP1, MP11 constitute another precharge sub-circuit. The transistors MP0 and MP01 are controlled by the precharge promoter signal PCSb and the control voltage Vpgp, respectively, and the transistors MP1 and MP11 are controlled by the precharge promoter signal PCWb and the control voltage Vpgp, respectively, and perform the precharge operation on the input terminal IN1 based on the power supply voltage VCC.

The details of the operation of the pre-charging circuit 512 are the same as those of the pre-charging circuit 400 in the embodiment of fig. 4, and are not repeated here. Like the precharge circuit 400, the precharge circuit 512 can perform the precharge operation for the input terminal IN1 according to the fixed driving capability independently of the variation of the power supply voltage VCC. IN this way, the voltage value of the voltage at the input terminal IN1 is raised during the precharge operation can be maintained.

IN addition, one end of the transistor MND is coupled to the input terminal IN1, and the other end of the transistor MND is coupled to the reference voltage VSS. The transistor MND is turned on according to the discharge control signal DisC to perform a discharge operation on the input terminal IN1.

The differential amplifier 511 includes transistors MP3, MP2, MN4, MPR2, and MNR3. The transistors MN4 and MNR3 form a differential input pair, and the transistors MP2 and MPR2 are coupled as an active load, and the transistor MP3 can form a current source.

The other input IN2 of the differential amplifier 511 receives the reference signal Vra. The differential amplifier 511 amplifies the difference between the reference signal Vra and the data signal Vsa to generate the output signal Sout.

In this embodiment, the sense amplifying device 510 further includes a data latch 513. The data latch 513 includes transistors MP4, MP5, MN6 and inverters IV1, IV2. The transistors MP4, MP5, MN5 and MN6 are serially connected between the power voltage VCC and the reference voltage VSS. The transistor MP4 is controlled by the signal SETN, the transistor MP5 and the transistor MN5 are commonly controlled by the input signal Sout, and the transistor MN6 is controlled by the signal SET. Wherein signals SET and SETN are inverted.

When the transistors MP4 and MN6 are turned on, the data latch 513 can transmit the output signal Sout to the latch composed of the inverters IV1 and IV2 through the transistor MP5 and the transistor MN5 to obtain the sensing data DO.

Based on the variation of the power supply voltage VCC, the precharge circuit 512 provides a constant precharge driving capability to perform a precharge operation on the input terminal IN1 of the differential amplifier. IN this way, the memory CELL can provide the correct data signal Vsa to the input terminal IN1, and the memory 500 can provide the correct sensing data DO even under the condition that the power voltage VCC varies, and effectively maintain the data sensing rate of the sense amplifying device 510.

It should be noted that, in the present embodiment, the circuit structures of the differential amplifier 511 and the data latch 513 are merely illustrative examples. In other embodiments of the present invention, the differential amplifying circuit and the data latch circuit, which are well known to those skilled in the art, can be applied to the present invention without specific limitation.

In addition, the memory CELL in the embodiment of the present invention may be a flash memory CELL, or any other memory CELL, without any fixed limitation.

Referring to fig. 6, fig. 6 is a schematic diagram of a memory according to another embodiment of the invention. The memory 600 includes one or more memory CELLs CELL, a sense amplifying device 610, and a reference memory CELL CELLR. The sense amplifying device 610 includes a differential amplifier 611, a precharge circuit 6121, a data latch 613, and a precharge circuit 6122. The bit line BL of the memory CELL is coupled to the data line DL through the switch of the transistor MN2 and is coupled to the input IN1 of the differential amplifier 611 through the switch of the transistor MN 3. When the transistors MN2 and MN3 are turned on according to the signals Y and Vsen, respectively, the memory CELL provides the data signal Vsa to the input terminal IN1 of the differential amplifier 611 via the bit line BL and the data line DL.

The bit line RBL of the reference cell CELR is coupled to the reference data line RDL through a switch constructed by the transistor MNR0, and is coupled to the input IN2 of the differential amplifier 611 through a switch constructed by the transistor MNR 1. When the transistors MNR0 and MNR1 are turned on according to the power voltage VCC and the signal Vsen, the reference cell CELLR provides the reference signal Vra to the input terminal IN2 of the differential amplifier 611 through the bit line RBL and the reference data line RDL.

In the present embodiment, the differential amplifier 611, the precharge circuit 6121 and the data latch 613 in the sense amplifying device 610 have the same circuit structure and the same circuit operation as the differential amplifier 511, the precharge circuit 512 and the data latch 513 in the embodiment of fig. 5, and are not repeated here. Unlike the previous embodiment, the sense amplifier 610 further includes a precharge circuit 6122 coupled to the input IN2 of the differential amplifier 611. The precharge circuit 6122 includes transistors MPR3, MPR4, MPR5, and MPR6. Transistors MPR3, MNR4 constitute a precharge sub-circuit, and transistors MPR5, MPR6 constitute another precharge sub-circuit. The transistors MPR3 and MPR4 are controlled by the precharge promoter signal PCWb and the control voltage Vpgp, respectively, and the transistors MPR5 and MPR6 are controlled by the precharge promoter signal PCSb and the control voltage Vpgp, respectively, and perform the precharge operation on the input terminal IN2 based on the power supply voltage VCC.

IN the data reading operation for the memory CELL, the precharge circuit 6122 may perform the precharge operation for the input terminal IN2. The details of the operation of the precharge circuit 6122 are the same as those of the precharge circuit 400 in the embodiment of fig. 4, and are not repeated here. The precharge circuit 6122 may perform a precharge operation with respect to the input terminal IN2 according to a fixed driving capability, independently of a variation of the power supply voltage VCC, like the precharge circuit 400. IN this way, the voltage value of the voltage at the input terminal IN2 is raised during the precharge operation can be maintained.

As can be seen from the above description, the memory 600 IN this embodiment can be precharged to a fixed voltage value by the precharge circuits 6121 and 6122 independently of the change of the power supply voltage VCC during the precharge operation when the read operation of the memory CELL is performed. IN this way, after the precharge operation, the memory CELL can provide the correct data signal Vsa to the input terminal IN1, and the reference memory CELL CELLR can also provide the correct reference signal Vra to the input terminal IN2. Accordingly, the sense amplifier 610 can accurately sense the recorded data of the memory CELL in real time to obtain the accurate sensing data DO.

Incidentally, the transistors MND1 and MND2 are respectively coupled between the input terminals IN1 and IN2 and the reference voltage VSS, and are turned on according to the discharging control signal DisC to make the input terminals IN1 and IN2 perform the discharging operation.

According to the above, the control voltage generator in the sense amplifier of the present invention is used for providing the control voltage positively correlated to the variation of the power supply voltage, and the precharge circuit performs the precharge operation independently with the power supply voltage on the input terminal of the differential amplifier according to the power supply voltage and the fixed difference value of the control voltage. In this way, when the power supply voltage fluctuates, the precharge circuit can maintain the voltage value of the voltage at the input terminal of the differential amplifier that is raised during the precharge operation. Therefore, the selected memory cell can correctly provide the data signal to the input end of the differential amplifier, and the sensing amplifying device can correctly obtain the sensing data in real time.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (19)

1. A sense amplifying device, comprising:

a differential amplifier having a first input terminal and a second input terminal for receiving a data signal and a reference signal, respectively;

the first pre-charging circuit is coupled to the first input end and is used for executing pre-charging action on the first input end according to a pre-charging starting signal and a control voltage based on a power supply voltage; and

and a control voltage generator for generating the control voltage according to the power supply voltage, wherein the control voltage is positively correlated with the power supply voltage.

2. The sense amplifying device of claim 1, wherein the control voltage generator makes the control voltage proportional to the power supply voltage when the power supply voltage is greater than a reference value.

3. The sense amplifying device according to claim 1, wherein the control voltage generator includes:

a first transistor having a first terminal receiving the power supply voltage, a second terminal generating the control voltage, a control terminal receiving a first reference voltage, a turn-on voltage value of the first transistor being equal to the reference value; and

and a constant current source coupled between the second terminal of the first transistor and a reference ground, wherein the reference ground receives the first reference voltage.

4. The sense amplifier unit of claim 3, wherein the constant current source is a second transistor, wherein a first terminal of the second transistor is coupled to a second terminal of the first transistor, wherein the second terminal of the second transistor is coupled to the reference ground, wherein a control terminal of the second transistor receives a second reference voltage,

wherein the second reference voltage is greater than the first reference voltage.

5. The sense amplifying device of claim 1, wherein the first precharge circuit comprises:

a first precharge sub-circuit coupled to the first input terminal for pulling up the first input terminal to the power supply voltage based on a first driving capability according to a first precharge sub-signal and the control voltage; and

a second precharge sub-circuit coupled to the first input terminal for pulling up the first input terminal to the power supply voltage based on a second driving capability according to a second precharge sub-signal and the control voltage,

wherein the first driving capability is greater than the second driving capability.

6. The sense amplifying device of claim 5, wherein the first pre-charge sub-circuit comprises:

a first transistor having a first terminal to receive the power supply voltage, a control terminal of the first transistor receiving the first precharge promoter signal; and

a second transistor having a first terminal coupled to a second terminal of the first transistor, a control terminal of the second transistor receiving the control voltage, a second terminal of the second transistor coupled to the first input terminal,

wherein a voltage difference between the first end of the second transistor and the control end is independent of the power supply voltage.

7. The sense amplifying device of claim 6, wherein the second precharge sub-circuit comprises:

a third transistor having a first terminal to receive the power supply voltage, a control terminal of the third transistor receiving the second precharge promoter signal; and

a fourth transistor having a first terminal coupled to the second terminal of the third transistor, a control terminal of the fourth transistor receiving the control voltage, a second terminal of the fourth transistor coupled to the first input terminal,

wherein a voltage difference between the first end of the fourth transistor and the control end is independent of the power supply voltage.

8. The sense amplifying device of claim 1, further comprising:

a second precharge circuit coupled to the second input terminal for performing a precharge operation on the second input terminal based on the power supply voltage according to the precharge enable signal and the control voltage,

the second input terminal is coupled to a reference memory unit for providing the reference signal.

9. The sense amplifier device of claim 1, wherein the first input is configured to be coupled to a selected memory cell, a bit line of the selected memory cell providing the data signal.

10. The sense amplifying device of claim 1, further comprising:

and the data latch is coupled to the output end of the differential amplifier and latches the output signal on the output end of the differential amplifier to generate sensing data.

11. A memory, comprising:

at least one memory cell; and

a sense amplifier coupled to the at least one memory cell, the sense amplifier comprising:

a differential amplifier having a first input terminal coupled to the at least one memory cell for receiving a data signal and a second input terminal for receiving a reference signal;

the first pre-charging circuit is coupled to the first input end and is used for executing pre-charging action on the first input end according to a pre-charging starting signal and a control voltage based on a power supply voltage; and

and a control voltage generator for generating the control voltage according to the power supply voltage, wherein the control voltage is positively correlated with the power supply voltage.

12. The memory of claim 11, wherein the control voltage generator causes the control voltage to be proportional to the supply voltage when the supply voltage is greater than a reference value.

13. The memory of claim 11, wherein the control voltage generator comprises:

a first transistor having a first terminal receiving the power supply voltage, a second terminal generating the control voltage, a control terminal receiving a first reference voltage, a turn-on voltage value of the first transistor being equal to the reference value; and

and a constant current source coupled between the second terminal of the first transistor and a reference ground, wherein the reference ground receives the first reference voltage.

14. The memory of claim 13 wherein the constant current source is a second transistor, wherein a first terminal of the second transistor is coupled to a second terminal of the first transistor, wherein a second terminal of the second transistor is coupled to the reference ground, wherein a control terminal of the second transistor receives a second reference voltage,

wherein the second reference voltage is greater than the first reference voltage.

15. The memory of claim 11, wherein the first precharge circuit comprises:

a first precharge sub-circuit coupled to the first input terminal for pulling up the first input terminal to the power supply voltage based on a first driving capability according to a first precharge sub-signal and the control voltage; and

a second precharge sub-circuit coupled to the first input terminal for pulling up the first input terminal to the power supply voltage based on a second driving capability according to a second precharge sub-signal and the control voltage,

wherein the first driving capability is greater than the second driving capability.

16. The memory of claim 15, wherein the first precharge sub-circuit comprises:

a first transistor having a first terminal to receive the power supply voltage, a control terminal of the first transistor receiving the first precharge promoter signal; and

a second transistor having a first terminal coupled to a second terminal of the first transistor, a control terminal of the second transistor receiving the control voltage, a second terminal of the second transistor coupled to the first input terminal,

wherein a voltage difference between the first end of the second transistor and the control end is independent of the power supply voltage.

17. The memory of claim 16, wherein the second precharge sub-circuit comprises:

a third transistor having a first terminal to receive the power supply voltage, a control terminal of the third transistor receiving the second precharge promoter signal; and

a fourth transistor having a first terminal coupled to the second terminal of the third transistor, a control terminal of the fourth transistor receiving the control voltage, a second terminal of the fourth transistor coupled to the first input terminal,

wherein a voltage difference between the first end of the fourth transistor and the control end is independent of the power supply voltage.

18. The memory of claim 11, further comprising:

a reference memory unit coupled to the second input terminal, the reference memory unit for providing the reference signal,

the sense amplifying device further comprises

The second pre-charging circuit is coupled to the second input terminal and is used for performing a pre-charging operation on the second input terminal according to the pre-charging start signal and the control voltage based on the power supply voltage.

19. The memory of claim 11, wherein the sense amplifying means further comprises:

and the data latch is coupled to the output end of the differential amplifier and latches the output signal on the output end of the differential amplifier to generate sensing data.