CN116775409A - Power consumption evaluation method, device, electronic equipment and computer readable storage medium - Google Patents
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Abstract
The application provides a power consumption evaluation method, a device, electronic equipment and a computer readable storage medium, and belongs to the field of integrated circuits. The method comprises the following steps: acquiring power consumption of each sub-module in the integrated chip in P clock cycles, wherein P is an integer greater than or equal to 2; determining the power consumption of the integrated chip in P clock cycles according to the power consumption of each sub-module in P clock cycles and the power consumption weight of each sub-module; and determining a power consumption evaluation window according to the power consumption of the integrated chip in P clock cycles, wherein the power consumption evaluation window is a window for performing power consumption evaluation on the integrated chip. The method improves the accuracy of analyzing the power consumption of the chip.
Description
Technical Field
The application belongs to the field of integrated circuits, and particularly relates to a power consumption evaluation method, a power consumption evaluation device, electronic equipment and a computer readable storage medium.
Background
With the development of information technology, chips are applied to various industries. For larger-scale chips, when the power consumption analysis of the chips is performed, the power consumption analysis of the chips is performed in a mode that subsystems with more modules and mutually coupled are manually observed or waveform windows are randomly intercepted, and a large error exists in analysis results.
Disclosure of Invention
In view of the above, an object of the present application is to provide a power consumption evaluation method, apparatus, electronic device, and computer readable storage medium, so as to solve the problem that when a chip power consumption is analyzed by manually observing or randomly intercepting a waveform window, a larger error exists in an analysis result.
Embodiments of the present application are implemented as follows:
in a first aspect, an embodiment of the present application provides a power consumption evaluation method, including: acquiring power consumption of each sub-module in the integrated chip in P clock cycles, wherein P is an integer greater than or equal to 2; determining the power consumption of the integrated chip in P clock cycles according to the power consumption of each sub-module in P clock cycles and the power consumption weight of each sub-module; and determining a power consumption evaluation window according to the power consumption of the integrated chip in P clock cycles, wherein the power consumption evaluation window is a window for performing power consumption evaluation on the integrated chip.
In this embodiment, power consumption of each sub-module in the integrated chip in P clock cycles is obtained, and then power consumption of the integrated chip in P clock cycles is determined according to power consumption of each sub-module in P clock cycles and power consumption weights of each sub-module, and a power consumption evaluation window is determined according to power consumption of the integrated chip in P clock cycles. The whole integrated system is split into a plurality of sub-modules, the power consumption analysis is independently carried out on each sub-module, and then the power consumption of the integrated chip in P clock cycles is determined by combining the power consumption weights, so that the problems that the power consumption analysis is directly carried out on the integrated system, the time is long or the analysis cannot be carried out due to the overlarge integrated system are solved. Meanwhile, the power consumption evaluation window determined by the power consumption of each sub-module of the integrated chip in P clock cycles is summarized, so that the data of the power consumption of the mark integrated chip can be intercepted, and the accuracy of power consumption analysis of the integrated chip is improved.
With reference to one possible implementation manner of the embodiment of the first aspect, obtaining power consumption of each sub-module in the integrated chip in P clock cycles includes: and aiming at each sub-module in the integrated chip, obtaining the power consumption of the sub-module in P clock cycles according to the power consumption weight of each group of signals in the sub-module and the turnover rate of each group of signals in the sub-module in P clock cycles.
In this embodiment, according to the power consumption weight of each group of signals in the sub-module in the integrated chip and the turnover rate of each group of signals in the sub-module in P clock cycles, the power consumption of the sub-module in P clock cycles is obtained, and the power consumption (the product of the turnover rate and the power consumption weight) of each group of signals in the sub-module is summarized, so that the purpose of accurately obtaining the power consumption of the sub-module in each clock cycle is achieved.
With reference to a possible implementation manner of the embodiment of the first aspect, the flip rate of each set of signals in the sub-module under P clock cycles is obtained by: for each group of signals in the submodule, the turnover rate of the group of signals is a default value in the first clock period; the flip rate of the set of signals at the ith clock cycle is: if the group of signals are invalid in the ith clock period, the corresponding turnover rate is a default value; if the group of signals is valid in the ith clock period, the corresponding turnover rate is the data corresponding to the group of valid signals in the ith clock period, and i is an integer from 2 to P in turn relative to the turnover rate of the data corresponding to the group of valid signals before and closest to the ith clock period.
In this embodiment, the inversion rate of the signal group in the first clock period and the invalid signal group is directly determined as a default value, and for the signal group in the ith clock period, the inversion rate of the signal group is determined by comparing the corresponding data with the inversion rate of the data corresponding to the valid signal of the signal group in the last clock period before the ith clock period, so that on the one hand, the inversion rate of the signal in the first clock period and the invalid signal can be quickly determined, and on the other hand, the inversion rate of the signal group is determined by comparing the data corresponding to the valid signal group in the first clock period with the inversion rate of the data corresponding to the valid signal group in the last clock period before the ith clock period, and correlating the inversion rate of the valid signal with the data corresponding to the signal, thereby realizing accurate determination of the inversion rate of the valid signal.
With reference to a possible implementation manner of the embodiment of the first aspect, the power consumption weight of each set of signals in each sub-module in the integrated chip is determined by: and aiming at each sub-module, acquiring the power consumption value of each group of signals in the sub-module under the maximum power consumption, and determining the power consumption ratio of each group of signals in the sub-module under the maximum power consumption as the power consumption weight of each group of signals in the sub-module, wherein the sum of the power consumption weights of the groups of signals in the sub-module is 1.
In this embodiment, the power consumption weight of each group of signals is determined by the power consumption ratio of each group of signals of the sub-module under the maximum power consumption, so that the power consumption weight of each group of signals can be accurately obtained.
With reference to a possible implementation manner of the embodiment of the first aspect, the power consumption weight of each sub-module in the integrated chip is determined by: aiming at each sub-module, acquiring the maximum power consumption of the sub-module; and determining the power consumption ratio of the maximum power consumption of the submodule as the power consumption weight of the submodule, wherein the sum of the power consumption weights of all the submodules is 1.
In this embodiment, the power consumption ratio of the maximum power consumption of each sub-module is determined as the power consumption weight of each sub-module in the integrated chip, so that the power consumption weight of each module can be accurately obtained.
With reference to a possible implementation manner of the embodiment of the first aspect, obtaining the maximum power consumption of the sub-module includes: carrying out power consumption analysis on the submodule by using different test cases to obtain power consumption values of the submodule under different test cases; and selecting the maximum power consumption value under different test cases as the maximum power consumption of the sub-module.
In this embodiment, the power consumption analysis is performed on each sub-module by using different test cases, and the maximum power consumption value under the different test cases is selected as the maximum power consumption of the sub-module, and the maximum power consumption of each sub-module is determined by using the power consumption values under the different test cases in different sub-modules, so that the maximum power consumption of each sub-module can be accurately obtained.
With reference to one possible implementation manner of the embodiment of the first aspect, the determining a power consumption evaluation window according to power consumption of the integrated chip in P clock cycles includes: intercepting P-Q+1 windows containing the power consumption of the integrated chip in Q clock cycles for analysis to obtain P-Q+1 window analysis results, wherein Q is an integer greater than or equal to 1 and Q is smaller than P; and obtaining the power consumption evaluation window based on the P-Q+1 window analysis results, wherein the power consumption evaluation window is the window with the largest power consumption value in the P-Q+1 windows.
In the embodiment, by means of sliding the windows, the window with the largest power consumption value in the P-Q+1 windows is selected as the power consumption evaluation window, so that the power consumption of the integrated chip in each period can be comprehensively analyzed, and the accuracy of power consumption analysis of the integrated chip is improved.
With reference to one possible implementation manner of the embodiment of the first aspect, the determining the power consumption of the integrated chip in P clock cycles according to the power consumption of each sub-module in P clock cycles and the power consumption weight of each sub-module includes: and determining the power consumption of the integrated chip in the P clock cycles according to the sum of the products of the power consumption of each sub-module in the P clock cycles and the power consumption weight.
In this embodiment, the power consumption of the integrated chip in P clock cycles is determined by the sum of the products of the power consumption and the power consumption weights of each sub-module in P clock cycles, so that the power consumption of the integrated chip can be accurately determined.
In a second aspect, an embodiment of the present application further provides a power consumption evaluation apparatus, including: the device comprises an acquisition module, a first determination module and a second determination module; the acquisition module is used for acquiring the power consumption of each sub-module in the integrated chip in P clock cycles, wherein P is an integer greater than or equal to 2; the first determining module is used for determining the power consumption of the integrated chip in P clock cycles according to the power consumption of each sub-module in P clock cycles and the power consumption weight of each sub-module; and the second determining module is used for determining a power consumption evaluation window according to the power consumption of the integrated chip in P clock cycles, wherein the power consumption evaluation window is an evaluation window of the power consumption of the integrated chip.
In a third aspect, an embodiment of the present application further provides an electronic device, including: a processor and a memory for storing one or more programs; the method as provided by the embodiments of the first aspect and any one of the possible implementations in combination with the embodiments of the first aspect is implemented when the one or more programs are executed by the processor.
In a fourth aspect, embodiments of the present application also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs a method as provided for implementing the embodiments of the first aspect and any one of the possible implementations in combination with the embodiments of the first aspect.
Additional features and advantages of the application will be set forth in the description which follows. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. The above and other objects, features and advantages of the present application will become more apparent from the accompanying drawings.
Fig. 1 shows a flow chart of a power consumption evaluation method according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a power consumption evaluation method according to an embodiment of the present application.
Fig. 3 is a schematic block diagram of a power consumption evaluation device according to an embodiment of the present application.
Fig. 4 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The following examples are given by way of illustration for more clearly illustrating the technical solution of the present application, and are not to be construed as limiting the scope of the application. Those skilled in the art will appreciate that the embodiments described below and features of the embodiments can be combined with one another without conflict.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely to distinguish one entity or action from another entity or action in the description of the application without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Furthermore, the term "and/or" in the present application is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone.
In order to solve the problem that a large error exists in an analysis result when the power consumption of a chip is analyzed by means of manually observing or randomly intercepting a waveform window, the embodiment of the application provides a power consumption assessment method, a device, electronic equipment and a computer-readable storage medium. The power consumption of each sub-module in the integrated chip is independently obtained, P is an integer greater than or equal to 2, the power consumption of the integrated chip in P clock cycles is determined according to the power consumption of each sub-module in P clock cycles and the power consumption weight of each sub-module, and the power consumption evaluation window for evaluating the power consumption of the integrated chip is determined according to the power consumption of the integrated chip in P clock cycles, so that the power consumption analysis of the integrated system is directly reduced, and the problem that the time is long or the analysis cannot be performed due to the overlarge integrated system is solved. Meanwhile, the power consumption evaluation window determined by the power consumption of each sub-module of the integrated chip in P clock cycles is summarized, so that the data of the power consumption of the mark integrated chip can be intercepted, and the accuracy of power consumption analysis of the integrated chip is improved.
In order to facilitate understanding, a power consumption evaluation method provided by an embodiment of the present application will be described below with reference to fig. 1. The power consumption evaluation method includes steps S100 to S300.
Step S100, power consumption of each sub-module in the integrated chip in P clock cycles is obtained, wherein P is an integer greater than or equal to 2.
The integrated chip is mainly a main board integrated chip, and can be various common integrated chips, such as a CPU (Central Processing Unit ) or GPU (Graphics Processing Unit, graphic processor) chip, a photon chip and the like, a plurality of sub-modules exist in the integrated chip, and each signal in each sub-module is matched with each other to complete various works, such as decoding, encoding, reading, writing and the like.
When power consumption of each sub-module in the integrated chip in P clock cycles is acquired, power consumption of each sub-module in the integrated chip in P clock cycles needs to be acquired, and therefore each sub-module contains P power consumption.
For better understanding, it is assumed that the integrated chip comprises 5 sub-modules, sub-module 1, sub-module 2, sub-module 3, sub-module 4, sub-module 5, respectively. Taking the power consumption of the sub-module 1 in P clock cycles as an example, the power consumption of the sub-module 1 in the first clock cycle, the power consumption of the sub-module 1 in the second clock cycle, the power consumption of the sub-module 1 in the third clock cycle, and so on, need to be obtained until the power consumption of the sub-module 1 in the P clock cycle is obtained. The process of obtaining the power consumption of the other sub-modules in P clock cycles is identical to the process of obtaining the power consumption of the sub-module 1 in P clock cycles, and will not be described.
When the integrated chip divides the sub-modules, different functions can be executed according to each sub-module, for example, a memory control module which is responsible for processing access requests of a memory and data transmission, and a video decoding module which is responsible for decoding video modules in various formats and outputting the video modules to a display or other devices. When the different sub-modules are running, they activate different signals to jointly implement the functions they are supposed to perform. For example, a data signal may transfer data to a memory chip, thereby writing the data to the memory chip.
The clock cycle is the smallest unit of time for an integrated chip, which is the most basic unit of processing operations. In the application, when the power consumption of each sub-module in the integrated chip in P (P is more than or equal to 2) clock cycles is obtained, the power consumption of each sub-module in the pre-stored integrated chip in P (P is more than or equal to 2) clock cycles can be directly obtained from a database.
In one possible implementation manner, power consumption of each sub-module in the integrated chip in P clock cycles can also be obtained in real time. When the power consumption of each sub-module in the integrated chip in P clock cycles is obtained, the power consumption of the sub-module may be obtained by calculating according to the turnover rate of each group of signals in the sub-module, or the power consumption of each sub-module may be obtained by other methods.
In an alternative embodiment, the process of obtaining the power consumption of each sub-module in the integrated chip in P clock cycles may be:
and aiming at each sub-module in the integrated chip, obtaining the power consumption of the sub-module in P clock cycles according to the power consumption weight of each group of signals in the sub-module and the turnover rate of each group of signals in the sub-module in P clock cycles.
The inversion rate of each group of signals in the sub-module can reflect the power consumption of the group of signals to a certain extent, so that the inversion rate of each group of signals of the sub-module in P clock cycles can be directly obtained as the power consumption of the signals of the sub-module in P clock cycles. According to the power consumption weight of each group of signals in the sub-module in the integrated chip and the turnover rate of each group of signals in the sub-module under P clock cycles, the power consumption of the sub-module under P clock cycles is obtained, and the purpose of accurately acquiring the power consumption of the sub-module under each clock cycle is realized because the turnover rate of each group of signals in the sub-module is summarized.
For better understanding, it is assumed that a certain sub-module in the integrated chip comprises 5 sets of signals, signal 1, signal 2, signal 3, signal 4, signal 5, respectively. Taking the inversion rate of the signal 1 in P clock cycles as an example, the inversion rate of the signal 1 in the first clock cycle, the inversion rate of the signal 1 in the second clock cycle, the inversion rate of the signal 1 in the third clock cycle, and so on, need to be obtained until the inversion rate of the signal 1 in the P clock cycle is obtained. The process of acquiring the flip rate of the remaining group of signals in P clock cycles is identical to the process of acquiring the flip rate of the signal 1 in P clock cycles, and will not be described.
It will be appreciated that the signals in the different sub-modules are different and, therefore, the power consumption corresponding to the different sub-modules is also different.
In an alternative embodiment, the slew rate of each set of signals in the sub-module at P clock cycles is obtained by:
for each set of signals in the sub-module, the slew rate of the each set of signals at the first clock period is a default value (e.g., 0); the flip rate of the set of signals at the ith clock cycle is: if the group of signals are invalid in the ith clock period, the corresponding turnover rate is a default value; if the group of signals is valid in the ith clock period, the corresponding turnover rate is the data corresponding to the group of valid signals in the ith clock period, and i is an integer from 2 to P in turn relative to the turnover rate of the data corresponding to the group of valid signals before and closest to the ith clock period. That is, for any group of signals, the group of signals is invalid, the corresponding inversion rate is a default value, and if i is greater than or equal to 2 and the group of signals is valid, the inversion rate of the group of signals is the inversion rate of the valid signal corresponding data under the adjacent 2 periods.
For better understanding, the sub-module is assumed to include 5 sets of signals, signal 1, signal 2, signal 3, signal 4, signal 5, respectively. Taking the inversion rate of the obtained signal 1 in P clock cycles as an example, for the 1 st clock cycle, the inversion rate corresponding to the signal 1 is a default value, for example, 0. For the 2 nd clock cycle, assuming that the signal 1 is valid in both the 1 st clock cycle and the 2 nd clock cycle, the flip rate corresponding to the signal 1 in the 2 nd clock cycle is: the inversion rate of the data corresponding to signal 1 at clock cycle 2 relative to the data corresponding to signal 1 at clock cycle 1. Assuming that signal 1 is valid only once in the 1 st clock cycle and the 2 nd clock cycle, the slew rate corresponding to signal 1 is also 0 in the 2 nd clock cycle. For the 3 rd clock period, assuming that the signal 1 is invalid in the 3 rd clock period, the flip rate corresponding to the signal 1 under the 3 rd clock period is set to be 0 as a default value, for the 4 th clock period, assuming that the signal 1 is valid in the 4 th clock period, since the signal 1 under the 3 rd clock period is invalid, the clock period in which the valid signal 1 closest to the 4 th clock period is located is the 2 nd clock period, and the flip rate corresponding to the signal 1 under the 4 th clock period is set to be: the data corresponding to signal 1 at clock cycle 4 is inverted relative to the inversion rate of the data corresponding to signal 1 at clock cycle 2. Similarly, the slew rate of signal 1 over P clock periods may be obtained.
For any sub-module, performing power consumption analysis on the sub-module alone, and extracting parameter information of each group of signals in the sub-module according to a clock cycle (clk) by using an fsdbreport tool after the analysis is finished, wherein the parameter information comprises: the value of valid (characterizes whether the signal is valid, e.g., valid=1 characterizes valid, valid=0 characterizes invalid), data (data), weight (weight), etc. It will be appreciated that the power consumption weights for the same set of signals at different clock cycles are the same.
In this embodiment, for each set of signals, if the valid value of the set of signals indicates that the set of signals is valid, the corresponding flip rate is the flip rate of the set of valid signals and the data of the last set of valid signals before, and if the valid value of the set of signals indicates that the set of signals is invalid, and the flip rate is 0.
In this embodiment, for the first clock cycle, the flip rate of each group of signals in the sub-module is defaulted to be a default value, for the ith clock cycle, if the group of signals is valid in the ith clock cycle, the data corresponding to the group of valid signals in the ith clock cycle is used as the flip rate of the group of signals, and the flip rate of each group of signals in each sub-module can be accurately determined as the flip rate of the group of signals, so that the power consumption of each sub-module can be accurately obtained.
After the turnover rate of each group of signals is obtained, the power consumption of each sub-module can be obtained according to the turnover rate of each group of signals and the corresponding power consumption weight.
The power consumption weight of each group of signals is obtained through the power consumption ratio of each group of signals when different test cases are run in each sub-module. Optionally, running multiple test cases in each sub-module, determining, for each sub-module, a power consumption value of each group of signals in the sub-module at maximum power consumption, and determining a power consumption ratio as a power consumption weight of each group of signals in the sub-module.
When the power consumption ratio of each group of signals in the sub-module is obtained, the maximum power consumption value of the sub-module when different test cases are run is determined, so that when the power consumption of the sub-module is calculated by using the turnover rate and the power consumption ratio of each group of signals under each clock cycle, the power consumption ratio of each group of signals in the sub-module is the same under different clock cycles.
In an alternative embodiment, before obtaining the power consumption of the submodule in P clock cycles according to the power consumption weight of each group of signals in the submodule and the inversion rate of each group of signals in the submodule in P clock cycles, the method further includes:
Carrying out power consumption analysis on the submodule by utilizing different test cases to obtain power consumption values (average power consumption in a period of time) of the submodule under different test cases and power consumption (average power consumption in a period of time) of each group of signals in the submodule;
and acquiring the power consumption value of each group of signals in the submodule under the maximum power consumption, and determining the power consumption weight of each group of signals in the submodule according to the power consumption value. Assuming that the sub-module includes 5 sets of signals, the power consumption weights of the sets of signals in the sub-module can be determined by directly comparing the power consumption of the 5 sets of signals.
In this embodiment, the power consumption weight of each group of signals is determined by the power consumption ratio of each group of signals of the sub-module under the maximum power consumption, so that the power consumption weight of each group of signals can be accurately obtained.
The power consumption of each sub-module in a certain clock period can be calculated according to formula 1:
wherein, module x Representing sub-module x, cycle z Representing the z-th clock cycle, bus y Representing the signal y, module x bus y weight represents the power consumption weight of signal y in sub-block x at the z-th clock cycle. y represents signals, the values of which are 0-n-1, and the submodule x comprises n groups of signals. It will be appreciated that the signals comprised by the different sub-modules are different, i.e. the value of n is different. x and z are integers.
And step 200, determining the power consumption of the integrated chip in P clock cycles according to the power consumption of each sub-module in P clock cycles and the power consumption weight of each sub-module.
After the power consumption of each sub-module in P clock cycles is obtained, the power consumption of each sub-module in P clock cycles can be calculated by combining the power consumption weight of each sub-module. For example, the power consumption of the integrated chip in P clock cycles is determined according to the sum of the products of the power consumption and the power consumption weights of the sub-modules in P clock cycles.
In some implementations, the power consumption of the integrated chip at each clock cycle may be calculated according to equation 2.
Wherein, system cycle z For integrating the power consumption of the chip in clock period z, module X cycle z Indicating that sub-module x is at the z-th clock cyclePeriod z power consumption, module x weight represents the power consumption weight corresponding to sub-module x at the z-th clock cycle. The value of x is 0-m-1, which means that the integrated chip comprises m sub-modules.
In some implementations, the power consumption weight of each sub-module may be determined based on the number of activation signals for each module when the integrated chip performs an operation.
For example, at clock cycle 3, sub-module A of the integrated chip initiates 8 sets of signals, sub-module B initiates 1 set of signals, and sub-module C initiates 1 set of signals. Then in the third clock cycle, the power consumption ratio of each sub-module (sub-module a, sub-module B, sub-module C) in the integrated chip is 0.8:0.1:0.1.
In some implementations, the power consumption weights for each sub-module in the integrated chip may be determined by: and aiming at each sub-module, acquiring the maximum power consumption of the sub-module, and determining the power consumption ratio of the maximum power consumption of the sub-module as the power consumption weight of the sub-module, wherein the sum of the power consumption weights of the sub-modules is 1.
For example, if the maximum power consumption of the sub-module A, B, C is determined to be 3W, 5W, and 2W for the sub-module A, B, C, respectively, the power consumption weight of the sub-module A, B, C can be determined to be 0.3, 0.5, and 0.2.
In this embodiment, the power consumption ratio of the maximum power consumption of each sub-module is determined as the power consumption weight of each sub-module in the integrated chip, so that the power consumption weight of each module can be accurately obtained.
In some embodiments, the process of obtaining the maximum power consumption of the sub-module may be: carrying out power consumption analysis on the submodule by utilizing different test cases to obtain power consumption values (average power consumption in a period of time) of the submodule under different test cases; and selecting the maximum power consumption value under different test cases as the maximum power consumption of the sub-module.
For example, the sub-module a runs 3 test cases to perform power consumption analysis, and when the power consumption of the sub-module a is 3W, 2W, and 5W during running each test case, the maximum power consumption of the sub-module is determined to be 5W.
According to the method, the maximum power consumption of each sub-module in the integrated chip is obtained respectively, and then the power consumption weight of each sub-module is obtained according to the ratio of the maximum power consumption of each sub-module.
It can be understood that when the power consumption ratio of the sub-module is obtained, the maximum power consumption value of the sub-module when running different test cases is determined, so that when the power consumption of the integrated chip in each clock cycle is utilized, the power consumption ratio of the sub-module is the same in different clock cycles.
It will be appreciated that when power consumption analysis is performed on sub-modules using different test cases, the test cases used are different for different sub-modules.
In an alternative embodiment, before step S200, the power consumption evaluation method further includes: aiming at any sub-module, carrying out power consumption analysis on the sub-module by utilizing different test cases to obtain power consumption values of the sub-module under different test cases; and selecting the maximum power consumption value under different test cases as the maximum power consumption of the submodule, and determining the power consumption ratio of the maximum power consumption of the submodule as the power consumption weight of the submodule.
And step S300, determining a power consumption evaluation window according to the power consumption of the integrated chip in P clock cycles, wherein the power consumption evaluation window is a window for performing power consumption evaluation on the integrated chip.
The power consumption evaluation window may be a window in which the power consumption of the integrated chip is greater than a preset power consumption in each clock cycle based on N consecutive clock cycles, as the power consumption evaluation window.
In one embodiment, according to the power consumption of the integrated chip in P clock cycles, the process of determining the power consumption evaluation window is: intercepting P-Q+1 windows containing the power consumption of the integrated chip in Q clock cycles for analysis to obtain P-Q+1 window analysis results, wherein Q is an integer greater than or equal to 1 and Q is smaller than P; and obtaining a power consumption evaluation window based on the P-Q+1 window analysis results, wherein the power consumption evaluation window is the window with the largest power consumption value in the P-Q+1 windows.
After the power consumption of the integrated chip in P clock cycles is obtained, the power consumption of the integrated chip in P clock cycles is intercepted and analyzed according to the window size of Q clock cycles, and after the interception is completed, the window is updated in a sliding mode. For example, the power consumption of the window size of Q clock cycles is intercepted from the first clock cycle for the first time, and after the analysis is completed, the power consumption of the window size of Q clock cycles is intercepted from the second clock cycle. And the same is repeated until the power consumption of the integrated chip under each window is obtained, namely P-Q+1 power consumption is obtained, and the window with the largest power consumption among the P-Q+1 power consumption is determined as the power consumption evaluation window of the integrated chip.
In the embodiment, by means of sliding the windows, the window with the largest power consumption value in the P-Q+1 windows is selected as the power consumption evaluation window, so that the power consumption of the integrated chip in each period can be comprehensively analyzed, and the accuracy of power consumption analysis of the integrated chip is improved.
In this embodiment, power consumption of each sub-module in the integrated chip in P clock cycles is obtained, and then power consumption of the integrated chip in P clock cycles is determined according to power consumption of each sub-module in P clock cycles and power consumption weights of each sub-module, and a power consumption evaluation window is determined according to power consumption of the integrated chip in P clock cycles. The whole integrated system is split into a plurality of sub-modules, the power consumption analysis is independently carried out on each sub-module, and then the power consumption of the integrated chip in P clock cycles is determined by combining the power consumption weights, so that the problems that the power consumption analysis is directly carried out on the integrated system, the time is long or the analysis cannot be carried out due to the overlarge integrated system are solved. Meanwhile, the power consumption evaluation window determined by the power consumption of each sub-module of the integrated chip in P clock cycles is summarized, so that the data of the power consumption of the mark integrated chip can be intercepted, and the accuracy of power consumption analysis of the integrated chip is improved.
In some possible implementations, referring to fig. 2, fig. 2 is a schematic diagram of a power consumption evaluation method according to an embodiment of the present application. It will be appreciated that the power consumption assessment method shown in fig. 2 is only one of many embodiments of the present application.
And aiming at any sub-module in the integrated chip, carrying out power consumption analysis on the sub-module by utilizing different test cases to obtain the power consumption value of the sub-module under different test cases and the power consumption value of each group of signals in the sub-module, obtaining the maximum power consumption of the sub-module and the power consumption value of each group of signals in the sub-module under the maximum power consumption, then determining the power consumption weight of each group of signals in the sub-module according to the power consumption value of each group of signals in the sub-module under the maximum power consumption, and determining the power consumption weight of the sub-module according to the maximum power consumption of the sub-module, so that the power consumption weight of each sub-module in the integrated chip and the power consumption weight of each group of signals in each sub-module can be determined.
Then, aiming at any sub-module in the integrated chip, according to the power consumption weight of each group of signals in the sub-module and the turnover rate of each group of signals in the sub-module under P clock cycles, obtaining the power consumption of the sub-module in the P clock cycles, and according to the power consumption of each sub-module in the P clock cycles and the power consumption weight of each sub-module, determining the power consumption of the integrated chip in the P clock cycles; and then, sliding window is carried out on the power consumption of the integrated chip in P clock cycles according to the window size of the Q clock cycles, the total power consumption of the integrated chip in the window size of the Q clock cycles is determined, the total power consumption corresponding to the integrated chip in the P-Q+1 windows is obtained, and the window with the maximum total power consumption is determined as the integrated chip power consumption analysis window.
For example, taking the power consumption of the integrated chip under the first clock cycle as the starting point of the window, taking Q clock cycles as the window length, intercepting to obtain the first window, and obtaining the total power consumption of the integrated chip under each clock cycle of the window. And then, taking the power consumption of the integrated chip in the second clock period as the starting point of a window, calculating the total power consumption of the integrated chip in each clock period under the window, obtaining the total power consumption of the P-Q+1 clock windows according to the mode, determining the window with the maximum total power consumption as a power consumption evaluation window, and integrally analyzing the power consumption condition of the integrated chip according to the power consumption of the integrated chip recorded by the window in each clock period.
In this embodiment, power consumption of each sub-module in the integrated chip in P clock cycles is obtained, and then power consumption of the integrated chip in P clock cycles is determined according to power consumption of each sub-module in P clock cycles and power consumption weights of each sub-module, and a power consumption evaluation window is determined according to power consumption of the integrated chip in P clock cycles. The whole integrated system is split into a plurality of sub-modules, the power consumption analysis is independently carried out on each sub-module, and then the power consumption of the integrated chip in P clock cycles is determined by combining the power consumption weights, so that the problems that the power consumption analysis is directly carried out on the integrated system, the time is long or the analysis cannot be carried out due to the overlarge integrated system are solved. Meanwhile, the power consumption evaluation window determined by the power consumption of each sub-module of the integrated chip in P clock cycles is summarized, so that the data of the power consumption of the mark integrated chip can be intercepted, and the accuracy of power consumption analysis of the integrated chip is improved.
Referring to fig. 3, fig. 3 is a schematic block diagram of a power consumption evaluation apparatus 100 according to an embodiment of the application. The risk detection apparatus 100 includes: the system comprises an acquisition module 10, a first determination module 20 and a second determination module 30.
The acquisition module 10 is configured to acquire power consumption of each sub-module in the integrated chip in P clock cycles, where P is an integer greater than or equal to 2;
the first determining module 20 is configured to determine the power consumption of the integrated chip in P clock cycles according to the power consumption of each sub-module in P clock cycles and the power consumption weight of each sub-module;
and the second determining module 30 is configured to determine a power consumption evaluation window according to the power consumption of the integrated chip in P clock cycles, where the power consumption evaluation window is an evaluation window of the power consumption of the integrated chip.
Optionally, the obtaining module 10 is configured to obtain, for each sub-module in the integrated chip, power consumption of the sub-module in P clock cycles according to the power consumption weight of each group of signals in the sub-module and the flip rate of each group of signals in the sub-module in P clock cycles.
Optionally, the second determining module 30 is configured to intercept P-q+1 windows including the power consumption of the integrated chip in Q clock cycles for analysis, to obtain P-q+1 window analysis results, where Q is an integer greater than or equal to 1 and Q is less than P; and obtaining the power consumption evaluation window based on the P-Q+1 window analysis results, wherein the power consumption evaluation window is the window with the largest power consumption value in the P-Q+1 windows.
In this embodiment, power consumption of each sub-module in the integrated chip in P clock cycles is obtained, power consumption of the integrated chip in P clock cycles is determined according to power consumption of each sub-module in P clock cycles and power consumption weights of each sub-module, and a power consumption evaluation window is determined according to power consumption of the integrated chip in P clock cycles. The power consumption evaluation window for determining the power consumption of each sub-module of the integrated chip in P clock cycles can intercept the data for marking the power consumption of the integrated chip, so that the accuracy of analyzing the power consumption of the integrated chip is improved.
As shown in fig. 4, fig. 4 shows a block diagram of an electronic device 200 according to an embodiment of the present application. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.
The transceiver 210, the memory 220, and the processor 240 are electrically connected directly or indirectly to each other to realize data transmission or interaction. For example, the components may be electrically coupled to each other via one or more communication buses 230 or signal lines. Wherein the transceiver 210 is configured to transmit and receive data. The memory 220 is used for storing a computer program, such as the software functional modules shown in fig. 3, i.e., the power consumption evaluation apparatus 100. The power consumption evaluation device 100 includes at least one software function module that may be stored in the memory 220 in the form of software or Firmware (Firmware) or cured in an Operating System (OS) of the electronic apparatus 200. The processor 240 is configured to execute executable modules stored in the memory 220, such as software functional modules or computer programs included in the power consumption evaluation apparatus 100. For example, a processor 240, for performing the power consumption assessment method described above.
The Memory 220 may be, but is not limited to, a random access Memory (Random Access Memory, RAM), a Read Only Memory (ROM), a programmable Read Only Memory (Programmable Read-Only Memory, PROM), an erasable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), an electrically erasable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.
The processor 240 may be an integrated circuit chip with signal processing capabilities. The processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; but also digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), field programmable gate arrays (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor 240 may be any conventional processor or the like.
The electronic device 200 includes, but is not limited to, a computer, an automobile, and the like.
The embodiment of the present application further provides a non-volatile computer readable storage medium (hereinafter referred to as a storage medium) having a computer program stored thereon, which when executed by a computer such as the above-described electronic device 200, performs the above-described power consumption evaluation method.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a computer-readable storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a notebook computer, a server, or an electronic device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned computer-readable storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A power consumption evaluation method, characterized by comprising:
acquiring power consumption of each sub-module in the integrated chip in P clock cycles, wherein P is an integer greater than or equal to 2;
determining the power consumption of the integrated chip in P clock cycles according to the power consumption of each sub-module in P clock cycles and the power consumption weight of each sub-module;
and determining a power consumption evaluation window according to the power consumption of the integrated chip in P clock cycles, wherein the power consumption evaluation window is a window for performing power consumption evaluation on the integrated chip.
2. The method of claim 1, wherein obtaining power consumption of each sub-module in the integrated chip for P clock cycles comprises:
and aiming at each sub-module in the integrated chip, obtaining the power consumption of the sub-module in P clock cycles according to the power consumption weight of each group of signals in the sub-module and the turnover rate of each group of signals in the sub-module in P clock cycles.
3. The method of claim 2, wherein the slew rate of each set of signals in the sub-module at P clock cycles is obtained by:
for each group of signals in the submodule, the turnover rate of the group of signals is a default value in the first clock period;
the flip rate of the set of signals at the ith clock cycle is:
if the group of signals are invalid in the ith clock period, the corresponding turnover rate is a default value;
if the group of signals is valid in the ith clock period, the corresponding turnover rate is the data corresponding to the group of valid signals in the ith clock period, and i is an integer from 2 to P in turn relative to the turnover rate of the data corresponding to the group of valid signals before and closest to the ith clock period.
4. The method of claim 2, wherein the power consumption weight for each set of signals in each sub-module in the integrated chip is determined by:
aiming at each sub-module, acquiring the power consumption value of each group of signals in the sub-module under the maximum power consumption;
and determining the power consumption ratio of each group of signals in the submodule under the maximum power consumption as the power consumption weight of each group of signals in the submodule, wherein the sum of the power consumption weights of the groups of signals in the submodule is 1.
5. The method of any of claims 1-4, wherein the power consumption weights for each sub-module in the integrated chip are determined by:
aiming at each sub-module, acquiring the maximum power consumption of the sub-module;
and determining the power consumption ratio of the maximum power consumption of the submodule as the power consumption weight of the submodule, wherein the sum of the power consumption weights of all the submodules is 1.
6. The method of claim 5, wherein obtaining the maximum power consumption of the sub-module comprises:
carrying out power consumption analysis on the submodule by using different test cases to obtain power consumption values of the submodule under different test cases;
and selecting the maximum power consumption value under different test cases as the maximum power consumption of the sub-module.
7. The method of claim 1, wherein determining a power consumption evaluation window based on the power consumption of the integrated chip over P clock cycles comprises:
intercepting P-Q+1 windows containing the power consumption of the integrated chip in Q clock cycles for analysis to obtain P-Q+1 window analysis results, wherein Q is an integer greater than or equal to 1 and Q is smaller than P;
and obtaining the power consumption evaluation window based on the P-Q+1 window analysis results, wherein the power consumption evaluation window is the window with the largest power consumption value in the P-Q+1 windows.
8. A power consumption evaluation apparatus, characterized by comprising:
the acquisition module is used for acquiring the power consumption of each sub-module in the integrated chip in P clock cycles, wherein P is an integer greater than or equal to 2;
the first determining module is used for determining the power consumption of the integrated chip in P clock cycles according to the power consumption of each sub-module in P clock cycles and the power consumption weight of each sub-module;
and the second determining module is used for determining a power consumption evaluation window according to the power consumption of the integrated chip in P clock cycles, wherein the power consumption evaluation window is a window for performing power consumption evaluation on the integrated chip.
9. An electronic device, comprising:
a processor and a memory for storing one or more programs; the method of any one of claims 1 to 7 is implemented when the one or more programs are executed by the processor.
10. A computer-readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, performs the method according to any of claims 1 to 7.
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