CN116774775B - On-chip clock controller and working method - Google Patents
On-chip clock controller and working method Download PDFInfo
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- CN116774775B CN116774775B CN202310752401.1A CN202310752401A CN116774775B CN 116774775 B CN116774775 B CN 116774775B CN 202310752401 A CN202310752401 A CN 202310752401A CN 116774775 B CN116774775 B CN 116774775B
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Abstract
The invention provides an on-chip clock controller, which comprises: the clock control module is used for generating different clock enabling signals to gate and shift the test clock module or the high-speed clock multiplexing module in the test mode, and generating clock signals selected and output by the clock selecting signals at the same time; the high-speed clock multiplexing module comprises a first digital selector, a second digital selector, an existing clock beating unit and a clock gating unit in a functional mode, and is used for generating a high-speed clock signal in a test mode according to a second clock enabling signal; and the shift test clock module is used for generating a test clock signal in a test mode according to the first clock enabling signal. The invention can avoid introducing an extra register, reduce the chip area and reduce the chip design and manufacturing cost by multiplexing the beat logic and the clock gating in the functional mode in the test mode.
Description
Technical Field
The invention relates to the technical field of clock control, in particular to an on-chip clock controller.
Background
The on-chip clock controller OCC (On chip Clock Controllers), also referred to as SCC (Scan Clock Controllers), is clock control logic inserted into the SoC for controlling the clock used for testing when the silicon chip is tested on the ATE (Automatic test Equipment) machine.
At present, if a control signal of an on-chip clock controller in a test mode needs to be beaten, a special beating register for the test mode needs to be added, when the control signal needs to be cloned for a large number of times, for example, a clock tree needs to be subjected to grid processing, and because of a time sequence, the beating register can be cloned for a large number of times, so that a large number of extra registers are introduced, the area of a chip is occupied, and the design and manufacturing cost of the chip are increased.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is to overcome the defect that the cost is increased due to the fact that the beat register is introduced in a large amount in the prior art, so that the on-chip clock controller is provided, the beat logic and the clock gating existing in the functional mode can be multiplexed, the beat register is not additionally introduced, the occupied area of the register to a chip is reduced, and the chip design and manufacturing cost is reduced.
The technical scheme for solving the technical problems is as follows:
in a first aspect, the present invention provides an on-chip clock controller comprising: the clock control module, the high-speed clock multiplexing module and the shift test clock module, wherein,
the clock control module is used for gating and shifting the test clock module or the high-speed clock multiplexing module by generating different clock enabling signals in the test mode;
the shift test clock module is used for releasing the slow clock signal according to the first clock enabling signal generated by the clock control module in a test mode to generate a test clock signal;
the high-speed clock multiplexing module comprises a first digital selector, a second digital selector, an existing clock beating unit and a clock gating unit under a functional mode, and is used for selecting to release high-frequency clock signals under a test mode through the first digital selector according to a second clock enabling signal generated by the clock control module to generate a preset number of high-speed clock signals;
the clock control module is also used for generating a clock selection signal in the test mode and selecting and outputting a test clock signal or a high-speed clock signal through a second digital selector of the high-speed clock multiplexing module.
In the on-chip clock controller provided by the embodiment of the invention, in a test mode, a clock enabling signal of a clock control module is used for controlling a high-speed clock multiplexing module or a shift test clock module to generate a clock signal, wherein the high-speed clock multiplexing module multiplexes a clock beating unit and a clock gating unit which are existing in a functional mode, a first digital selector is used for selecting and beating the clock enabling signal based on the functional mode or the test mode, a post-beating enabling signal is used for controlling the clock gating unit to generate the high-speed clock signal, and in the test mode, the high-speed clock signal or the test clock signal is selected and output according to a selection signal of the clock control module and a second digital selector. The invention can avoid introducing an extra register, reduce the chip area and reduce the chip design and manufacturing cost by multiplexing the beat logic and the clock gating in the functional mode in the test mode.
Optionally, the first digital selector is disposed before the clock beating unit, and is used for selecting to perform clock control in the test mode or perform clock control in the functional mode; the second digital selector is disposed after the clock gating unit for selecting output of the test clock signal or the high-speed clock signal in the test mode.
Optionally, the selection ports of the first digital selector are controlled by using configurable registers, so as to gate the first input terminal or the second input terminal of the first digital selector; in the functional mode, a functional clock enable signal controls the multiplexing high-speed clock module to gate or turn off the high-speed clock signal according to the high-frequency clock signal through the first input end of the first digital selector; in the test mode, the second clock enable signal controls the multiplexing high-speed clock module to gate or gate off the high-speed clock signal according to the high-frequency clock signal through the second input terminal of the first digital selector.
According to the invention, the digital selector is arranged, so that one path of data can be selected for transmission according to the requirements in the process of multi-path data transmission. The digital selector is arranged before multiplexing the high-speed clock, clock control can be carried out according to the current mode, and the generated clock signal meets the operation of a functional mode or a test mode, so that the additional registers which are required to be added for cloning the beat device and the gate control logic for multiple times are reduced, the occupied area of the registers on a chip is reduced, and the chip design and manufacturing cost is reduced. After multiplexing the high-speed clock, the digital selector is arranged, so that clock signals meeting different test sub-modes in a test mode can be selected and output, and testing at different stages is realized, thereby adjusting the circuit structure according to the test result, and improving the testability, i.e. controllability and observability of the circuit.
Optionally, the high-speed clock multiplexing module performs clone replication for preset times according to the time sequence requirement, and second clock enabling signals of all the high-speed clock multiplexing modules in the test mode come from the same clock control module; when the high-speed clock multiplexing module is duplicated, the selection ports of the first digital selectors which are different in the high-speed clock multiplexing module are set to be the same configurable register or are correspondingly set with the high-speed clock multiplexing module.
In the test mode, the invention needs to clone the beat register due to the time sequence in the functional mode, so that the existing clock beat unit and clock gating in the functional mode and the matched digital selector are duplicated to form a plurality of high-speed clock multiplexing modules, and all multiplexing clock generating modules are controlled by a unified clock control module so as to generate clock signals meeting different control signals. On the basis, the control ports of the first digital selectors of all the high-speed clock multiplexing modules can be controlled through unified configurable registers, and a plurality of continuous configurable registers can be dispersed to realize the selection of a functional mode or a test mode.
Optionally, the clock beating unit includes: the third digital selector and the multi-stage register are used for beating the stored and transmitted clock enabling signals, and the beating times correspond to the register stages; a selection port of a third digital selector in the clock beating unit is controlled by a configurable register, and a multi-stage register is selected to be reset based on a functional mode reset signal or to be reset based on a test mode reset signal; a first input port of a third digital selector in the clock beating unit resets the multi-stage register under a function mode through a function mode reset signal; the second input port of the third digital selector in the clock beating unit is controlled through the configurable register, and the multi-stage register is reset in a test mode according to the test mode reset signal.
According to the invention, the digital selector of the clock beating unit is used for resetting the beating registers based on different reset signals, so that multiplexing of beating logic and clock gating is realized. In addition, the second input port of the digital selector is controlled through the configurable register, so that the control of the beating register reset port in the test mode can be ensured, and the unstable state is eliminated.
In a second aspect, an embodiment of the present invention provides a method for operating an on-chip clock controller, where the method includes the following steps:
in a test mode, the clock control module generates different clock enabling signals, and the shift test clock module or the high-speed clock multiplexing module is gated according to the clock enabling signals;
the second clock enabling signal passes through the second input end of the first digital selector, the multiplexing high-speed clock module is controlled to pass the high-frequency clock signal according to the second clock enabling signal to generate a preset number of high-speed clock signals, or the shift test clock module passes the slow-speed clock signal according to the first clock enabling signal to generate a test clock signal;
the clock control module generates a clock selection signal and selects to output a test clock signal or a high-speed clock signal through a second digital selector.
In the working method of the on-chip clock controller provided by the embodiment of the invention, in a test mode, a clock enabling signal of a clock control module is used for controlling a high-speed clock multiplexing module or a shift test clock module to generate corresponding clock signals, wherein the high-speed clock multiplexing module multiplexes a clock beating unit and a clock gating unit which are existing in a functional mode, a first digital selector is used for selecting and beating the clock enabling signal in the functional mode or the test mode, a post-beating enabling signal is used for controlling the clock gating unit to generate the high-speed clock signals, and in the test mode, the high-speed clock signals or the test clock signals are selectively output through a second digital selector according to the selection signals of the clock control module. The invention can avoid introducing an extra register, reduce the chip area and reduce the chip design and manufacturing cost by multiplexing the beat logic and the clock gating in the functional mode in the test mode.
Optionally, the test mode includes: a first test sub-mode and a second test sub-mode; a first test sub-mode comprising: a shift test sub-mode and a stuck-at capture test sub-mode; the second test sub-mode is transition capture test sub-mode; in the first test sub-mode, the shift test clock module is gated, and in the second test sub-mode, the high-speed clock multiplexing module is gated.
The invention realizes the test of different sub-modes in the test mode by controlling different clock enabling signals. In the transition capture test sub-mode, two pulse signals with the same frequency as the functional clock are needed, so that the clock control module gates the high-speed clock multiplexing module to control the clock gating to release the preset number of high-frequency clock pulse signals, and the test requirement is met. Under the shift test sub-mode and the stuck-at capture test sub-mode, high-speed pulse is not needed, so that the clock control module directly gates and shifts the test clock module, and the slow clock signal is released, thereby meeting the test requirement.
Optionally, the beating process of the clock beating unit includes: in the test mode, the selection port of the third digital selector is set to be a preset value, the second input port of the third digital selector is gated to reset the multi-stage register, and the multi-stage register beats the first clock enabling signal after reset.
According to the invention, the digital selector of the clock beating unit is used for selecting to beat the clock in the functional mode or beat the clock in the test mode, so that multiplexing of beating logic and clock gating in the functional mode is realized, the occupied area of the register on the chip is reduced, and the chip design and manufacturing cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an on-chip clock controller according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a detailed structure of an on-chip clock controller according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a clock beating unit of an on-chip clock controller according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a clone structure of an on-chip clock controller according to an embodiment of the present invention;
fig. 5 is a flowchart of a working method of an on-chip clock controller according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1
An embodiment of the present invention provides an on-chip clock controller, as shown in fig. 1, including: the clock control module, the high-speed clock multiplexing module and the shift test clock module, wherein,
the clock control module is used for gating and shifting the test clock module or the high-speed clock multiplexing module by generating different clock enabling signals in the test mode; the shift test clock module is used for releasing the slow clock signal according to the first clock enabling signal generated by the clock control module in a test mode to generate a test clock signal; the high-speed clock multiplexing module comprises a first digital selector, a second digital selector, an existing clock beating unit and a clock gating unit under a functional mode, and is used for selecting to release high-frequency clock signals under a test mode through the first digital selector according to a second clock enabling signal generated by the clock control module to generate a preset number of high-speed clock signals; the clock control module is also used for generating a clock selection signal in the test mode and selecting and outputting a test clock signal or a high-speed clock signal through a second digital selector of the high-speed clock multiplexing module.
Specifically, in the embodiment of the present invention, as shown in fig. 2, OCC control module is a clock control module according to the embodiment of the present invention, and the input of the clock control module is a high-frequency clock signal clock_in, which is a clock signal generated by an on-chip PLL. The output of which comprises three signals: two clock enable signals and one clock select signal. Wherein the generated clock enable signal comprises: the first clock enable signal slow_clock_en and the second clock enable signal fast_clock_en generate clock selection signals which are clock_mux_select.
In the embodiment of the present invention, cg_pipe in the dashed box shown in fig. 2 is an existing clock-beating unit in the functional mode, and CG is an existing clock-gating unit in the functional mode. As shown in fig. 3, the clock beating unit includes: and the third digital selector and the multi-stage register are used for beating the stored and transmitted clock enabling signals, and the beating times correspond to the register stages. The selection port of the third digital selector is controlled by a configurable register, and the multi-stage register is selected to be reset based on a functional mode reset signal or to be reset based on a test mode reset signal; the first input port resets the multi-stage register in a functional mode through a functional mode reset signal; the second input port is controlled by the configurable register and resets the multi-stage register in a test mode according to the test mode reset signal.
In the embodiment of the invention, the high-speed clock multiplexing module is formed by arranging the first digital selector before the clock beating unit cg_pipe and arranging the second digital selector after the clock gating unit CG. The lowest clock gating unit CG is the shift test clock module according to the embodiment of the present invention. The first digital selector is used for selecting to perform clock control in a test mode or perform clock control in a functional mode, and the second digital selector is used for selecting to output a test clock signal or a high-speed clock signal in the test mode.
The control process of the high-speed clock signal in the embodiment of the invention comprises the following steps: the high-speed clock multiplexing module is controlled by a configurable register TDR through a selection port of the first selector and is used for gating a first input port or a second input port of the first selector, so that the high-speed clock multiplexing module is determined to perform clock control in a functional mode or in a test mode. In the functional mode, a functional clock enable signal clock_en controls the multiplexing high-speed clock module to gate or turn off the high-speed clock signal according to the high-frequency clock signal clock_in through the first input end of the first digital selector; in the test mode, the second clock enable signal fast_clock_en controls the multiplexing high-speed clock module to gate or gate off the high-speed clock signal according to the high-frequency clock signal clock_in through the second input terminal of the first digital selector.
The control process of the test clock signal in the embodiment of the invention comprises the following steps: the clock control module OCC control module generates a first clock enable signal slow_clock_en, and controls the shift test clock module to gate or turn off the slow clock signal shift_capture_clock according to the first clock enable signal slow_clock_en, so as to generate a test clock signal, wherein the slow clock signal shift_capture_clock is a slow clock.
After the on-chip clock controller in the embodiment of the present invention is inserted into a design for test (DFT), when the beater and the gating logic on the control signal path need to clone a large number of times, for example, the clock tree needs to perform latticed processing, the high-speed clock multiplexing module in the dashed frame of fig. 2 may be copied when the subsequent physical implementation performs cloning processing, the number of copying times is determined according to the timing requirement, and the second clock enable signals fast_clock_en of all the high-speed clock multiplexing modules in the test mode come from the same clock control module OCC control module and may be processed as synchronous clock signals. Meanwhile, when the high-speed clock multiplexing module is duplicated, the configurable registers TDR at the selection port of the first digital selector in the high-speed clock multiplexing module are set to be the same, or a plurality of reserved configurable registers TDR are connected in a scattered mode to be correspondingly set with the high-speed clock multiplexing module.
The embodiment of the present invention is shown in fig. 4 after cloning and copying the TDR distributed settings of the configurable register, which is only an example and not limited thereto. The structure is mainly used for a DFT high-speed scan test mode, and a high-frequency clock signal clock_in is a high-frequency clock signal input by a PLL and is input to a clock control module OCC control module and a clock gating unit CG to provide a high-speed clock. The clock control module OCC control module generates a first clock enable signal slow_clock_en, a second clock enable signal fast_clock_en, and a clock select signal clock_mux_select. The second clock enable signal fast_clock_en and the functional clock enable signal clock_en are input to the first digital selector mux1, and are selected by the corresponding configurable register TDR. The method comprises the steps of selecting a second clock enabling signal fast_clock_en to pass under a high-speed scan test mode, inputting the second clock enabling signal fast_clock_en to a corresponding clock gating unit CG after being beaten by a clock beating unit cg_pipe, controlling the clock gating unit CG to output a preset number of high-speed clock pulses as a clock source under the high-speed scan test mode, inputting a slow clock signal shift_capture_clock to the clock gating unit CG at a first input port of a second digital selector mux2, controlling the clock gating unit CG to output a test clock signal to a second input port of the second digital selector CG by the first clock enabling signal slow_clock_en, and switching the clock sources of a capture sub-mode and a shift sub-mode under the high-speed scan test mode. Because the clock control signals in the DFT mode are all from the same clock control module OCC control module, the clock signals generated by cloning are also treated as synchronous clock signals in the DFT mode.
Example 2
The embodiment of the invention provides a working method of an on-chip clock controller, as shown in fig. 5, the method is based on the on-chip clock controller provided in the embodiment 1 to control clock in a test mode, and the method comprises the following steps:
step S1: in the test mode, the clock control module generates different clock enabling signals and gates and shifts the test clock module or the high-speed clock multiplexing module according to the clock enabling signals.
Specifically, in the embodiment of the present invention, as shown in fig. 2, the clock control module OCC control module generates the second clock enable signal fast_clock_en and the first clock enable signal slow_clock_en in the test mode. The test mode comprises a first test sub-mode and a second test sub-mode, wherein the first test sub-mode comprises: a shift test sub-mode and a stuck-at capture test sub-mode; the second test sub-mode is the transition capture test sub-mode. In the first test sub-mode, the shift test clock module is gated by a first clock enable signal slow_clock_en, and in the second test sub-mode, the high-speed clock multiplexing module is gated by a second clock enable signal fast_clock_en.
Step S2: the second clock enabling signal passes through the second input end of the first digital selector, the multiplexing high-speed clock module is controlled to pass the high-frequency clock signal according to the second clock enabling signal to generate a preset number of high-speed clock signals, or the shift test clock module passes the slow-speed clock signal according to the first clock enabling signal to generate the test clock signal.
Specifically, in the embodiment of the present invention, the selection port of the first digital selector is controlled by a configurable register, and the TDR is set to a preset value to represent that the first digital selector is currently in the DFT test mode. In the functional mode, TDR is set to 0, the first digital selector outputs a functional enable signal clock_en from the first input port, and the second clock enable signal fast_clock_en of the second input port is disabled. The functional enabling signal clock_en is beaten through the clock beating unit cg_pipe, then the enabling port of the clock gating unit CG on the high-speed clock path is controlled by the beaten enabling signal, and the clock gating unit CG generates a preset number of high-speed clock signals according to the high-frequency clock signal clock_in.
In the embodiment of the present invention, in the transition capture test sub-mode of the test mode, the TDR is set to 1, the first digital selector outputs the second clock enable signal fast_clock_en from the second input port, and the function enable signal clock_en of the first input port is disabled. The second clock enabling signal fast_clock_en is subjected to beat through the clock beat unit cg_pipe, then the enabling port of the clock gating unit CG on the high-speed clock path is controlled by the beat enabling signal, and a preset number of high-speed clock signals are generated by the clock gating unit CG according to the high-frequency clock signal clock_in.
In the embodiment of the invention, in a shift test sub-mode or a stuck-at capture test sub-mode of a test mode, a first clock enable signal slow_clock_en controls an enable port of a clock gating unit CG on a slow clock signal shift_capture_clock path, the slow clock signal shift_capture_clock is released, and a test clock signal is generated by the clock gating unit CG.
Step S3: the clock control module generates a clock selection signal and selects to output a test clock signal or a high-speed clock signal through a second digital selector.
Specifically, in the test mode, the clock control module OCC control module generates the clock selection signal clock_mux_select, which controls the control port of the second digital selector to enable the second digital selector to select and output the high-speed clock signal of the first input port or the test clock signal of the second input port.
In the working method of the on-chip clock controller provided by the embodiment of the invention, in a test mode, a clock enabling signal of a clock control module is used for controlling a high-speed clock multiplexing module or a shift test clock module to generate a clock signal, wherein the high-speed clock multiplexing module multiplexes a clock beating unit and a clock gating unit which are already in a functional mode, a first digital selector is used for selecting to generate a high-speed clock signal in the test mode or the functional mode, and a second digital selector is used for selecting to output the high-speed clock signal or the test clock signal according to a selection signal of the clock control module in the test mode. The invention can avoid introducing an extra register, reduce the chip area and reduce the chip design and manufacturing cost by multiplexing the beat logic and the clock gating in the functional mode in the test mode.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations are within the scope of the invention as defined by the appended claims.
Claims (8)
1. An on-chip clock controller, comprising: the clock control module, the high-speed clock multiplexing module and the shift test clock module, wherein,
the clock control module is used for gating the shift test clock module or the high-speed clock multiplexing module by generating different clock enabling signals in a test mode;
the shift test clock module is used for releasing the slow clock signal according to the first clock enabling signal generated by the clock control module in a test mode to generate a test clock signal;
the high-speed clock multiplexing module comprises a first digital selector, a second digital selector, an existing clock beating unit and a clock gating unit under a functional mode, and is used for selecting to release high-frequency clock signals under a test mode through the first digital selector according to a second clock enabling signal generated by the clock control module to generate a preset number of high-speed clock signals;
the clock control module is further used for generating a clock selection signal in a test mode, and selecting and outputting a test clock signal or a high-speed clock signal through a second digital selector of the high-speed clock multiplexing module.
2. The on-chip clock controller of claim 1, wherein,
the first digital selector is arranged in front of the clock beating unit and is used for selecting to perform clock control in a test mode or perform clock control in a functional mode;
the second digital selector is arranged behind the clock gating unit and is used for selecting and outputting a test clock signal or a high-speed clock signal in a test mode.
3. The on-chip clock controller of claim 2, wherein the select port of the first digital selector is controlled using a configurable register to gate either the first input or the second input of the first digital selector;
in a functional mode, a functional clock enable signal controls the high-speed clock multiplexing module to gate or gate off a high-speed clock signal according to a high-frequency clock signal through a first input end of the first digital selector;
in the test mode, a second clock enable signal controls the high-speed clock multiplexing module to gate or gate off the high-speed clock signal according to the high-frequency clock signal through the second input terminal of the first digital selector.
4. The on-chip clock controller of claim 3, wherein the high-speed clock multiplexing module performs clone replication for a preset number of times according to a timing requirement, and the second clock enable signals of all the high-speed clock multiplexing modules in the test mode are all from the same clock control module;
when the high-speed clock multiplexing module is duplicated, the selection ports of the first digital selectors which are different in the high-speed clock multiplexing module are set to be the same configurable register or are correspondingly set with the high-speed clock multiplexing module.
5. The on-chip clock controller of claim 1, wherein the clock beating unit comprises: the third digital selector and the multi-stage register are used for beating the stored and transmitted clock enabling signals, and the beating times correspond to the register stages;
a selection port of a third digital selector in the clock beating unit is controlled by a configurable register, and a multi-stage register is selected to be reset based on a functional mode reset signal or to be reset based on a test mode reset signal;
a first input port of a third digital selector in the clock beating unit resets the multi-stage register in a functional mode through a functional mode reset signal;
and a second input port of a third digital selector in the clock beating unit is controlled through a configurable register, and the multi-stage register is reset in a test mode according to a test mode reset signal.
6. A method of operating an on-chip clock controller, based on the on-chip clock controller of claims 1-5, for controlling clocks in a test mode, comprising:
in a test mode, the clock control module generates different clock enabling signals, and the test clock module or the high-speed clock multiplexing module is subjected to gating shift according to the clock enabling signals;
the second clock enabling signal passes through the second input end of the first digital selector, the high-speed clock multiplexing module is controlled to pass the high-frequency clock signal according to the second clock enabling signal, a preset number of high-speed clock signals are generated, or the shift test clock module passes the slow-speed clock signals according to the first clock enabling signal, and a test clock signal is generated;
the clock control module generates a clock selection signal and selectively outputs the test clock signal or the high-speed clock signal through a second digital selector.
7. The method of operating an on-chip clock controller of claim 6, wherein the test mode comprises: a first test sub-mode and a second test sub-mode;
the first test sub-mode includes: a shift test sub-mode and a stuck-at capture test sub-mode;
the second test sub-mode is a transition capture test sub-mode;
and in the first test sub-mode, gating the shift test clock module, and in the second test sub-mode, gating the high-speed clock multiplexing module.
8. The method of claim 6, wherein the process of beating by the clock beating unit comprises:
in the test mode, the selection port of the third digital selector is set to be a preset value, the second input port of the third digital selector is gated to reset the multistage register, and after the reset, the multistage register beats the first clock enabling signal.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2017000274A1 (en) * | 2015-07-01 | 2017-01-05 | Mediatek Inc. | Devices and methods for multi-clock-domain testing |
| CN114117972A (en) * | 2022-01-26 | 2022-03-01 | 之江实验室 | Synchronous device and method of asynchronous circuit |
| CN115236493A (en) * | 2022-07-28 | 2022-10-25 | 摩尔线程智能科技(北京)有限责任公司 | DFT test circuit, test system and test method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017000274A1 (en) * | 2015-07-01 | 2017-01-05 | Mediatek Inc. | Devices and methods for multi-clock-domain testing |
| CN114117972A (en) * | 2022-01-26 | 2022-03-01 | 之江实验室 | Synchronous device and method of asynchronous circuit |
| CN115236493A (en) * | 2022-07-28 | 2022-10-25 | 摩尔线程智能科技(北京)有限责任公司 | DFT test circuit, test system and test method |
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