CN116760425A - CRC auxiliary OSD decoding method of LDPC code - Google Patents

CRC auxiliary OSD decoding method of LDPC code Download PDF

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Publication number
CN116760425A
CN116760425A CN202310678635.6A CN202310678635A CN116760425A CN 116760425 A CN116760425 A CN 116760425A CN 202310678635 A CN202310678635 A CN 202310678635A CN 116760425 A CN116760425 A CN 116760425A
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crc
osd
decoding
code
sequence
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包嘉筠
史治平
韦祖恩
杨海芬
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University of Electronic Science and Technology of China
Yangtze River Delta Research Institute of UESTC Huzhou
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University of Electronic Science and Technology of China
Yangtze River Delta Research Institute of UESTC Huzhou
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45—Soft decoding, i.e. using symbol reliability information
    • H03M13/451—Soft decoding, i.e. using symbol reliability information using a set of candidate code words, e.g. ordered statistics decoding [OSD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

The invention discloses a CRC auxiliary OSD decoding method of LDPC codes. The invention mainly selects decoding output from candidate code words based on a hierarchical statistical decoding (Ordered Statistic Decoding, OSD) method, introduces cyclic redundancy check (Cyclic Redundancy Check, CRC) except adopting Euclidean distance minimum judgment, selects the candidate code words passing CRC as decoding output with the minimum Euclidean distance, thereby improving the error code performance of OSD decoding. The LDPC codes with different code length code rates are simulated, and the result shows that the CRC auxiliary OSD decoding method provided by the invention can obtain lower block error rate than the OSD decoding method with the same order, and meanwhile, the number of test error modes (Test Error Patterns, TEPs) participating in recoding can be reduced by setting reasonable list length in the CRC auxiliary OSD method, so that the complexity of the OSD decoding in recoding link is reduced.

Description

CRC auxiliary OSD decoding method of LDPC code
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a CRC (cyclic redundancy check) auxiliary OSD (on-screen display) decoding method of an LDPC (Low Density parity check) code, which can be used for a communication system scene of LDPC code channel coding.
Background
With the continuous development of communication technology, in order to ensure the reliability of a communication system, a channel coding technology with superior performance is one of key technologies for reducing transmission error rate. Low-Density Parity-Check (LDPC) codes have been widely used in various large communication systems as a channel code having a certain advantage in both error correction performance and time delay. Although iterative decoding algorithms represented by belief propagation (Belief Propagation, BP) algorithms perform well when decoding LDPC long codes, BP-type decoding algorithms are prone to error floor when the LDPC code length is short. In response to this problem, in 1995, fossorier et al proposed hierarchical statistical decoding (Ordered Statistic Decoding, OSD) which can achieve maximum likelihood decoding performance with increasing order. However, the OSD decoding involves Gao Sixiao yuan, sorting, recoding and the like, so that the algorithm complexity is high, and the large-scale implementation of the method is limited. In particular, as the order increases, the complexity of OSD coding will be higher and higher, so more low order OSDs are typically used. However, the performance of the low order OSD decoding still has a certain gap from achieving maximum likelihood decoding.
Disclosure of Invention
Aiming at the problem that the error code performance of the low-order OSD decoding still increases the space, the invention provides a CRC auxiliary OSD decoding method, which aims to increase the error code performance of the low-order OSD. In the proposed CRC-assisted OSD decoding method, compared with the original OSD, the main difference is that, by introducing CRC check bits at the encoding end, when decoding is performed by OSD at the receiving end, for a certain candidate codeword estimate, the information estimate with the CRC check bits is first extracted, CRC check is performed, and a List (List) with a length Len is set, which is called "preliminary output codeword List". And storing only codeword estimates passing through CRC (cyclic redundancy check) in the list, and finally, respectively calculating Euclidean distances between Len codeword estimates in the list and a receiving sequence, and selecting the codeword estimate with the minimum Euclidean distance as final decoding output.
The technical scheme of the invention is as follows:
let the information sequence m= [ m ] of length K 0 ,m 1 ,…,m K-1 ]Performing CRC encoding, and introducing r bits of CRC check bits to obtain a sequence m crc ＝[m 0 ′,m 1 ′,…,m′ K+r-1 ]LDPC coding with a code length of N is carried out on an information sequence with CRC check bits, and an LDPC codeword c= [ c ] is obtained 0 ,c 1 ,…,c N-1 ]. The codeword c is BPSK modulated to obtain a sequence x= [ x ] 0 ,x 1 ,…,x N-1 ]. The mean value of the sequence x is 0, and the variance is sigma 2 Is transmitted by AWGN channel, and the receiving sequence of the receiving end is y= [ y ] 0 ,y 1 ,…,y N-1 ]. For the received sequence y= [ y ] 0 ,y 1 ,…,y N-1 ]Performing hard decision to obtain a hard decision sequence defined as h= [ h ] 0 ,h 1 ,…,h N-1 ]. Assuming that the most reliable first k+r MRBs have been found according to the original OSD decoding, then the CRC-aided OSD decoding method needs to be performed: k+r bit MRB sequence m 0 Substitution relation lambda 1 、λ 2 Generating matrix G for completing replacement 2 Reception sequence for completing substitutionThe original receiving sequence y and the order L, CRC generate a polynomial G_crc and store the list length Len of the code word passing the CRC; decoding method output is codeword estimationThe specific implementation steps of the CRC-assisted OSD decoding method of the L-order LDPC code are as follows, wherein symbols "" to "" are used to represent related sequences corresponding to MRB.
The method comprises the following specific steps:
s1, performing CRC (cyclic redundancy check) coding on an information sequence before transmission, and performing LDPC coding;
s2, transmitting the sequence obtained by LDPC coding through an AWGN channel;
s3, the receiving end receives the transmitted information and then decodes the information, and the specific method comprises the following steps:
a. obtaining MRB sequence m by OSD decoding method 0 ；
b. At m 0 Optionally selecting l bits for overturn, and recording all possible overturned information sequencesStoring the code set to obtain total +.>Code sets of candidate information sequences, wherein L is more than or equal to 0 and less than or equal to L, L is an order, t is a positive integer, and K+r is m 0 K is the length of the transmitted information sequence, and r is the length of the CRC check bit;
c. sequentially extracting a candidate information sequence from the code setLet it and generate matrix G 2 Multiplying to obtain corresponding codeword estimate, denoted +.>I.e. < ->Wherein G is 2 Is a permutation generation matrix;
d. estimation of current codewordPerforming a back-substitution to obtain a codeword estimate +.>I.e.Wherein lambda is 1 、λ 2 Is a replacement relationship;
e. from the slaveExtracting information sequence estimation +.>And according to G_crc pair->Performing CRC check, wherein G_crc is a CRC generator polynomial; if->If the CRC check is satisfied, the corresponding codeword is estimated +.>Store in list, otherwise consider information sequence estimate +.>Error, discard the corresponding codeword estimate +.>
f. Judging whether the code word sequence in the list has reached the set list length Len, if the element in the list has reached Len, or the number of the candidate information sequences for recoding has reached P t Step g, turning to step g at this time; otherwise, turning to step c, selecting a new candidate information sequence for recoding and checking;
g. calculating all candidate codewords in the listThe Euclidean distance between the code word and the original receiving sequence y, selecting the code word with the minimum Euclidean distance as the final decoding output +.>
The beneficial effects of the invention are mainly reflected by two points:
1. in the CRC auxiliary OSD decoding method provided by the invention, different from the method of selecting only by Euclidean distance in the original OSD decoding method, the obtained candidate codeword estimation in the CRC auxiliary OSD decoding method needs to be checked by CRC codes, then the list is used for storing the codeword passing the CRC check, and then the most likely codeword estimation is selected as decoding output through Euclidean distance calculation of the candidate codeword and the receiving sequence in the list. The mode of selecting and outputting the code word not only passes the CRC check, but also adopts the Euclidean distance to carry out comparison and judgment, thus the code word output is more accurate than the original OSD decoding method in terms of positioning the correct code word, and the error code performance is improved.
2. In the CRC auxiliary OSD decoding method provided by the invention, a prepared output codeword list is used for storing candidate codewords passing CRC check, and the list length is set to be Len, which is mainly used for reducing the error probability of non-error detection of CRC check. The longer the length of the list is, the more codeword estimation sequences are used for calculating the Euclidean distance, the more probability is that correct codewords are obtained, the lower the bit error rate is, and the higher the calculation complexity is; conversely, the shorter the list length, the higher the bit error rate and the lower the computational complexity. Therefore, in the CRC auxiliary OSD decoding method provided by the invention, the setting of the list length Len can be used for balancing the error code performance and the decoding complexity.
Drawings
FIG. 1 is a flow chart illustrating an implementation of a CRC-assisted OSD decoding method of an LDPC code according to the present invention;
FIG. 2 is a graph of block error rate performance of a (64, 32) LDPC code under different decoding methods;
FIG. 3 is a graph of block error rate performance of (64,48) LDPC codes under different decoding methods;
fig. 4 is a graph of block error rate performance of (128,96) LDPC codes under different decoding methods.
Detailed Description
The following describes the technical scheme of the present invention in detail with reference to the accompanying drawings and simulation examples:
fig. 1 shows a flow chart of an implementation of the CRC-assisted OSD decoding method of an LDPC code according to the present invention, that is, before decoding starts, a length of a preliminary output codeword list is set to Len. And obtaining an MRB sequence through OSD decoding, and performing heuristic overturn on the MRB. Recoding and replacing a certain sequence after overturning to obtain corresponding codeword estimation, performing CRC, and storing the codeword estimation passing the CRC into a list until the list is full or all possible overturned sequences are recoded. Thereafter, instead of calculating new codeword estimates, the Euclidean distances between the codeword estimates in the list and the received sequence are calculated, respectively, and the codeword with the smallest Euclidean distance is obtained as a decoding output.
The LDPC code constructed by PEG is simulated, the channel model adopts the mean value of 0 and the variance of sigma 2 The modulation mode is BPSK modulation. The method is mainly characterized in that an OSD decoding method and a CRC auxiliary OSD decoding method are respectively adopted for simulation aiming at LDPC codes with different code length code rates, wherein the number of OSD orders is 3.
Fig. 2 and 3 show the block error performance curves of the (64, 32) LDPC code and the (64,48) LDPC code when decoding by two methods, OSD and CRC-assisted OSD, respectively, wherein the CRC check bit used in the CRC-assisted OSD decoding method is 11 bits, and the corresponding CRC generation polynomial is [ 11 10 0 0 10 0 0 0 1]. The adopted list length is different according to the signal-to-noise ratio, and when the signal-to-noise ratio of the (64, 32) LDPC code is smaller than or equal to 4dB, the adopted list length Len=4; when the signal-to-noise ratio is greater than 4, the adopted list length len=3; (64,48) when the signal-to-noise ratio is less than or equal to 4dB, the adopted list length len=10; when the signal-to-noise ratio is greater than 4, the employed list length len=3.
As can be seen from fig. 2 and 3, the LDPC code has a lower block error rate than the OSD decoding method when using the CRC-assisted OSD decoding method under most signal-to-noise conditions. The block error rate is 10 -4 When (64, 32) LDPC adopts CRC auxiliary OSD decoding method to compare with OSD decoding method, it has 0.13dB performance gain. The block error rate is 10 -3 When compared with the OSD decoding method, the (64,48) LDPC adopts the CRC auxiliary OSD decoding method to have 0.2dB performance gain. In addition, as the signal-to-noise ratio increases, the more significant the error performance advantage of the CRC-aided OSD decoding method over OSD.
Tables 1 and 2 respectively count the number of test error patterns (Test Error Patterns, TEPs) involved in the recoding process when the (64, 32) LDPC code and the (64,48) LDPC code adopt an OSD decoding method and a CRC-aided OSD decoding method, wherein the complexity of OSD decoding in the recoding link is smaller as the number of TEPs is smaller. It can be found from the table that the number of TEPs in the OSD decoding method is determined by the order and is the same at each signal-to-noise ratio point, while the number of TEPs in the CRC-assisted OSD decoding method is mainly determined by the list length Len, the smaller the list length, the smaller the number of TEPs involved in recoding. From the data in tables 1 and 2, it is found that the LDPC code with code length 64 achieves better error code performance than OSD under the condition of low signal-to-noise ratio by adopting CRC auxiliary OSD decoding method, the number of required TEPs is slightly more than that of OSD, and under the condition of high signal-to-noise ratio, the better decoding performance can be obtained by using fewer TEPs than original OSD to participate in recoding.
Fig. 4 and table 3 respectively count (128,96) the block error rate performance curve and the number of TEPs involved in the recoding process when the OSD and the CRC-assisted OSD decoding method are adopted for the LDPC code, wherein the CRC check bit adopted in the CRC-assisted OSD decoding method is 11 bits, and the corresponding CRC generation polynomial is [ 11 10 0 0 10 0 0 0 1]. It can be seen from fig. 4 that the trend of the block error rate is substantially consistent with that of the LDPC code with the code length of 64, and the block error rate of the CRC-assisted OSD decoding method is lower than that of OSD. It can be found from table 3 that by setting a reasonable list length Len, the (128,96) LDPC code adopts the CRC-assisted OSD decoding method to participate in recoding, and can obtain better decoding performance, so that the complexity of the OSD decoding method in recoding can be reduced.
TABLE 1 number of TEPs involved in recoding when LDPC codes (64, 32) employ different decoding methods
TABLE 2 (64,48) number of TEPs involved in recoding when LDPC codes employ different decoding methods
TABLE 3 (128,96) number of TEPs involved in recoding when LDPC codes employ different decoding methods
In summary, from the above groups of simulation result data, the CRC-assisted OSD decoding method of the LDPC code provided by the invention can obtain better error code performance than the OSD decoding method with the same order. Meanwhile, in the CRC auxiliary OSD decoding method, by setting a reasonable list length Len, the method can realize better error code performance by only needing fewer TEPs to participate in recoding than the original OSD, and simultaneously reduces the complexity of the OSD decoding recoding link.

Claims (1)

1. A CRC-aided OSD decoding method of an LDPC code, comprising the steps of:
s1, performing CRC (cyclic redundancy check) coding on an information sequence before transmission, and performing LDPC coding;
s2, transmitting the sequence obtained by LDPC coding through an AWGN channel;
s3, the receiving end receives the transmitted information and then decodes the information, and the specific method comprises the following steps:
a. obtaining MRB sequence m by OSD decoding method 0 ；
b. At m 0 Optionally selecting l bits for overturn, and recording all possible overturned information sequencesStoring the code set to obtain total +.>Code sets of candidate information sequences, wherein L is more than or equal to 0 and less than or equal to L, L is an order, t is a positive integer, and K+r is m 0 K is the length of the transmitted information sequence, and r is the length of the CRC check bit;
c. sequentially taking from code setTo generate candidate information sequenceLet it and generate matrix G 2 Multiplying to obtain corresponding codeword estimate, denoted +.>I.e. < ->Wherein G is 2 Is a permutation generation matrix;
d. estimation of current codewordPerforming a back-substitution to obtain a codeword estimate +.>I.e.Wherein lambda is 1 、λ 2 Is a replacement relationship;
e. from the slaveExtracting information sequence estimation +.>And according to G_crc pair->Performing CRC check, wherein G_crc is a CRC generator polynomial; if->If the CRC check is satisfied, the corresponding codeword is estimated +.>Store in list, otherwise consider information sequence estimate +.>Error, discard the corresponding codeword estimate +.>
f. Judging whether the code word sequence in the list has reached the set list length Len, if the element in the list has reached Len, or the number of the candidate information sequences for recoding has reached P t Step g, turning to step g at this time; otherwise, turning to step c, selecting a new candidate information sequence for recoding and checking;
g. calculating all candidate codewords in the listThe Euclidean distance between the code word and the original receiving sequence y, selecting the code word with the minimum Euclidean distance as the final decoding output +.>
CN202310678635.6A 2023-06-09 2023-06-09 CRC auxiliary OSD decoding method of LDPC code Pending CN116760425A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117527150A (en) * 2023-12-29 2024-02-06 哈尔滨工业大学(深圳)(哈尔滨工业大学深圳科技创新研究院) Order statistics decoding method, device, equipment and medium based on turnover weight

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117527150A (en) * 2023-12-29 2024-02-06 哈尔滨工业大学(深圳)(哈尔滨工业大学深圳科技创新研究院) Order statistics decoding method, device, equipment and medium based on turnover weight
CN117527150B (en) * 2023-12-29 2024-04-12 哈尔滨工业大学(深圳)(哈尔滨工业大学深圳科技创新研究院) Order statistics decoding method, device, equipment and medium based on turnover weight

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