CN116759458B - Gallium oxide junction field effect transistor and preparation method thereof - Google Patents
Gallium oxide junction field effect transistor and preparation method thereof Download PDFInfo
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Abstract
The invention relates to the technical field of semiconductors, in particular to a gallium oxide junction field effect transistor and a preparation method thereof, and aims to solve the problem that the conventional gallium oxide is difficult to effectively doped with P type and the performance of the junction field effect transistor is greatly affected. Therefore, the gallium oxide junction field effect transistor of the invention uses the first doped semiconductor epitaxial layer as the gate region, and the first doped semiconductor epitaxial layer at least covers the upper surface exposed by the flat part of the fin type gallium oxide drift layer and is different from the material of the fin type gallium oxide drift layer, so that the problem that effective P type doping is difficult in the prior art is avoided, good gate control characteristics can be ensured, and the performance of the junction field effect transistor is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, and particularly provides a gallium oxide junction field effect transistor and a preparation method thereof.
Background
Gallium oxide has received extensive attention and has been used in the preparation of semiconductor devices because of its excellent characteristics such as wide forbidden band, withstand voltage, stability, etc. For example, junction field effect transistors may be fabricated based on gallium oxide. When the junction field effect transistor is prepared based on gallium oxide, a P-type doped region can be formed on N-type gallium oxide in an ion implantation mode, but the performance of the junction field effect transistor is greatly affected due to the difficulty in performing effective P-type doping on gallium oxide.
Disclosure of Invention
The invention aims to solve the technical problems that the conventional gallium oxide is difficult to be doped effectively in a P type manner and the performance of a junction field effect transistor is greatly affected.
In a first aspect, the present invention provides a gallium oxide junction field effect transistor comprising:
a gallium oxide substrate of a first conductivity type;
a first electrode layer on the first surface of the gallium oxide substrate;
a fin gallium oxide drift layer on a second surface of the gallium oxide substrate opposite the first surface; the fin-type gallium oxide drift layer comprises a fin portion and a flat portion, and is of a first conductivity type;
a first doped semiconductor epitaxial layer covering at least the exposed upper surface of the flat portion, the first doped semiconductor epitaxial layer being of a second conductivity type, the first doped semiconductor epitaxial layer being of a different material than the fin gallium oxide drift layer;
a gate electrode layer on the first doped semiconductor epitaxial layer; the method comprises the steps of,
and the second electrode layer is positioned on the upper surface of the fin part.
In some embodiments, further comprising:
and the second doped semiconductor epitaxial layer at least covers the first doped semiconductor epitaxial layer, and the second doped semiconductor epitaxial layer is of a first conductive type or is of a second conductive type and has a doping concentration smaller than that of the first doped semiconductor epitaxial layer.
In some embodiments, the first doped semiconductor epitaxial layer covers an upper surface of the planar portion that is exposed.
In some embodiments, the second doped semiconductor epitaxial layer conformally covers the first doped semiconductor epitaxial layer and sidewalls of the fin.
In some embodiments, the second doped semiconductor epitaxial layer covers the first doped semiconductor epitaxial layer and the second doped semiconductor epitaxial layer is flush with an upper surface of the fin.
In some embodiments, the first doped semiconductor epitaxial layer conformally covers the exposed upper surface of the planar portion and the sidewalls of the fin portion.
In some embodiments, the second doped semiconductor epitaxial layer conformally covers the first doped semiconductor epitaxial layer.
In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type.
In a second aspect, the present invention provides a method for preparing a gallium oxide junction field effect transistor, comprising:
forming a first electrode layer on a first surface of a gallium oxide substrate;
forming a gallium oxide drift layer on a second surface of the gallium oxide substrate opposite to the first surface, wherein the gallium oxide substrate and the gallium oxide drift layer are both of a first conductivity type;
patterning the gallium oxide drift layer to obtain a fin-type gallium oxide drift layer; the fin-type gallium oxide drift layer comprises a fin portion and a flat portion;
epitaxially growing a first doped semiconductor epitaxial layer at least covering the upper surface exposed by the flat part, wherein the first doped semiconductor epitaxial layer is of a second conductivity type, and the first doped semiconductor epitaxial layer is different from the fin gallium oxide drift layer in material;
forming a gate electrode layer on the first doped semiconductor epitaxial layer;
and forming a second electrode layer on the upper surface of the fin part.
In some embodiments, prior to forming a gate electrode layer on the first doped semiconductor epitaxial layer, the method further comprises:
and epitaxially growing a second doped semiconductor epitaxial layer at least covering the first doped semiconductor epitaxial layer, wherein the second doped semiconductor epitaxial layer is of a first conductivity type, or the second doped semiconductor epitaxial layer is of a second conductivity type and has a doping concentration smaller than that of the first doped semiconductor epitaxial layer.
Under the condition of adopting the technical scheme, the first doped semiconductor epitaxial layer can be used as the grid electrode area, and the first doped semiconductor epitaxial layer at least covers the upper surface exposed by the flat part of the fin type gallium oxide drift layer and is different from the material of the fin type gallium oxide drift layer, so that the problem that effective P type doping is difficult in the prior art is avoided, good grid control characteristics can be ensured, and the performance of the junction type field effect transistor is improved.
Drawings
Preferred embodiments of the present invention are described below with reference to the accompanying drawings, in which:
fig. 1 is a schematic side view of a gallium oxide junction field effect transistor according to an embodiment of the present invention;
fig. 2 is a schematic side view of a gan junction field effect transistor according to another embodiment of the present invention;
fig. 3 is a schematic side view of a gallium oxide junction field effect transistor forming a reverse-biased PN structure according to an embodiment of the present invention;
fig. 4 is a schematic side view of a gallium oxide junction field effect transistor forming a reverse-biased PN structure according to another embodiment of the present invention;
fig. 5 is a schematic side view of a gallium oxide junction field effect transistor forming a reverse-biased PN structure according to another embodiment of the present invention;
fig. 6 is a schematic side view of a gan junction field effect transistor with schottky contact according to an embodiment of the present invention;
fig. 7 is a schematic side view of a gan junction field effect transistor with schottky contact according to another embodiment of the present invention;
fig. 8 is a schematic flow chart of a method for manufacturing a gallium oxide junction field effect transistor according to an embodiment of the invention.
Detailed Description
Some embodiments of the invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are merely for explaining the technical principles of the present invention, and are not intended to limit the scope of the present invention.
In the description of the present invention, it should be noted that directions or positional relationships indicated as being "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. are directions or positional relationships described based on the drawings are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Moreover, use of ordinal words (e.g., "first," "second," etc.) are used to distinguish between objects, and are not limited to this order, but rather are not to be construed to indicate or imply relative importance.
As described in the background section, the existing efficient P-type doping of gallium oxide is difficult, greatly affecting the performance of junction field effect transistors. In view of this, the present invention provides a gallium oxide junction field effect transistor that may include a gallium oxide substrate of a first conductivity type; a first electrode layer on the first surface of the gallium oxide substrate; a fin gallium oxide drift layer on a second surface of the gallium oxide substrate opposite the first surface; the fin-type gallium oxide drift layer comprises a fin portion and a flat portion, and is of a first conductivity type; the first doped semiconductor epitaxial layer at least covers the upper surface exposed by the flat part, the first doped semiconductor epitaxial layer is of a second conductivity type, and the first doped semiconductor epitaxial layer is different from the fin gallium oxide drift layer in material; a gate electrode layer on the first doped semiconductor epitaxial layer; and a second electrode layer positioned on the upper surface of the fin part. By forming the first doped semiconductor epitaxial layer with a material different from that of the fin-type gallium oxide drift layer, the problem that effective P-type doping is difficult in the prior art is avoided, good gate control characteristics can be ensured, and the performance of the junction field effect transistor is improved.
In some embodiments, the first doped semiconductor epitaxial layer may cover only the exposed upper surface of the flat portion, and particularly, as shown in fig. 1, fig. 1 is a schematic side view structure of a gallium oxide junction field effect transistor according to an embodiment of the present invention, which may include:
a gallium oxide substrate 10 of a first conductivity type;
a first electrode layer 11 on the first surface of the gallium oxide substrate 10;
a fin gallium oxide drift layer 12 on a second surface of the gallium oxide substrate 10 opposite the first surface; the fin gallium oxide drift layer 12 includes a fin 121 and a flat 122, and the fin gallium oxide drift layer 12 is of a first conductivity type;
a first doped semiconductor epitaxial layer 13 covering the upper surface exposed by the flat portion 122, the first doped semiconductor epitaxial layer 13 being of the second conductivity type, the first doped semiconductor epitaxial layer 13 being of a different material than the fin gallium oxide drift layer 12;
a gate electrode layer 14 on the first doped semiconductor epitaxial layer 13; the method comprises the steps of,
and the second electrode layer 15 is positioned on the upper surface of the fin 121.
In some embodiments, the first conductivity type may be N-type, the second conductivity type may be P-type, and the gallium oxide substrate 10 may be N+ -doped Ga 2 O 3 A substrate.
In some embodiments, the first electrode layer 11 may be made by depositing at least one of Ni, au, ti, al, mo and Cu by means of magnetron sputtering or electron beam evaporation.
In some embodiments, where the first conductivity type is N-type, the fin gallium oxide drift layer 12 may be N-type doped Ga 2 O 3 A layer. In some embodiments, a chemical vapor deposition, physical vapor deposition, or atomic layer deposition method may be used to deposit a gallium oxide drift layer on the gallium oxide substrate 10, and then etching a portion of the gallium oxide drift layer to obtain the fin gallium oxide drift layer 12.
In some embodiments, the P-type doped first doped semiconductor epitaxial layer 13 may be formed on the flat portion 122 by a heteroepitaxial growth method, in some embodiments, the first doped semiconductor epitaxial layer 13 may be a p+ type doped GaN layer or a NiO layer, and in other embodiments, the first doped semiconductor epitaxial layer 13 may be another suitable semiconductor material layer.
As an example, a p+ -type doped GaN layer may be formed on the upper surface of the flat portion 122 exposed by any one of a hydride epitaxial growth method, a molecular beam epitaxy method, and a metal organic chemical vapor deposition method as the first doped semiconductor epitaxial layer 13.
The hetero PN junction is formed between the first doped semiconductor epitaxial layer 13 and the fin gallium oxide drift layer 12, the gate electrode layer 14 can control the on and off of the gallium oxide junction field effect transistor by changing the width of the depletion region of the hetero PN junction, the problem that the P type doping is difficult to form in the gallium oxide drift layer in an ion implantation mode in the prior art is avoided, good gate control characteristics can be ensured, and the performance of the junction field effect transistor is improved.
In some embodiments, the gate electrode layer 14 may be made by depositing at least one of Ni, au, ti, al, mo and Cu by means of magnetron sputtering or electron beam evaporation.
In some embodiments, the second electrode layer 15 may be made by depositing at least one of Ni, au, ti, al, mo and Cu by means of magnetron sputtering or electron beam evaporation.
In some embodiments, the first electrode layer 11 may be a source electrode and the second electrode layer 15 may be a drain electrode; in other embodiments, the first electrode layer 11 may be a drain electrode, and the second electrode layer 15 may be a source electrode, which may be specifically set according to practical requirements.
In other embodiments, the first conductivity type may be P-type, and the second conductivity type may be N-type, and accordingly, a gallium oxide drift layer may be formed on the gallium oxide substrate 10 by using an epitaxial growth method, and the fin gallium oxide drift layer 12 is obtained by etching the gallium oxide drift layer.
In some embodiments, referring to fig. 2, the first doped semiconductor epitaxial layer 13' covering the exposed upper surface of the flat portion 122 and the sidewalls of the fin portion 121 in a conformal manner may also be formed by a heteroepitaxial growth method.
In some embodiments, the first doped semiconductor epitaxial layer 13 'may be a p+ doped GaN layer or a NiO layer, and in other embodiments, the first doped semiconductor epitaxial layer 13' may be another suitable semiconductor material layer.
As an example, a p+ -type doped GaN layer may be formed as the first doped semiconductor epitaxial layer 13' on the exposed upper surface of the flat portion 122 and the sidewall of the fin portion 121 by any one of a hydride epitaxial growth method, a molecular beam epitaxy method, and a metal organic chemical vapor deposition method.
In some embodiments, in order to further improve the withstand voltage capability of the gate of the gallium oxide junction field effect transistor and improve the maximum gate voltage allowed by the gate, a second doped semiconductor epitaxial layer covering at least the first doped semiconductor epitaxial layer may be further formed, where the second doped semiconductor epitaxial layer is of the first conductivity type, or where the second doped semiconductor epitaxial layer is of the second conductivity type and has a doping concentration smaller than that of the first doped semiconductor epitaxial layer, which will be described in detail in the following embodiments.
Referring to fig. 3, fig. 3 is a schematic side view of a gallium oxide junction field effect transistor forming a reverse-biased PN structure according to an embodiment of the present invention, which may include:
a gallium oxide substrate 10 of a first conductivity type;
a first electrode layer 11 on the first surface of the gallium oxide substrate 10;
a fin gallium oxide drift layer 12 on a second surface of the gallium oxide substrate 10 opposite the first surface; the fin gallium oxide drift layer 12 includes a fin 121 and a flat 122, and the fin gallium oxide drift layer 12 is of a first conductivity type;
a first doped semiconductor epitaxial layer 13 covering the upper surface exposed by the flat portion 122, the first doped semiconductor epitaxial layer 13 being of the second conductivity type, the first doped semiconductor epitaxial layer 13 being of a different material than the fin gallium oxide drift layer 12;
a second doped semiconductor epitaxial layer 16A conformally covering the first doped semiconductor epitaxial layer 13 and the sidewalls of the fin 121; the second doped semiconductor epitaxial layer 16A is of the first conductivity type;
a gate electrode layer 14 on the second doped semiconductor epitaxial layer 13; the method comprises the steps of,
and the second electrode layer 15 is positioned on the upper surface of the fin 121.
The gallium oxide substrate 10, the first electrode layer 11, the fin gallium oxide drift layer 12, the first doped semiconductor epitaxial layer 13, and the second electrode layer 15 may be made of the same materials and by the same manufacturing method as those of the embodiment corresponding to fig. 1. For brevity, details are not described here again, and reference is made specifically to the description above.
In the embodiment of the present invention, the second doped semiconductor epitaxial layer 16A is of the first conductivity type, the first conductivity type is N-type, and when the second conductivity type is P-type, the second doped semiconductor epitaxial layer 16A and the first doped semiconductor epitaxial layer 13 form a reverse bias PN structure, so that the maximum gate voltage allowed by the gate can be increased, and the voltage withstand capability of the gate can be improved, thereby improving the performance of the device.
In some embodiments, the second doped semiconductor epitaxial layer 16A may be the same or different material as the first doped semiconductor epitaxial layer 13, and as an example, the second doped semiconductor epitaxial layer 16A may be an N-type doped GaN layer or NiO layer.
In some embodiments, the second doped semiconductor epitaxial layer 16A of N-type doping may be formed using any one of a hydride epitaxial growth method, a molecular beam epitaxy method, or a metal organic chemical vapor deposition method.
In some embodiments, the gate electrode layer 14 may be formed by depositing at least one of Ni, au, ti, al, mo and Cu on the second doped semiconductor epitaxial layer 16A by magnetron sputtering or electron beam evaporation, wherein the front projections of the gate electrode layer 14 and the first doped semiconductor epitaxial layer 13 on the gallium oxide substrate 10 at least partially overlap. In other embodiments, the second doped semiconductor epitaxial layer may cover only the first doped semiconductor epitaxial layer 13.
In other embodiments, referring to fig. 4, a second doped semiconductor epitaxial layer 16B may also be formed on the first doped semiconductor epitaxial layer 13 by an epitaxial growth method, the second doped semiconductor epitaxial layer 16B being flush with the upper surface of the fin 121.
The thicknesses of the first doped semiconductor epitaxial layer 13 and the second doped semiconductor epitaxial layer 16B may be the same or different, and may be specifically set according to practical requirements.
In other embodiments, referring to fig. 5, fig. 5 is a schematic side view of a gallium oxide junction field effect transistor forming a reverse-biased PN structure according to another embodiment of the present invention, which may include:
a gallium oxide substrate 10 of a first conductivity type;
a first electrode layer 11 on the first surface of the gallium oxide substrate 10;
a fin gallium oxide drift layer 12 on a second surface of the gallium oxide substrate 10 opposite the first surface; the fin gallium oxide drift layer 12 includes a fin 121 and a flat 122, and the fin gallium oxide drift layer 12 is of a first conductivity type;
the first doped semiconductor epitaxial layer 13 'is of a second conductivity type and covers the upper surface exposed by the flat portion 122 and the side wall of the fin portion 121, and the first doped semiconductor epitaxial layer 13' is of a different material from the fin gallium oxide drift layer 12;
a second doped semiconductor epitaxial layer 16C conformally covering the first doped semiconductor epitaxial layer 13'; the second doped semiconductor epitaxial layer 16C is of the first conductivity type;
a gate electrode layer 14 on the second doped semiconductor epitaxial layer 16C; the method comprises the steps of,
and the second electrode layer 15 is positioned on the upper surface of the fin 121.
The gallium oxide substrate 10, the first electrode layer 11, the fin gallium oxide drift layer 12, the first doped semiconductor epitaxial layer 13', the gate electrode layer 14, the second electrode layer 15, and the second doped semiconductor epitaxial layer 16C may be made of the same materials and by the same manufacturing method as those of the embodiment shown in fig. 3. For brevity, details are not described here again, and reference is made specifically to the description above.
The gallium oxide junction field effect transistor forming the reverse bias PN structure is favorable for providing a larger gate voltage range, but the preparation process is relatively complex and the cost is relatively high. Based on this, in another aspect of the present invention, there is also provided a gallium oxide junction field effect transistor forming a schottky contact, particularly as will be described below.
Referring to fig. 6, fig. 6 is a schematic side view of a gallium oxide junction field effect transistor with schottky contact according to an embodiment of the invention, which may include:
a gallium oxide substrate 10 of a first conductivity type;
a first electrode layer 11 on the first surface of the gallium oxide substrate 10;
a fin gallium oxide drift layer 12 on a second surface of the gallium oxide substrate 10 opposite the first surface; the fin gallium oxide drift layer 12 includes a fin 121 and a flat 122, and the fin gallium oxide drift layer 12 is of a first conductivity type;
a first doped semiconductor epitaxial layer 13 covering the upper surface exposed by the flat portion 122, the first doped semiconductor epitaxial layer 13 being of the second conductivity type, the first doped semiconductor epitaxial layer 13 being of a different material than the fin gallium oxide drift layer 12;
a second doped semiconductor epitaxial layer 16a of a second conductivity type covering the first doped semiconductor epitaxial layer 13; the doping concentration of the second doped semiconductor epitaxial layer 16a is smaller than the doping concentration of the first doped semiconductor epitaxial layer 13;
a gate electrode layer 14 on the second doped semiconductor epitaxial layer 16a; the method comprises the steps of,
and the second electrode layer 15 is positioned on the upper surface of the fin 121.
The gallium oxide substrate 10, the first electrode layer 11, the fin gallium oxide drift layer 12, the first doped semiconductor epitaxial layer 13, and the second electrode layer 15 may be made of the same materials and by the same manufacturing method as those of the embodiment corresponding to fig. 2. For brevity, details are not described here again, and reference is made specifically to the description above.
In some embodiments, the second doped semiconductor epitaxial layer 16a may be a P-type doped semiconductor epitaxial layer, the first doped semiconductor epitaxial layer 13 may be a p+ type doped semiconductor epitaxial layer, and schottky contact is formed between the second doped semiconductor epitaxial layer 16a and the gate electrode layer 14, so that the maximum allowable gate voltage of the gate may be increased, and the voltage withstand capability of the gate may be improved, thereby improving the performance of the device. In addition, the p+ doped first doped semiconductor epitaxial layer 13 can also effectively avoid gate voltage breakdown.
In other embodiments, the second doped semiconductor epitaxial layer of the second conductivity type may also conformally cover the first doped semiconductor epitaxial layer 13 and the sidewalls of the fin 121.
In some embodiments, the gate electrode layer 14 may be formed by depositing at least one of Ni, au, ti, al, mo and Cu on the second doped semiconductor epitaxial layer 16a by magnetron sputtering or electron beam evaporation, wherein the front projections of the gate electrode layer 14 and the first doped semiconductor epitaxial layer 13 on the gallium oxide substrate 10 overlap.
In other embodiments, referring to fig. 7, fig. 7 is a schematic side view of a gallium oxide junction field effect transistor with schottky contact according to another embodiment of the present invention, which may include:
a gallium oxide substrate 10 of a first conductivity type;
a first electrode layer 11 on the first surface of the gallium oxide substrate 10;
a fin gallium oxide drift layer 12 on a second surface of the gallium oxide substrate 10 opposite the first surface; the fin gallium oxide drift layer 12 includes a fin 121 and a flat 122, and the fin gallium oxide drift layer 12 is of a first conductivity type;
the first doped semiconductor epitaxial layer 13' covers the upper surface exposed by the flat portion 122 and the side wall of the fin portion 121, the first doped semiconductor epitaxial layer 13' is of the second conductivity type, and the first doped semiconductor epitaxial layer 13' is different from the fin gallium oxide drift layer 12 in material;
a second doped semiconductor epitaxial layer 16b of the second conductivity type conformal over the first doped semiconductor epitaxial layer 13'; the doping concentration of the second doped semiconductor epitaxial layer 16b is less than the doping concentration of the first doped semiconductor epitaxial layer 13';
a gate electrode layer 14 on the second doped semiconductor epitaxial layer 16b; the method comprises the steps of,
and the second electrode layer 15 is positioned on the upper surface of the fin 121.
The gallium oxide substrate 10, the first electrode layer 11, the fin gallium oxide drift layer 12, the first doped semiconductor epitaxial layer 13', the gate electrode layer 14, the second electrode layer 15, and the second doped semiconductor epitaxial layer 16b may be made of the same materials and by the same manufacturing method as those of the embodiment shown in fig. 6. For brevity, details are not described here again, and reference is made specifically to the description above.
In another aspect of the present invention, there is provided a method for preparing a gallium oxide junction field effect transistor, as shown in fig. 8, which may include:
step S81: forming a first electrode layer on a first surface of a gallium oxide substrate;
step S82: forming a gallium oxide drift layer on a second surface of the gallium oxide substrate opposite to the first surface, wherein the gallium oxide substrate and the gallium oxide drift layer are of a first conductivity type;
step S83: patterning the gallium oxide drift layer to obtain a fin-type gallium oxide drift layer; the fin-type gallium oxide drift layer comprises a fin part and a flat part;
step S84: epitaxially growing a first doped semiconductor epitaxial layer which at least covers the upper surface exposed by the flat part, wherein the first doped semiconductor epitaxial layer is of a second conductivity type, and the first doped semiconductor epitaxial layer is different from the fin gallium oxide drift layer in material;
step S85: forming a gate electrode layer on the first doped semiconductor epitaxial layer;
step S86: and forming a second electrode layer on the upper surface of the fin part.
In some embodiments, step S81 may specifically be to form a first electrode layer on the first surface of the gallium oxide substrate by means of magnetron sputtering or electron beam evaporation.
In some embodiments, the first electrode layer may be at least one of Ni, au, ti, al, mo and Cu.
In some embodiments, the first conductivity type may be N-type, the second conductivity type may be P-type, and the gallium oxide substrate may be N+ -doped Ga 2 O 3 The gallium oxide drift layer may be N-doped Ga 2 O 3 A layer.
In some embodiments, step S82 may specifically be depositing a gallium oxide drift layer on a gallium oxide substrate using a chemical vapor deposition, physical vapor deposition, or atomic layer deposition method.
In some embodiments, step S83 may specifically be to form a mask on the gallium oxide drift layer, transfer the pattern of the mask onto the gallium oxide drift layer through exposure and development, and finally obtain the fin-shaped gallium oxide drift layer through etching.
In some embodiments, step S84 may be specifically: and forming a first doped semiconductor epitaxial layer doped with the P type by a heteroepitaxial growth method, wherein the first doped semiconductor epitaxial layer can cover the upper surface exposed by the flat part or cover the upper surface exposed by the flat part and the side wall of the fin part.
In some embodiments, the first doped semiconductor epitaxial layer may be a p+ doped GaN layer or a NiO layer, and in other embodiments, the first doped semiconductor epitaxial layer may be another suitable semiconductor material layer.
As an example, a p+ -type doped GaN layer may be formed on the upper surface of the flat portion exposed by any one of a hydride epitaxial growth method, a molecular beam epitaxy method, and a metal organic chemical vapor deposition method as the first doped semiconductor epitaxial layer.
A hetero PN junction is formed between the first doped semiconductor epitaxial layer and the fin gallium oxide drift layer, the gate electrode layer can control the on and off of the gallium oxide junction field effect transistor by changing the width of a depletion region of the hetero PN junction, the problem that in the prior art, P-type doping is formed in the gallium oxide drift layer in an ion implantation mode and the effective P-type doping is difficult is avoided, good gate control characteristics can be ensured, and the performance of the junction field effect transistor is improved.
In some embodiments, step S85 may specifically be to manufacture the gate electrode layer by depositing at least one material of Ni, au, ti, al, mo and Cu by means of magnetron sputtering or electron beam evaporation.
In some embodiments, step S86 may specifically be to manufacture the second electrode layer by depositing at least one material of Ni, au, ti, al, mo and Cu by means of magnetron sputtering or electron beam evaporation.
In some embodiments, the first electrode layer may be a source electrode and the second electrode layer may be a drain electrode; in other embodiments, the first electrode layer may be a drain electrode, and the second electrode layer may be a source electrode, which may be specifically set according to practical requirements.
In other embodiments, the method may further include, after step S84 and before step S85:
and epitaxially growing a second doped semiconductor epitaxial layer at least covering the first doped semiconductor epitaxial layer, wherein the second doped semiconductor epitaxial layer is of the first conductivity type, or the second doped semiconductor epitaxial layer is of the second conductivity type and has a doping concentration smaller than that of the first doped semiconductor epitaxial layer.
The second doped semiconductor epitaxial layer may be formed by any one of a hydride epitaxial growth method, a molecular beam epitaxy method, or a metal organic chemical vapor deposition method.
In some embodiments, the second doped semiconductor epitaxial layer may be the same or different material as the first doped semiconductor epitaxial layer, and as an example, the second doped semiconductor epitaxial layer may be an N-type doped GaN layer or NiO layer.
When the second doped semiconductor epitaxial layer is of the first conductivity type, the first conductivity type is N type, and the second conductivity type is P type, the second doped semiconductor epitaxial layer and the first doped semiconductor epitaxial layer form a reverse bias PN structure, so that the maximum gate voltage allowed by the gate can be improved, the voltage withstand capability of the gate is improved, and the performance of the device is improved.
When the second doped semiconductor epitaxial layer is of the first conductivity type, the first conductivity type is N type, and the second conductivity type is P type, the second doped semiconductor epitaxial layer can be a P-type doped semiconductor epitaxial layer, the first doped semiconductor epitaxial layer can be a P+ type doped semiconductor epitaxial layer, schottky contact is formed between the second doped semiconductor epitaxial layer and the gate electrode layer, maximum gate voltage allowed by a gate can be improved, and voltage resistance of the gate is improved, so that performance of a device is improved. In addition, the P+ type doped first doped semiconductor epitaxial layer can also effectively avoid gate voltage breakdown.
Thus far, the technical solution of the present invention has been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of protection of the present invention is not limited to these specific embodiments. Equivalent modifications and substitutions for related technical features may be made by those skilled in the art without departing from the principles of the present invention, and such modifications and substitutions will fall within the scope of the present invention.
Claims (8)
1. A gallium oxide junction field effect transistor, comprising:
a gallium oxide substrate of a first conductivity type;
a first electrode layer on the first surface of the gallium oxide substrate;
a fin gallium oxide drift layer on a second surface of the gallium oxide substrate opposite the first surface; the fin-type gallium oxide drift layer comprises a fin portion and a flat portion, and is of a first conductivity type;
a first doped semiconductor epitaxial layer covering at least the exposed upper surface of the flat portion, the first doped semiconductor epitaxial layer being of a second conductivity type, the first doped semiconductor epitaxial layer being of a different material than the fin gallium oxide drift layer;
a gate electrode layer on the first doped semiconductor epitaxial layer; the method comprises the steps of,
the second electrode layer is positioned on the upper surface of the fin part;
further comprises: and the second doped semiconductor epitaxial layer at least covers the first doped semiconductor epitaxial layer, and the second doped semiconductor epitaxial layer is of a first conductive type or is of a second conductive type and has a doping concentration smaller than that of the first doped semiconductor epitaxial layer.
2. The gallium oxide junction field effect transistor of claim 1, wherein the first doped semiconductor epitaxial layer covers an upper surface of the flat portion that is exposed.
3. The gallium oxide junction field effect transistor of claim 2, wherein the second doped semiconductor epitaxial layer conformally covers sidewalls of the first doped semiconductor epitaxial layer and the fin.
4. The gallium oxide junction field effect transistor of claim 2, wherein the second doped semiconductor epitaxial layer overlies the first doped semiconductor epitaxial layer and the second doped semiconductor epitaxial layer is flush with an upper surface of the fin.
5. The gallium oxide junction field effect transistor of claim 1, wherein the first doped semiconductor epitaxial layer conformally covers the exposed upper surface of the planar portion and the sidewalls of the fin portion.
6. The gallium oxide junction field effect transistor of claim 5, wherein the second doped semiconductor epitaxial layer conformally covers the first doped semiconductor epitaxial layer.
7. Gallium oxide junction field effect transistor according to any of claims 1 to 6, characterized in that the first conductivity type is N-type and the second conductivity type is P-type.
8. A method for manufacturing a gallium oxide junction field effect transistor, comprising:
forming a first electrode layer on a first surface of a gallium oxide substrate;
forming a gallium oxide drift layer on a second surface of the gallium oxide substrate opposite to the first surface, wherein the gallium oxide substrate and the gallium oxide drift layer are both of a first conductivity type;
patterning the gallium oxide drift layer to obtain a fin-type gallium oxide drift layer; the fin-type gallium oxide drift layer comprises a fin portion and a flat portion;
epitaxially growing a first doped semiconductor epitaxial layer at least covering the upper surface exposed by the flat part, wherein the first doped semiconductor epitaxial layer is of a second conductivity type, and the first doped semiconductor epitaxial layer is different from the fin gallium oxide drift layer in material;
forming a gate electrode layer on the first doped semiconductor epitaxial layer;
forming a second electrode layer on the upper surface of the fin part;
before forming the gate electrode layer on the first doped semiconductor epitaxial layer, the method further comprises:
and epitaxially growing a second doped semiconductor epitaxial layer at least covering the first doped semiconductor epitaxial layer, wherein the second doped semiconductor epitaxial layer is of a first conductivity type, or the second doped semiconductor epitaxial layer is of a second conductivity type and has a doping concentration smaller than that of the first doped semiconductor epitaxial layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018035044A (en) * | 2016-08-31 | 2018-03-08 | 株式会社Flosfia | Crystalline oxide semiconductor film and semiconductor device |
| CN110112206A (en) * | 2019-05-20 | 2019-08-09 | 中山大学 | A kind of gallium oxide junction field effect transistor |
| CN110148625A (en) * | 2019-05-20 | 2019-08-20 | 中山大学 | A kind of gallium oxide verticle noded type field effect transistor and preparation method thereof |
| CN113257922A (en) * | 2021-05-13 | 2021-08-13 | 电子科技大学 | Multi-channel enhanced gallium oxide junction field effect transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018035044A (en) * | 2016-08-31 | 2018-03-08 | 株式会社Flosfia | Crystalline oxide semiconductor film and semiconductor device |
| CN110112206A (en) * | 2019-05-20 | 2019-08-09 | 中山大学 | A kind of gallium oxide junction field effect transistor |
| CN110148625A (en) * | 2019-05-20 | 2019-08-20 | 中山大学 | A kind of gallium oxide verticle noded type field effect transistor and preparation method thereof |
| CN113257922A (en) * | 2021-05-13 | 2021-08-13 | 电子科技大学 | Multi-channel enhanced gallium oxide junction field effect transistor |
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