CN116759452A - Reverse-conduction IGBT device and preparation method thereof - Google Patents

Reverse-conduction IGBT device and preparation method thereof Download PDF

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Publication number
CN116759452A
CN116759452A CN202310892475.5A CN202310892475A CN116759452A CN 116759452 A CN116759452 A CN 116759452A CN 202310892475 A CN202310892475 A CN 202310892475A CN 116759452 A CN116759452 A CN 116759452A
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region
conductive type
collector region
type collector
reverse
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陈开宇
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Yaoxin Microelectronics Technology Shanghai Co ltd
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Yaoxin Microelectronics Technology Shanghai Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors

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Abstract

The application provides a reverse-conduction IGBT device and a preparation method thereof. According to the application, the step is formed between the first conductive type collector region and the second conductive type collector region, so that the expansion resistance of the buffer layer is improved, the voltage drop between the second conductive type collector region and the first conductive type collector region is increased, the device is enabled to enter a bipolar conduction mode as soon as possible, and the voltage folding effect of the device is reduced. The preparation method provided by the application has the advantages of simple and controllable manufacturing process and strong compatibility with the existing process.

Description

Reverse-conduction IGBT device and preparation method thereof
Technical Field
The application belongs to the technical field of semiconductors, and relates to a reverse-conducting IGBT device and a preparation method thereof.
Background
The reverse-conducting insulated gate bipolar transistor (Reverse Conducting Insulated Gate Bipolar Transistor, abbreviated as RC-IGBT) is an important branch of the insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, abbreviated as IGBT). Compared with a conventional IGBT structure, the back surface of the reverse-conduction IGBT transistor is divided into a combined area formed by combining the second conduction type collector area and the first conduction type collector area by the single second conduction type collector area, and the reverse-conduction IGBT transistor has the advantages of low cost, high power density and the like and is successfully applied to the fields of motor driving, inversion and the like. However, when the RC-IGBT is turned on in the forward direction, a unipolar MOS conduction mode is turned on to a bipolar IGBT conduction mode, and a voltage turn-back phenomenon, that is, a so-called negative resistance (snapback) effect, occurs, which becomes an important factor for limiting the wide application of the conventional RC-IGBT.
As shown in fig. 1, a schematic cross-sectional structure of the RC-IGBT includes a buffer layer 010, a second conductivity-type collector region 011, a first conductivity-type collector region 012, a drift region 020, a body region 021, a first conductivity-type source region 022, a gate structure 023, an emitter electrode 030, and a collector 050. Taking unidirectional conduction as an N-type channel MOS as an example, at the initial stage of forward conduction, before the RC-IGBT generates conductivity modulation, only electrons in the body flow, and the emission region cannot inject holes into the drift region, so that the device works in a VDMOS (Vertical Double-diffused MOSFET) mode. When the voltage drop between the emitting region and the drift region is larger than the built-in potential difference, the conduction modulation effect starts to occur, and a large amount of holes are injected into the drift region. At this time, the VDMOS mode is switched to the IGBT mode, and the resistance is suddenly changed, so that the voltage is reduced, and a voltage folding phenomenon occurs. In addition, in the actual process, the problem of process deviation or anode layout design often causes that the emission region and the drift region cannot be forward biased at the same time, so that the output characteristic curve of the RC-IGBT can be folded back by multiple times, further, current distribution is uneven, and the reliability of the device is affected.
At present, an isolation structure is additionally arranged between a first conductive type collector region and a second conductive type collector region to improve the expansion resistance of a buffer layer, so that the voltage folding phenomenon in an RC-IGBT device is restrained, and the technical problem of complex process exists in the manufacturing method of the existing structure.
Accordingly, an improved structure and method of a reverse-conducting IGBT device is provided to suppress the voltage folding back effect without significantly increasing the process complexity.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a reverse-conducting IGBT device and a method for manufacturing the same, which are used for solving the problems of poor device reliability and increased switching loss caused by a voltage folding effect existing before the reverse-conducting IGBT device enters an IGBT mode in an early forward conduction stage in the prior art.
To achieve the above and other related objects, the present application provides a reverse-conducting IGBT device comprising:
the semiconductor device comprises a drift region, a first conductive type collector region, a second conductive type collector region, a first conductive type buffer layer and a first conductive type drift region, wherein the drift region is provided with a second conductive type body region, a first conductive type source region and a grid structure from bottom to top in a stacked mode;
the emitter electrode covers the exposed surfaces of the source region and the body region, the gate lead-out terminal covers the upper surface of the gate structure, and the collector electrode covers the first conductive type collector region and the second conductive type collector region.
Optionally, the gate structure is a trench gate structure or a planar gate structure.
Optionally, the bottom surface of the second conductivity type collector region is spaced apart from the top surface of the first conductivity type collector region.
Optionally, the first conductivity type is one of N-type and P-type, and the second conductivity type is the other of N-type and P-type.
Optionally, the doping concentration of the buffer layer is higher than the doping concentration of the drift region.
Further, the gate structure comprises a gate dielectric layer positioned on the drift region and a gate conductive layer positioned on the upper surface of the gate dielectric layer.
The application also provides a preparation method of the reverse-conduction IGBT device, which comprises the following steps:
providing a first conductive type substrate, wherein the upper surface layer of the substrate is formed into a first conductive type drift region;
and performing a device front process on the upper surface layer of the drift region: forming a second conductive type body region, a first conductive type source region, a grid structure, an emission electrode and a grid leading-out end, wherein the body region is arranged on the upper surface layer of the drift region, the source region is positioned on the upper surface layer of the body region and is spaced from the side wall of the body region by a preset distance, the grid structure is arranged between the adjacent body regions, the emission electrode is arranged on the exposed surfaces of the body region and the source region, and the grid leading-out end covers the upper surface of the grid structure;
forming a first conductive type buffer layer in the substrate;
patterning the back surface of the substrate to form a step;
forming a second conductive type collector region on the bottom surface of the step, forming a first conductive type collector region on the top surface of the step, and enabling the bottom surface of the second conductive type collector region to be not lower than the top surface of the first conductive type collector region;
and forming a collector electrode covering the second conductive type collector region and the first conductive type collector region.
Optionally, the step of forming the buffer layer includes: and performing ion implantation on the back surface of the substrate, wherein the doping concentration of the buffer layer is higher than that of the drift region.
Further, the step of forming the second conductive-type collector region includes: photoetching and defining a step area on the back surface of the substrate to form an etching mask; and performing a dry etching process based on the etching mask to form a step on the back surface of the substrate.
As described above, the reverse-conduction type IGBT device and the method for manufacturing the same of the present application have the following beneficial effects:
according to the reverse-conduction IGBT device, the step is formed between the first conductive type collector region and the second conductive type collector region by improving the arrangement of the device back collector region, so that the first conductive type collector region is buried below the second conductive type collector region and the buffer layer, rc is increased on the basis of the original expansion region resistance Rn of the buffer layer by arranging the step, so that the voltage drop between the second conductive type collector region and the first conductive type collector region is increased, the device enters a bipolar conduction mode as soon as possible, the voltage retracing effect of the reverse-conduction IGBT device is reduced, and the device reliability and switching loss are improved.
The preparation method of the application comprises the steps of etching the back of the substrate by introducing photoetching and etching, and sequentially forming the first conductive type collector region and the second conductive type collector region on the bottom surface and the top surface of the step, so that the preparation method has simple and controllable process and strong compatibility with the prior art.
Drawings
Fig. 1 shows a schematic structure of a conventional reverse-conducting IGBT device.
Fig. 2 shows a process flow diagram of the fabrication of the reverse-conducting IGBT device of the application.
Fig. 3 is a schematic diagram showing the structure of a body region and a source region formed in the method for manufacturing a reverse conducting IGBT device according to the present application.
Fig. 4 is a schematic structural diagram of a device front-side process performed in the method for manufacturing a reverse-conducting IGBT device according to the present application.
Fig. 5 is a schematic diagram showing a structure of a buffer layer formed in the method for manufacturing a reverse conducting IGBT device of the present application.
Fig. 6 is a schematic structural diagram of a step formed on the back surface of a substrate in the method for manufacturing a reverse conducting IGBT device according to the present application.
Fig. 7 is a schematic structural diagram showing steps formed on the back surface of a substrate in the method for manufacturing a reverse conducting IGBT device according to the present application.
Fig. 8 is a schematic diagram showing a structure of forming a first conductivity type collector region and a second conductivity type collector region in a method of manufacturing a reverse conducting type IGBT device according to the present application.
Fig. 9 is a schematic structural diagram of a reverse conducting IGBT device according to the present application.
Description of element reference numerals
010. Buffer layer
011. Collector region of second conductivity type
012. Collector region of first conductivity type
020. Drift region
021. Body region
022. Source region
023. Gate structure
0231. Gate dielectric layer
0232. Gate conductive layer
030. Transmitting electrode
050. Collector electrode
1. Substrate and method for manufacturing the same
11. Collector region of second conductivity type
12. Collector region of first conductivity type
10. Buffer layer
20. Drift region
21. Body region
22. Source region
23. Gate structure
231. Gate dielectric layer
232. Gate conductive layer
30. Transmitting electrode
40. Gate electrode
50. Collector electrode
61. Etching mask
S1 to S6 steps
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
As described in detail in the embodiments of the present application, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Furthermore, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers may also be present.
In the context of the present application, unless otherwise specified and defined, the structural terminology "above" a first feature described is to be understood in a broad sense, and may include, for example, embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Please refer to fig. 2 to fig. 9. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As used herein, the semiconductor field vocabulary is a technical vocabulary commonly used by those skilled in the art, for example, the first conductivity type may be one of N-type and P-type, and the second conductivity type may be the other of P-type and N-type, and the first conductivity type is opposite to the second conductivity type, for example, when the first conductivity type is N-type, the second conductivity type is P-type, or when the first conductivity type is P-type, the second conductivity type is N-type. For convenience of description below regarding the first conductivity type and the second conductivity type, the first conductivity type is described by taking N type as an example, and the second conductivity type is described by taking P type as an example.
In order to distinguish the doping concentration, the P+ type represents the P type with heavy doping concentration, the P type represents the P type with medium doping concentration, the P-type represents the P type with light doping concentration, the N+ type represents the N type with heavy doping concentration, the N type represents the N type with medium doping concentration, and the N type represents the N type with light doping concentration.
Example 1
The present embodiment provides a reverse-conducting IGBT device, where the reverse-conducting IGBT device includes, but is not limited to: a planar gate structure reverse-conduction IGBT device and a trench gate structure reverse-conduction IGBT device.
Referring to fig. 9, which is a schematic cross-sectional structure of one structure of a reverse-conductivity type IGBT device, at least one second conductivity type collector region 11, at least one first conductivity type collector region 12, a first conductivity type buffer layer 10, and a first conductivity type drift region 20 are stacked from bottom to top, a first conductivity type body region 21, a first conductivity type source region 22, and a gate structure 23 are formed on an upper surface of the drift region 20, the body region 21 is disposed at a distance from the upper surface of the body region 21 and a predetermined distance from a sidewall of the body region 21, a gate structure 23 is disposed on the drift region 20 between adjacent body regions 21, wherein a step is formed between adjacent first conductivity type collector regions 12 and second conductivity type collector regions 11, and a bottom surface of the second conductivity type collector region 11 is not lower than a top surface of the first conductivity type region 12 such that the first conductivity type collector regions 12 are buried away from the drift region 20 and disposed below the second conductivity type collector regions 11 and the buffer layer 10.
As shown in fig. 9, the reverse-conduction IGBT device further includes an emitter electrode 30, a gate electrode 40, and a collector electrode 50, wherein the emitter electrode 30 covers exposed surfaces of the source region 22 and the body region 21, the gate electrode 40 covers an upper surface of the gate structure 23, and the collector electrode 50 covers the first conductivity type collector region 12 and the second conductivity type collector region 11.
Specifically, the material of the substrate 1 includes silicon, germanium, silicon carbide or other suitable semiconductor materials. In this embodiment, the substrate 1 is an N-type silicon substrate.
Specifically, the doping concentrations of the body region 21 and the source region 22 may be set according to actual conditions, and are not limited here.
The gate structure is a trench gate structure or a planar gate structure, as examples. When the gate structure is selected as a planar gate structure, a gate structure 23 is disposed on the drift region 20 between adjacent body regions 21, and the gate structure 23 includes a gate dielectric layer 231 disposed on the upper surface of the drift region 20 and a gate conductive layer 232 disposed on the upper surface of the gate dielectric layer 231, so that the gate structure 23 controls the opening of a conductive channel between the source region 22 and the drift region 20 in the body region 31. Similarly, when the gate structure is selected as a trench gate structure, the upper surface layer of the drift region is provided with a gate trench, and the gate structure is located between adjacent body regions and includes a gate dielectric layer located on the inner surface of the gate trench and a gate conductive layer located on the upper surface of the gate dielectric layer.
As an example, the gate dielectric layer 231 may be made of silicon oxide or other suitable dielectric material; the thickness of the gate dielectric layer 231 may be set according to practical situations, which is not limited herein.
As an example, the gate conductive layer 232 may be made of polysilicon or other suitable conductive material; the thickness of the gate conductive layer 232 may be set according to practical situations, and is not limited herein.
Specifically, the drift region 20 may be a lightly doped region, and the doping concentration of the drift region 20 needs to be a compromise between the withstand voltage characteristics and the on-loss of the device.
Specifically, the buffer layer 10 is configured such that the doping concentration of the drift region 20 is lower than that of the buffer layer 10, so as to ensure that the specific gravity of the extension resistance of the buffer layer 10 at the total resistance further contributes to the suppression of the voltage folding back effect. The thickness of the buffer layer 10 may be set according to practical situations, and is not limited herein.
As an example, the bottom surface of the second conductive-type collector region 11 is spaced apart from the top surface of the first conductive-type collector region 12 such that the first conductive-type collector region 12 is isolated from the second conductive-type collector region 11 by a buffer layer region located thereon without an overlap region therebetween, such that a point in the VDMOS mode closest to the first conductive-type collector region around the second conductive-type collector region moves down in the step height direction, a larger voltage drop is generated between the second conductive-type collector region and the first conductive-type collector region via a flow path denoted Rc as shown in fig. 9, the first conductive-type collector region to the metallized collector region, thereby reducing a trigger current of the device and enabling the device to enter the IGBT mode as soon as possible.
As an example, the second conductivity type collector region 11 is a heavily doped region, and when the device enters IGBT mode, the second conductivity type collector region 11 injects carriers into the drift region 20, causing a conductivity modulation effect, thereby reducing the on-resistance of the device. In this embodiment, the first conductivity type is N-type, the second conductivity type is P-type, and when the IGBT cell is turned on, the P-type collector region injects holes into the N-type drift region.
The reverse conducting type IGBT device of the embodiment enables the first conducting type collector region to be embedded below the second conducting type collector region and the buffer layer by improving the arrangement mode of the device back collector region, and enables the voltage drop generated by current in the path to be increased by further introducing the extension resistance Rc in the depth direction of the buffer layer, so that the voltage drop between the second conducting type collector region and the first conducting type collector region is increased, and the device is enabled to enter a bipolar conducting mode as soon as possible.
Example two
The preparation method of the reverse conducting type IGBT device according to the first embodiment of the present application is preferably obtained by adopting the preparation method of the present embodiment, and of course, other methods may also be adopted. It should be noted that the above sequence does not strictly represent the manufacturing sequence of the manufacturing method of the reverse-conducting IGBT device protected by the present application, and those skilled in the art may vary depending on the actual process steps.
The embodiment provides a method for manufacturing a reverse-conducting type IGBT device, referring to fig. 2, which is a schematic flow chart for manufacturing a reverse-conducting type IGBT device, comprising the following steps:
s1: providing a first conductive type substrate, wherein the upper surface layer of the substrate is formed into a first conductive type drift region;
s2: and performing a device front process on the upper surface layer of the drift region: forming a second conductive type body region, a first conductive type source region, a grid structure, an emission electrode and a grid leading-out terminal;
s3: forming a first conductive type buffer layer in the substrate;
s4: patterning the back surface of the substrate to form a step;
s5: forming a second conductive type collector region on the bottom surface of the step, forming a first conductive type collector region on the top surface of the step, and enabling the bottom surface of the second conductive type collector region to be not lower than the top surface of the first conductive type collector region;
s6: and forming a collector electrode covering the second conductive type collector region and the first conductive type collector region.
First, referring to fig. 3, step S1 is performed to provide a first conductivity type substrate 1, and an upper surface layer of the substrate 1 is formed as a first conductivity type drift region 20.
Specifically, the material of the substrate 1 includes silicon, germanium, silicon carbide or other suitable semiconductor materials. In this embodiment, the substrate 1 is an N-type silicon substrate, and the upper surface layer of the substrate 1 forms a drift region of the RC-IGBT, and the drift region may be formed by an ion implantation process or other suitable processes. The doping concentration and thickness of the drift region 20 are adjusted according to the withstand voltage capability of the device. Next, referring to fig. 3 to 4, step S2 is performed: performing a device front side process on the upper surface layer of the drift region 20: a second conductivity type body region 21, a first conductivity type source region 22, a gate structure 23, an emitter electrode 30 and a gate electrode 40 are formed, wherein the body region 21 is arranged on the upper surface layer of the drift region 20 at intervals, the source region 22 is positioned on the upper surface layer of the body region 21 and is spaced from the side wall of the body region by a preset distance, the gate structure is arranged between adjacent body regions 21, the emitter electrode 30 is arranged on the exposed surfaces of the body region 21 and the source region 22, and the gate electrode 40 covers the upper surface of the gate structure.
Specifically, the second conductivity type body region 21 and the first conductivity type source region 22 may be sequentially formed by a conventional method in the art, and are not limited herein.
As an example, the gate structure is a trench gate structure or a planar gate structure, as shown in fig. 4, the gate structure 23 includes a gate dielectric layer 231 located on the upper surface of the drift region and a gate conductive layer 232 located on the upper surface of the gate dielectric layer. Or, the gate structure is a trench gate structure, and the step of forming the trench gate structure includes: forming a gate groove on the upper surface of the drift region through a photoetching process, wherein the gate groove is positioned between two adjacent body regions; and then, sequentially forming a gate dielectric layer and a gate conducting layer on the inner surface of the gate trench so as to isolate the gate conducting layer from the source region, the body region and the drift region.
Then, the process is carried out. Referring to fig. 5, step S3 is performed: a first conductive type buffer layer 10 is formed in the substrate 1.
Specifically, step S3 includes: ion implantation is performed on the back surface of the substrate 1 to form a buffer layer 10, wherein the buffer layer 10 is configured such that the doping concentration of the buffer layer 10 is higher than the doping concentration of the drift region 20.
As an example, in step S3, after the gate structure is formed, an interlayer dielectric layer, a contact hole, and a front metal layer are sequentially formed, and the front metal layer is patterned to be separated into the emitter electrode 30 and the gate electrode 40. For example, the emitter electrode 30 and the gate electrode 40 may be made of one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials.
Next, referring to fig. 6, step S4 is performed: the back surface of the substrate 1 is patterned to form steps.
Specifically, step S4 includes: forming a photoresist layer on the back surface of the substrate 1 far away from the device, defining a step area by photoetching, and forming an etching mask 61; a dry etching process is performed based on the etching mask 61 to form a step on the back surface of the substrate 1, wherein the step is defined by a bottom surface, a top surface, and sidewalls between the bottom surface and the top surface. By arranging the step, the first conductive type collector region and the second conductive type collector region are respectively formed on the top surface and the bottom surface of the step, so that the first conductive type collector region is embedded below the buffer layer and the second conductive type collector region away from the drift region, the resistor in the height direction of the step is additionally introduced, higher voltage drop is generated between the second conductive type collector region and the drift region, the conversion from the VDMOS mode to the IGBT mode is realized earlier, and the voltage folding effect is obviously reduced. The height of the step here may be appropriately determined based on the size and doping of the buffer layer.
Next, referring to fig. 7 to 8, step S5 is performed: a second conductivity type collector region 11 is formed on the bottom surface of the step obtained in step S4, a first conductivity type collector region 12 is formed on the top surface of the step, and the bottom surface of the second conductivity type collector region 11 is not lower than the top surface of the first conductivity type collector region 12.
As an example, a method of forming the second conductive-type collector region 11 includes ion implantation or other suitable method. In this embodiment, the second conductivity type collector region 11 is formed by an ion implantation process with the etching mask as the first implantation barrier layer.
By way of example, the method of forming the first conductivity type collector region 12 includes ion implantation or other suitable method. In this embodiment, the step of forming the first conductivity type collector region 12 includes: photoetching a defined pattern on the back surface of the substrate 1 to form a second injection barrier layer; the first conductive type collector region 12 is formed by an ion implantation process using the second implantation blocking layer, and the bottom surface of the second conductive type collector region 11 is not lower than the top surface of the first conductive type collector region 12.
Then, step S6 is performed: collector 50 is formed overlying the second conductivity type collector region 11 and the first conductivity type collector region 12. As shown in fig. 9, a collector 50 covers the first conductivity type collector region 12 and the second conductivity type collector region 11.
As an example, the material of the collector 50 may include one of titanium, titanium nitride, silver, gold, copper, aluminum, and tungsten, and may be other suitable conductive materials.
According to the preparation method of the reverse conducting IGBT device, a step is formed between the first conducting type collector region and the second conducting type collector region by introducing photoetching and etching, the preparation method is simple in process and good in adaptability, a buffer layer region above the first conducting type collector region serves as an isolation structure, besides the resistor on a current transverse flow path, the resistor in the step height direction is introduced, the voltage drop generated by current in the path is increased, the voltage drop between the second conducting type collector region and the first conducting type collector region is increased, the device enters a bipolar conduction mode as soon as possible, and the voltage folding effect of the RC-IGBT is effectively reduced.
In summary, according to the reverse-conduction type IGBT device and the method for manufacturing the same, the back surface of the first-conductivity-type substrate is etched to form the step by improving the device structure of the reverse-conduction type IGBT, so that the step is formed between the first-conductivity-type collector region and the second-conductivity-type collector region, rc is increased on the basis of the original expansion region resistance Rn of the buffer layer, and the voltage drop between the second-conductivity-type collector region and the first-conductivity-type collector region is increased, so that the device enters the bipolar conduction mode as soon as possible. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (9)

1. A reverse-conducting IGBT device, comprising:
the semiconductor device comprises a drift region, a first conductive type collector region, a second conductive type collector region, a first conductive type buffer layer and a first conductive type drift region, wherein the drift region is provided with a second conductive type body region, a first conductive type source region and a grid structure from bottom to top in a stacked mode;
the emitter electrode covers the exposed surfaces of the source region and the body region, the gate lead-out terminal covers the upper surface of the gate structure, and the collector electrode covers the first conductive type collector region and the second conductive type collector region.
2. The reverse-conducting IGBT device of claim 1 wherein: the grid structure is a trench grid structure or a planar grid structure.
3. The reverse-conducting IGBT device of claim 1 wherein: the bottom surface of the second conductivity type collector region is spaced apart from the top surface of the first conductivity type collector region.
4. The reverse-conducting IGBT device of claim 1 wherein: the first conductivity type is one of N-type and P-type, and the second conductivity type is the other of N-type and P-type.
5. The reverse-conducting IGBT device of claim 1 wherein: the doping concentration of the buffer layer is higher than that of the drift region.
6. The reverse-conducting IGBT device of claim 2 wherein: the gate structure comprises a gate dielectric layer positioned above the drift region and a gate conductive layer positioned on the upper surface of the gate dielectric layer.
7. The preparation method of the reverse-conduction IGBT device is characterized by comprising the following steps of:
providing a first conductive type substrate, wherein the upper surface layer of the substrate is formed into a first conductive type drift region;
and performing a device front process on the upper surface layer of the drift region: forming a second conductive type body region, a first conductive type source region, a grid structure, an emission electrode and a grid leading-out end, wherein the body region is arranged on the upper surface layer of the drift region, the source region is positioned on the upper surface layer of the body region and is spaced from the side wall of the body region by a preset distance, the grid structure is arranged between the adjacent body regions, the emission electrode is arranged on the exposed surfaces of the body region and the source region, and the grid leading-out end covers the upper surface of the grid structure;
forming a first conductive type buffer layer in the substrate;
patterning the back surface of the substrate to form a step;
forming a second conductive type collector region on the bottom surface of the step, forming a first conductive type collector region on the top surface of the step, and enabling the bottom surface of the second conductive type collector region to be not lower than the top surface of the first conductive type collector region;
and forming a collector electrode covering the second conductive type collector region and the first conductive type collector region.
8. The method of manufacturing according to claim 7, wherein the step of forming the buffer layer includes: and performing ion implantation on the back surface of the substrate, wherein the doping concentration of the buffer layer is higher than that of the drift region.
9. The method of manufacturing according to claim 8, wherein the step of forming the second conductivity type collector region comprises: photoetching and defining a step area on the back surface of the substrate to form an etching mask; and performing a dry etching process based on the etching mask to form a step on the back surface of the substrate.
CN202310892475.5A 2023-07-20 2023-07-20 Reverse-conduction IGBT device and preparation method thereof Pending CN116759452A (en)

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CN202310892475.5A CN116759452A (en) 2023-07-20 2023-07-20 Reverse-conduction IGBT device and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310892475.5A CN116759452A (en) 2023-07-20 2023-07-20 Reverse-conduction IGBT device and preparation method thereof

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CN116759452A true CN116759452A (en) 2023-09-15

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