CN116738910A - FPGA chip - Google Patents

Abstract

An FPGA chip. The FPGA chip comprises a winding resource, a logic resource and an IP module and is characterized by further comprising a first connection module group, wherein the first connection module group comprises a plurality of connection modules; each connecting module in the first connecting module group is respectively positioned between different winding resources and the IP module, and each connecting module is respectively electrically connected with the adjacent winding resources and the adjacent IP module; each connecting module except the first connecting module and the last connecting module in the first connecting module group is electrically connected with the adjacent connecting modules on two sides of the connecting module; each connection module is used for receiving data from the winding resource, the IP module and the lower connection module which are electrically connected with the connection module and sending data to the winding resource, the IP module and the upper connection module which are electrically connected with the connection module.

Description

FPGA chip

Technical Field

The application relates to the technical field of integrated circuits, in particular to an FPGA chip.

Background

FPGA is a field programmable gate array, which is a product of further development based on programmable devices such as programmable array logic (Programming Array Logic, PAL), general-purpose array logic (Generic Array Logic, GAL), complex programmable logic devices (Complex Programmable Logic Device, CPLD), etc. The programmable device is used as a semi-custom circuit in the field of application specific integrated circuits, not only solves the defect of custom circuits, but also overcomes the defect of limited gate circuits of the original programmable device. The FPGA can select to build a storage module, or can select the FPGA with an internal storage block. The FPGA chip may include logic resources and routing resources (also referred to as routing resources, routing Resources), and the two are electrically connected to each other for data interaction. More specifically, in the FPGA chip of the siren, the logic resource is called a programmable logic function block (Configurable Logic Blocks, CLB).

The IP module is a pre-designed and even verified integrated circuit, device or component with certain determined functions, and is used for chip designers to integrate and select. In order to be able to more efficiently implement a specific function, such as a video codec function, a data stream compression and decompression function, or a protocol conversion function, it is generally employed to integrate a corresponding dedicated IP module into an FPGA chip. Each IP module can be electrically connected with a corresponding winding resource, so that the logic resource can perform data interaction with the IP module. However, with this design, the problem of wiring congestion is easy to occur when the IP module performs data interaction with the logic resource, and this problem is more serious especially when the logic resource that needs to perform data interaction with the IP module is more. For example, the first IP module is electrically connected to the first routing resource through the first connection line, so that the logic resource must be locked through the first connection line when performing data interaction with the first IP module. The wiring must be connected to the first connection line, which places a relatively strict limitation on the wiring and easily causes a problem of wiring congestion.

Therefore, a technical problem of wiring congestion in the FPGA chip is currently needed to be solved.

Disclosure of Invention

In order to solve the above-mentioned problems, an FPGA chip is provided in an embodiment of the present application. The FPGA chip comprises a winding resource, a logic resource and an IP module, and also comprises a first connection module group, wherein the first connection module group comprises a plurality of connection modules; each connecting module in the first connecting module group is respectively positioned between different winding resources and the IP module, and each connecting module is respectively electrically connected with the adjacent winding resources and the adjacent IP module; each connecting module except the first connecting module and the last connecting module in the first connecting module group is electrically connected with the adjacent connecting modules on two sides of the connecting module; each connection module is used for receiving data from the winding resource, the IP module and the lower connection module which are electrically connected with the connection module and sending data to the winding resource, the IP module and the upper connection module which are electrically connected with the connection module.

When the logic resource sends data to the IP module, the lower connection module of the first connection module group in the present application (the first connection module is any connection module in the first connection module group) may receive data from the winding resource and send the data to the first connection module, and the first connection module may receive the data and send the data to the IP module electrically connected to the first connection module. In this way, in the data transmission process, in addition to selecting the first connection line between the first connection module and the winding resource for transmitting data, the second connection line between the lower connection module of the first connection module and the winding resource can be selected for transmitting data. Therefore, when wiring, the first connecting wire can be selected to be connected, the second connecting wire can be selected to be connected, more connecting wires can be selected for wiring, locking of the first connecting wire is eliminated, limitation on wiring direction is reduced, and therefore the problem of wiring congestion can be solved.

When the logic resource receives data from the IP module, the first connection module may receive the data from the IP module and transmit the data to an upper connection module of the first connection module, which may receive the data and transmit the data to a winding resource electrically connected thereto. In this way, in the data transmission process, in addition to selecting the first connection line between the first connection module and the winding resource for data transmission, the third connection line between the upper connection module of the first connection module and the winding resource can be selected for data transmission. Therefore, when wiring is conducted, the first connecting wire can be selected to be connected with the first connecting wire, the third connecting wire can be selected to be connected with the third connecting wire, more connecting wires are selected for wiring, locking of the first connecting wire is eliminated, limitation on wiring direction is reduced, and therefore the problem of wiring congestion can be solved.

In one embodiment, each connection module is provided with an input port, and the input ports include a first input port, a second input port and a third input port; wherein the first input port is configured to receive first data from a winding resource electrically connected thereto; the second input port is used for receiving second data from an IP module electrically connected with the second input port; the third input port is used for receiving third data from a lower-level connection module electrically connected with the third input port; the connecting modules are respectively provided with an output port, and the output ports comprise a first output port, a second output port and a third output port; the first output port is used for sending fourth data to a winding resource electrically connected with the first output port; the second output port is used for sending fifth data to the IP module electrically connected with the second output port; and the third output port is used for sending sixth data to the upper-level connection module electrically connected with the third output port.

In this embodiment, each connection module may receive data from its lower connection module and transmit data to its upper connection module. Meanwhile, the connection module can perform data interaction with the IP module and also perform data interaction with winding resources electrically connected with the connection module.

In one embodiment, each connection module is provided with a data strobe control port, which is used for receiving strobe signals and controlling the strobe of the input port and the strobe of the output port according to the strobe signals.

In this embodiment, since each connection module has three input ports and three output ports, in order to implement different requirements for transmitting data, a data strobe control interface may be provided on the connection module, so that which input port and which (or those) output ports are strobed may be controlled according to strobe signals received by the strobe control interface.

In one embodiment, a first connection module of the first connection module group is electrically connected to a last connection module.

In this embodiment, after the first connection module and the last connection module in the first connection module group are electrically connected, each connection module in the first connection module group may form an annular structure, and data may be serially transmitted in the annular structure, so that data may be transmitted from a certain connection module in the first module group to any other connection module, which expands the range of data transmission, and makes the selection of the wiring mode more flexible.

In one embodiment, the FPGA chip further comprises a second set of connection modules, the second set of connection modules comprising a plurality of connection modules; each connecting module in the second connecting module group is respectively positioned between different winding resources and the IP module, and each connecting module is respectively electrically connected with the adjacent winding resources and the adjacent IP module; each connecting module except the first connecting module and the last connecting module in the second connecting module group is electrically connected with the adjacent connecting modules on two sides of the connecting module; each connection module is used for receiving data from the winding resource, the IP module and the lower connection module which are electrically connected with the connection module and sending data to the winding resource, the IP module and the upper connection module which are electrically connected with the connection module.

In this embodiment, the first connection module group and the second connection module group are respectively arranged around the winding resources in the FPGA chip, and data can be transmitted in the first connection module group and the second connection module group, so that the number of connection modules around the winding resources is increased, the range of data transmission is expanded, and the selection of the wiring mode is more flexible.

In one embodiment, the IP blocks transmit data using parallel buses, and the number of the first connection block groups is equal to the number of bits of the parallel data buses.

In this embodiment, each bit in the parallel bus may be connected to one first connection module group, each bit of data may be transmitted through one first connection module group, and all bits of data (for example, 32 bits) in the parallel bus may be simultaneously transmitted through a plurality (32) of first connection module groups.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an FPGA chip in the prior art;

fig. 2 is a schematic structural diagram of an FPGA chip according to an embodiment of the present disclosure;

FIGS. 3A-3C are schematic diagrams of three transmission lines for data transmitted by an IP block to a logical resource;

FIG. 4A is a schematic view of the internal structure of a connection module;

FIG. 4B is a schematic diagram illustrating a connection between a connection module and a winding resource;

FIG. 4C is a schematic diagram illustrating a connection between a connection module and an IP module;

FIG. 4D is a schematic diagram of a plurality of connection modules;

FIG. 4E is a schematic diagram illustrating another connection between a connection module and a winding resource;

FIG. 4F is a schematic diagram illustrating another connection between a connection module and an IP module;

FIGS. 5A-5K are eleven gated data transmission routes internal to the connection module;

fig. 6 is a schematic structural diagram of another FPGA chip according to an embodiment of the present disclosure.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

The term "and/or" is used herein to describe an association relationship of associated objects, and means that there may be three relationships, for example, a and/or B, and that there may be three cases where a exists alone, while a and B exist together, and B exists alone. The symbol "/" herein indicates a relationship in which the associated object is "or", e.g., a/B indicates a or B.

The terms "first" and "second" and the like in the description and in the claims are used for distinguishing between different objects and not for describing a particular sequential order of objects. For example, the first response message and the second response message, etc. are used to distinguish between different response messages, and are not used to describe a particular order of response messages.

In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration.

Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the description of the embodiments of the present application, unless otherwise specified, the meaning of "plurality" means two or more, for example, the meaning of a plurality of processing units means two or more, or the like; the plurality of elements means two or more elements and the like.

In order to achieve a specific function more efficiently, a special IP module is generally integrated in an FPGA chip, and the IP module is connected to a winding resource of the FPGA chip through a connection line. However, with this design, when a certain IP module performs data interaction with a logic resource, data must pass through a connection line between the IP module and a winding resource, that is, the connection line is locked, and when wiring is performed, the data must be connected with the connection line, so that a strict limitation is generated on the wiring direction, and a problem of wiring congestion is easily caused. As shown in fig. 1, the IP13 is an IP module, the IP13 is electrically connected to the winding resource 1N and the winding resource 0N, all data input and output from the IP13 must pass through a connection line between the winding resources 1N and IP13 or a connection line between the winding resource 0N and IP13, and must be connected to the connection line in the wiring process, which generates a stricter limitation on the wiring direction and is easy to cause a problem of wiring congestion. The same technical problems apply to IP11, IP12, and IP 14.

In order to solve the technical problem of wiring congestion in an FPGA chip, the application provides a solution. The FPGA chip comprises a winding resource, a logic resource and an IP module, and is characterized by further comprising a first connection module group, wherein the first connection module group comprises a plurality of connection modules; each connecting module in the first connecting module group is respectively positioned between different winding resources and the IP module, and each connecting module is respectively electrically connected with the adjacent winding resources and the adjacent IP module; each connecting module except the first connecting module and the last connecting module in the first connecting module group is electrically connected with the adjacent connecting modules on two sides of the connecting module; each connection module is used for receiving data from the winding resource, the IP module and the lower connection module which are electrically connected with the connection module and sending data to the winding resource, the IP module and the upper connection module which are electrically connected with the connection module.

In the embodiment of the application, when the logic resource sends data to the IP module, the lower-level connection module of the first connection module group (the first connection module is any connection module in the first connection module group) in the application can receive the data from the winding resource and send the data to the first connection module, and the first connection module can receive the data and send the data to the IP module electrically connected with the first connection module. In this way, in the data transmission process, in addition to selecting the first connection line between the first connection module and the winding resource for transmitting data, the second connection line between the lower connection module of the first connection module and the winding resource can be selected for transmitting data. Therefore, when wiring, the first connecting wire can be selected to be connected, the second connecting wire can be selected to be connected, more connecting wires can be selected for wiring, locking of the first connecting wire is eliminated, limitation on wiring direction is reduced, and therefore the problem of wiring congestion can be solved.

When the logic resource receives data from the IP module, the first connection module may receive the data from the IP module and transmit the data to an upper connection module of the first connection module, which may receive the data and transmit the data to a winding resource electrically connected thereto. In this way, in the data transmission process, in addition to selecting the first connection line between the first connection module and the winding resource for data transmission, the third connection line between the upper connection module of the first connection module and the winding resource can be selected for data transmission. Therefore, when wiring is conducted, the first connecting wire can be selected to be connected with the first connecting wire, the third connecting wire can be selected to be connected with the third connecting wire, more connecting wires are selected for wiring, locking of the first connecting wire is eliminated, limitation on wiring direction is reduced, and therefore the problem of wiring congestion can be solved.

Fig. 2 is a block diagram of an FPGA chip according to an embodiment of the present application. The embodiment of the application provides an FPGA chip, wherein the FPGA chip 1 can comprise a winding resource, a logic resource and an IP module. The number of winding resources and the number of logic resources are plural, and as shown in fig. 2, the winding resources include a winding resource 01, a winding resource 02, and a winding resource 03 up to a winding resource NN. The logical resources include logical resource 01, logical resource 02, and logical resource 03 up to logical resource NN, respectively.

The FPGA chip 1 may further include a first connection module group, where the first connection module group includes a plurality of connection modules (abbreviated as IPC), and as illustrated in fig. 2, the number of connection modules in the first connection module group may be 4, which are respectively IPC11, IPC12, IPC13, and IPC14. Each connection module in the first connection module group can be distributed around winding resources in the FPGA chip, and each connection module is located between different connection modules and the IP module. Thus, each connection module is adjacent to a different winding resource, and each connection module can be electrically connected with its adjacent winding resource and its adjacent IP module. In this way, since each connection module is located between the IP module and the winding resource, when the IP performs data interaction with the winding resource, the data needs to pass through the connection module. Illustratively, when the logical resource interacts with the IP13, it is required to pass through the connection module IPC13.

The connection modules except the first connection module and the last connection module in the first connection module group can be respectively and electrically connected with the adjacent connection modules on two sides of the connection module, so that the connection modules except the last connection module is not electrically connected with the first connection module are sequentially connected, the connection modules can respectively receive data from the lower connection modules and can also transmit data to the upper connection modules, and the data can be serially transmitted in the first connection module group. For example, data may be transferred serially from IPC11 to IPC12, from IPC12 to IPC13, and from IPC13 to IPC14.

Each connection module is used for receiving data from the winding resource, the IP module and the lower connection module which are electrically connected with the connection module and sending data to the winding resource, the IP module and the upper connection module which are electrically connected with the connection module.

Therefore, in the embodiment of the present application, when the logic resource transmits data to the IP module, the logic resource may transmit the data to the winding resource, the lower connection module of the first connection module (any connection module in the first connection module group) may receive the data from the winding resource and transmit the data to the first connection module, and the first connection module may receive the data and transmit the data to the IP module electrically connected thereto. In this way, in the data transmission process, in addition to selecting the first connection line between the first connection module and the winding resource for transmitting data, the second connection line between the lower connection module of the first connection module and the winding resource can be selected for transmitting data. Therefore, the connection with the first connecting wire or the second connecting wire can be selected during wiring, more connecting wires are selected for wiring, locking of the first connecting wire is eliminated, limitation on wiring direction is reduced, and therefore the problem of wiring congestion can be solved.

When the logic resource receives data from the IP module, the first connection module may receive the data from the IP module and transmit the data to an upper connection module of the first connection module, which may receive the data and transmit the data to a winding resource electrically connected thereto. In this way, in the data transmission process, in addition to selecting the first connection line between the first connection module and the winding resource for data transmission, the third connection line between the upper connection module of the first connection module and the winding resource can be selected for data transmission. Therefore, the first connecting wire can be selectively connected with the third connecting wire, and more connecting wires can be selectively connected with the third connecting wire during wiring, so that the locking of the first connecting wire is eliminated, the limitation on the wiring direction is reduced, and the problem of wiring congestion can be solved.

Illustratively, as shown in FIG. 2, IP14 is a directly superior connection module to IP13, and IP13 is a directly inferior connection module to IP 14. IP14 is an indirect upper connection module of IP12, and IP12 is an indirect lower connection module of IP 14. Similarly, IP13 is a directly upper connection module of IP12, IP12 is a directly upper connection module of IP11, and IP11, IP12, IP13, and IP14 are sequentially connected.

Fig. 3A to 3C show three data transmission lines through which data is transmitted from the IP block to the logic resource. When the logic resource N-11 needs to send data to the IP13, one of the data transmission lines is that, first, the logic resource N-11 may transmit the data to the IPC11 through the connection line between the IPC11 and the winding resource, the IPC11 transmits the data to the IPC12, the IPC12 transmits the data to the IPC13, and the IPC13 transmits the data to the IP13, as shown in fig. 3A. Another data transmission line is that the logic resource N-11 may first transmit data to the IPC12 through a connection line between the IPC12 and the winding resource, the IPC12 transmits data to the IPC13, and the IPC13 transmits data to the IP13, as shown in fig. 3B. In another data transmission line, the logic resource N-11 may first transmit data to the IPC13 through a connection line between the IPC13 and the winding resource, and then the IPC13 transmits the data to the IP13, as shown in fig. 3C. Therefore, when wiring, three choices exist, namely, the wiring can select any one of the three connection lines (the connection line between the IPC11 and the winding resource, the connection line between the IPC12 and the winding resource and the connection line between the IPC13 and the winding resource) to connect the logic resource N-11, thereby reducing the limitation on the wiring direction and solving the problem of wiring congestion

In one embodiment, the connection modules are each provided with an input port for receiving data. Specifically, the input ports may include three input ports, namely, a first input port LOGin, a second input port IPin, and a third input port IPCin, as shown in fig. 4A. The first input port LOGin may be electrically connected to a winding resource, and is configured to receive first data from the winding resource electrically connected to the first input port LOGin, so as to implement a function of receiving data from the winding resource by the connection module. FIG. 4B shows a schematic diagram of a connection module to a winding resource, specifically, winding resource N-1N is electrically connected to a LOgin port of the connection module. In this way, the logic resource N-1N-1 can transmit data to the connection module through the connection line between the winding resource N-1N and the LOGin port.

Similarly, the second input port IPin of the connection module may be electrically connected to the IP module for receiving second data from the IP module to implement the function of the connection module for receiving data from the IP module. Fig. 4C shows a schematic diagram of a connection between a connection module and an IP module, specifically, an IPin port of the connection module is electrically connected to an Output (OUT) port of the IP module, for receiving data sent by the IP module.

In addition, the third input port IPCin of the connection module can be electrically connected with the IPCout port of the connection module directly below the connection module, and is used for receiving third data from the connection module below the connection module, so that the function of receiving data from the connection module below the connection module is realized. Fig. 4D shows a connection schematic diagram of a plurality of connection modules, specifically, the connection modules IPC11, IPC12 and IPC13 are sequentially connected, the IPCout port of IPC11 is connected with the IPCin port of IPC12, and the IPCout port of IPC12 is connected with the IPCin port of IPC13. Illustratively, when the logical resource N-11 sends data to the IP13, the logical resource N-11 may transmit the data into the IPC11 through the LOgin port of the IPC 11. Then, the data is transferred from the IPCout port of the IPC11 to the IPCin port of the IPC12, and then transferred to the IPCout port of the IPC12 through the IPC 12. Next, data is transferred from the IPCout port of the IPC12 to the IPCin port of the IPC13, then transferred again to the IPCout port of the IPC13 through the IPC13, and finally transferred from the IPCout port of the IPC13 into the IP 13.

And each connecting module is provided with an output port for outputting data. As shown in fig. 4A, the output ports may include a first output port LOGout, a second output port IPout, and a third output port IPCout. The first output port LOGout is electrically connected with the winding resource, and transmits fourth data to the first output port LOGout so as to realize the function of transmitting data from the connection module to the winding resource electrically connected with the connection module. For example, as shown in fig. 4E, the LOGout port of the connection module is electrically connected to the winding resource N-1N, and data can be transmitted to the winding resource N-1N through the LOGout port, and then data can be transmitted from the winding resource N-1N to the logic resource N-1, so that data transmission from the connection module to the logic resource is realized.

The second output port IPout may be used to send fifth data to the IP module electrically connected thereto, so as to implement a function of IPC sending data to the IP module electrically connected thereto. For example, as shown in fig. 4F, data input by IPCin, IPin or LOGin may be output from the IPout port to the IP block through the connection block.

And the third output port IPCout is used for sending sixth data to the upper-level connection module electrically connected with the third output port IPCout so as to realize the function of sending data to the upper-level IPC by the IPC. For example, as shown in fig. 4D, the connection modules IPC11, IPC12 and IPC13 are sequentially connected, the IPC out port of the IPC11 is connected with the IPCin port of the IPC12, and the IPCin port of the IPC12 is connected with the IPCin port of the IPC13, so that data can be transmitted to the IPCin port of the IPC12 through the IPCin port of the IPC11, then transmitted to the IPCin port of the IPC12 through the IPC12, and transmitted to the IPCin port of the IPC13 from the IPCin port of the IPC12, thereby entering the IPC13, that is, the data can be serially transmitted in the connection modules connected with each other.

In one embodiment, since each connection module has three input ports and three output ports, in order to realize different requirements for transmitting data, a data strobe control interface may be provided on the connection module, so that according to strobe signals received by the strobe control interface, which input port and which output port(s) are strobed can be controlled.

For example, the connection module may be composed of two AND gates AND1 AND2 AND two multiplexers MUX1 AND MUX2, AND the specific connection manner is shown in fig. 4A, AND the strobe control interface on the connection module may include EN1, EN2, SEL1 AND SEL2, where the strobe signal received by the strobe control interface is generated by the configuration file generated by the configuration tool.

In one example, when the strobe signal received by SEL1 is 00, the strobe signals received by sel2 are 00, and the strobe signals received by EN1 and EN2 are 0, the first input port LOGin of MUX1 and the first output port LOGout of MUX2 may be strobed, so that the connection module may output the data received by the first input port LOGin from the first output port LOGout, and the strobed data transmission route is shown in fig. 5A.

In another gating manner, when the strobe signal received by SEL1 is 00 AND the strobe signal received by sel2 is 10 (at this time, the MUX2 outputs an invalid default value), AND the strobe signals received by EN1 AND EN2 are 0 AND1, respectively, the first input port LOGin of MUX1 AND the second output port IPout of AND2 may be gated, so that the connection module may output the data received by the first input port LOGin from the second output port IPout, AND the gated data transmission route is shown in fig. 5B.

In another gating manner, when the strobe signal received by SEL1 is 00, the strobe signals received by sel2 is 10, AND the strobe signals received by EN1 AND EN2 are 1 AND 0, respectively, the first input port LOGin of MUX1 AND the third output port IPCout of AND1 may be gated, so that the connection module may output the data received by the first input port LOGin from the third output port IPCout, AND the gated data transmission route is shown in fig. 5C.

In still another gating manner, when the strobe signal received by SEL1 is 01, the strobe signals received by SEL2 are 00, and the strobe signals received by EN1 and EN2 are 0, the second input port IPin of MUX1 and the first output port LOGout of MUX2 may be gated, so that the connection module may output the data received by the second input port IPin from the first output port LOGout, and the gated data transmission route is shown in fig. 5D.

In another gating manner, when the strobe signal received by SEL1 is 01, the strobe signals received by sel2 is 10, AND the strobe signals received by EN1 AND EN2 are 0 AND1, respectively, the second input port IPin of MUX1 AND the second output port IPout of AND2 may be gated, so that the connection module may output the data received by the second input port IPin from the second output port IPout, AND the gated data transmission route is shown in fig. 5E.

In the sixth gating manner, when the gating signal received by SEL1 is 01, the gating signal received by sel2 is 10, AND the gating signals received by EN1 AND EN2 are 1 AND 0, respectively, the second input port IPin of MUX1 AND the third output port IPCout of AND1 may be gated, so that the connection module may output the data received by the second input port IPin from the third output port IPCout, AND the gated data transmission route is shown in fig. 5F.

In the seventh gating manner, when the strobe signal received by SEL1 is 10, the strobe signals received by SEL2 is 00, and the strobe signals received by EN1 and EN2 are 0, the third input port LOGin of MUX1 and the first output port LOGout of MUX2 may be gated, so that the connection module may output the data received by the third input port LOGin from the first output port LOGout, and the gated data transmission route is shown in fig. 5G.

In the eighth gating manner, when the gating signal received by SEL1 is 10, the gating signals received by sel2 is 10, AND the gating signals received by EN1 AND EN2 are 0 AND1, respectively, the third input port LOGin of MUX1 AND the second output port IPout of AND2 may be gated, so that the connection module may output the data received by the third input port LOGin from the second output port IPout, AND the gated data transmission route is shown in fig. 5H.

In the ninth gating manner, when the gating signal received by SEL1 is 10, the gating signals received by sel2 is 10, AND the gating signals received by EN1 AND EN2 are 1 AND 0, respectively, the third input port LOGin of MUX1 AND the third output port IPCout of AND1 may be gated, so that the connection module may output the data received by the third input port LOGin from the third output port IPCout, AND the gated data transmission route is shown in fig. 5I.

In the tenth gating manner, when the strobe signal received by SEL1 is 11 and the strobe signal received by sel2 is 01, the first output port LOGout of the MUX2 may be gated, so that the connection module may output the data received by the first input port LOGin from the first output port LOGout, and the gated data transmission route is shown in fig. 5J.

In addition, when one input port is gated, a plurality of output ports can also be controlled to be simultaneously gated by a gating control signal. For example, when the strobe signal received by SEL1 is 00, the strobe signals received by sel2 is 10, AND the strobe signals received by EN1 AND EN2 are 1, the first input port LOGin of MUX1, the second output port IPout of AND2, AND the third output port IPCout of AND1 may be strobed, so that the connection block may simultaneously output data received by the first input port LOGin from the second output port IPout AND the third output port IPCout, AND the strobed data transmission route is as shown in fig. 5K.

It should be noted that, there are other cases where multiple output ports are simultaneously gated, and the basic principle is the same as that of the above case, and will not be described in detail here.

As shown in fig. 2, the IPC11, the IPC12, the IPC13 and the IPC14 are sequentially connected, and by setting the strobe control signal of EN1 of the IPC12 to a disable signal (e.g., 0), data in the IPC12 can be made unable to be transmitted to the IPC13, so that the connection module chain is divided into two segments, namely, a first segment formed by connecting the IPC11 and the IPC12 and a second segment formed by connecting the IPC13 and the IPC14. Therefore, the connecting module chain can be set to be in the form of a programmable line segment by controlling the level of the gating control signal, and each segment can independently transmit different data, so that parallel transmission of the data can be realized, and the data transmission efficiency is improved. For example, the total number of connection modules may be 320, which may be divided into 32 connection module groups by a control strobe signal, each connection module group including 10 connection modules, each connection module group being used to transmit one bit of data, and thus may be used to transmit 32 bits of data in parallel.

In one embodiment, the first connection module of the first connection module group is electrically connected to the last connection module, and as illustrated in fig. 6, the connection module IPC14 may be electrically connected to the connection module IPC 11. Therefore, each connecting module in the first connecting module group can form an annular structure, and data can be transmitted in the annular structure in series, so that the data can be transmitted from one connecting module in the first module group to any other connecting module, the range of data transmission is expanded, the wiring mode is more flexible to select, and the problem of wiring congestion can be better avoided.

In one embodiment, the FPGA chip 1 may further include a second connection module group including a plurality of connection modules; each connecting module in the second connecting module group is respectively positioned between different winding resources and the IP module, and each connecting module is respectively electrically connected with the adjacent winding resources and the adjacent IP module; each connecting module except the first connecting module and the last connecting module in the second connecting module group is electrically connected with the adjacent connecting modules on two sides of the connecting module; each connection module is used for receiving data from the winding resource, the IP module and the lower connection module which are electrically connected with the connection module and sending data to the winding resource, the IP module and the upper connection module which are electrically connected with the connection module.

In this way, the first connection module group and the second connection module group are respectively arranged around the winding resources in the FPGA chip 1, and data can be transmitted in the first connection module group and the second connection module group respectively, so that the number of connection modules around the winding resources is increased, the range of data transmission is expanded, and the selection of the wiring mode is more flexible. Meanwhile, the embodiment of the application can flexibly set the positions of the connecting modules of the first connecting module group according to actual needs, and can flexibly set the positions of the connecting modules of the second connecting module group, so that the connecting modules play a better role in transferring when data interaction is carried out between logic resources and IP modules.

It should be noted that, in the embodiment of the present application, the number of the connection module groups may be set according to actual needs, and may be three, four or even more, which is not limited in the embodiment of the present application.

In an embodiment, when the IP module performs data interaction with the logic resource by using a parallel bus, the parallel bus may be an exemplary 32-bit bus, and the number of the first connection module groups may also be 32 bits, so that each bit of the parallel bus may be connected to one first connection module group, each bit of data may be transmitted through one first connection module group, and 32 bits of data may be synchronously and parallelly transmitted through 32 first connection module groups, thereby improving data transmission efficiency. Of course, the number of bits of the parallel bus may be other, and the basic principle is the same as that of the above case, and will not be described in detail here.

Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.

The foregoing embodiments have been provided for the purpose of illustrating the general principles of the present application in further detail, and are not to be construed as limiting the scope of the application, but are merely intended to cover any modifications, equivalents, improvements, etc. based on the teachings of the application.

Claims (6)

1. The FPGA chip comprises a winding resource, a logic resource and an IP module, and is characterized by further comprising a first connection module group, wherein the first connection module group comprises a plurality of connection modules; each connecting module in the first connecting module group is respectively positioned between different winding resources and the IP module, and each connecting module is respectively electrically connected with the adjacent winding resources and the adjacent IP module; each connecting module except the first connecting module and the last connecting module in the first connecting module group is electrically connected with the adjacent connecting modules on two sides of the connecting module;

each connection module is used for receiving data from the winding resource, the IP module and the lower connection module which are electrically connected with the connection module and sending data to the winding resource, the IP module and the upper connection module which are electrically connected with the connection module.

2. The chip of claim 1, wherein each of the connection modules has an input port, the input ports including a first input port, a second input port, and a third input port; wherein the first input port is configured to receive first data from a winding resource electrically connected thereto; the second input port is used for receiving second data from an IP module electrically connected with the second input port; the third input port is used for receiving third data from a lower-level connection module electrically connected with the third input port;

the connecting modules are respectively provided with an output port, and the output ports comprise a first output port, a second output port and a third output port; the first output port is used for sending fourth data to a winding resource electrically connected with the first output port; the second output port is used for sending fifth data to the IP module electrically connected with the second output port; and the third output port is used for sending sixth data to the upper-level connection module electrically connected with the third output port.

3. The chip of claim 2, wherein the chip comprises a plurality of chips,

and each connection module is provided with a data gating control port for receiving gating signals and controlling gating of the input port and gating of the output port according to the gating signals.

4. The chip of claim 1, wherein a first connection module of the first set of connection modules is electrically connected to a last connection module.

5. The chip of claim 1, wherein the FPGA chip further comprises a second set of connection modules, the second set of connection modules comprising a plurality of connection modules; each connecting module in the second connecting module group is respectively positioned between different winding resources and the IP module, and each connecting module is respectively electrically connected with the adjacent winding resources and the adjacent IP module; each connecting module except the first connecting module and the last connecting module in the second connecting module group is electrically connected with the adjacent connecting modules on two sides of the connecting module;

each connection module is used for receiving data from the winding resource, the IP module and the lower connection module which are electrically connected with the connection module and sending data to the winding resource, the IP module and the upper connection module which are electrically connected with the connection module.

6. The chip of claim 1, wherein the IP blocks transmit data using a parallel bus, and the number of first groups of connection blocks is equal to the number of bits of the parallel data bus.