CN116736935A

CN116736935A - Event time calibration method, system, equipment and medium

Info

Publication number: CN116736935A
Application number: CN202310749045.8A
Authority: CN
Inventors: 孙宇
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2023-06-25
Filing date: 2023-06-25
Publication date: 2023-09-12

Abstract

The invention belongs to the field of computers, and particularly relates to an event time calibration method, an event time calibration system, event time calibration equipment and event time calibration media, wherein the event time calibration method comprises the following steps: setting an event capturing module independent of a processor, and counting time according to a clock signal in the event capturing module; the method comprises the steps that an event signal circuit is connected to an event capturing module, and whether signal change occurs on the signal circuit or not is judged through the event capturing module; in response to generating the signal change, the event is marked by taking the value of the time count when the signal changes as the time stamp of the event corresponding to the signal. According to the event time calibration method provided by the invention, the event calibration task is processed by setting the event capture module independent of the CPU, so that errors caused by the influence of the performance of the CPU processor and the complexity of system software can be effectively solved, and the accuracy of the event calibration task is improved.

Description

Event time calibration method, system, equipment and medium

Technical Field

The invention belongs to the field of computers, and particularly relates to an event time calibration method, an event time calibration system, event time calibration equipment and event time calibration media.

Background

In the embedded field, an embedded processor is the core of an embedded system and is a hardware unit used to control and/or assist the operation of the system. The range of applications is extremely broad. From the development of the embedded field, from the first 4-bit processor and the 8-bit singlechip which is still applied on a large scale, to the latest and widely favored 32-bit and 64-bit embedded CPU (Central Processing Unit ). The embedded processor is used as the core of the embedded system and is used for carrying important tasks of controlling the system to work, so that the host equipment is intelligent and flexible in function design and convenient to operate. To accomplish these tasks reasonably efficiently, embedded processors typically have the following features: strong real-time multitasking support capability, memory area protection, scalable microprocessor architecture, strong interrupt handling capability, and low power consumption. The embedded CPU processor realizes the management, control and man-machine interaction functions of various intelligent products through specific hardware and software, and plays an important role in realizing the functions of the intelligent products. In the field of industrial automation, an embedded CPU is added into an intelligent instrument and a control device to realize an important function, namely, the time of occurrence of key events such as a sensor, a control switch, a warning and the like can be accurately recorded. In a CPU processor, an RTC (Real Time Clock) built in a chip is generally used to implement an application of a function related to Time information. In embedded CPU system designs, calibration of a particular input-output event timestamp is typically implemented based on the RTC.

The event input/event output is an external interface associated with the implementation of a particular application by the embedded CPU system, such as a control switch input/output signal in a circuit protection device, or a temperature, humidity sensor alarm input and cooling fan control output on an industrial automation line, etc. The signals generated by the special events are converted into interrupt input and event type signals which can be identified by the CPU through a monitoring input/output event circuit in the embedded CPU system design, and then the interrupt input and the event type signals are input to a CPU processor. After the CPU receives the signals, the software responds to the interrupt application and enters an interrupt service routine, the CPU event interrupt service routine reads the current time from the RTC function module and generates an event record message after being related to the event of the current application interrupt, and the data record or forwarding is completed through the software, so that the submitting of upper network management information or the man-machine interaction function is further realized.

However, in the whole process above, it can be found that the embedded CPU system needs to undergo multiple hardware and software processes in the process of completing the recording of an event, and each process may bring a certain error to the precision of the timestamp calibration corresponding to the event.

Further, as shown in fig. 1, a general input/output event is input to the embedded CPU, and a corresponding interrupt program or a processing program in the embedded CPU obtains a current clock from the RTC module to determine a time corresponding to the current clock, and the corresponding time is used as an event occurrence time of the input/output event to perform calibration. In view of fig. 1 and the above-mentioned time calibration process, after an event signal is input to a CPU, a program on the CPU is required to process the event, and in this process, there is a problem that a plurality of programs compete for the execution authority of the CPU, so a certain time delay is caused, and secondly, after a corresponding interrupt program or a processing program acquires the execution authority of the CPU, a clock signal is acquired from an RTC module to calculate a corresponding time, and in this process, a situation of requesting the clock signal and responding to the clock signal exists, so a time delay is further caused, which results in inaccurate time calibration of the event, especially when tasks executed on the CPU are excessive, and a larger error is caused by the input/output of the target of the event. Further, serious errors are generated in the time of the input/output events, and even when a plurality of events arrive at the CPU, a certain time gap may exist between the actual occurrence time of the plurality of events, but the processing mechanism of the interrupt program may time-scale the plurality of events in a short time, so that the time of scaling the plurality of events is almost the same.

Therefore, an effective way is needed to solve the problem of inaccurate event time calibration caused by the conventional event time calibration method.

Disclosure of Invention

In order to solve the above-mentioned problems, the present invention provides an event time calibration system, comprising:

the clock signal module is connected with the event capturing module and is configured to provide a clock signal for the event capturing module;

the event capturing module is independent of the processor and is communicated with the processor, and is used for acquiring an event signal input to the processor, calibrating the occurrence time of the event signal according to a clock signal of the clock signal module, and transmitting the calibrated event signal to the processor;

and the processor is configured to execute corresponding event processing logic according to the calibration time of the event signal by the event capturing module.

The invention also provides an event time calibration method, which comprises the following steps:

setting an event capturing module independent of a processor, and counting time according to a clock signal in the event capturing module;

the method comprises the steps that an event signal circuit is connected to an event capturing module, and whether signal change occurs on the signal circuit or not is judged through the event capturing module;

in response to generating the signal change, the event is marked by taking the value of the time count when the signal changes as the time stamp of the event corresponding to the signal.

In some embodiments of the invention, the setting an event capture module independent of the processor, and the counting time in the event capture module according to the clock signal comprises:

judging whether the clock period of the clock signal is greater than the target measurement precision of event time calibration;

and in response to the judgment, the frequency of the clock signal is increased in a preset mode so that the clock period of the increased clock signal is smaller than the target measurement precision.

In some embodiments of the present invention, increasing the frequency of the clock signal in a predetermined manner such that the clock period of the increased clock signal is less than the target measurement accuracy comprises:

calculating the frequency of a corresponding target clock signal according to the target measurement accuracy;

determining the frequency of a basic clock crystal oscillator of a crystal oscillator chip, and dividing the frequency of the target clock signal by the frequency of the basic clock crystal oscillator to obtain a corresponding first frequency multiplication value;

and inputting the first frequency multiplication value into the crystal oscillator chip to acquire the frequency of the clock signal which is greater than or equal to the frequency of the target clock signal after the lifting.

In some embodiments of the present invention, increasing the frequency of the clock signal in a predetermined manner such that the clock period of the increased clock signal is less than the target measurement accuracy further comprises:

dividing the target measurement accuracy by the period of the clock signal output by the crystal oscillator chip to obtain the number of clock arrays when the clock phase-locked loop is adopted for spread spectrum;

and determining the phase value of the clock phase-locked loop based on the number of the clock arrays, and setting the phase value into the corresponding phase-locked loop to obtain a plurality of clock arrays with equal phase difference.

In some embodiments of the invention, in response to generating the signal change, calibrating the event with a value of a time count at the time of the signal change as a timestamp of the event corresponding to the signal comprises:

setting a time counter updated synchronously with a clock signal of each clock array based on each clock array;

and generating a signal change by a signal circuit corresponding to the event in response to the corresponding event, and calibrating a value of a time counter corresponding to a clock array, which is obtained by adding one to the corresponding incomplete time count when the signal change is generated, as a time stamp of the event.

and converting the value of the time count when the signal changes into a common time to be used as the time stamp of the event, and sending the event and the corresponding converted time stamp to a processor or an event processor.

In some embodiments of the invention, the method further comprises:

and responding to the result of the judgment to be no, and taking the period of the clock signal as the target measurement precision.

Yet another aspect of the present invention is directed to a computer device comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of any of the above embodiments.

Yet another aspect of the invention also proposes a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method of any of the above embodiments.

According to the event time calibration method provided by the invention, the event calibration task is processed by setting the event capture module independent of the CPU, so that errors caused by the influence of the performance of the CPU processor and the complexity of system software can be effectively solved, and the accuracy of the event calibration task is improved.

Furthermore, the corresponding target measurement precision can be specified, the count value meeting the target measurement precision is realized by means of the clock signal based on the clock signal of the system according to different measurement precision, and the quick and accurate calibration of the event is realized according to the count value.

Furthermore, when the target measurement precision cannot be met by clock signals of the system because of the needs of other modules, a plurality of clock arrays are generated in a clock phase-locked loop mode, and corresponding time counters are arranged for each clock array, so that on one hand, accurate calibration of time stamps when events occur can be realized, and on the other hand, the occurrence of a plurality of events can be effectively monitored simultaneously, and the overall event calibration capability is improved.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an event time calibration process of a conventional embedded system according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an event time calibration process of an embedded system implemented by an FPGA according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an embedded system implemented by an FPGA according to an embodiment of the present invention;

FIG. 4 is a schematic flow chart of an event time calibration method according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an event time calibration system according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of an event time calibration process of an embedded system according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a computer device according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a computer readable storage medium according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

The invention aims to solve the problem that the time of event calibration caused by a traditional event calibration mechanism in an embedded system is inconsistent with the occurrence time of a real event. As mentioned above, the calibration of the event is completed by the related program in the CPU when the event occurs in the conventional embedded system, and the CPU in the embedded system usually adopts the time slice rotation method to schedule a plurality of sequences when running the program, so that the situation that the event cannot be calibrated in time when the event occurs, and the time calibration accuracy of the event is affected due to the fact that the CPU obtains the time from the RTC module in the communication process.

As shown in fig. 4, in order to solve the above-mentioned problems, the present invention provides an event time calibration method, which includes:

step S1, setting an event capturing module independent of a processor, and counting time in the event capturing module according to a clock signal;

s2, accessing an event signal circuit to the event capturing module, and judging whether signal change occurs on the signal circuit or not through the event capturing module;

and step S3, responding to the generation of the signal change, and marking the event by taking the time count value when the signal is changed as the time stamp of the event corresponding to the signal.

In the embodiment of the present invention, in step S1, a separate time capturing module is set outside the CPU of the embedded system, and the event capturing module may be other logic devices or logic circuits separately designed during the design of the embedded CPU, and in some embodiments of the present invention, the event capturing module is implemented by an FPGA (Field Programmable Gate Array ) design.

Therefore, in step S1, the corresponding time counter is incremented by one by counting according to the clock signal, i.e. every time a clock signal passes, by an event capture module independent of the CPU.

In step S2, the corresponding event signal circuit is connected to the event capturing module, and then the event capturing module monitors whether a corresponding potential change occurs on the connected circuit of the corresponding event signal. It should be noted that the signal circuit of the access event capturing module is not limited to only one, but at least one. The potential change may include from high level to low level or from low level to high level depending on the specification of the particular event signal. The event capturing module monitors the potential change of the accessed response event signal in real time.

In step S3, if there is a signal change in a certain signal circuit, the value of the current time counter in the event capturing module is latched, a specific event type is determined according to an event corresponding to the signal circuit in which the signal change occurs, and then the latched value of the time counter is used as a time stamp of the event type to calibrate the event. In some embodiments of the present invention, the event is further converted into a common time format according to the value of the time counter.

Further, in some embodiments of the invention, the calibrated event is sent to other computing units, such as a CPU or other computing module, that process the time.

In some embodiments, event calibration requires that the corresponding target measurement accuracy be specified, i.e., the minimum time unit for event calibration required by the project or upper layer application. Therefore, when the clock signal is used as a count basis, it is necessary to first determine whether or not the period (the reciprocal of the frequency) of the clock signal is greater than the set target measurement accuracy.

Further, if the period of the clock signal is greater than the target measurement accuracy, then when counting is performed according to the clock period, the time of one clock period is greater than the target measurement accuracy, and the target measurement accuracy requirement cannot be met. It is therefore necessary to boost the frequency of the clock signal to meet the demands on the accuracy of the target measurement.

In some embodiments, if the module for generating the clock signal is provided by a specific crystal oscillator chip, calculating the frequency of the corresponding target clock signal according to the target measurement accuracy, and calculating the inverse of the target measurement accuracy to obtain the frequency of the target clock signal corresponding to the target measurement accuracy.

Further, according to the frequency of the target clock signal divided by the frequency of the basic clock crystal oscillator of the crystal oscillator chip, a corresponding first frequency multiplication value is calculated, then the first frequency multiplication value is input into the crystal oscillator chip, and the crystal oscillator chip increases or exceeds the frequency of the basic clock crystal oscillator to the frequency of the target clock signal according to the first frequency multiplication value.

In this embodiment, when the clock signal has a strong correlation with other modules such as a CPU, that is, when the modules such as the CPU all need the crystal oscillator chip to provide a unified clock signal, it may be difficult to separately provide the clock signal meeting the target measurement accuracy for the event capturing module through one crystal oscillator chip. Therefore, in this case, the phase of the clock signal output by the crystal oscillator chip can be changed by the phase-locked loop to obtain a corresponding clock signal.

Specifically, the target measurement accuracy is first divided by the period of the clock signal output by the crystal oscillator chip, and the result of the division is used as the number of clock arrays when the clock phase-locked loop spreads. That is, assuming that the target measurement accuracy is 1 nanosecond (ns), and the frequency of the clock signal output by the crystal oscillator chip is 125Mhz, the period corresponding to the clock signal is 1/125 mhz=1/8 ns, and the target measurement accuracy is 1ns, 1 is divided by 1/8, and the number of corresponding clock arrays is 8 when the clock phase-locked loop is used for spreading.

Further, after determining the number of clock arrays, the phase of the phase-locked loop is 360 degrees, and 8 clock phases are in accordance with a uniform offset rule, and each clock array should be offset by 45 degrees, and the phase offset value can be input into the corresponding clock phase-locked loop to obtain 8 clock arrays with equal phase differences.

In this embodiment, as described above, after 8 clock arrays are acquired through the pll, a time count value is set based on each clock array, and it is also specified that after the clock pll expands, the value of each counter is incremented by 1 in turn every 1ns, i.e., in the first nanosecond, the value of the first time counter is incremented by 1, and the values of the other counters are unchanged. The value of the second counter is incremented by 1 for the second nanosecond, the values of the other counters are unchanged, and so on for each counter every 8ns, 1 is incremented.

When the corresponding event is generated, judging which clock counter corresponding to the clock array has not increased, and marking the event by multiplying the value of the counter by 8 and adding the number of the time counter as the time stamp of the event.

Further, in some embodiments of the invention, events are marked in terms of adult, month, day, hour, minute, second, nanosecond, by converting the counter value as needed. And then sending the event and the corresponding converted timestamp to a CPU or other modules for processing the event.

In some embodiments of the invention, the method further comprises:

In this embodiment, when the period of the clock signal is smaller than the target measurement accuracy, the period of the clock signal is used as the target measurement accuracy for event time calibration.

Several examples are further given below:

as shown in fig. 2, in this embodiment, an FPGA is taken as an example, and a corresponding event capturing module is designed in the FPGA to implement a time calibration function for an input/output event, and the calibrated event record is sent to a data recording and forwarding module, that is, a subsequent event processing module.

Specifically, the design structure inside the FPGA is shown in fig. 3, and the design principle is as follows:

the high-speed clock synchronization design module is designed in the FPGA capture event module, so that jump of a hardware interrupt source signal can be monitored in real time, when the monitored interrupt signal is sampled to trigger jump, real-time calibration of a trigger event and a corresponding time stamp is completed by latching the cnt_alarm and the event type at the same time, and the obtained event record is written into the FIFO (First In First Out, first-in first-out) memory.

Further, whether data exist in the FIFO memory is detected through the UART interface function, if so, the FIFO memory reading operation is initiated, the data are read out from the FIFO memory, the baud rate is set to be the same as that of the serial port of the CPU, and the data are sent to the CPU from the FPGA.

Furthermore, the clock signal is realized by DCM (Data Communication Module ), the DCM is a digital clock management function resource in the FPGA, and can multiply the clock signal output by the temperature compensation crystal oscillator chip.

Inside the FPGA, the bus configuration is converted into internal signals by means of an APB (an interface protocol) interface. The sync_fifo module can synchronize information from the bus configuration to the inside of cnt_alarm. The read_sync module can synchronize information to the APB bus clock domain. The LED lights may bind the cnt_alarm internal signal and may light up to alarm when certain events occur. The design can be realized by utilizing verilog codes according to functions and requirements of each module.

Specifically, the logic content of the event capturing module implemented in the FPGA is as follows:

the capture event module adopts a 125MHz high-speed clock synchronization design, but because external events are random relative to the high-speed clock inside the FPGA, if clock signals are directly used for capturing the events, errors of one clock cycle can exist. Therefore, in order to improve the measurement accuracy of the capture event, two clock phase-locked loops are adopted in the FPGA to obtain 8 clock arrays with equal phase differences, and the adjacent clock output phases of the clock arrays are sequentially offset by 1ns. These 8 125MHz clocks are used at the time of the capture event. (named as CLK125M_0, CLK125M_1, CLK125M_2, CLK125M_3, CLK125M_4, CLK125M_5, CLK125M_6, CLK125 M_7) as the time test clock of the pulse signal under test, the adjacent clock phase offset is 45 DEG, the rising edge time offset is 1ns. 32-bit time measurement counters controlled by the 8 clock excitation respectively, and jump time deviation of each counter is 1ns. The value of each time counter is updated once every 8 ns. The event is sampled to occur while latching cnt_alarm and event type.

Further, as shown in fig. 3, the cnt_alarm module function logic is as follows:

assume that a time counter corresponding to a signal change of an external event when a rising edge transition is detected by clk125_0 is tx+n (where Tx represents a count value of a current time counter and n represents a number corresponding to the time counter). The time when the pulse jump edge of the detected event occurs is the time. The unit of measurement resolution is ns, and the test accuracy can reach 1ns. The cnt_alarm module contains the transition of counts of year, month, day, hour, minute, second, nanosecond, and alarm interrupt functions, etc. The output signal links to each other with the LED lamp, when catching some events, detects rising edge jump, and the output signal links to each other with the LED lamp, can produce the bright lamp and indicate corresponding personnel in the outside.

Further, the method also comprises a DCM module:

DCM is a digital clock management function resource inside the FPGA, which multiplies the clock signal input from the temperature compensation crystal oscillator to 125MHz and outputs from BUFG (global clock buffer inside the FPGA) global clock network, through which high-speed clocks can be introduced into the FPGA internal function modules, providing them with working clocks, which can also be used for cnt_alarm modules and event capturing modules.

Further, a sync_fifo memory module is included for synchronizing APB bus clock domain and cnt_alarm internal working clock domain signals, synchronizing bus configuration information to the inside of cnt_alarm.

Further, a read_sync module is included for synchronizing time etc. information to the APB bus clock domain, which enables real-time reading of registers.

The bus configuration is further received via the APB interface and converted into an internal signal.

Further, the system also comprises a FIFO memory (First In First Out, first-in first-out) module, wherein the FIFO memory is composed of a BRAM data memory and read-write control logic in the FPGA and can store events.

Further, as shown in fig. 6, another embodiment of the present invention is as follows:

in a conventional embedded system, an event capturing module is implemented in front of an RTC module through a corresponding logic device, clock information is directly obtained from the RTC module, a signal for monitoring an input/output event is accessed to the logic device, the logic device calibrates the input/output event based on the clock signal of the RTC according to the above method, and the calibrated event is sent to a CPU. The method can be flexibly applied to the traditional embedded system, and the time calibration of the event can be accurately realized by only adding corresponding logic devices and updating a software system of the embedded system.

Furthermore, in some embodiments of the present invention, the calibration information of the corresponding event output by the logic device may also be directly skipped from the CPU and sent to the data recording and forwarding module in fig. 6, so as to completely implement an efficient manner without requiring CPU management. But the corresponding event information is sent to the CPU, and the CPU processes the corresponding event.

As shown in fig. 5, another aspect of the present invention further proposes an event time calibration system, including:

the clock signal module 1 is connected with the event capturing module, and the clock signal module 1 is configured to provide a clock signal for the event capturing module;

the event capturing module 2 is independent of the processor and is in communication with the processor, and is configured to acquire an event signal input to the processor, calibrate the occurrence time of the event signal according to the clock signal of the clock signal module, and send the calibrated event signal to the processor;

and a processor 3, wherein the processor 3 is configured to execute corresponding event processing logic according to the calibration time of the event signal by the event capturing module.

In this embodiment, the clock signal module 1 may be an RTC clock module existing in the current system, the event capturing module 2 may be a specially-made chip for executing the above method process, or a logic device for implementing the above method process through a corresponding logic device, such as an FPGA, etc., specifically using a scenario as shown in fig. 6, setting the event module 2 independently of a processor, inputting the clock signal of the RTC clock signal module to the event capturing module 2, inputting the corresponding event input signal to the event capturing module 2, calibrating the event signal by the event capturing module 2, and sending the calibrated event signal to the CPU for processing. The corresponding processing program in the CPU directly processes according to the calibrated event signals and the corresponding processing strategy, so that the situation that the event signal calibration is wrong caused when the corresponding event marking program in the CPU competes with CPU resources can be effectively avoided.

As shown in fig. 7, a further aspect of the present invention also proposes a computer device, including:

at least one processor 2001; and

a memory 2002, said memory 2002 storing computer instructions 2003 executable on said processor 2001, said instructions 2003 implementing an event time calibration method when executed by said processor 2001, comprising:

In some embodiments of the invention, the method further comprises:

As shown in fig. 8, a further aspect of the present invention further proposes a computer readable storage medium 401, said computer readable storage medium 401 storing a computer program 402, said computer program 402 implementing the steps of the method according to any of the above embodiments when being executed by a processor.

The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.

It should be understood that as used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The foregoing embodiment of the present invention has been disclosed with reference to the number of embodiments for the purpose of description only, and does not represent the advantages or disadvantages of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

Those of ordinary skill in the art will appreciate that: the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the disclosure of embodiments of the invention, including the claims, is limited to such examples; combinations of features of the above embodiments or in different embodiments are also possible within the idea of an embodiment of the invention, and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the embodiments should be included in the protection scope of the embodiments of the present invention.

Claims

1. An event time calibration system, comprising:

2. An event time calibration method, comprising:

3. The method of claim 1, wherein the setting up an event capture module independent of a processor and wherein the time counting in the event capture module based on a clock signal comprises:

4. A method according to claim 3, wherein said raising the frequency of the clock signal in a predetermined manner such that the clock period of the raised clock signal is less than the target measurement accuracy comprises:

and inputting the first frequency multiplication value to the crystal oscillator chip to acquire the frequency of the clock signal after the lifting of the frequency of the target clock signal.

5. A method according to claim 3, wherein said raising the frequency of the clock signal in a predetermined manner such that the clock period of the raised clock signal is less than the target measurement accuracy further comprises:

6. The method of claim 5, wherein in response to generating the signal change, calibrating the event with a value of a time count of the signal change as a timestamp of the event corresponding to the signal comprises:

7. The method of claim 1, wherein said calibrating the event with a value of a time count of the signal change as a timestamp of the event corresponding to the signal in response to generating the signal change comprises:

8. A method according to claim 3, further comprising:

9. A computer device, comprising:

at least one processor; and

a memory storing computer instructions executable on the processor, which when executed by the processor, perform the steps of the method of any one of claims 1-7.

10. A computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method of any one of claims 1-7.