CN116736191A - Pin state detection circuit, battery protection chip and battery management system - Google Patents

Pin state detection circuit, battery protection chip and battery management system Download PDF

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Publication number
CN116736191A
CN116736191A CN202310418230.9A CN202310418230A CN116736191A CN 116736191 A CN116736191 A CN 116736191A CN 202310418230 A CN202310418230 A CN 202310418230A CN 116736191 A CN116736191 A CN 116736191A
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CN
China
Prior art keywords
module
pin
signal
selection
state
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Pending
Application number
CN202310418230.9A
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Chinese (zh)
Inventor
朱治鼎
杨小华
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Shenzhen Chuangxin Microelectronics Co ltd
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Shenzhen Chuangxin Microelectronics Co ltd
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Priority to CN202310418230.9A priority Critical patent/CN116736191A/en
Publication of CN116736191A publication Critical patent/CN116736191A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/04—Voltage dividers
    • G01R15/06—Voltage dividers having reactive components, e.g. capacitive transformer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/36—Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC]
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/10—Energy storage using batteries

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)

Abstract

The application discloses a pin state detection circuit, a battery protection chip and a battery management system. The pin state detection circuit is used for protecting a chip of the battery, the selection pin is connected with the external resistor, the pin state detection circuit comprises a detection module, a control module, a switch module, a reference generation module and a state selection module, the reference generation module is used for generating selection voltage together with the external resistor, the detection module is used for generating a clock signal when the power-on reset pin is electrified, the control module is used for generating a control signal after receiving the clock signal at intervals of a preset period, and the switch module is used for disconnecting the power supply end from the reference generation module and the state selection module according to the control signal; the state selection module is used for being started according to the selection voltage of the reference generation module and the clock signal of the detection module, generating a state signal and being closed according to the control signal of the control module. The housekeeper state detection circuit can reduce power consumption and ensure accurate pin detection.

Description

Pin state detection circuit, battery protection chip and battery management system
Technical Field
The application relates to the technical field of electronics, in particular to a pin state detection circuit, a battery protection chip and a battery management system.
Background
The battery protection chip can realize the functions of overcharge protection, overdischarge protection, overcurrent protection, short-circuit protection and the like of the lithium battery. At present, the battery protection chip can be provided with a plurality of working modes, and different working modes can be switched according to the peripheral circuit, so that the battery protection chip can be adapted to different lithium batteries, and the universality of the battery protection chip is enhanced.
In the related art, the internal resistor and the external resistor of the battery protection chip form a voltage division, and the working mode is switched according to the voltage division difference of the external resistor. However, the application scene of the multi-string lithium battery is complex, large-current discharge or charge and even pulse load possibly exist in the use process, serious interference is caused to the peripheral environment of the chip, the external resistor is large, the anti-interference capability is poor, and safety accidents are easily caused. In addition, the internal resistance inevitably needs to consume power continuously, so that the power consumption of the battery protection chip is high.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the application provides a pin state detection circuit, a battery protection chip and a battery management system.
The pin state detection circuit is used for a battery protection chip, the battery protection chip comprises a selection pin, the selection pin is connected with an external resistor, the pin state detection circuit comprises a detection module, a control module, a switch module, a reference generation module and a state selection module, the reference generation module is connected with the selection pin, and the reference generation module is connected with the selection pin and is used for generating a selection voltage together with the external resistor;
the detection module is connected with a power-on reset pin and is used for generating a clock signal under the condition that the power-on reset pin is detected to be powered on;
the control module is connected with the detection module and is used for generating a control signal after receiving the clock signal and a preset period of time;
the switch module is connected with the control module, the power supply end, the reference generation module and the state selection module and is used for disconnecting the power supply end from the reference generation module and the state selection module according to the control signal;
the state selection module is connected with the detection module, the control module and the reference generation module and is used for being started according to the selection voltage of the reference generation module and the clock signal of the detection module and generating a state signal, and being closed according to the control signal of the control module.
In certain embodiments, the detection module comprises:
the detection unit is connected with the power-on reset pin and is used for detecting whether the power-on reset pin is powered on or not and generating an enabling signal after the power-on reset pin is powered on;
and the clock unit is connected with the detection unit and used for generating a clock signal according to the enabling signal.
In certain embodiments, the control module comprises:
the first delay unit is connected with the clock unit and is used for generating a starting signal according to the first preset time interval after the clock signal;
the second delay unit is connected with the first delay unit and is used for generating a control signal when receiving the starting signal at a second preset time interval, and the sum of the first preset time and the second preset time is equal to a preset time period.
In some embodiments, the state selection module includes:
the voltage dividing unit is respectively connected with the switch module and the grounding end and is used for generating a reference voltage;
the comparison unit is connected with the voltage division unit, the reference generation module and the control module and is used for generating a level signal according to the reference voltage and the selection voltage;
and the decoding unit is connected with the comparing unit and is used for generating the state signal according to the level signal.
In some embodiments, the voltage dividing unit includes a plurality of voltage dividing resistors, the plurality of voltage dividing resistors are connected in series, and the comparing unit includes a plurality of voltage dividing resistors, and each comparing unit is connected to one of the voltage dividing resistors.
In some embodiments, each of the comparison units comprises:
the comparator is respectively connected with the reference generation module, the voltage dividing resistor and the second delay unit, and is used for generating a level signal according to the selection signal and the voltage of the voltage dividing resistor and closing after receiving the control signal;
the third delay unit is respectively connected with the comparator and the detection module and is used for outputting the level signal at intervals of a first preset time after receiving the enabling signal;
and the trigger is connected with the third delay unit, the first delay unit and the decoding unit and is used for latching and outputting the level signal to the decoding unit when the starting signal is received.
In certain embodiments, the switch module comprises:
the first connecting end of the P-type switching tube is connected with the power supply end, the second connecting end of the P-type switching tube is connected with the reference generating module and the state selecting module, and the control end of the P-type switching tube is connected with the control module;
the P-type switching tube is closed under the condition that the control end does not receive a control signal, so that the power supply end is connected with the reference generation module and the state selection module, and is disconnected under the control of the control end, so that the power supply end is connected with the reference generation module and the state selection module.
In some embodiments, the reference generation module includes:
and the first end of the reference resistor is connected with the switch module, and the second end of the reference resistor is connected with the selection pin of the battery protection chip.
The battery protection chip of the embodiment of the application comprises the pin state detection circuit.
The battery management system comprises the battery protection chip, a battery and an external resistor, wherein the battery protection chip is connected with the battery and the external resistor, and the external resistor is also connected with the battery.
In the pin state detection circuit, the battery protection chip and the battery management system, the detection module is used for detecting the power-on condition of the power-on reset pin, so that whether the battery protection chip is powered on or not is determined, and a clock signal is generated after the battery protection chip is powered on, so that the state selection module can jointly generate the state signal according to the clock signal and the selection voltage of the reference generation module, the battery protection chip can switch the working mode according to the state signal, the state signal is detected when the battery protection chip is just powered on, no high current is ensured in the application environment, the periphery of the battery protection chip is prevented from being infected, the accuracy of the state signal is ensured, the control module can generate a control signal after a preset period of time interval according to the clock signal so as to control the switch module to be disconnected and the state selection module to be disconnected, the power supply of the reference generation module and the state selection module by the power supply terminal is avoided, and the power consumption of the pin state detection circuit is reduced.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a block diagram of a pin status detection circuit according to an embodiment of the present application;
fig. 2 is a schematic block diagram of a battery protection chip according to an embodiment of the present application;
fig. 3 is a block diagram of a battery management system according to an embodiment of the present application.
Description of main reference numerals:
the power-on reset pin POR comprises a pin state detection circuit 10, a detection module 11, a detection unit 111, a clock unit 112, a control module 12, a first delay unit 121, a second delay unit 122, a switch module 13, a P-type switch tube PMOS, a reference generation module 14, a reference resistor Ru, a state selection module 15, a voltage division unit 151, a voltage division resistor Rn, a comparison unit 152, a comparator 1521, a third delay unit 1522, a trigger 1523, a decoding unit 153, a battery protection chip 100, a selection pin SEL, a power-on reset pin POR, a power supply end VDD, a ground end GND, an external resistor Rex, a clock signal Clk, a start signal Por1, a control signal Por2, a state signal SATAE, a selection voltage SEL, a battery 200 and a battery management system 1000.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The following disclosure provides many different embodiments, or examples, for implementing different features of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
In various portable electronic products, low power consumption and long endurance are the trends. Therefore, low power chip design is a common pursuit. Meanwhile, the chip is controlled to work in different modes through the periphery of the chip so as to adapt to different customer requirements, and the chip also becomes a requirement of terminal manufacturers. Therefore, for the battery protection chip, the peripheral circuit is used for controlling the battery protection chip to work in different battery node number states so as to adapt to more requirements and scenes, and the enhancement of the universality is very necessary.
In the related art, the battery protection chip can work in different battery sections or other different functional modes through the size of the external resistor of the SEL pin. The main principle is that the internal resistor and the external resistor of the battery protection chip form partial pressure, and the external resistor is different in partial pressure due to different sizes, so that the corresponding node number or working mode is identified. Or, a bias current flows to the pin of the SEL through the inside of the battery, and different voltages are generated through different resistances connected to the outside of the SEL, so that the corresponding number of nodes or the working mode of the battery can be identified. And provides possibility for flexible application of the battery protection chip.
However, the application scene of the multi-string lithium battery is complex, a large current discharge or charge or even a pulse load may exist in the use process, so that serious interference is caused to the peripheral environment of the battery protection chip, the resistance of the SEL pin is large, the anti-interference capability is poor, and in the application process, the battery protection chip cannot be normally protected or is erroneously protected due to the fact that an error state is recognized due to interference, so that safety accidents are caused. In addition, the SEL pin also depends on an internal resistor to form voltage division or depends on an internal flowing current to generate voltage of a corresponding state, and the unavoidable requirement is that power consumption is continuously consumed, which is contrary to the current pursuit of low power consumption.
In view of this, please refer to fig. 1-3 in combination, the pin state detection circuit 10 of the embodiment of the present application is used for setting the battery protection chip 100 to an operation mode, the battery protection chip 100 includes a selection pin SEL, the selection pin SEL is connected to the external resistor Rex, the pin state detection circuit 10 includes a detection module 11, a control module 12, a switch module 13, a reference generation module 14 and a state selection module 15, and the reference generation module 14 is connected to the selection pin SEL for generating the selection voltage SEL.
The detection module 11 is connected to a power-on reset pin POR for generating a clock signal Clk in case a power-on of the power-on reset pin POR is detected.
The control module 12 is connected to the detection module 11 for generating a control signal Por2 after a predetermined period of time after receiving the clock signal Clk.
The switch module 13 is connected to the control module 12, the power supply terminal VDD, the reference generation module 14, and the state selection module 15, and is configured to disconnect the power supply terminal VDD from the reference generation module 14 and the state selection module 15 according to the control signal port 2.
The state selection module 15 is connected to the detection module 11, the control module 12 and the reference generation module 14, and is configured to turn on and generate a state signal SATAE of the selection pin SEL according to the selection voltage SEL of the reference generation module 14 and the clock signal Clk of the detection module 11, and turn off according to the control signal Por2 of the control module 12.
In the pin state detection circuit 10 of the present application, the detection module 11 detects the power-on condition of the power-on reset pin POR, so as to determine whether the battery protection chip 100 is powered on, and generate the clock signal Clk after the battery protection chip 100 is powered on, so that the state selection module 15 can jointly generate the state signal SATAE of the selection pin SEL according to the clock signal Clk and the selection voltage SEL of the reference generation module 14, so that the battery protection chip 100 can switch the working mode according to the state signal SATAE.
The pin state detection circuit 10 of the present embodiment is located in the battery protection chip 100 and is used for detecting the state of the selection pin SEL, that is, the battery protection chip 100 includes the pin state detection circuit 10, and the battery protection chip 100 can operate in different battery number or other different functional modes according to the state signal SATAE generated by the pin state detection circuit 10.
Note that, the duration of the predetermined period is longer than the time of generating the state signal SATAE, that is, the time of generating the control signal port 2 needs to be after the time of generating the state signal SATAE of the selection pin SEL. It will be appreciated that the control signal port 2 is for turning off the switching module 13 and the state selection module 15, thereby reducing the power consumption of the pin state detection circuit 10, and therefore, the control signal port 2 is regenerated to turn off the pin state detection circuit 10 only after the generation of the state signal SATAE determines the operation mode of the battery protection chip 100.
Referring to fig. 2, in some embodiments, the detection module 11 includes a detection unit 111 and a clock unit 112, where the detection unit 111 is connected to a power-on reset pin POR, and is configured to detect whether the power-on reset pin POR is powered on, and generate an enable signal after the power-on reset pin POR is powered on, and the clock unit 112 is connected to the detection unit 111, and is configured to generate the clock signal Clk according to the enable signal.
Specifically, when the power-on reset pin POR is powered up, the voltage of the power-on reset pin POR is set high, the detection unit 111 is connected to the power-on reset pin POR and the control module 12 respectively, and when the power-on reset pin POR is confirmed to be powered up after the voltage for detecting the power-on reset pin POR is set high is detected, a clock signal Clk is generated and transmitted to the control module 12, so that the control module 12 generates a control signal POR2 at intervals of a predetermined period after receiving the clock signal Clk, thereby controlling the switch module 13 and the state selection module 15 to be turned off, and reducing the power consumption of the pin state detection circuit 10.
Referring to fig. 2, in some embodiments, the control module 12 includes a first delay unit 121 and a second delay unit 122, where the first delay unit 121 is connected to the clock unit 112 and is configured to generate the start signal Por1 according to a first preset time interval after the clock signal Clk, and the second delay unit 122 is connected to the first delay unit 121 and is configured to generate the control signal Por2 according to a second preset time interval after the start signal Por1 is received, and a sum of the first preset time interval and the second preset time interval is equal to a predetermined period.
Specifically, the first delay unit 121 and the second delay unit 122 may be delays, and delay times of the first delay unit 121 and the second delay unit 122 are determined by a clock signal Clk, that is, the clock signal Clk is used to control delay lengths of the first delay unit 121 and the second delay unit 122. The first preset time may be greater than, equal to, or less than the second preset time.
It should be noted that, the first delay unit 121 may also be connected to the state selection module 15, so that the first delay unit 121 may send the start signal Por1 to the state selection module 15 to start the state selection module 15.
In this way, the first delay unit 121 delays the first preset time to generate the start signal Por1 after receiving the clock signal Clk to start the state selection module 15 and the second delay unit 122, so that the state selection module 15 may output the state signal SATAE, and the second delay unit 122 may delay the second preset time to generate the control signal Por2, so as to control the switch module 13 and the state selection module 15 to be turned off, thereby reducing the power consumption of the pin state detection circuit 10.
Referring to fig. 2, in some embodiments, the state selection module 15 includes a voltage division unit 151, a comparison unit 152, and a decoding unit 153, where the voltage division unit 151 is connected to the switch module 13 and the ground GND, respectively, for generating a reference voltage, the comparison unit 152 is connected to the voltage division unit 151, the reference generation module 14, and the control module 12, for generating a level signal according to the reference voltage and the selection voltage sel, and the decoding unit 153 is connected to the comparison unit 152, for generating a state signal SATAE according to the level signal.
Specifically, the voltage dividing unit 151 includes a plurality of voltage dividing resistors Rn connected in series, and the voltage dividing resistors Rn at the head and tail are respectively connected with the switch module 13 and the ground GND to form a loop, and each voltage dividing resistor Rn forms a reference voltage.
The comparing units 152 include a plurality of comparing units 152, each of which is connected to the reference generating module 14 and a voltage dividing resistor Rn, and each of the comparing units 152 respectively compares the reference voltage of the corresponding voltage dividing resistor Rn with the selection voltage sel to generate a level signal, so that each of the comparing units 152 can generate a level signal.
The level signal may be a digital signal or an analog signal. For example, the level signal may be a digital signal in the present application.
The decoding unit 153 is connected to each comparing unit 152, and is configured to receive the level signals generated by each comparing unit 152 and generate the status signal SATAE according to the level signals.
For example, in some examples, the voltage dividing resistor Rn includes R1, R2, R3, and R4, where R1, R2, R3, and R4 are sequentially connected in series between the switch module 13 and the ground GND. The comparing unit 152 includes a first comparing unit connected to the R1 and the reference generating module 14 for comparing the voltage at the R1 with the magnitude of the selection voltage sel and generating a first level signal, a second comparing unit connected to the R2 and the reference generating module 14 for comparing the voltage at the R2 with the magnitude of the selection voltage sel and generating a second level signal, a third comparing unit connected to the R3 and the reference generating module 14 for comparing the voltage at the R3 with the magnitude of the selection voltage sel and generating a third level signal, and a fourth comparing unit connected to the R4 and the reference generating module 14 for comparing the voltage at the R4 with the magnitude of the selection voltage sel and generating a fourth level signal. The decoding unit 153 may generate a unique state signal SATAE according to values of the first level signal, the second level signal, the third level signal, and the fourth level signal.
In this way, the battery protection chip 100 can set the operation mode according to the state signal SATAE of the select pin SEL to adapt to the battery.
In some embodiments, each comparison unit 152 includes a comparator 1521, a third delay unit 1522, and a flip-flop 1523.
The comparator 1521 is connected to the reference generating module 14, the voltage dividing resistor Rn and the second delay unit 122, and the comparator 1521 is configured to generate a level signal according to the selection signal and the voltage of the voltage dividing resistor Rn, and is turned off after receiving the control signal Por2. The third delay unit 1522 is connected to the comparator 1521 and the detection module 11, respectively, and is configured to output a level signal at a first preset time interval after receiving the enable signal. The flip-flop 1523 is connected to the third delay unit 1522, the first delay unit, and the decoding unit 153, and is configured to latch and output the level signal to the decoding unit 153 when receiving the start signal Por 1.
Specifically, the comparator 1521 includes a first input terminal, a second input terminal, a control terminal, and an output terminal, where the first input terminal is connected to the reference generating module 14, the second input terminal is connected to the voltage dividing resistor Rn, the control terminal is connected to the second delay unit 122, the output terminal is connected to the third delay unit 1522, and the comparator 1521 is configured to generate a level signal according to the selection voltage sel input by the first input terminal and the voltage input by the second input terminal, where the level signal may be a high level signal or a low level signal, and the level signal is output to the third delay unit 1522 by the output terminal. The comparator 1521 is also turned off in response to the control signal port 2 received by the control terminal. In this way, the power consumption of the pin state detection circuit 10 can be reduced and the performance of the battery protection chip 100 can be improved by turning off the pin state detection circuit 10 after generating the state signal SATAE.
The third delay unit 1522 is connected to the output terminal of the comparator 1521, the clock unit 112, and the trigger 1523, where the third delay unit 1522 is turned on when receiving the clock signal Clk of the clock unit 112, and outputs the level signal to the trigger 1523 at intervals of a first preset time after receiving the level signal output from the output terminal of the comparator 1521.
The flip-flop 1523 is further connected to the first delay unit 121 and the decoding unit 153, and the flip-flop 1523 latches and outputs the received level signal to the decoding unit 153 when the start signal Por1 inputted from the first delay unit 121 arrives as a clock edge, so that the decoding unit 153 can generate the status signal SATAE from the level signals transmitted from all the flip-flops 1523.
In some embodiments, the switch module 13 includes a P-type switch transistor PMOS, where a first connection terminal of the P-type switch transistor PMOS is connected to the power supply terminal VDD, a second connection terminal is connected to the reference generating module 14 and the state selecting module 15, and a control terminal is connected to the control module 12.
The P-type switching tube PMOS is closed when the control terminal does not receive the control signal Por2, so that the power supply terminal VDD is turned on with the reference generating module 14 and the state selecting module 15, and is opened under the control of the control terminal VDD so that the power supply terminal VDD is connected with the reference generating module 14 and the state selecting module 15.
It should be noted that the first connection end of the P-type switch tube PMOS may be a drain electrode, the second connection end may be a source electrode, and the control end may be a gate electrode. The P-type switch tube PMOS is turned on when the control terminal receives the low level signal and turned off when the control terminal receives the high level signal, that is, the control signal Por2 may be at a high level.
In this way, by setting the P-type switch transistor PMOS, it is able to control whether the power supply terminal VDD supplies power to the switch module 13 and the state selection module 15, so that after the state selection module 15 generates the state signal SATAE, it is able to control the power supply terminal VDD to stop supplying power to the switch module 13 and the state selection module 15, thereby reducing the power consumption of the battery protection chip 100.
In some embodiments, the reference generating module 14 includes a reference resistor Ru, a first end of which is connected to the switching module 13, and a second end of which is connected to the selection pin SEL of the battery protection chip 100.
In this way, the reference resistor Ru can be connected to the external resistor Rex connected to the selection pin SEL to generate the selection voltage SEL. Therefore, the purpose of controlling the battery protection chip 100 to work in different modes through the peripheral circuit of the battery protection chip 100 is achieved, so that the battery protection chip 100 can adapt to different customer requirements, and the application range of the battery protection chip 100 is widened.
Referring to fig. 3, the embodiment of the present application further provides a battery management system 1000, which includes a battery protection chip 100, a battery 200 and an external resistor Rex, wherein the battery protection chip 100 includes the pin status detection circuit 10 of any one of the embodiments, the battery protection chip 100 is connected to the battery 200 and the external resistor Rex, and the external resistor Rex is further connected to the battery 200.
In the battery management system 1000 and the battery protection chip 100 of the present application, the detection module 11 of the pin status detection circuit 10 detects the power-on condition of the power-on reset pin POR, so as to determine whether the battery protection chip 100 is powered on, and generate the clock signal Clk after the battery protection chip 100 is powered on, so that the status selection module 15 can jointly generate the status signal SATAE of the selection pin SEL according to the clock signal Clk and the selection voltage SEL of the reference generation module 14, so that the battery protection chip 100 can switch the working mode according to the status signal SATAE, and since the status signal SATAE is detected when the battery protection chip 100 is just powered on, it is ensured that the application environment has no large current, the periphery of the battery protection chip 100 is prevented from being infected, the accuracy of the status signal SATAE is ensured, and the control module 12 can generate the control signal POR2 according to the clock signal Clk after a predetermined period of time interval, so as to control the switch module 13 to be disconnected and control the status selection module 15 to be disconnected, thus, the power consumption of the power supply terminal VDD to the reference generation module 14 and the status selection module 15 is prevented from being powered on by the switch module 13, and the power consumption of the power supply terminal VDD of the state detection circuit 10 is reduced.
It should be noted that, the battery protection chip 100 may take the control signal Por2 generated by the control module 12 in the pin status detection circuit 10 as a global power-on enabling signal, and before the control signal Por2 is generated, the battery protection chip 100 does not allow other circuits to work, so as to ensure that no large current is applied to the environment, thus avoiding interference to the periphery of the battery protection chip 100 and ensuring that the status signal SATAE generated by the pin status detection circuit 10 is accurate.
Specifically, the battery protection chip further comprises a power supply pin (VCC), battery voltage sampling pins (VC 4-VC 1), a ground pin (VSS), a selection pin (SEL), a discharge overcurrent timing pin (TEC), a temperature sampling pin (CLR, DHR, CHR), a discharge/charge current sampling pin (VIN 1), a discharge control pin (DO), a charge control pin (CO) and a load and charger detection pin (VM).
The power supply pin (VCC) is used for supplying power to a circuit in the battery protection chip, the battery voltage sampling pins (VC 4-VC 1) are used for collecting the voltage of the battery, the ground pin (VSS) is connected with the ground terminal, the selection pin (SEL) is connected with the external resistor Rex, the selection pin (SEL) is used for determining whether the battery protection chip works in a three-lithium battery protection mode or a four-lithium battery protection mode, and meanwhile, whether the battery protection chip works in a low-voltage chargeable mode or a low-voltage forbidden charging mode can be determined.
A discharge overcurrent timing pin (TEC) controls the discharge control pin to output a low-level signal when the timing arrives, thereby prohibiting the battery from discharging.
The temperature sampling pin (CLR, DHR, CHR) is used for detecting the temperature of the battery, and when the detected temperature is abnormal, a low-level signal is output through the control discharging control pin (TEC) and the charging control pin (CO) to inhibit the battery from being charged or discharged.
And a discharging/charging current sampling pin (VIN 1) for prohibiting the battery from continuously charging or discharging by controlling the discharging control pin (DO) or the charging control pin (CO) when the charging/discharging current exceeds a preset value.
And the discharging control pin (DO) is used for controlling the discharging MOS to turn off to inhibit discharging when the under-voltage or the over-current of the battery is detected.
The charging control pin (CO) is used for controlling the charge MOS to be turned off and inhibit charging when the battery charging overvoltage or the charging overcurrent is detected. The load and charger detection pin (VM) is used to detect the presence or absence of the charger and load through the pin after charge and discharge protection to determine whether to resume charge and discharge behavior.
In the description of the present specification, reference to the terms "one embodiment," "certain embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the application, the scope of which is defined by the claims and their equivalents.

Claims (10)

1. The pin state detection circuit is used for a battery protection chip and is characterized by comprising a selection pin, wherein the selection pin is connected with an external resistor, the pin state detection circuit comprises a detection module, a control module, a switch module, a reference generation module and a state selection module, and the reference generation module is connected with the selection pin and is used for generating a selection voltage together with the external resistor;
the detection module is connected with a power-on reset pin and is used for generating a clock signal under the condition that the power-on reset pin is detected to be powered on;
the control module is connected with the detection module and is used for generating a control signal after receiving the clock signal and a preset period of time;
the switch module is connected with the control module, the power supply end, the reference generation module and the state selection module and is used for disconnecting the power supply end from the reference generation module and the state selection module according to the control signal;
the state selection module is connected with the detection module, the control module and the reference generation module and is used for being started according to the selection voltage of the reference generation module and the clock signal of the detection module and generating a state signal, and being closed according to the control signal of the control module.
2. The pin status detection circuit of claim 1, wherein the detection module comprises:
the detection unit is connected with the power-on reset pin, and is used for detecting whether the power-on reset pin is powered on or not and generating an enabling signal after the power-on reset pin is powered on;
and the clock unit is connected with the detection unit and used for generating a clock signal according to the enabling signal.
3. The pin status detection circuit of claim 2, wherein the control module comprises:
the first delay unit is connected with the clock unit and is used for generating a starting signal according to the first preset time interval after the clock signal;
the second delay unit is connected with the first delay unit and is used for generating a control signal when receiving the starting signal at a second preset time interval, and the sum of the first preset time and the second preset time is equal to a preset time period.
4. A pin status detection circuit according to claim 3 wherein the status selection module comprises:
the voltage dividing unit is respectively connected with the switch module and the grounding end and is used for generating a reference voltage;
the comparison unit is connected with the voltage division unit, the reference generation module and the control module and is used for generating a level signal according to the reference voltage and the selection voltage;
and the decoding unit is connected with the comparing unit and is used for generating the state signal according to the level signal.
5. The pin state detecting circuit of claim 4, wherein the voltage dividing unit comprises a plurality of voltage dividing resistors, the plurality of voltage dividing resistors are connected in series, the comparing unit comprises a plurality of comparing units, and each comparing unit is connected with one of the voltage dividing resistors.
6. The pin state detection circuit of claim 5, wherein each of the comparison units comprises:
the comparator is respectively connected with the reference generation module, the voltage dividing resistor and the second delay unit, and is used for generating a level signal according to the selection signal and the voltage of the voltage dividing resistor and closing after receiving the control signal;
the third delay unit is respectively connected with the comparator and the detection module and is used for outputting the level signal at intervals of a first preset time after receiving the enabling signal;
and the trigger is connected with the third delay unit, the first delay unit and the decoding unit and is used for latching and outputting the level signal to the decoding unit when the starting signal is received.
7. The pin status detection circuit of claim 1, wherein the switch module comprises:
the first connecting end of the P-type switching tube is connected with the power supply end, the second connecting end of the P-type switching tube is connected with the reference generating module and the state selecting module, and the control end of the P-type switching tube is connected with the control module;
the P-type switching tube is closed under the condition that the control end does not receive a control signal, so that the power supply end is connected with the reference generation module and the state selection module, and is disconnected under the control of the control end, so that the power supply end is connected with the reference generation module and the state selection module.
8. The pin state detection circuit of claim 1, wherein the reference generation module comprises:
and the first end of the reference resistor is connected with the switch module, and the second end of the reference resistor is connected with the selection pin of the battery protection chip.
9. A battery protection chip comprising the pin state detection circuit of any one of claims 1-8.
10. A battery management system, comprising the battery protection chip, a battery and an external resistor according to claim 9, wherein the battery protection chip is connected with the battery and the external resistor, and the external resistor is also connected with the battery.
CN202310418230.9A 2023-04-17 2023-04-17 Pin state detection circuit, battery protection chip and battery management system Pending CN116736191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310418230.9A CN116736191A (en) 2023-04-17 2023-04-17 Pin state detection circuit, battery protection chip and battery management system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310418230.9A CN116736191A (en) 2023-04-17 2023-04-17 Pin state detection circuit, battery protection chip and battery management system

Publications (1)

Publication Number Publication Date
CN116736191A true CN116736191A (en) 2023-09-12

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Family Applications (1)

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Country Link
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