CN116722047A - Power device - Google Patents

Power device Download PDF

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Publication number
CN116722047A
CN116722047A CN202310823581.8A CN202310823581A CN116722047A CN 116722047 A CN116722047 A CN 116722047A CN 202310823581 A CN202310823581 A CN 202310823581A CN 116722047 A CN116722047 A CN 116722047A
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CN
China
Prior art keywords
layer
metal electrode
power device
passivation layer
material layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310823581.8A
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Chinese (zh)
Inventor
陶永洪
蔡文必
徐少东
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Xiamen Sanan Integrated Circuit Co Ltd
Original Assignee
Xiamen Sanan Integrated Circuit Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xiamen Sanan Integrated Circuit Co Ltd filed Critical Xiamen Sanan Integrated Circuit Co Ltd
Priority to CN202310823581.8A priority Critical patent/CN116722047A/en
Publication of CN116722047A publication Critical patent/CN116722047A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices

Abstract

A power device relates to the technical field of semiconductor devices. The power device includes: a wide band gap substrate; a wide bandgap drift layer disposed on the wide bandgap substrate; a termination region and an active region disposed in the wide bandgap drift layer, the active region being located between the termination regions; the metal electrode layer is arranged on the active region, and schottky contact is formed between the metal electrode layer and the active region; the metal electrode layer has a top surface facing away from the wide bandgap drift layer and a first sidewall facing the termination region; a first material layer disposed on the first sidewall of the metal electrode layer; and a passivation layer covering the first material layer, the first material layer completely separating the metal electrode layer from the passivation layer. The power device can improve the reliability of the device.

Description

Power device
The application relates to a divisional application of application number CN202110725060.X, application date 2021, year 06, month 29 and the name of the application of a power device and a preparation method thereof.
Technical Field
The disclosure relates to the technical field of semiconductor devices, and in particular relates to a power device.
Background
The semiconductor power device is used as a core device in a power electronic circuit to realize efficient transmission and conversion of electric energy and effective and accurate control in the process of the electric energy, and high-quality and efficient utilization of the electric energy is realized. Due to research and development of power semiconductor devices, power electronics technology is developed toward miniaturization, large capacity, high frequency, high efficiency, energy saving, high reliability and low cost.
Conventional semiconductor power devices are typically covered with a passivation layer extending all the way to the front electrode surface in the termination area of the power device in order to prevent external moisture and mobile ions (such as sodium) from affecting the internal structure of the device. However, when the TCT (Temperature Cycle Test ) is performed on the power device, since the thermal expansion coefficients of the plastic package body, the front electrode and the passivation layer in the packaged device are different, stress is generated between the plastic package body and the front electrode due to mutual extrusion, so that the front electrode surface and the passivation layer are cracked, and water vapor and mobile ions in the air can enter the device along the cracks, thereby degrading the device performance and even causing the device to fail.
Disclosure of Invention
In order to improve the reliability of the device, the power device and the power are provided. The power device includes: a wide band gap substrate; a wide bandgap drift layer disposed on the wide bandgap substrate; a termination region and an active region disposed in the wide bandgap drift layer, the active region being located between the termination regions; the metal electrode layer is arranged on the active region, and schottky contact is formed between the metal electrode layer and the active region; the metal electrode layer has a top surface facing away from the wide bandgap drift layer and a first sidewall facing the termination region; a first material layer disposed on the first sidewall of the metal electrode layer; and a passivation layer covering the first material layer, the first material layer completely separating the metal electrode layer from the passivation layer.
By adopting the power device disclosed by the application, the reliability of the device is improved after TCT test.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present disclosure and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic structural diagram of a power device according to some embodiments of the present disclosure;
FIG. 2 is a second schematic diagram of a power device according to some embodiments of the present disclosure;
fig. 3 is a third schematic structural diagram of a power device according to some embodiments of the present disclosure;
fig. 4 is a schematic diagram of a power device according to some embodiments of the present disclosure;
fig. 5 is a schematic diagram of a power device according to some embodiments of the present disclosure;
fig. 6 is a schematic diagram of a power device according to some embodiments of the present disclosure.
Icon: 10-a wide bandgap substrate; a 20-wide bandgap drift layer; 21-an active region; a 22-terminal region; 31-schottky contact metal; 311-sub-metal layer; 32-a metal electrode layer; 321-top surface; 322-a first sidewall; 33-metal electrode contact areas; 41-a first material layer; 411-a first end face; 412-top; 413-a second end face; a 50A-passivation layer; 70-a protective layer; an 80-ohm metal layer; 90-back electrode layer.
Detailed Description
The embodiments set forth below represent the information necessary to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly extending onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "over" another element, it can be directly on or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Related terms such as "below" or "above" … "or" upper "or" lower "or" horizontal "or" vertical "may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It should be understood that these terms, and those terms discussed above, are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present disclosure provides a power device including: a wide bandgap substrate 10; a wide bandgap drift layer 20 disposed on the wide bandgap substrate 10; a termination region 22 and an active region 21 disposed in the wide bandgap drift layer 20, the active region 21 being located within the termination region 22; a metal electrode layer 32 disposed on the active region 21, the metal electrode layer 32 being in schottky contact with the active region 21, the metal electrode layer 32 having a top surface 321 facing away from the wide bandgap drift layer 20 and a first sidewall 322 facing the termination region 22; a first material layer 41 disposed on the first sidewall 322 of the metal electrode layer 32; and a passivation layer 50A covering the first material layer 41, the first material layer 41 completely separating the passivation layer 50A from the metal electrode layer 32.
According to the method, the passivation layer 50A is separated from the metal electrode layer 32 through the first material layer 41, and the first material layer 41 can balance thermal stress between the first material layer 41 and the metal electrode layer 32, so that when the passivation layer 50A is subjected to stress generated by thermal cycling in the TCT reliability test, the passivation layer 50A cannot crack due to the existence of the first material layer 41, and the problem that the device reliability is reduced due to the fact that the passivation layer 50A cracks after the TCT test of the device can be effectively solved.
In some embodiments, the material of the first material layer 41 has a coefficient of expansion a, the material of the metal electrode layer 32 has a coefficient of expansion b, and the material of the passivation layer 50A has a coefficient of expansion c, where a > b > c.
When the expansion coefficient of the material of the first material layer 41 is a, the expansion coefficient of the material of the metal electrode layer 32 is b, and the expansion coefficient of the material of the passivation layer 50A is c, wherein a > b > c, when the TCT reliability test is performed, the passivation layer 50A is subjected to stress generated by thermal cycling, and the passivation layer 50A is not cracked due to the existence of the first material layer 41, so that the problem that the device reliability is reduced due to the cracking of the passivation layer 50A after the device is subjected to the TCT test can be effectively solved.
In some embodiments, as shown in fig. 1, the wide bandgap substrate 10 is an N-type silicon carbide wide bandgap substrate 10. In some embodiments, the wide bandgap substrate 10 is in the form of 4H-SiC. In some embodiments, the wide bandgap substrate 10 has a thickness of 350 μm. In some embodiments, the wide bandgap substrate 10 has a doping concentration of 1×10 19 cm 3 Up to 1X 10 20 /cm 3 Between them. It should be understood that the above-described crystal form, thickness, and doping concentration of the wide bandgap substrate 10 are merely examples provided by some embodiments of the present disclosure and are not the only limitations of the present disclosure.
In some embodiments, as shown in fig. 1, the thickness of the wide bandgap drift layer 20 may be between 5 μm and 80 μm, for example, may be 5 μm, 10 μm, 30 μm, 50 μm, 70 μm, 80 μm, etc., which are not further listed in this disclosure. In some embodiments, the doping concentration of the wide bandgap drift layer 20 may be 1×10 14 /cm 3 Up to 5X 10 16 /cm 3 Between them.
In some embodiments, as shown in fig. 1, the active region 21 disposed in the wide band gap drift layer 20 may be stripe-shaped, hexagonal, or a combination of stripe-shaped and hexagonal.
In some embodiments, as shown in fig. 1, the metal electrode layer 32 is in schottky contact with the active region 21. In some embodiments, metal electrode layer 32 includes a schottky contact metal 31 disposed on a side of active region 21 facing away from wide bandgap substrate 10 and a sub-metal layer 311 disposed on a side of schottky contact metal 31 facing away from wide bandgap substrate 10. In some embodiments, the schottky contact metal 31 may have a thickness between 100nm and 500 nm. In some embodiments, the material of the schottky metal layer 31 may be any one of Ti, W, ta, ni, mo, and Pt or a combination of at least two of the foregoing metals. The thickness of the schottky metal layer 31 may be between 100nm and 500 nm. For example, the thickness of the schottky metal layer 31 may be 100nm, 200nm, 300nm, 400nm, 500nm, or the like.
In some embodiments, as shown in fig. 1, the thickness of the metal electrode layer 32 may be between 2 μm and 5 μm. Illustratively, the thickness of the metal electrode layer 32 may be 2 μm, 3 μm, 4 μm, 5 μm, or the like. The material of the metal electrode layer 32 may be any one of Al, ag, cu, and Au or a combination of at least two metals.
In some embodiments, as shown in fig. 1-6, passivation layer 50A extends over termination region 22 and is disposed in conforming relation with termination region 22.
In some embodiments, as shown in fig. 1, first material layer 41 is configured to extend from an edge of top surface 321 toward first sidewall 322 and over first sidewall 322, and passivation layer 50A is configured to extend from termination region 22 and over first material layer 41. The first material layer 41 is provided to completely or partially separate the passivation layer 50A and the metal electrode layer 32. In some embodiments, first material layer 41 may be polyimide. The polyimide material has a certain elasticity, so that when the passivation layer 50A is subjected to stress generated by thermal cycle during TCT test, the problem of reduced device reliability caused by cracking of the passivation layer 50A can be effectively avoided.
In some embodiments, as shown in fig. 1, the passivation layer 50A has a thickness between 1 μm and 3 μm. For example, the passivation layer 50A may have a thickness of 1 μm, 2 μm, 3 μm, or the like. In some embodiments, the material of passivation layer 50A is silicon oxide (e.g., siO 2) or silicon nitride (e.g., si3N 4). In some embodiments, the material of the first material layer 41 has a coefficient of expansion a, the material of the metal electrode layer 32 has a coefficient of expansion b, and the material of the passivation layer 50A has a coefficient of expansion c, where a > b > c. In this way, the present disclosure can effectively improve the problem of stress generated by mutual extrusion between the passivation layer 50A and the metal electrode layer 32 when TCT test is performed, so as to reduce the risk of cracking the passivation layer 50A and improve the reliability of the device.
In some embodiments, as shown in fig. 6, the power device provided by the present disclosure further includes a protective layer 70 overlying passivation layer 50A and metal electrode layer 32. In some embodiments, in actual use, protective layer 70 may be etched to expose portions of metal electrode layer 32, thereby forming metal electrode contact regions 33 (see fig. 6). The material of the protective layer 70 is polyimide. In some embodiments, the protective layer 70 may have a thickness between 3 μm and 5 μm, for example, 3 μm, 4 μm, or 5 μm.
In some embodiments, as shown in fig. 6, the power device provided by the present disclosure may further include an ohmic metal layer 80 on a side of the wide bandgap substrate 10 facing away from the wide bandgap drift layer 20, and a back electrode layer 90 on a side of the ohmic metal layer 80 facing away from the wide bandgap substrate 10. Wherein the thickness of the back electrode layer 90 may be between 2 μm and 5 μm. The material of the ohmic metal layer 80 may be any one metal of Ni, ti, nb, and Mo, and the thickness of the ohmic metal layer 80 may be between 100nm and 500 nm.
The power device provided by the disclosure can be a common schottky diode, a junction barrier schottky diode or a hybrid PIN schottky diode.
In some embodiments, as shown in fig. 1 to 3, the first material layer 41 is configured to extend from an edge of the top surface 321 toward the first sidewall 322 and cover the first sidewall 322, and the passivation layer 50A is configured to extend from the terminal region 22 and cover onto the first material layer 41, and hereinafter, the positions where the first material layer 41 and the passivation layer 50A are disposed will be exemplified, respectively.
In some embodiments, as shown in fig. 1, first material layer 41 includes a first end face 411 facing active region 21, and passivation layer 50A is configured to extend flush with first end face 411, at which point first material layer 41 completely separates passivation layer 50A from metal electrode layer 32.
In some embodiments, as shown in fig. 2, first material layer 41 includes a top end 412 facing away from metal electrode layer 32, and passivation layer 50A is configured to extend flush with top end 412 of first material layer 41. At this time, the passivation layer 50A is also completely separated from the metal electrode layer 32 by the first material layer 41.
In some embodiments, the first sidewall 322 has a height H as shown in fig. 3, and the passivation layer 50A is configured to extend over the first sidewall 322 above 1/2H. At this time, the first material layer 41 may also completely separate the passivation layer 50A and the metal electrode layer 32.
In some embodiments, as shown in fig. 4, 5 and 6, the first material layer 41 is configured to be flush with the top surface 321 of the metal electrode layer 32, and the passivation layer 50A is configured to cover the terminal region 22 and extend over the first material layer 41, and hereinafter, the positions where the first material layer 41 and the passivation layer 50A are disposed will be exemplified, respectively.
In some embodiments, as shown in fig. 5, the first material layer 41 includes a second end face 413 facing away from the wide bandgap drift layer 20, and the passivation layer 50A is configured to extend flush with the second end face 413. At this time, the first material layer 41 may completely separate the passivation layer 50A and the metal electrode layer 32.
In some embodiments, as shown in fig. 6, the first sidewall 322 has a height H, and the passivation layer 50A is configured to extend over the first sidewall 322 above 1/2H. At this time, the passivation layer 50A is also completely separated from the metal electrode layer 32 by the first material layer 41.
It should be noted that, in some embodiments, when the terminal regions 22 are distributed on opposite sides of the active region 21, the related designs related to the first material layer 41 and the passivation layer 50A mentioned in the disclosure may be disposed on one side of the active region 21, or may be disposed on opposite sides of the active region 21, respectively, which is not particularly limited in the disclosure.
The foregoing is merely an alternative embodiment of the present disclosure, and is not intended to limit the present disclosure, so that various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
In addition, the specific features described in the foregoing embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, the present disclosure does not further describe various possible combinations.

Claims (10)

1. A power device, comprising:
a wide band gap substrate;
a wide bandgap drift layer disposed on the wide bandgap substrate;
a termination region and an active region disposed in the wide bandgap drift layer, the active region being located between the termination regions;
the metal electrode layer is arranged on the active region, and schottky contact is formed between the metal electrode layer and the active region; the metal electrode layer has a top surface facing away from the wide bandgap drift layer and a first sidewall facing the termination region;
a first material layer disposed on a first sidewall of the metal electrode layer;
and a passivation layer covering the first material layer, the first material layer completely separating the metal electrode layer from the passivation layer.
2. The power device of claim 1, wherein the power device comprises a power source,
the expansion coefficient of the material of the first material layer is a, the expansion coefficient of the material of the metal electrode layer is b, and the expansion coefficient of the material of the passivation layer is c, wherein a > b > c.
3. The power device of claim 1, wherein the passivation layer extends onto and is disposed in conforming relation to the termination region.
4. The power device of claim 3, wherein the first material layer is configured to extend from an edge of the top surface toward and over the first sidewall, and the passivation layer is configured to extend from the termination region and over the first material layer.
5. The power device of claim 4, wherein the first material layer includes a first end face facing the active region, the passivation layer configured to extend flush with the first end face.
6. The power device of claim 4, wherein the first material layer includes a top end facing away from the metal electrode layer, the passivation layer configured to extend flush with the top end of the first material layer.
7. The power device of claim 4, wherein the first sidewall has a height H, and the passivation layer is configured to extend over the first sidewall above 1/2H.
8. The power device of claim 3, wherein the first material layer is configured to be flush with a top surface of the metal electrode layer, and the passivation layer is configured to cover the termination region and extend over the first material layer.
9. The power device of claim 8, wherein the first material layer includes a second end face facing away from the wide bandgap drift layer, the passivation layer configured to extend flush with the second end face.
10. The power device of claim 8, wherein the first sidewall has a height H, and the passivation layer is configured to extend over the first sidewall above 1/2H.
CN202310823581.8A 2021-06-29 2021-06-29 Power device Pending CN116722047A (en)

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