CN116721634A

CN116721634A - Display panel and display device

Info

Publication number: CN116721634A
Application number: CN202310603464.0A
Authority: CN
Inventors: 张文帅
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2023-05-25
Filing date: 2023-05-25
Publication date: 2023-09-08

Abstract

The invention relates to the technical field of display, and discloses a display panel and a display device, wherein the display panel comprises: a substrate base plate and sub-pixels; the sub-pixel includes a pixel circuit and a light emitting element; the pixel circuit comprises a driving module and a data writing module, wherein a control end of the data writing module is connected with a first scanning signal end, a first end of the data writing module is electrically connected with a first end of the driving module, and a second end of the data writing module is connected with a data signal end; the data signal ends of the sub-pixels arranged along the second direction are electrically connected with at least one data line; the working process of the pixel circuit comprises a data writing stage and a first bias stage; in the data writing stage, writing a data voltage signal to a data signal end by a data wire; in the first bias phase, the data line writes a bias compensation voltage signal to the data signal terminal. The invention can improve the offset and hysteresis of the characteristics of the driving transistor after long-term operation without increasing the wiring difficulty.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device.

Background

The organic light emitting display displays by utilizing the self-luminescence property of the organic semiconductor material, and compared with a liquid crystal display, the organic light emitting display does not need a backlight, and can effectively reduce the thickness of a display screen. In general, a pixel array composed of sub-pixels is provided in a display area of an organic light emitting display. Each sub-pixel comprises an organic light emitting diode, and is driven to emit light by a pixel circuit.

The pixel circuit generally comprises a driving transistor, a plurality of switching transistors and a storage capacitor, wherein a driving current generated by the driving transistor drives the organic light emitting element to emit light for display. In the prior art, in order to improve the offset and hysteresis of the long-term operation characteristics of the driving transistor, a signal line is generally added to transmit a bias compensation voltage signal to the source electrode of the driving transistor. However, the addition of the signal lines causes an increase in wiring difficulty, affects the design of the existing pixel circuit, and increases production cost.

Disclosure of Invention

In view of the above, the present invention provides a display panel and a display device, which can improve the offset and hysteresis of the characteristics of the driving transistor after long-term operation without increasing the difficulty of wiring.

The present invention provides a display panel, comprising: a substrate base; the plurality of sub-pixels are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction are intersected; the sub-pixel includes a pixel circuit and a light emitting element; the pixel circuit comprises a driving module and a data writing module, wherein the control end of the data writing module is connected with a first scanning signal end, the first end of the data writing module is electrically connected with the first end of the driving module, and the second end of the data writing module is connected with a data signal end; a plurality of data lines extending in a second direction, the data signal terminals of the sub-pixels arranged in the second direction being electrically connected to at least one data line; the working process of the pixel circuit comprises a data writing stage and a first bias stage; in the data writing stage, writing a data voltage signal to a data signal end by a data wire; in the first bias phase, the data line writes a bias compensation voltage signal to the data signal terminal.

Based on the same thought, the invention also provides a display device which comprises the display panel provided by the invention.

Compared with the prior art, the display panel and the display device provided by the invention have the advantages that at least the following effects are realized:

in the display panel provided by the invention, in the data writing stage, the data line writes the data voltage signal into the data signal end, in the first biasing stage, the data line writes the bias compensation voltage signal into the data signal end, namely, in the first biasing stage, the data line can be multiplexed to write the bias compensation voltage signal into the data signal end in the pixel circuit electrically connected with the data line, so that the bias compensation voltage signal is transmitted to the first end of the driving module, the signal line is not required to be additionally arranged to be electrically connected with the pixel circuit, the bias compensation voltage signal is transmitted to the first end of the driving module, the offset and hysteresis phenomena of the characteristics of the driving transistor after long-term working can be improved, meanwhile, the number of the signal lines in the display panel is effectively reduced, the wiring difficulty is effectively reduced, and the condition that the design difficulty of the pixel circuit is increased due to the increase of the signal line is avoided.

Of course, it is not necessary for any one product to practice the invention to achieve all of the technical effects described above at the same time.

Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic plan view of a display panel according to the present invention;

FIG. 2 is a schematic circuit diagram of a pixel circuit according to the present invention;

FIG. 3 is a timing diagram of a pixel circuit according to the present invention;

FIG. 4 is a schematic plan view of another display panel according to the present invention;

FIG. 5 is a schematic plan view of a display panel according to another embodiment of the present invention;

FIG. 6 is another driving timing diagram of a pixel circuit according to the present invention;

FIG. 7 is a schematic plan view of a display panel according to another embodiment of the present invention;

FIG. 8 is a further drive timing diagram of a pixel circuit provided by the present invention;

FIG. 9 is a further drive timing diagram of a pixel circuit provided by the present invention;

FIG. 10 is a further drive timing diagram of a pixel circuit provided by the present invention;

fig. 11 is a schematic plan view of a display device according to the present invention.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.

The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

Fig. 1 is a schematic plan view of a display panel provided by the present invention, fig. 2 is a schematic circuit diagram of a pixel circuit provided by the present invention, and referring to fig. 1 and 2, the present embodiment provides a display panel, which includes a substrate 10 and a plurality of sub-pixels 20 located on one side of the substrate 10, wherein the plurality of sub-pixels 20 are arranged in an array along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect. Optionally, the first direction X and the second direction Y are perpendicular. The sub-pixel 20 includes a pixel circuit 30 and a light emitting element 40. The base substrate 10 is usually made of a rigid glass substrate, or may be made of a flexible organic material such as polyimide or polyethylene terephthalate. The respective sub-pixels 20 on the base substrate 10 can form a picture display by the cooperation of color and brightness. The luminance adjustment of the sub-pixel 20 is controlled by the pixel circuit 30, and the pixel circuit 30 supplies a driving current to the light emitting element 40 electrically connected thereto, and the light emitting element 40 displays a certain luminance according to the magnitude of the driving current.

The pixel circuit 30 includes a driving module 31 and a data writing module 32, wherein a control end of the data writing module 32 is connected to the first scanning signal end S1, a first end of the data writing module 32 is electrically connected to the first end of the driving module 31, and a second end of the data writing module 32 is connected to the data signal end data.

The display panel further includes a plurality of data lines D extending in the second direction Y, and the data signal terminals data of the sub-pixels 20 arranged in the second direction Y are electrically connected to at least one data line D, and can transmit signals to the data signal terminals data of the pixel circuits 30 in the sub-pixels 20 electrically connected thereto through the data lines D.

Fig. 3 is a driving timing chart of a pixel circuit according to the present invention, and referring to fig. 1 to 3, in a display panel according to an embodiment of the present invention, an operation process of the pixel circuit 30 includes a data writing stage a and a first bias stage b. In the data writing stage a, the data line D writes the data voltage signal Vdata to the data signal terminal data. That is, in the data writing stage a, the data line D writes the data voltage signal Vdata to the second terminal of the data writing module 32, at this time, the data writing module 32 is turned on, the data voltage signal Vdata can be transmitted to the first terminal of the driving module 31, and the driving module 31 drives the light emitting element 40 to emit light according to the driving current generated based on the data voltage signal Vdata.

In the first bias phase b, the data line D writes the bias compensation voltage signal DVH to the data signal terminal data. That is, in the first bias phase b, the data line D writes the bias compensation voltage signal DVH to the second terminal of the data writing module 32, and at this time, the data writing module 32 is turned on, and the bias compensation voltage signal DVH may be transmitted to the first terminal of the driving module 31, thereby stabilizing the electrical performance of the driving module 31.

Specifically, as shown in fig. 2, the driving module 31 is generally provided with a driving transistor M3, and in the data writing stage a, the data line D writes the data voltage signal Vdata to the data signal terminal data, and the driving transistor M3 drives the light emitting element 40 to emit light based on the driving current generated by the data voltage signal Vdata. In the first bias phase b, the data line D writes the bias compensation voltage signal DVH to the data signal terminal data, thereby stabilizing the electrical performance of the driving module 31. The threshold voltage of the driving transistor M3 may be adjusted by the bias compensation voltage signal DVH so that the threshold voltage of the driving transistor M3 is adjusted before the light emitting element 40 is driven to emit light, improving the driving effect of the driving module 31.

In the display panel provided by the embodiment of the invention, in the data writing stage a, the data line D writes the data voltage signal Vdata into the data signal end data, in the first biasing stage b, the data line D writes the bias compensation voltage signal DVH into the data signal end data, that is, in the first biasing stage b, the data line D can be multiplexed to write the bias compensation voltage signal DVH into the data signal end data in the pixel circuit 30 electrically connected with the data line D, so that the bias compensation voltage signal DVH is transmitted to the first end of the driving module 31, and the signal line is not required to be additionally arranged to be electrically connected with the pixel circuit 30 so as to realize the transmission of the bias compensation voltage signal DVH to the first end of the driving module 31, thereby improving the offset and hysteresis phenomena of the characteristics of the driving transistor after long-term operation.

It should be noted that, in fig. 1, the data signal terminals data of the sub-pixels 20 arranged along the second direction Y in the display panel are shown to be electrically connected to one data line D, and in other embodiments of the present invention, the data signal terminals data of the sub-pixels 20 arranged along the second direction Y may also be electrically connected to two or more data lines D, which are not described herein again.

With continued reference to fig. 1-3, in some alternative embodiments, the pixel circuit 30 further includes a threshold compensation module 33, a control terminal of the threshold compensation module 33 is connected to the second scanning signal terminal S2, a first terminal of the threshold compensation module 33 is electrically connected to the control terminal of the driving module 31, a second terminal of the threshold compensation module 33 is electrically connected to the second terminal of the driving module 31, and the threshold compensation module 33 is configured to compensate for a threshold voltage of the driving module 31. Specifically, in the data writing stage a, the first scan signal terminal S1 is connected to the enable signal, the data writing module 32 is turned on, and the data voltage signal Vdata can be transmitted to the first terminal of the driving module 31. Meanwhile, the second scan signal terminal S2 is connected to the enable signal, and can compensate the threshold voltage of the driving module 31 to the control terminal of the driving module 31.

In the first bias stage b, the first scan signal terminal S1 is connected to an enable signal, and the second scan signal terminal S2 is connected to a disable signal.

Specifically, in the first bias phase b, the first scan signal terminal S1 is connected to the enable signal, the data writing module 32 is turned on, and the bias compensation voltage signal DVH may be transmitted to the first terminal of the driving module 31, so as to stabilize the electrical performance of the driving module 31. And the second scan signal terminal S2 is connected to the disable signal, the threshold compensation module 33 is turned off, so as to avoid the bias compensation voltage signal DVH from affecting the signal of the control terminal of the driving module 31.

With continued reference to fig. 2, in some alternative embodiments, the pixel circuit 30 further includes a first reset module 34, a first light emission control module 35, a second light emission control module 36, a threshold compensation module 33, and a second reset module 37.

The control end of the driving module 31 is electrically connected to the first node N1, the first end of the driving module 31 is electrically connected to the second node N2, and the second end of the driving module 31 is electrically connected to the third node N3.

The control end of the first light emitting control module 35 is electrically connected to the light emitting control signal end Emit, the first end of the first light emitting control module 35 is electrically connected to the first power signal end PVDD, the second end of the first light emitting control module 35 is electrically connected to the first node N1, and the first light emitting control module 35 is configured to provide the first end of the driving module 31 with the first power signal transmitted to the first power signal end PVDD.

The control end of the second light-emitting control module 36 is electrically connected to the light-emitting control signal end Emit, the first end of the second light-emitting control module 36 is electrically connected to the third node N3, the second end of the second light-emitting control module 36 is electrically connected to the anode of the light-emitting element 40, and the second light-emitting control module 36 is configured to control the driving current generated by the driving module 31 to be transmitted to the light-emitting element 40.

The control end of the threshold compensation module 33 is connected to the second scan signal end S2, the first end of the threshold compensation module 33 is electrically connected to the first node N1, the second end of the threshold compensation module 33 is electrically connected to the third node N3, and the threshold compensation module 33 is configured to compensate the threshold voltage of the driving module 31.

The control end of the first reset module 34 is electrically connected to the third scan signal end S3, the first end of the first reset module 34 is electrically connected to the reset signal end Vref1, the second end of the first reset module 34 is electrically connected to the first node N1, and the first reset module 34 is configured to provide a reset signal to the control end of the driving module 31.

The control end of the second reset module 37 is electrically connected to the first scan signal end S1, the first end of the second reset module 37 is electrically connected to the reset signal end Vref2, the second end of the second reset module 37 is electrically connected to the anode of the light emitting element 40, and the second reset module 37 is configured to provide a reset signal to the anode of the light emitting element 40.

It should be noted that, in the embodiment of the present invention, specific structures of the switch module, the driving module, the reset module, the data writing module, the threshold compensation module and the light emitting control module are not limited in particular, and each module of the pixel driving circuit may be designed according to actual needs on the premise that the bias compensation function of the threshold voltage of the driving transistor can be implemented. For convenience of understanding, the following embodiments of the present invention exemplify specific structures of a switching module, a driving module, a reset module, a data writing module, a threshold compensation module, and a light emission control module, where each module may optionally include a thin film transistor. With continued reference to fig. 2, a circuit configuration of 7T1C for the pixel circuit 30 in the sub-pixel 20 in the display panel is exemplarily shown in fig. 2. The first reset module 34 may include a fourth transistor M4, where a gate of the fourth transistor M4 is electrically connected to the third scan signal terminal S3. In the reset period, the third scan signal terminal S3 controls the fourth transistor M4 to be turned on, and at this time, the reset signal terminal Vref resets the first node N1 through the fourth transistor M4, and in the non-reset period, the third scan signal terminal S3 controls the fourth transistor M4 to be turned off. The data writing module 32 may include a fifth transistor M5 having a gate electrically connected to the first scan signal terminal S1, one terminal electrically connected to the data signal terminal data, and the other terminal electrically connected to one terminal of the driving module 31. The threshold compensation module 33 includes a sixth transistor M6, wherein a gate of the sixth transistor M6 is electrically connected to the second scan signal terminal S2, one end of the sixth transistor M6 is electrically connected to the first node N1, and the other end is electrically connected to the third node N3. In the data writing stage a, the first scan signal terminal S1 is connected to an enable signal, the fifth transistor M5 is turned on, the second scan signal terminal S2 is connected to an enable signal, the sixth transistor M6 is turned on, and at this time, the data voltage signal Vdata is written into the first node N1 through the fifth transistor M5, the driving transistor M3 and the sixth transistor M6 by the threshold compensated data voltage signal, and in the non-data writing stage a, the second scan signal terminal S2 controls the sixth transistor M6 to be turned off. In the first bias phase b, the first scan signal terminal S1 is connected to the enable signal, the fifth transistor M5 is turned on, and the bias compensation voltage signal DVH can be transmitted to the second node N2. The second reset module 37 may be provided to include a seventh transistor M7. The first light emitting control module 35 may be configured to include an eighth transistor M8, and the second light emitting control module 36 may be configured to include a ninth transistor M9, and gates of the eighth transistor M8 and the ninth transistor M9 are electrically connected to the light emitting control signal terminal Emit. In the light emitting period, the light emission control signal terminal Emit controls the eighth transistor M8 and the ninth transistor M9 to be turned on, and at this time, the first power signal terminal PVDD, the eighth transistor M8, the driving transistor M3, the ninth transistor M9 and the light emitting element 40 form a conductive channel, the driving transistor M3 generates a driving current to drive the light emitting element 40 to Emit light, and in the non-light emitting period, the light emission control signal terminal Emit controls the eighth transistor M8 and the ninth transistor M9 to be turned off.

It should be noted that the transistors and the driving transistors of the above modules may be N-type transistors or P-type transistors, and further, silicon-based transistors, such as a-Si transistors, P-Si transistors, LTPS transistors, or oxide transistors, such as indium gallium zinc oxide IGZO transistors, may be used, which is not limited by the embodiment of the present invention. In this embodiment, the transistors M3-M9 are P-type transistors, and in other embodiments of the present invention, the transistors M3-M9 may be configured according to actual requirements. Accordingly, the driving timing sequence of the pixel circuit in the sub-pixel is correspondingly changed, and the invention is not described herein.

Fig. 4 is a schematic plan view of another display panel according to the present invention, and referring to fig. 2-4, in some alternative embodiments, the display panel further includes a driving chip 50, the driving chip 50 includes a plurality of pads 51, different data lines D are electrically connected to the different pads 51, and signals are provided to the data lines D electrically connected thereto through the pads 51.

In the data writing stage a, the first scanning signal terminal S1 is connected to an enable signal, the second scanning signal terminal S2 is connected to an enable signal, and the driving chip 50 writes the data voltage signal Vdata to the data line D;

In the first bias phase b, the driving chip 50 writes the bias compensation voltage signal DVH to the data line D.

Specifically, in the data writing stage a, the pad 51 in the driving chip 50 transmits the data voltage signal Vdata to the data line D electrically connected thereto, thereby implementing writing of the data voltage signal Vdata to the data signal terminal data by the corresponding data line D. In the first bias phase b, the pad 51 in the driving chip 50 transmits the bias compensation voltage signal DVH to the data line D electrically connected thereto, thereby implementing writing of the bias compensation voltage signal DVH to the data signal terminal data by the corresponding data line D. The data voltage signals Vdata and the bias compensation voltage signals DVH can be directly transmitted to each data line D through the driving chip 50, so that the bias compensation voltage signals DVH can be written into the data signal ends data of the pixel circuits 30 electrically connected with the data lines D through the multiplexing data lines D, the bias compensation voltage signals DVH can be transmitted to the first ends of the driving modules 31, the signal lines do not need to be additionally arranged to be electrically connected with the pixel circuits 30, the bias compensation voltage signals DVH can be transmitted to the first ends of the driving modules 31, the offset and hysteresis phenomena of the driving transistors after long-term working can be improved, meanwhile, the number of the signal lines in the display panel can be effectively reduced, the wiring difficulty can be effectively reduced, and the situation that the design difficulty of the pixel circuits 30 is increased due to the fact that the signal lines are increased can be avoided.

Fig. 5 is a schematic plan view of a display panel according to another embodiment of the present invention, and fig. 6 is another driving timing diagram of a pixel circuit according to another embodiment of the present invention, referring to fig. 2, 5 and 6, in some alternative embodiments, the display panel further includes a plurality of first gate units 60 and N first control signal lines 71, the first gate units 60 include N first gate modules 61, where N is equal to or greater than 2, and N is a positive integer;

in the same first gating unit 60, the control ends of the N first gating modules 61 are respectively and electrically connected with the N first control signal lines 71 in a one-to-one correspondence manner, the first ends of the first gating modules 61 are electrically connected with the same first signal line 81, and the second ends of the N first gating modules 61 are respectively and electrically connected with the N data lines D in a one-to-one correspondence manner;

the data writing stage a includes N sub-stages a1, and in each sub-stage a1, each first control signal line 71 is sequentially connected to an enable signal.

Specifically, the display panel further includes first gate units 60, the number of the first gate modules 61 in the first gate units 60 is the same as the number of the first control signal lines 71, the first gate modules 61 in the first gate units 60 are in one-to-one correspondence with the first control signal lines 71, the first control signal lines 71 are electrically connected with the control ends of the corresponding first gate modules 61, the first ends of the first gate modules 61 in the first gate units 60 are electrically connected with the same first signal line 81, and the second ends of the first gate modules 61 in the first gate units 60 are respectively in one-to-one correspondence with different data lines D. The data writing stage a includes N sub-stages a1, and in each sub-stage a1, each first control signal line 71 is sequentially connected to an enable signal, so that in each sub-stage a1, each first gate module 61 in the first gate unit 60 is sequentially turned on, and in each sub-stage a1, a corresponding data voltage signal Vdata can be sequentially supplied to each data line D through the first signal line 81. The signal can be transmitted to at least two data lines D through one first signal line 81, and the first signal line 81 is electrically connected to the pads 51 in the driving chip 50, so that the number of the pads 51 in the driving chip 50 is reduced, and the production cost is reduced.

As an example, with continued reference to fig. 2, 5 and 6, the first gating unit 60 includes a first gating module 61a, 61b, the control terminal of the first gating module 61a is electrically connected to a first control signal line 711, the control terminal of the first gating module 61b is electrically connected to a first control signal line 712, the data voltage signal Vdata1 is transmitted on the first signal line 81 in the sub-stage a11, the first control signal line 711 is connected to an enable signal so that the first gating module 61a is turned on, the data voltage signal Vdata1 transmitted on the first signal line 81 is transmitted on a data line D electrically connected to the second terminal of the first gating module 61a, the data voltage signal Vdata2 is transmitted on the first signal line 81 in the sub-stage a12, the first control signal line 712 is connected to an enable signal so that the first gating module 61b is turned on, and the data voltage signal Vdata2 transmitted on the first signal line 81 is transmitted on a data line D electrically connected to the second terminal of the first gating module 61 b.

It should be noted that, in fig. 5, n=2 is exemplarily shown, that is, the first gating unit 60 includes 2 first gating modules 61, correspondingly, in fig. 6, a timing chart is exemplarily shown when the first gating unit 60 includes 2 first gating modules 61, in other embodiments of the present invention, N may also be other values, and the corresponding timing chart may be set with reference to fig. 6, which is not described herein.

With continued reference to fig. 2, 5 and 6, in some alternative embodiments, in the last sub-stage a11, the first scan signal terminal S1 is connected to the enable signal and the second scan signal terminal S2 is connected to the enable signal.

Specifically, the data writing stage a includes N sub-stages a1, and in each sub-stage a1, each first control signal line 71 is sequentially connected to an enable signal, so that in each sub-stage a1, each first gate module 61 in the first gate unit 60 is sequentially turned on, and in each sub-stage a1, a corresponding data voltage signal Vdata can be sequentially provided to each data line D through the first signal line 81. Meanwhile, in the last sub-stage a11, the first scan signal terminal S1 is connected to an enable signal, the second scan signal terminal S2 is connected to an enable signal, the data writing module 32 in each pixel circuit 30 is turned on, the corresponding data voltage signal Vdata on each data line D is respectively transmitted to the first terminal of the driving module 31 in the pixel circuit 30 electrically connected thereto, and the driving module 31 in the pixel circuit 30 can drive the light emitting element 40 to emit light according to the driving current generated based on the corresponding data voltage signal Vdata.

With continued reference to fig. 2, 5 and 6, in some alternative embodiments, the display panel further includes a driving chip 50, the driving chip 50 including a plurality of pads 51, the different first signal lines 81 being electrically connected to the different pads 51;

In the data writing stage a, the driving chip 50 writes the data voltage signal Vdata to the first signal line 81;

in the first bias stage b, the driving chip 50 writes the bias compensation voltage signal DVH to the first signal lines 81, and the respective first control signal lines S1 are simultaneously connected with the enable signal.

Specifically, in the data writing stage a, the driving chip 50 writes the data voltage signal Vdata to the first signal line 81 electrically connected thereto through the pad 51. The data writing stage a includes N sub-stages a1, in each of the sub-stages a1, the driving chip 50 transmits the data voltage signal Vdata corresponding to each data line D to the first signal line 81 electrically connected thereto through the pad 51, and in each of the sub-stages a1, each of the first control signal lines 71 is sequentially connected to an enable signal, so that in each of the sub-stages a1, each of the first gate modules 61 in the first gate unit 60 is sequentially turned on, and thus in each of the sub-stages a1, the corresponding data voltage signal Vdata can be sequentially supplied to each of the data lines D through the first signal line 81.

In the first bias stage b, the driving chip 50 writes the bias compensation voltage signal DVH to the first signal line 81, and each of the first control signal lines S1 is simultaneously connected with the enable signal, so that the bias compensation voltage signal DVH can be supplied to each of the data lines D electrically connected thereto through the first signal line 81. Therefore, the multiplexing data line D can write the offset compensation voltage signal DVH into the data signal terminal data of the pixel circuit 30 electrically connected with the multiplexing data line D, so that the offset compensation voltage signal DVH is transmitted to the first terminal of the driving module 31, the signal line is not required to be additionally arranged to be electrically connected with the pixel circuit 30 so as to transmit the offset compensation voltage signal DVH to the first terminal of the driving module 31, thereby improving the offset and hysteresis of the characteristics of the driving transistor after long-term operation, effectively reducing the number of signal lines in the display panel, effectively reducing the wiring difficulty, and avoiding the situation that the design difficulty of the pixel circuit 30 is increased due to the increase of the signal lines. Furthermore, the pixel circuits 30 in each row of the sub-pixels 20 are provided with the data voltage signal Vdata and the jump of the bias compensation voltage signal DVH, so that the bias compensation voltage signal DVH can be transmitted to the first end of the driving module 31 at high frequency, thereby stabilizing the electrical performance of the driving module 31.

With continued reference to fig. 2, 5, and 6, in some alternative embodiments, the first gating module 61 includes a first transistor M1;

in the same first gating unit 60, the gates of the N first transistors M1 are respectively and electrically connected to the N first control signal lines in a one-to-one correspondence, the first poles of the first transistors are electrically connected to the same first signal line 71, and the second poles of the N first transistors M1 are respectively and electrically connected to the N data lines D in a one-to-one correspondence.

Specifically, the display panel further includes a first gate unit 60, the number of the first gate modules 61 in the first gate unit 60 is the same as the number of the first control signal lines 71, the first gate modules 61 include first transistors M1, that is, the number of the first transistors M1 in the first gate unit 60 is the same as the number of the first control signal lines 71, the first transistors M1 in the first gate unit 60 are in one-to-one correspondence with the first control signal lines 71, the first control signal lines 71 are electrically connected with gates of the corresponding first transistors M1, first poles of the first transistors M1 in the first gate unit 60 are electrically connected with the same first signal lines 81, and second poles of the first transistors M1 in the first gate unit 60 are respectively in one-to-one correspondence with different data lines D. The data writing stage a includes N sub-stages a1, and in each sub-stage a1, each first control signal line 71 is sequentially connected to an enable signal, so that in each sub-stage a1, each first transistor M1 in the first gating unit 60 is sequentially turned on, and in each sub-stage a1, a corresponding data voltage signal Vdata can be sequentially supplied to each data line D through the first signal line 81.

It should be noted that, the first transistor M1 in the first gating module 61 may be an N-type transistor, a P-type transistor, a silicon-based transistor, such as an a-Si transistor, a P-Si transistor, an LTPS transistor, or an oxide transistor, such as an indium gallium zinc oxide IGZO transistor, which is not limited in the embodiments of the present invention. In this embodiment, the first transistor M1 is an N-type transistor, and in other embodiments of the present invention, the first transistor M1 may be set according to actual requirements. Accordingly, the driving timing sequence of the pixel circuit in the sub-pixel is correspondingly changed, and the invention is not described herein.

Fig. 7 is a schematic plan view of a further display panel according to the present invention, and fig. 8 is a further driving timing diagram of a pixel circuit according to the present invention, and referring to fig. 2, 7 and 8, in some alternative embodiments, the display panel further includes a second control signal line 72, and a plurality of second gate units 90 corresponding to the first gate units 60, the second gate units 90 including N second gate modules 91;

in the same second gating unit 90, the control end of the second gating module 91 is electrically connected with the same second control signal line 72, the first end of the second gating module 91 is electrically connected with the same second signal line 82, and the second ends of the N second gating modules 91 are respectively and correspondingly electrically connected with N data lines D one by one;

The display panel further includes a driving chip 50, the driving chip 50 including a plurality of pads 51, the first signal lines 81, the second signal lines 82 being electrically connected to different pads 51;

in the data writing stage a, the second control signal line 72 is connected to the disable signal, and the driving chip 50 writes the data voltage signal Vdata to the first signal line 81;

in the first bias stage b, the first control signal lines 71 are simultaneously connected to the disable signal, the second control signal lines 72 are connected to the enable signal, and the driver chip 50 writes the bias compensation voltage signal DVH to the second signal lines 82.

Specifically, the display panel further includes a plurality of second gate units 90 corresponding to the first gate units 60, and the second gate units 90 include N second gate modules 91, respectively. In the same second gating unit 90, the control end of the second gating module 91 is electrically connected to the same second control signal line 72, the first end of the second gating module 91 is electrically connected to the same second signal line 82, the second ends of the N second gating modules 91 are respectively electrically connected to the N data lines D in a one-to-one correspondence, and the second signal line 82 is electrically connected to one pad 51 in the driving chip 50, so that the driving chip 50 can transmit the bias compensation voltage signal DVH to the second signal line 82 electrically connected thereto through the pad 51.

In the data writing stage a, the second control signal lines 72 are connected to the disable signal, i.e., each of the second gate units 90 is turned off, and the driving chip 50 writes the data voltage signal Vdata to the first signal line 81 electrically connected thereto through the pad 51. And the data writing stage a includes N sub-stages a1, in each of the sub-stages a1, the driving chip 50 transmits the data voltage signal Vdata corresponding to each data line D to the first signal line 81 electrically connected thereto through the pad 51, and in each of the sub-stages a1, each of the first control signal lines 71 is sequentially connected to an enable signal, so that in each of the sub-stages a1, each of the first gate modules 61 in the first gate unit 60 is sequentially turned on, and thus in each of the sub-stages a1, the corresponding data voltage signal Vdata can be sequentially supplied to each of the data lines D through the first signal line 81.

In the first bias phase b, each first control signal line 71 is simultaneously connected with a disable signal, the first gating module 61 is turned off, the second control signal line 72 is connected with an enable signal, each second gating module 91 is turned on, the driving chip 50 writes the bias compensation voltage signal DVH to the second signal line 82 electrically connected with the driving chip via the bonding pad 51, thereby realizing transmission of the bias compensation voltage signal DVH to the data line D electrically connected with the driving chip, and realizing writing of the bias compensation voltage signal DVH to the data signal terminal data by the corresponding data line D.

The first signal line 81 and the second signal line 82 are electrically connected with different pads 51, that is, only the data voltage signal Vdata needs to be transmitted by the pad 51 electrically connected with the first signal line 81 in the driving chip 50, only the bias compensation voltage signal DVH needs to be transmitted by the pad 51 electrically connected with the second signal line 82 in the driving chip 50, and each pad 51 in the driving chip 50 does not need to jump the data voltage signal Vdata and the bias compensation voltage signal DVH, so that the requirement on the output capability of the IC is effectively reduced, and the power consumption is effectively reduced.

With continued reference to fig. 2, 7, and 8, in some alternative embodiments, the second gating module 91 includes N second transistors M2;

in the same second gating unit 90, the gates of the N second transistors M2 are electrically connected to the same second control signal line 72, the first poles of the N second transistors M2 are electrically connected to the same second signal line 82, and the second poles of the N second transistors M2 are respectively electrically connected to the N data lines D in a one-to-one correspondence.

In the first bias stage b, the second control signal line 72 is connected to an enable signal, the gate of the second transistor M2 is electrically connected to the same second control signal line 72, so that each second transistor M2 is turned on, the first pole of the second transistor M2 is electrically connected to the same second signal line 82, the second poles of different second transistors M2 are respectively and correspondingly electrically connected to different data lines D, and the driving chip 50 writes the bias compensation voltage signal DVH to the second signal line 82 electrically connected thereto through the bonding pad 51, thereby realizing transmission of the bias compensation voltage signal DVH to the data line D electrically connected thereto, and realizing writing of the bias compensation voltage signal DVH to the data signal terminal data by the corresponding data line D.

It should be noted that the second transistor M2 in the second gating module 91 may be an N-type transistor, a P-type transistor, a silicon-based transistor, such as an a-Si transistor, a P-Si transistor, an LTPS transistor, or an oxide transistor, such as an IGZO transistor, which is not limited in the embodiment of the present invention. In this embodiment, the second transistor M2 is an N-type transistor, and in other embodiments of the present invention, the second transistor M2 may be configured according to actual requirements. Accordingly, the driving timing sequence of the pixel circuit in the sub-pixel is correspondingly changed, and the invention is not described herein.

With continued reference to fig. 2, 7, and 8, in some alternative embodiments, the transmission of the bias compensation voltage signal DVH to the first end of the drive module 31 during the first bias phase b stabilizes the electrical performance of the drive module 31. The first bias phase b is arranged after the data writing phase a, namely, the first bias phase b is arranged between the data writing phase a and the light-emitting phase, so that the display effect of the light-emitting phase is improved.

Fig. 9 is a further driving timing diagram of the pixel circuit provided by the present invention, and referring to fig. 2, 7 and 9, the first bias stage b may be set before the data writing stage a, so that the effect of the display image of the previous frame on the display image of the next frame can be effectively alleviated, the smear phenomenon can be effectively alleviated, and the display effect can be improved.

Fig. 10 is a further driving timing diagram of the pixel circuit according to the present invention, referring to fig. 2, 7 and 10, in some alternative embodiments, the operation of the pixel circuit 30 further includes a hold phase c, where the second scan signal terminal S2 is connected to the disable signal;

the hold phase c includes at least one second bias phase B in which each of the first control signal lines 71 is simultaneously connected to a disable signal, the second control signal line 72 is connected to an enable signal, and the driver chip 50 writes the bias compensation voltage signal DVH to the second signal line 82.

Specifically, the working process of the pixel circuit 30 further includes a holding stage c, in which the second scan signal terminal S2 is connected to the disable signal, and the data voltage signal Vdata is not written into the data signal terminal data of the pixel circuit 30, so that the driving transistor M3 continuously drifts to cause brightness variation, and the display effect is affected. At least one second bias stage B is set in the holding stage c, in the second bias stage B, each first control signal line 71 is simultaneously connected to a disable signal, the second control signal line 72 is connected to an enable signal, the driving chip 50 writes the bias compensation voltage signal DVH to the second signal line 82, at this time, the data writing module 32 is turned on, and the bias compensation voltage signal DVH can be transmitted to the first end of the driving module 31, thereby stabilizing the electrical performance of the driving transistor M3 and improving the display effect.

In some alternative embodiments, please refer to fig. 11, fig. 11 is a schematic plan view of a display device provided by the present invention, and a display device 1000 provided by the present embodiment includes a display panel 100 provided by the above-mentioned embodiments of the present invention. The embodiment of fig. 11 is only an example of a mobile phone, and the display device 1000 is described, and it is to be understood that the display device 1000 provided in the embodiment of the present invention may be any other display device 1000 having a display function, such as a computer, a television, a vehicle-mounted display device, etc., which is not particularly limited in this respect. The display device 1000 provided in the embodiment of the present invention has the beneficial effects of the display panel 100 provided in the embodiment of the present invention, and the specific description of the display panel 100 in the above embodiments may be referred to in the embodiments, and the description of the embodiment is omitted herein.

As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, comprising:

a substrate base;

the plurality of sub-pixels are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect;

the sub-pixel includes a pixel circuit and a light emitting element;

the pixel circuit comprises a driving module and a data writing module, wherein the control end of the data writing module is connected with a first scanning signal end, the first end of the data writing module is electrically connected with the first end of the driving module, and the second end of the data writing module is connected with a data signal end;

a plurality of data lines extending in the second direction, the data signal terminals of the sub-pixels arranged in the second direction being electrically connected to at least one of the data lines;

The working process of the pixel circuit comprises a data writing stage and a first bias stage;

in the data writing stage, writing a data voltage signal to the data signal end by the data wire;

in the first bias stage, the data line writes a bias compensation voltage signal to the data signal terminal.

2. The display panel of claim 1, wherein the display panel comprises,

the pixel circuit further comprises a threshold compensation module, wherein the control end of the threshold compensation module is connected with the second scanning signal end, the first end of the threshold compensation module is electrically connected with the control end of the driving module, and the second end of the threshold compensation module is electrically connected with the second end of the driving module;

in the first bias stage, the first scanning signal end is connected with an enabling signal, and the second scanning signal end is connected with a non-enabling signal.

3. The display panel of claim 2, wherein the display panel comprises,

the display panel further comprises a driving chip, wherein the driving chip comprises a plurality of bonding pads, and different data lines are electrically connected with different bonding pads;

in the data writing stage, the first scanning signal end is connected with an enabling signal, the second scanning signal end is connected with an enabling signal, and the driving chip writes the data voltage signal into the data line;

In the first bias stage, the driving chip writes the bias compensation voltage signal to the data line.

4. The display panel of claim 2, wherein the display panel comprises,

the display panel further comprises a plurality of first gating units and N first control signal lines, wherein the first gating units comprise N first gating modules, N is more than or equal to 2, and N is a positive integer;

in the same first gating unit, the control ends of N first gating modules are respectively and electrically connected with N first control signal lines in a one-to-one correspondence manner, the first ends of the first gating modules are electrically connected with the same first signal line, and the second ends of N first gating modules are respectively and electrically connected with N data lines in a one-to-one correspondence manner;

the data writing stage comprises N sub-stages, and in each sub-stage, each first control signal line is sequentially connected with an enabling signal.

5. The display panel of claim 4, wherein the display panel comprises,

in the last sub-stage, the first scanning signal end is connected with an enabling signal, and the second scanning signal end is connected with an enabling signal.

6. The display panel of claim 4, wherein the display panel comprises,

The display panel further comprises a driving chip, wherein the driving chip comprises a plurality of bonding pads, and different first signal lines are electrically connected with different bonding pads;

in the data writing stage, the driving chip writes the data voltage signal to the first signal line;

in the first bias stage, the driving chip writes the bias compensation voltage signals into the first signal lines, and each first control signal line is simultaneously connected with an enabling signal.

7. The display panel of claim 4, wherein the display panel comprises,

the display panel further comprises a second control signal line and a plurality of second gating units corresponding to the first gating units, and the second gating units comprise N second gating modules;

in the same second gating unit, the control end of the second gating module is electrically connected with the same second control signal line, the first end of the second gating module is electrically connected with the same second signal line, and the second ends of the N second gating modules are respectively and correspondingly electrically connected with the N data lines one by one;

the display panel further comprises a driving chip, wherein the driving chip comprises a plurality of bonding pads, and the first signal lines and the second signal lines are electrically connected with different bonding pads;

In the data writing stage, the second control signal line is connected with a non-enabling signal, and the driving chip writes the data voltage signal into the first signal line;

in the first bias stage, each first control signal line is simultaneously connected with a non-enable signal, the second control signal line is connected with an enable signal, and the driving chip writes the bias compensation voltage signal into the second signal line.

8. The display panel of claim 4, wherein the display panel comprises,

the first gating module includes a first transistor;

in the same first gating unit, the gates of the N first transistors are respectively and electrically connected with the N first control signal lines in a one-to-one correspondence manner, the first poles of the first transistors are electrically connected with the same first signal line, and the second poles of the N first transistors are respectively and electrically connected with the N data lines in a one-to-one correspondence manner.

9. The display panel of claim 7, wherein the display panel comprises,

the second gating module comprises N second transistors;

in the same second gating unit, the gates of the N second transistors are electrically connected with the same second control signal line, the first poles of the N second transistors are electrically connected with the same second signal line, and the second poles of the N second transistors are respectively and correspondingly electrically connected with the N data lines one by one.

10. The display panel of claim 1, wherein the display panel comprises,

the data writing phase is preceded and/or followed by the first biasing phase.

11. The display panel of claim 7, wherein the display panel comprises,

the working process of the pixel circuit further comprises a holding stage, and in the holding stage, the second scanning signal end is connected with a non-enabling signal;

the hold stage includes at least one second bias stage in which each of the first control signal lines is simultaneously connected to a disable signal, the second control signal line is connected to an enable signal, and the driving chip writes the bias compensation voltage signal to the second signal line.

12. The display panel of claim 1, wherein the display panel comprises,

the pixel circuit further comprises a first reset module, a first light-emitting control module, a second light-emitting control module, a threshold compensation module and a second reset module;

the control end of the driving module is electrically connected with the first node, the first end of the driving module is electrically connected with the second node, and the second end of the driving module is electrically connected with the third node;

the control end of the first light-emitting control module is electrically connected with the light-emitting control signal end, the first end of the first light-emitting control module is electrically connected with the first power signal end, and the second end of the first light-emitting control module is electrically connected with the first node;

The control end of the second light-emitting control module is electrically connected with the light-emitting control signal end, the first end of the second light-emitting control module is electrically connected with the third node, and the second end of the second light-emitting control module is electrically connected with the anode of the light-emitting element;

the control end of the threshold compensation module is connected with a second scanning signal end, the first end of the threshold compensation module is electrically connected with the first node, and the second end of the threshold compensation module is electrically connected with the third node;

the control end of the first reset module is electrically connected with a third scanning signal end, the first end of the first reset module is electrically connected with a reset signal end, and the second end of the first reset module is electrically connected with the first node;

the control end of the second reset module is electrically connected with the first scanning signal end, the first end of the second reset module is electrically connected with the reset signal end, and the second end of the second reset module is electrically connected with the anode of the light-emitting element.

13. A display device, characterized in that the display device comprises a display panel according to any one of claims 1-12.