CN116708235A - CAN bus node rack automatic test system and method - Google Patents

CAN bus node rack automatic test system and method Download PDF

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Publication number
CN116708235A
CN116708235A CN202310781812.3A CN202310781812A CN116708235A CN 116708235 A CN116708235 A CN 116708235A CN 202310781812 A CN202310781812 A CN 202310781812A CN 116708235 A CN116708235 A CN 116708235A
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CN
China
Prior art keywords
test
node
bus
control unit
software control
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Pending
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CN202310781812.3A
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Chinese (zh)
Inventor
黄鹤
肖云博
郭至尊
秦强
王修通
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xuzhou XCMG Excavator Machinery Co Ltd
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Xuzhou XCMG Excavator Machinery Co Ltd
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Application filed by Xuzhou XCMG Excavator Machinery Co Ltd filed Critical Xuzhou XCMG Excavator Machinery Co Ltd
Priority to CN202310781812.3A priority Critical patent/CN116708235A/en
Publication of CN116708235A publication Critical patent/CN116708235A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
    • H04L43/0817—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Environmental & Geological Engineering (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)

Abstract

The application relates to the technical field of engineering machinery, and discloses an automatic test system and method for a CAN bus node rack, wherein the automatic test system comprises a plurality of test nodes, a circuit switching unit, a bus test unit, a processor MCU and a software control unit; the circuit switching unit comprises a plurality of relays, and CANH and CANL of each test node are respectively connected with one end of the corresponding relay; CANH and CANL of the bus test unit are respectively connected with the other ends of the relays; the relay corresponding to the test node at the starting end is connected with the normally-closed contact, and the other relays are connected with the normally-open contact; the bus test unit is in communication connection with the processor MCU, and the processor MCU is in communication connection with the software control unit; the output end of the software control unit is connected with the signal control end of the relay. The beneficial effects of the application are as follows: repeated disassembly and assembly power-on and power-off tests are not needed by a tester in the test process, so that time and labor are saved, and man-machine fatigue is reduced.

Description

CAN bus node rack automatic test system and method
Technical Field
The application relates to the technical field of engineering machinery, in particular to an automatic test system and method for a CAN bus node rack.
Background
Along with the development of engineering machinery intellectualization and electric control, more CAN bus nodes on engineering machinery are increased, and problems are difficult to analyze thoroughly during bus test of the whole vehicle, so that test analysis on a single node, such as an excavator, is required. However, because the engineering machinery has a huge structure, the wiring is inserted into the structural member, and the test points are very troublesome to disassemble and build. It is therefore necessary to take out the nodes to be tested separately from the wiring test.
In the prior art, a test bench is built, and a certain node to be tested is electrified for testing. After the test is finished, if the test of another node is required, the last test is required to be manually closed, then the circuit is removed, the circuit is connected to the next test node to be tested, and finally the power-on test is performed. If all the nodes are tested separately, repeated disassembly, wire replacement and power on-off operation are time-consuming and labor-consuming, and man-machine fatigue is caused.
Disclosure of Invention
Aiming at the defects of the prior art, the application provides an automatic test system and method for a CAN bus node rack, and the test system is used for reducing time and labor and man-machine fatigue without repeated power-on and power-off test of disassembly and assembly by a tester in the test process.
In order to achieve the above purpose, the present application provides the following technical solutions:
in a first aspect, the present application provides an automated test system for a CAN bus node rack, including a plurality of test nodes, a circuit switching unit, a bus test unit, a processor MCU, and a software control unit; the circuit switching unit comprises a plurality of relays, each relay is arranged in one-to-one correspondence with each test node, and CANH and CANL of each test node are respectively connected with one end of the corresponding relay; the CANH and the CANL of the bus test unit are respectively connected with the other ends of the relays; the plurality of test nodes are arranged in sequence, the relay corresponding to the test node at the starting end is connected with the normally-closed contact, and the other relays are connected with the normally-open contact; the bus test unit is in communication connection with the processor MCU, and the processor MCU is in communication connection with the software control unit; the processor MCU is used for receiving the test data of the bus test unit, carrying out data processing analysis, judging whether the test data are normal or not, and sending a judging result signal to the software control unit; if the data of the test node is normal, the processor MCU outputs a PASS signal to the software control unit, and if the data of the test node is abnormal, the processor MCU outputs a FAIL signal to the software control unit; the software control unit receives a result signal sent by the processor MCU, and sends an action instruction to a relay corresponding to a current test node or sends an action instruction to the relay corresponding to the current test node and a relay corresponding to a next test node together according to the result signal, and the output end of the software control unit is connected with the signal control end of the relay; if the software control unit receives the PASS signal, a trigger signal is output to control the relay contact of the current test node to be opened, the contact of the relay connected in series with the next test node is closed, and the bus test unit automatically starts the test of the next test node until an abnormality is encountered or the final test is completely passed; if the software control unit receives the FAIL signal, another trigger signal for only switching off the contacts of the relays connected in series of the current test node is output, and the test is automatically interrupted.
With reference to the first aspect, further, the processor MCU receives test data of the bus test unit through RXD and TXD data lines and performs processing analysis.
With reference to the first aspect, further, the automatic test system is suitable for the automatic test of the CAN bus node rack for the engineering machinery, and is particularly suitable for the automatic test of the CAN bus node rack for the excavator.
With reference to the first aspect, further, the number of the test nodes is N, and the N test nodes are built together on a node test bench. Each component test node of the bench comprises all bus nodes used on engineering machinery, and the test nodes comprise a radio, an instrument, an air conditioner, a controller and the like.
In combination with the first aspect, further, the test nodes on the rack are sequentially arranged according to the load sizes of the test nodes, and the test can be performed according to the load size sequence during the test, or according to the specific analysis of the specific problem, the related test nodes can be further performed.
In combination with the first aspect, further, a termination resistor R is connected in parallel between the respective CAN lines of the test nodes, and the termination resistor R is configured to stabilize communication.
With reference to the first aspect, further, the termination resistor R is a 120Ω resistor.
With reference to the first aspect, further, the bus test unit is internally provided with a resistor R capable of being activated or not 0 For testing of matching test nodes.
With reference to the first aspect, further, the resistor R 0 Is 120 omega resistance.
With reference to the first aspect, a diode D is further connected in series between the software control unit and each relay, for preventing reverse voltage caused by test outage and other anomalies from striking the software control unit.
With reference to the first aspect, further, the software control unit has a memory function, and can hold the signal received before. When the test is interrupted due to the abnormal test of a certain node, if the reason is analyzed, the relay can be controlled, and the test node is connected to continue the test.
In combination with the first aspect, the test system of the application further comprises an indicator light, wherein the output end of the processor MCU is also connected with the indicator light, and the indicator light receives the test result judged by the processor MCU and expresses the test result through the color of the indicator light. If the judging result of the processor MCU is a PASS signal, a green light is lighted on a screen externally connected with the processor MCU to indicate that the test is passed; if the judging result of the processor MCU is the FAIL signal, a red light is lighted on a screen externally connected with the processor MCU, and the test is not passed. Of course, the indicator light may also express the test result by other indication modes such as lighting or non-lighting and flashing.
In combination with the first aspect, further, as the relay is not necessarily the same as the voltage used by the test system, the relay is externally connected with a power supply, and the arrangement of the externally connected power supply is convenient for replacement, maintenance and management, and meanwhile, the influence of a system circuit or a certain path of power supply fault on other switching units is prevented.
In a second aspect, the application provides an automated testing method for a CAN bus node rack, comprising the following steps:
step S1: turning on a bench power supply, turning on each test node switch, and electrifying to normally work;
step S2: turning on the power supply of the bus test unit, and switching on the first test node (such as a radio) to the bus test unit; selecting whether to select the internal resistor R of the bus test unit according to the resistance value of the terminal resistor R connected with the first test node in parallel 0 The method comprises the steps of carrying out a first treatment on the surface of the Setting the test duration on the bus test unit to be 300s, and observing the test result in the test duration;
step S3: if the test result is normal, the green light on the external screen of the processor MCU is turned on, and a PASS signal (the PASS signal is set to be high level 1) is output to the software control unit;
step S4: when the software control unit obtains a PASS signal, outputting a trigger signal to open a normally-closed contact of the relay connected in series with the first test node and close a normally-open contact of the relay connected in series with the second test node;
step S5: the second test node (such as an instrument) is communicated with the bus test unit, and the steps S2-S4 are repeated for testing;
step S6: if the test result is abnormal, the red light on the external screen of the processor MCU is lightened, and a FAIL signal (the FAIL signal is set to be 0 with low level) is output to the software control unit;
step S7: when the software control unit obtains the FAIL signal, outputting another trigger signal to disconnect the normally-closed contact of the relay connected in series with the current test node;
step S8: interrupting the test and analyzing the cause of the abnormality;
step S9: finding out an abnormal reason, controlling the relay corresponding to the current node to be conducted, and restarting the test of the current node;
step S10: if no abnormal reason is found, exiting the software control unit, storing the test state of each node to a background processing program XML file, loading the XML file after the software control unit is retested and opened next time, importing the test state of each node, and directly starting the test from the node after the last closing;
step S11: and after the test is finished, closing the switch of each test node, closing the power supply of the bench, and analyzing the test result.
Compared with the prior art, the application provides an automatic test system and method for a CAN bus node rack, which have the following beneficial effects:
(1) By using the test system provided by the application, repeated disassembly, assembly, power-on and power-off tests are not required by a tester in the test process, the test can be automated, the time and the labor are saved, and the fatigue of a human machine is reduced.
(2) The test system provided by the application has the function of testing abnormal memory, and can directly continue testing from the fault node.
(3) The test system can cover all the test nodes for the engineering machinery, and has strong test universality.
(4) The test system has the advantages of simple principle, easy realization and lower construction and maintenance cost.
(5) The test system adopts automatic test, avoids errors caused by manual operation, and has more objective and reliable test results.
Drawings
FIG. 1 is a schematic diagram of an automated test system according to the present application;
FIG. 2 is a flow chart of an automated test method of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present application unless it is specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may also include different values. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
In the description of the present application, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the protection of the present application.
As shown in fig. 1, the test system provided by the application comprises a plurality of test nodes, a circuit switching unit, a bus test unit, a processor MCU and a software control unit; the circuit switching unit comprises a plurality of relays, each relay is arranged in one-to-one correspondence with each test node, and CANH and CANL of each test node are respectively connected with one end of the corresponding relay; CANH and CANL of the bus test unit are respectively connected with the other ends of the relays; the plurality of test nodes are arranged in sequence, the relay corresponding to the test node at the starting end is connected with the normally-closed contact, and the other relays are connected with the normally-open contact; the bus test unit is in communication connection with the processor MCU, and the processor MCU is in communication connection with the software control unit; the processor MCU is used for receiving the test data of the bus test unit, performing data processing analysis, judging whether the test data are normal or not, and sending a judging result signal to the software control unit; if the data of the test node is normal, the processor MCU outputs a PASS signal to the software control unit, and if the data of the test node is abnormal, the processor MCU outputs a FAIL signal to the software control unit; the software control unit receives a result signal sent by the processor MCU, and sends an action command to the relay corresponding to the current test node or sends an action command to the relay corresponding to the current test node and the relay corresponding to the next test node together according to the result signal, and the output end of the software control unit is connected with the signal control end of the relay; if the software control unit receives the PASS signal, a trigger signal is output to control the relay contact of the current test node to be opened, the contact of the relay connected in series with the next test node is closed, and the bus test unit automatically starts the test of the next test node until an abnormality is encountered or the final test is completely passed; if the software control unit receives the FAIL signal, another trigger signal for only switching off the contacts of the relays connected in series of the current test node is output, and the test is automatically interrupted.
In a specific implementation of this embodiment, the processor MCU receives test data of the bus test unit through RXD and TXD data lines and performs processing analysis.
In a specific implementation manner of this embodiment, the automatic test system is suitable for the automatic test of the CAN bus node rack for the engineering machinery, and is particularly suitable for the automatic test of the CAN bus node rack for the excavator.
In a specific implementation manner of this embodiment, there are N test nodes, where the N test nodes are built together on one node test bench. Each component test node of the bench comprises all bus nodes used on engineering machinery, and the test nodes comprise a radio, an instrument, an air conditioner, a controller and the like.
In a specific implementation manner of this embodiment, the test nodes on the bench are sequentially arranged according to the load sizes of the test nodes, and the test can be performed according to the load size sequence during the test, or the test of the related test nodes can be performed according to specific analysis of specific problems.
In a specific implementation manner of this embodiment, a termination resistor R is connected in parallel between the respective CAN lines of the test nodes, and the termination resistor R is configured to stabilize communications.
In a specific implementation of this embodiment, the termination resistor R is a 120Ω resistor.
In a specific implementation manner of this embodiment, the Relay1 is connected to the normally-closed contact, so that the bus test unit is opened to directly perform measurement. The other relays are connected to the normally open contact, and the contact is closed by means of a trigger signal and then is in communication test with the bus test unit, so that the bus test unit is internally provided with a resistor R capable of being activated or not 0 For testing of matching test nodes.
In one embodiment of the present embodiment, the resistor R 0 A resistance of 120 Ω, in particular because: because the CAN bus test standard needs to be externally connected with a 60 omega resistor test environment so as to lead the test result to be more stable and accurate, but only the CANH and CANL of the test node are short-circuited with a 120 omega resistor, the condition needs to be externally connected with a 120 omega resistor (such as the terminal resistor R of the application), and the resistor R of the application does not need to be arranged 0 A 60 omega test environment can be formed. However, since the CAN channels of all the test nodes cannot be eliminated from shorting a 120Ω resistor, the application provides a 120Ω resistor R inside the bus test unit 0 Thus, when needed, the switch between the CANH and CANL bundles on the bus test unit (switch see left side of the bus test unit in fig. 1) is toggled to activate resistor R 0 So that it is connected in parallel with the termination resistor R into a 60 omega test environment.
In a specific implementation manner of this embodiment, a diode D is connected in series between the software control unit and each relay, so as to prevent reverse voltage caused by test outage and other anomalies from striking the software control unit.
In a specific implementation of this embodiment, the software control unit has a memory function, capable of holding the previously received signal. When the test is interrupted due to the abnormal test of a certain node, if the reason is analyzed, the relay can be controlled, and the test node is connected to continue the test.
In a specific implementation manner of this embodiment, the test system of the present application further includes an indicator light, and the output end of the processor MCU is further connected to the indicator light, where the indicator light receives the test result determined by the processor MCU, and expresses the test result by using the color of the indicator light. If the judging result of the processor MCU is a PASS signal, a green light is lighted on a screen externally connected with the processor MCU to indicate that the test is passed; if the judging result of the processor MCU is the FAIL signal, a red light is lighted on a screen externally connected with the processor MCU, and the test is not passed. Of course, the indicator light may also express the test result by other indication modes such as lighting or non-lighting and flashing.
In a specific implementation of this embodiment, the relays are all externally connected to a power supply.
As shown in FIG. 1, when the bus test of the first test node is performed, the whole rack is electrified, at this time, all the test nodes can work normally, and after the bus test unit is opened, the relay connected in series with the first test node is connected with a normally closed contact, so that the bus test unit directly tests the first test node, and the measured bus data is imported into the processor MCU for data analysis. And after the test is finished, if the test result is normal, the processor MCU outputs a PASS signal to the software control unit, and the software control unit generates a trigger signal to control the Relay1 to be switched off and the Relay2 to be switched on, so that the test of the second test node is started. Similarly, the Relay2 is controlled to be disconnected and the Relay3 is controlled to be connected by performing a third test node test; if the test result is abnormal, the processor MCU outputs a FAIL signal to the software control unit, and the software control unit generates a trigger signal to directly disconnect the relay connected with the current test node, so that the test is interrupted.
As shown in fig. 2, the testing method provided by the application comprises the following steps:
step S1: turning on a bench power supply, turning on each test node switch, and electrifying to normally work;
step S2: turning on the power supply of the bus test unit, and switching on the first test node (such as a radio) to the bus test unit; selecting whether to select the internal resistor R of the bus test unit according to the resistance value of the terminal resistor R connected with the first test node in parallel 0 The method comprises the steps of carrying out a first treatment on the surface of the Setting the test duration on the bus test unit to be 300s, and observing the test result in the test duration;
step S3: if the test result is normal, the green light on the external screen of the processor MCU is turned on, and a PASS signal (the PASS signal is set to be high level 1) is output to the software control unit;
step S4: when the software control unit obtains a PASS signal, outputting a trigger signal to open a normally-closed contact of a Relay1 connected in series with a first test node, and closing a normally-open contact of a Relay2 connected in series with a second test node;
step S5: the second test node (such as an instrument) is communicated with the bus test unit, and the steps S2-S4 are repeated for testing;
step S6: if the test result is abnormal, the red light on the external screen of the processor MCU is lightened, and a FAIL signal (the FAIL signal is set to be 0 with low level) is output to the software control unit;
step S7: when the software control unit obtains the FAIL signal, outputting another trigger signal to disconnect the normally-closed contact of the relay connected in series with the current test node;
step S8: interrupting the test and analyzing the cause of the abnormality;
step S9: finding out an abnormal reason, controlling the relay corresponding to the current node to be conducted, and restarting the test of the current node;
step S10: if no abnormal reason is found, exiting the software control unit, storing the test state of each node to a background processing program XML file, loading the XML file after the software control unit is retested and opened next time, importing the test state of each node, and directly starting the test from the node after the last closing;
step S11: and after the test is finished, closing the switch of each test node, closing the power supply of the bench, and analyzing the test result.
It is noted that in the present application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Although embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the application, the scope of which is defined in the appended claims and their equivalents.

Claims (10)

1. The CAN bus node rack automatic test system is characterized in that: the device comprises a plurality of test nodes, a circuit switching unit, a bus test unit, a processor MCU and a software control unit; the circuit switching unit comprises a plurality of relays, each relay is arranged in one-to-one correspondence with each test node, and CANH and CANL of each test node are respectively connected with one end of the corresponding relay; the CANH and the CANL of the bus test unit are respectively connected with the other ends of the relays; the plurality of test nodes are arranged in sequence, the relay corresponding to the test node at the starting end is connected with the normally-closed contact, and the other relays are connected with the normally-open contact; the bus test unit is in communication connection with the processor MCU, and the processor MCU is in communication connection with the software control unit; the processor MCU is used for receiving the test data of the bus test unit, carrying out data processing analysis, judging whether the test data are normal or not, and sending a judging result signal to the software control unit; the software control unit receives a result signal sent by the processor MCU, and sends an action command to the relay corresponding to the current test node or sends an action command to the relay corresponding to the current test node and the relay corresponding to the next test node together according to the result signal, and the output end of the software control unit is connected with the signal control end of the relay.
2. The CAN bus node stand automated test system of claim 1, wherein: the automatic test system is suitable for CAN bus node rack automatic test for engineering machinery.
3. The CAN bus node stand automated test system of claim 1, wherein: the number of the test nodes is N, and the N test nodes are built on a node test bench.
4. The CAN bus node stand automated test system of claim 1, wherein: the test nodes on the rack are sequentially arranged according to the load of each test node.
5. The CAN bus node stand automated test system of claim 1, wherein: and a terminal resistor R is connected in parallel between the CAN lines of the test nodes.
6. The CAN bus node stand automated test system of claim 1, wherein: and a diode is connected in series between the software control unit and each relay.
7. The CAN bus node stand automated test system of claim 1, wherein: the software control unit has a memory function and can hold signals received before.
8. The CAN bus node stand automated test system of claim 1, wherein: the display device further comprises an indicator lamp, wherein the output end of the processor MCU is further connected with the indicator lamp, and the indicator lamp receives a test result judged by the processor MCU and expresses the test result through the color of the indicator lamp.
9. The CAN bus node stand automated test system of claim 1, wherein: the relays are externally connected with a power supply.
10. The CAN bus node rack automatic test method is characterized by comprising the following steps of:
step S1: turning on a bench power supply, turning on each test node switch, and electrifying to normally work;
step S2: turning on a power supply of the bus test unit, and connecting the first test node to the bus test unit; selecting whether to select the internal resistor R of the bus test unit according to the resistance value of the terminal resistor R connected with the first test node in parallel 0 The method comprises the steps of carrying out a first treatment on the surface of the Setting the test time length on the bus test unit, and observing the test result;
step S3: if the test result is normal, the green light on the external screen of the processor MCU is turned on, and a PASS signal is output to the software control unit;
step S4: when the software control unit obtains a PASS signal, outputting a trigger signal to open a normally-closed contact of the relay connected in series with the first test node and close a normally-open contact of the relay connected in series with the second test node;
step S5: the second test node is communicated with the bus test unit, and the steps S2-S4 are repeated for testing;
step S6: if the test result is abnormal, the red light on the external screen of the processor MCU is lightened, and a FAIL signal is output to the software control unit;
step S7: when the software control unit obtains the FAIL signal, outputting another trigger signal to disconnect the normally-closed contact of the relay connected in series with the current test node;
step S8: interrupting the test and analyzing the cause of the abnormality;
step S9: finding out an abnormal reason, controlling the relay corresponding to the current node to be conducted, and restarting the test of the current node;
step S10: if no abnormal reason is found, exiting the software control unit, storing the testing state of each node, and directly starting testing from the node after the last closing when retesting is carried out next time;
step S11: and (5) ending the test.
CN202310781812.3A 2023-06-29 2023-06-29 CAN bus node rack automatic test system and method Pending CN116708235A (en)

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CN202310781812.3A CN116708235A (en) 2023-06-29 2023-06-29 CAN bus node rack automatic test system and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310781812.3A CN116708235A (en) 2023-06-29 2023-06-29 CAN bus node rack automatic test system and method

Publications (1)

Publication Number Publication Date
CN116708235A true CN116708235A (en) 2023-09-05

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