CN116707524A - Phase-locked loop circuit applied to 16Gbps and above interface technology - Google Patents
Phase-locked loop circuit applied to 16Gbps and above interface technology Download PDFInfo
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Abstract
The embodiment of the application discloses a phase-locked loop circuit applied to a 16Gbps interface technology and above, wherein the input end of a first charge pump in the phase-locked loop circuit applied to the 16Gbps interface technology and above is connected with the signal output end of a frequency-phase discriminator, the output end of the first charge pump is respectively connected with the input end of a voltage-controlled oscillator and a first loop filter, the output end of the voltage-controlled oscillator is connected with the input end of a phase compensation fractional divider, the output end of the phase compensation fractional divider is connected with the feedback signal input end of the frequency-phase discriminator, and the phase compensation fractional divider is used for compensating phase errors generated in the process of dividing the output signal of the voltage-controlled oscillator. The technical scheme provided by the application can compensate when phase errors exist between the signal after frequency division of the voltage-controlled oscillator and the reference clock signal, so that the feedback signal obtained after compensation is consistent with the reference clock signal.
Description
Technical Field
The application relates to the technical field of communication, in particular to a phase-locked loop circuit applied to 16Gbps and above interface technology.
Background
In the field of high-speed interfaces, phase Lock Loop (PLL) is an important component in transceiver chips. The phase-locked loop can keep the frequency and phase of the controlled oscillator synchronous with the input reference clock signal, which is called phase locking, for short phase locking. The feedback control system takes phase error as a control object, compares the phase between a reference clock signal and an output signal of a controlled oscillator, and generates a phase error voltage to adjust the phase of the output signal of the controlled oscillator so as to enable the output frequency of the controlled oscillator to be consistent with the frequency of the reference clock signal. In the case where the two signals are identical in frequency and not identical in phase, the phase difference between the two signals can be stabilized within a small range. At present, the phase-locked loop has been widely used in many technical fields such as filtering, frequency synthesis, modulation and demodulation, signal detection, etc., and has become an indispensable basic component in analog and digital communication systems.
The traditional decimal phase-locked loop design based on the analog circuit has the advantages of higher and better noise performance, faster locking time and the like, and becomes the main stream of the analog phase-locked loop. However, conventional analog fractional phase locked loops use a fractional divider based on a delta-sigma modulator (delta-sigma modulator) that randomly changes the division ratio of a dual-mode divider to produce a fractional division, the output period of the divider still being an integer multiple of the period of the oscillator. Each phase discrimination period, a phase error is generated between the reference clock signal received by the phase-locked loop circuit and the feedback signal output by the frequency divider, and the phase error passes through the loop and generates jitter at the output end of the phase-locked loop circuit.
Disclosure of Invention
In order to solve the above technical problems, an embodiment of the present application provides a phase-locked loop circuit applied to an interface technology of 16Gbps and above, which aims to solve the technical problem that in the prior art, a phase error generated between a reference clock signal received by the phase-locked loop circuit and a feedback signal output by a frequency divider can generate jitter at an output end of the phase-locked loop circuit through a loop.
Other features and advantages of the application will be apparent from the following detailed description, or may be learned by the practice of the application.
According to an aspect of an embodiment of the present application, there is provided a phase-locked loop circuit applied to an interface technology of 16Gbps and above, including a phase frequency detector, a first charge pump, a voltage controlled oscillator, a first loop filter, and a phase compensation fractional divider:
the phase frequency detector is provided with a reference clock signal input end, a feedback signal input end and a signal output end, and is used for detecting and outputting phase difference signals of the reference clock signal and the feedback signal;
the input end of the first charge pump is connected with the signal output end of the phase frequency detector, the output end of the first charge pump is respectively connected with the input end of the voltage-controlled oscillator and the first loop filter, the first charge pump is used for converting a phase difference signal into a current signal, the first loop filter is used for converting the current signal into a voltage signal, and a loop formed by the phase frequency detector, the first charge pump, the voltage-controlled oscillator and the phase compensation fractional divider is filtered;
the output end of the voltage-controlled oscillator is connected with the input end of the phase compensation fractional frequency divider, the output end of the phase compensation fractional frequency divider is connected with the feedback signal input end of the frequency-discrimination phase detector, and the phase compensation fractional frequency divider is used for compensating phase errors generated in the process of dividing the output signal of the voltage-controlled oscillator.
In further embodiments, the phase compensated fractional divider includes a phase compensation module, a dual mode divider, a first flip-flop, and a digital accumulator:
the output end of the voltage controlled oscillator is respectively connected with the first end of the dual-mode frequency divider and the third end of the first trigger, the second end of the dual-mode frequency divider is connected with the first end of the digital accumulator, the third end of the dual-mode frequency divider is respectively connected with the first end of the first trigger and the first end of the phase compensation module, the second end of the digital accumulator is connected with the second end of the phase compensation module, the third end of the phase compensation module is connected with the second end of the first trigger, and the fourth end of the phase compensation module is connected with the feedback signal input end of the phase frequency detector.
In further embodiments, the phase compensation module comprises a delay locked loop circuit.
In a further embodiment, the delay locked loop circuit comprises a second charge pump, a phase detector, a second loop filter, and a voltage controlled delay unit:
the first end of the phase discriminator is connected with the second end of the first trigger, the second end of the phase discriminator is connected with the first end of the second charge pump, the second end of the second charge pump is connected with the first end of the voltage-controlled delay unit and the second loop filter respectively, the second end of the voltage-controlled delay unit is connected with the third end of the dual-mode frequency divider, the third end of the voltage-controlled delay unit is connected with the third end of the phase discriminator, the fourth end of the voltage-controlled delay unit is connected with the second end of the digital accumulator, and the fifth end of the voltage-controlled delay unit is connected with the feedback signal input end of the phase discriminator and the third end of the digital accumulator respectively.
In further embodiments, the second loop filter includes a first capacitor having a first end connected to the second end of the second charge pump and a second end grounded.
In a further embodiment, the voltage controlled delay unit comprises a plurality of delay modules in cascade.
In further embodiments, the phase compensation module includes a second flip-flop and a phase interpolator:
the second end of the first trigger is connected with the first end of the second trigger and the first end of the phase interpolator respectively, the second end of the second trigger is connected with the second end of the phase interpolator, the third end of the second trigger is connected with the output end of the voltage-controlled oscillator, the third end of the phase interpolator is connected with the feedback signal input end of the phase frequency detector, and the fourth end of the phase interpolator is connected with the second end of the digital accumulator.
In further embodiments, the first flip-flop and the second flip-flop each comprise a D-type flip-flop.
In a further embodiment, the first loop filter comprises a low pass filter.
In a further embodiment, the low pass filter comprises a second capacitance, a third capacitance and a resistance:
the output end of the first charge pump is respectively connected with the first end of the second capacitor and the first end of the resistor, the second end of the resistor is connected with the first end of the third capacitor, and the second end of the second capacitor and the second end of the third capacitor are grounded.
In the technical scheme provided by the embodiment of the application, the phase frequency detector is provided with two input ends, a reference clock signal and a feedback signal are respectively received, when the phase difference signals of the reference clock signal and the feedback signal are detected, the detected phase difference signals are output to the first charge pump, the first charge pump generates current signals according to the received phase difference signals, the generated current signals are transmitted to the first loop filter, the first loop filter filters the input current signals to enable the signals to be smooth, control voltage for the voltage-controlled oscillator is formed, the voltage-controlled oscillator generates output signals according to the control voltage, and the output signals are input to the phase compensation fractional divider for processing to form feedback signals to be input to the phase frequency detector. The phase frequency detector constantly modulates the output signal of the voltage controlled oscillator by the detected phase difference signal. The phase compensation fractional frequency divider can divide the output signal of the voltage-controlled oscillator, and compensates when phase errors exist between the divided signal and the reference clock signal, so that feedback signals obtained after compensation of the phase compensation fractional frequency divider are consistent with the reference clock signal, and spurious emissions are avoided when the phase-locked loop circuit is locked. The phase-locked loop circuit applied to the interface technology of 16Gbps and above provided by the application does not need to introduce extra hardware cost, and can use less circuits to meet the application requirement in an application scene with low output frequency resolution. The phase-locked loop circuit applied to the interface technology of 16Gbps and above can obtain higher resolution than an integer frequency divider, and compared with a delta-sigma fractional frequency divider, the phase-locked loop circuit has no interference of quantization noise and digital noise, and has stray performance superior to the delta-sigma fractional frequency divider.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. It is evident that the drawings in the following description are only some embodiments of the present application and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
Fig. 1 is a schematic diagram of a prior art phase locked loop circuit according to the present application.
Fig. 2 is a schematic diagram of a pll circuit for use with 16Gbps and beyond interface technology in accordance with the present application.
Fig. 3 is a schematic diagram of a pll circuit for use with 16Gbps and beyond interface technology in accordance with the present application.
Fig. 4 is a schematic diagram of a pll circuit for use with 16Gbps and beyond interface technology in accordance with the present application.
Fig. 5 is a schematic diagram of a pll circuit for use with 16Gbps and beyond interface technology in accordance with the present application.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
Also to be described is: in the present application, the term "plurality" means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., a and/or B may represent: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
Fig. 1 is a schematic diagram of a phase locked loop circuit of the prior art. As shown in fig. 1, the phase-locked loop circuit includes: a phase frequency detector (Phase Frequency Detector, PFD), a Charge Pump (CP), a voltage controlled oscillator, a loop filter and a Dual-Mode Divider (DMD), and a delta-sigma modulator;
the phase frequency detector is provided with a reference clock signal input end (Fref), a feedback signal input end (Fbk) and a signal output end, the input end of the charge pump is connected with the signal output end of the phase frequency detector, the output end of the charge pump is respectively connected with the input end of the voltage-controlled oscillator and the loop filter, the output end of the voltage-controlled oscillator is connected with the first input end of the dual-mode frequency divider, the output end of the dual-mode frequency divider is respectively connected with the feedback signal input end of the phase frequency detector and the input end of the delta-sigma modulator, and the output end of the delta-sigma modulator is connected with the second input end of the dual-mode frequency divider.
In the pll circuit shown in fig. 1, the phase frequency detector compares the frequency and the phase of the input reference clock signal with the feedback signal input to the phase frequency detector by the dual-mode frequency divider, and outputs a signal representing the difference between the two signals to the loop filter when the two signals are inconsistent. The loop filter filters out high frequency components in the input signal, and the direct current component is reserved and sent to the voltage-controlled oscillator. The feedback signal of the phase frequency detector is a signal obtained by dividing the output signal (Fvco) of the voltage-controlled oscillator by the dual-mode frequency divider, and in theory, the frequency and the phase of the feedback signal are consistent with each other, namely, the frequency of the reference clock signal input by the phase frequency detector is xHZ, and the frequency of the feedback signal fed back to the phase frequency detector after the output signal of the voltage-controlled oscillator is processed by the frequency divider is xHZ.
In the phase-locked loop circuit shown in fig. 1, the frequency divider adopts a dual-mode frequency divider. According to the difference of the 1/N value modes of the frequency divider, the phase-locked loop circuit can be divided into an integer frequency division phase-locked loop circuit and a fractional frequency division phase-locked loop circuit. When N is an integer, the phase-locked loop circuit is an integer frequency division; when N takes the decimal, the decimal frequency division phase-locked loop circuit is adopted.
In the phase-locked loop circuit shown in fig. 1, for an n-bit delta-sigma modulator, the input-output relationship of the phase-locked loop circuit is:
；
wherein in the above formulaFor the period of the input reference clock signal, +.>For the period of the output signal of the voltage-controlled oscillator, N is an integer frequency division, k is a decimal input, the minimum value is 0, and the maximum value is +.>，/>The total length is input for a fraction.
When the feedback dual-mode frequency divider is divided by N, the instantaneous time error is:
；
when the feedback dual-mode frequency divider is divided by n+1, the instantaneous time error is:
；
so for the frequency division ratio ofThe time error sequence of the loop is as follows:
；
the delta-sigma modulator randomly varies the division ratio of the dual-mode divider for each phase and frequency discrimination period, thereby producing fractional divisions. The output period of the dual-mode divider is still an integer multiple of the voltage-controlled oscillator period. Each phase detection period, a phase error is generated between the reference clock signal input by the phase frequency detector and the output of the dual-mode frequency divider, and the phase error passes through the loop and generates jitter at the output end of the phase-locked loop circuit. In the prior art, various schemes are adopted to solve the jitter problem, the first scheme is to use a high-order modulator to push the quantization error to a higher frequency, but the high-order modulator needs a high-order loop filter to filter the quantization noise, which increases the problem of circuit stability. The second approach is to input a dithering technique in the modulator, which, although it breaks up the periodicity, inevitably introduces additional input noise. The third scheme is based on maximizing the cycle length of the digital modulator, and adopts feedback and other technologies, but this increases the complexity of hardware design; the fourth solution is to use additional circuitry for compensation etc., but this would add additional circuitry costs.
To solve the above problems, an embodiment of the present application provides a pll circuit applied to 16Gbps and above interface technology as shown in fig. 2, and fig. 2 is a schematic diagram of a pll circuit applied to 16Gbps and above interface technology according to an exemplary embodiment. In an exemplary embodiment, the phase-locked loop circuit applied to the interface technology of 16Gbps and above comprises a phase frequency detector, a first charge pump (CP-1), a voltage controlled oscillator, a first loop filter and a phase compensation fractional divider (Phase Compensation Fractional Divider, PCFD):
the phase frequency detector is provided with a reference clock signal input end, a feedback signal input end and a signal output end, and is used for detecting and outputting phase difference signals of the reference clock signal and the feedback signal;
the input end of the first charge pump is connected with the signal output end of the phase frequency detector, the output end of the first charge pump is respectively connected with the input end of the voltage-controlled oscillator and the first loop filter, the first charge pump is used for converting a phase difference signal into a current signal, the first loop filter is used for converting the current signal into a voltage signal, and a loop formed by the phase frequency detector, the first charge pump, the voltage-controlled oscillator and the phase compensation fractional divider is filtered;
the output end of the voltage-controlled oscillator is connected with the input end of the phase compensation fractional frequency divider, the output end of the phase compensation fractional frequency divider is connected with the feedback signal input end of the frequency-discrimination phase detector, and the phase compensation fractional frequency divider is used for compensating phase errors generated in the process of dividing the output signal of the voltage-controlled oscillator.
In the embodiment of the application, the phase frequency detector is provided with a reference clock signal input end, a feedback signal input end and a signal output end, and is used for detecting the phase difference signals of the received reference clock signal and the feedback signal, outputting the detected phase difference signals to the first charge pump, generating current signals according to the received phase difference signals by the first charge pump, transmitting the generated current signals to the first loop filter, filtering high-frequency components in the input current signals by the first loop filter, retaining a direct current part, generating control voltage for the voltage-controlled oscillator, and transmitting the control voltage to the voltage-controlled oscillator, and continuously modulating the voltage output by the voltage-controlled oscillator through the phase difference signals by the phase frequency detector, so that the voltage-controlled oscillator generates a periodic output signal and outputs the periodic output signal.
As described above, each phase-detecting period of the phase-locked loop circuit in the prior art, a phase error is generated between the reference clock signal input to the phase-frequency detector and the output of the dual-mode frequency divider. The phase compensation fractional frequency divider provided by the embodiment of the application realizes frequency division of the output signal of the voltage-controlled oscillator, and meanwhile, the feedback signal is formed after compensating the phase error generated in the frequency division process and is input into the phase frequency detector, so that the formed feedback signal is consistent with the phase of the reference clock signal received by the phase frequency detector, and the jitter generated at the output end of the phase-locked loop circuit is avoided. The periodic output signal of the voltage controlled oscillator can be used to generate a clock signal in an electronic system.
In the embodiment of the application, the phase frequency detector is provided with two input ends, respectively receives a reference clock signal and a feedback signal, and when detecting the phase difference signals of the reference clock signal and the feedback signal, outputs the detected phase difference signals to the first charge pump, the first charge pump generates current signals according to the received phase difference signals, then transmits the generated current signals to the first loop filter, the first loop filter filters the input current signals to smooth the signals, so that control voltage of the voltage-controlled oscillator is formed, the voltage-controlled oscillator generates output signals according to the control voltage, and the output signals are input to the phase compensation fractional divider for processing to form feedback signals to be input to the phase frequency detector. The phase frequency detector constantly modulates the output signal of the voltage controlled oscillator by the detected phase difference signal. The phase compensation fractional frequency divider can divide the output signal of the voltage-controlled oscillator, and compensates when phase errors exist between the divided signal and the reference clock signal, so that feedback signals obtained after compensation of the phase compensation fractional frequency divider are consistent with the reference clock signal, and spurious emissions are avoided when the phase-locked loop circuit is locked. The phase-locked loop circuit provided by the application is applied to the interface technology of 16Gbps and above, does not need to introduce extra hardware cost, and can use less circuits to meet the application requirement in the application scene with low output frequency resolution. The phase-locked loop circuit applied to the interface technology of 16Gbps and above can obtain higher resolution than an integer frequency divider, and compared with a delta-sigma fractional frequency divider, the phase-locked loop circuit has no interference of quantization noise and digital noise, and has stray performance superior to the delta-sigma fractional frequency divider.
In an exemplary embodiment of the present application, referring to fig. 3, the phase compensation fractional divider includes a phase compensation module, a dual mode divider, a first flip-flop (DFF-1) and a digital ACCUMULATOR (ACCUMULATOR):
the output end of the voltage controlled oscillator is respectively connected with the first end of the dual-mode frequency divider and the third end of the first trigger, the second end of the dual-mode frequency divider is connected with the first end of the digital accumulator, the third end of the dual-mode frequency divider is respectively connected with the first end of the first trigger and the first end of the phase compensation module, the second end of the digital accumulator is connected with the second end of the phase compensation module, the third end of the phase compensation module is connected with the second end of the first trigger, and the fourth end of the phase compensation module is connected with the feedback signal input end of the phase frequency detector.
In the embodiment of the application, the output signal of the voltage-controlled oscillator is input into the dual-mode frequency divider as the input signal of the dual-mode frequency divider, the dual-mode frequency divider is used for dividing the input signal, the divided signal is transmitted to the first trigger and the phase compensation module, the first trigger is triggered and then is input into the phase compensation module, at the moment, a phase error is formed between the output signal of the phase compensation module and the reference clock signal, the phase corresponding to the phase error is selected and output through the digital accumulator and is inserted into the output signal of the phase compensation module to form a feedback signal, and the compensation of the phase error can be realized. The feedback signal formed after compensation is consistent with the reference clock signal, and the phase frequency detector continuously modulates the output signal of the voltage-controlled oscillator according to the feedback signal, so that when the output signal of the voltage-controlled oscillator is processed by the phase compensation fractional frequency divider and then fed back to the phase frequency detector, the same stable frequency and phase as the reference clock signal are maintained.
In the embodiment of the application, the trigger is an edge-sensitive storage unit, and the action of data storage is triggered by the rising edge or the falling edge of the clock. The output signal of the flip-flop remains unchanged when the clock is low or high. The output of the flip-flop is sensitive, i.e. it changes only on the rising or falling edge of the enable signal (clock signal). After the rising or falling edge of the clock signal, the contents of the flip-flop remain unchanged even if the input changes.
In an exemplary embodiment of the application, the phase compensation module includes a Delay-locked Loop (DLL) circuit.
In the embodiment of the application, the output signal of the first trigger is used as the input signal of the delay phase-locked loop circuit, namely the output signal can be used as the delay reference clock signal of the delay phase-locked loop circuit, the delay phase-locked loop circuit inserts delay between the delay reference clock signal corresponding to the delay phase-locked loop circuit and the corresponding delay feedback signal based on a digital sampling mode, so that the rising edges of the corresponding delay reference clock signal and the delay feedback signal are consistent, and the delay phase-locked loop circuit is locked.
In an exemplary embodiment of the present application, referring to fig. 4, the delay locked loop circuit includes a second charge pump (CP-2), a Phase Detector (PD), a second loop filter, and a voltage controlled delay unit (Voltage Controlled Delay Line, VCDL):
the first end of the phase discriminator is connected with the second end of the first trigger, the second end of the phase discriminator is connected with the first end of the second charge pump, the second end of the second charge pump is connected with the first end of the voltage-controlled delay unit and the second loop filter respectively, the second end of the voltage-controlled delay unit is connected with the third end of the dual-mode frequency divider, the third end of the voltage-controlled delay unit is connected with the third end of the phase discriminator, the fourth end of the voltage-controlled delay unit is connected with the second end of the digital accumulator, and the fifth end of the voltage-controlled delay unit is connected with the feedback signal input end of the phase discriminator and the third end of the digital accumulator respectively.
In the embodiment of the present application, as described above, the output signal of the first flip-flop is used as the input signal of the delay locked loop circuit, that is, the output signal of the first flip-flop is used as the delay reference clock signal of the delay locked loop circuit to be input to the first end of the phase discriminator, and the phase difference between the delay reference clock signal and the output signal of the dual-mode frequency divider. The signal output by the third end of the voltage-controlled delay unit is used as a delay feedback signal of the delay phase-locked loop circuit to be input to the third end of the phase detector, the phase detector detects a delay phase difference signal of a received delay reference clock signal and the delay feedback signal and outputs the detected delay phase difference signal to the second charge pump, the second charge pump generates a current signal according to the received delay phase difference signal and then transmits the generated current signal to the second loop filter, the second loop filter filters high-frequency components in the input current signal, retains a direct current part, generates a control voltage for the voltage-controlled delay unit and transmits the control voltage to the voltage-controlled delay unit, and the voltage-controlled delay unit continuously modulates the signal output by the voltage-controlled delay unit through the phase detector so that the voltage-controlled delay unit generates a delay periodic outputAnd outputting the signals.
When the delay phase-locked loop circuit is locked, the input phase of the phase detector is aligned, so that the input phase of the voltage-controlled delay unit is different from the output phase of the voltage-controlled delay unit. The digital accumulator outputs and selects the phase corresponding to the phase error to be interpolated in the output signal of the voltage-controlled delay unit to form a feedback signal, and the feedback signal is input to the feedback signal input end of the phase frequency detector through the fifth end of the voltage-controlled delay unit to realize the compensation of the phase error.
In an embodiment, an output frequency of an output signal of a voltage-controlled oscillator in a phase-locked loop circuit applied to an interface technology of 16Gbps and above is 3GHz, a frequency offset requirement is 0.5% (15 MHz), a frequency of a reference clock signal input to a phase frequency discriminator is 100MHz, a 5bit digital accumulator is selected, a fractional input k=4 of a dual-mode frequency divider is selected, a frequency offset value is 100×4/32=12.5 MHz (0.42%), each feedback clock rising edge, and an output phase of the delay-locked loop circuit is sequentially changed to:
；
selecting a decimal input k=5 of the dual-mode frequency divider, wherein the frequency offset value is 100×5/32=15.625 MHz (0.52%), and the output phase of the delay phase-locked loop circuit is sequentially changed to be:
。
in an exemplary embodiment of the application, the second loop filter comprises a first capacitor, a first end of the first capacitor being connected to a second end of the second charge pump, the second end of the first capacitor being grounded.
In the embodiment of the application, the second loop filter is composed of the first capacitor and is used for filtering out high-frequency components in the current signal output by the second charge pump, reserving the direct current part, generating control voltage for the voltage-controlled delay unit and sending the control voltage to the voltage-controlled delay unit.
In an exemplary embodiment of the application, the voltage controlled delay unit comprises a cascade of a plurality of delay modules.
In the embodiment of the application, n identical delay modules are selected to form a voltage-controlled delay unit, and the phase difference of each delay module isThe phase corresponding to the phase error is selected and interpolated in the input of the phase frequency detector through the output of the digital accumulator, and then the compensation of the phase error can be realized.
In an exemplary embodiment of the present application, referring to fig. 5, the phase compensation module includes a second flip-flop (DFF-2) and a phase interpolator (Phase Interpolator, PI):
the second end of the first trigger is connected with the first end of the second trigger and the first end of the phase interpolator respectively, the second end of the second trigger is connected with the second end of the phase interpolator, the third end of the second trigger is connected with the output end of the voltage-controlled oscillator, the third end of the phase interpolator is connected with the feedback signal input end of the phase frequency detector, and the fourth end of the phase interpolator is connected with the second end of the digital accumulator.
In the embodiment of the application, the phase interpolator is a device capable of proportionally mixing two periodic input clock signals with the same frequency and different phases to generate an output clock signal with the same frequency and the phase between the two clock signals. The phase corresponding to the phase error is selected from the phase interpolators by the digital accumulator and interpolated in the input of the phase frequency detector, so that the compensation of the phase error can be realized. The embodiment of the application realizes phase compensation through the phase interpolator, the frequency interval which can be realized is smaller, the frequency resolution which can be realized is higher, and for the phase-locked loop circuit with higher output frequency, a phase compensation module which is composed of the phase interpolator can be used for forming the phase-locked loop circuit which is applied to the interface technology of 16Gbps and above.
In an exemplary embodiment of the application, the first flip-flop and the second flip-flop each comprise a D-type flip-flop.
In the embodiment of the application, the first Flip-Flop and the second Flip-Flop each include a D-type Flip-Flop (DFF), where the D-type Flip-Flop is an information storage device having a memory function and having two stable states of 0 and 1, and the interface of the D-type Flip-Flop may be a standard interface, that is, the interface of the D-type Flip-Flop has a data terminal D terminal, a clock terminal CLK terminal, a positive phase data output terminal Q terminal, and a negative phase data output terminal Q terminal. When the D-type flip-flop is used as a frequency divider 2, the data terminal D terminal is used for receiving and storing feedback data, and the clock input terminal CLK terminal is used for receiving a clock signal. In the time sequence circuit, clock terminals of the D-type flip-flops are electrically connected with each other and connected to a clock terminal of a system, when a clock pulse arrives, the state of the circuit is changed synchronously until the next clock pulse arrives, and the state of the circuit is changed again.
In another embodiment, the D-type flip-flop may be a dynamic D-type flip-flop based on a true single-phase clock (1 Single Phase Clock, TSPC), where the true single-phase clock is a dynamic logic circuit, and has the advantages of low power consumption and no static loss.
In an exemplary embodiment of the application, the first loop filter comprises a low pass filter.
In the embodiment of the application, the first loop Filter is formed by a Low Pass Filter (LPF), which can allow signals below the cut-off frequency to Pass, i.e. allow Low frequency signals to Pass, but not allow signals above the cut-off frequency to Pass.
In an exemplary embodiment of the application, the low pass filter comprises a second capacitance, a third capacitance and a resistance:
the output end of the first charge pump is respectively connected with the first end of the second capacitor and the first end of the resistor, the second end of the resistor is connected with the first end of the third capacitor, and the second end of the second capacitor and the second end of the third capacitor are grounded.
In the embodiment of the application, the low-pass filter is formed by the second capacitor, the third capacitor and the resistor, so that the low-frequency signal can pass through, and the high-frequency signal can be weakened (or reduced). The degree of attenuation of the signal at each frequency is different for different filters.
In the description of the present specification, reference to the terms "some embodiments," "exemplary," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present application have been shown and described, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made in the above embodiments by those skilled in the art within the scope of the application, which is therefore intended to be covered by the appended claims and their equivalents.
Claims (10)
1. A phase-locked loop circuit applied to 16Gbps and above interface technology, comprising a phase frequency detector, a first charge pump, a voltage controlled oscillator, a first loop filter and a phase compensation fractional divider:
the phase frequency detector is provided with a reference clock signal input end, a feedback signal input end and a signal output end, and is used for detecting and outputting phase difference signals of the reference clock signal and the feedback signal;
the input end of the first charge pump is connected with the signal output end of the phase frequency detector, the output end of the first charge pump is respectively connected with the input end of the voltage-controlled oscillator and the first loop filter, the first charge pump is used for converting the phase difference signal into a current signal, the first loop filter is used for converting the current signal into a voltage signal, and a loop formed by the phase frequency detector, the first charge pump, the voltage-controlled oscillator and the phase compensation fractional divider is filtered;
the output end of the voltage-controlled oscillator is connected with the input end of the phase compensation fractional frequency divider, the output end of the phase compensation fractional frequency divider is connected with the feedback signal input end of the phase frequency detector, and the phase compensation fractional frequency divider is used for compensating phase errors generated in the process of dividing the output signal of the voltage-controlled oscillator.
2. The phase-locked loop circuit of claim 1 applied to 16Gbps and above interface technologies, wherein the phase-compensated fractional divider comprises a phase compensation module, a dual-mode divider, a first flip-flop, and a digital accumulator:
the output end of the voltage-controlled oscillator is respectively connected with the first end of the dual-mode frequency divider and the third end of the first trigger, the second end of the dual-mode frequency divider is connected with the first end of the digital accumulator, the third end of the dual-mode frequency divider is respectively connected with the first end of the first trigger and the first end of the phase compensation module, the second end of the digital accumulator is connected with the second end of the phase compensation module, the third end of the phase compensation module is connected with the second end of the first trigger, and the fourth end of the phase compensation module is connected with the feedback signal input end of the phase frequency detector.
3. The phase-locked loop circuit of claim 2 applied to interface technologies of 16Gbps and above, wherein the phase compensation module comprises a delay-locked loop circuit.
4. The phase-locked loop circuit of claim 3 applied to interface technologies of 16Gbps and above, wherein the delay-locked loop circuit comprises a second charge pump, a phase detector, a second loop filter, and a voltage-controlled delay unit:
the first end of the phase discriminator is connected with the second end of the first trigger, the second end of the phase discriminator is connected with the first end of the second charge pump, the second end of the second charge pump is respectively connected with the first end of the voltage-controlled delay unit and the second loop filter, the second end of the voltage-controlled delay unit is connected with the third end of the dual-mode frequency divider, the third end of the voltage-controlled delay unit is connected with the third end of the phase discriminator, the fourth end of the voltage-controlled delay unit is connected with the second end of the digital accumulator, and the fifth end of the voltage-controlled delay unit is respectively connected with the feedback signal input end of the frequency-controlled phase discriminator and the third end of the digital accumulator.
5. The phase-locked loop circuit of claim 4 applied to interface technology of 16Gbps and above, wherein the second loop filter comprises a first capacitor, a first terminal of the first capacitor being coupled to a second terminal of the second charge pump, a second terminal of the first capacitor being coupled to ground.
6. The phase-locked loop circuit of claim 4 applied to interface technologies of 16Gbps and above, wherein the voltage controlled delay unit comprises a plurality of delay modules in cascade.
7. The phase-locked loop circuit of claim 2 applied to 16Gbps and above interface technologies, wherein the phase compensation module comprises a second flip-flop and a phase interpolator:
the second end of the first trigger is connected with the first end of the second trigger and the first end of the phase interpolator respectively, the second end of the second trigger is connected with the second end of the phase interpolator, the third end of the second trigger is connected with the output end of the voltage-controlled oscillator, the third end of the phase interpolator is connected with the feedback signal input end of the phase frequency detector, and the fourth end of the phase interpolator is connected with the second end of the digital accumulator.
8. The phase-locked loop circuit of claim 7 applied to interface technologies of 16Gbps and above, wherein the first flip-flop and the second flip-flop each comprise a D-type flip-flop.
9. A phase-locked loop circuit for use in interface technologies of 16Gbps and beyond as claimed in any of claims 1 to 8, wherein the first loop filter comprises a low pass filter.
10. The phase-locked loop circuit of claim 9 applied to 16Gbps and above interface technology, wherein the low-pass filter comprises a second capacitor, a third capacitor, and a resistor:
the output end of the first charge pump is respectively connected with the first end of the second capacitor and the first end of the resistor, the second end of the resistor is connected with the first end of the third capacitor, and the second end of the second capacitor and the second end of the third capacitor are grounded.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0986178A2 (en) * | 1998-07-17 | 2000-03-15 | Nortel Networks Corporation | Frequency synthesizer |
| US6236278B1 (en) * | 2000-02-16 | 2001-05-22 | National Semiconductor Corporation | Apparatus and method for a fast locking phase locked loop |
| CN110504962A (en) * | 2019-07-17 | 2019-11-26 | 晶晨半导体(上海)股份有限公司 | Digital compensation simulates fractional frequency-division phase-locked loop and control method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0986178A2 (en) * | 1998-07-17 | 2000-03-15 | Nortel Networks Corporation | Frequency synthesizer |
| US6236278B1 (en) * | 2000-02-16 | 2001-05-22 | National Semiconductor Corporation | Apparatus and method for a fast locking phase locked loop |
| CN110504962A (en) * | 2019-07-17 | 2019-11-26 | 晶晨半导体(上海)股份有限公司 | Digital compensation simulates fractional frequency-division phase-locked loop and control method |
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