CN116705947B - LED epitaxial wafer based on silicon substrate, preparation method of LED epitaxial wafer and LED - Google Patents

LED epitaxial wafer based on silicon substrate, preparation method of LED epitaxial wafer and LED Download PDF

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CN116705947B
CN116705947B CN202310927826.1A CN202310927826A CN116705947B CN 116705947 B CN116705947 B CN 116705947B CN 202310927826 A CN202310927826 A CN 202310927826A CN 116705947 B CN116705947 B CN 116705947B
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silicon substrate
epitaxial wafer
gan layer
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CN116705947A (en
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郑文杰
程龙
高虹
刘春杨
胡加辉
金从龙
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Jiangxi Zhao Chi Semiconductor Co Ltd
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Jiangxi Zhao Chi Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004—Devices characterised by their operation
    • H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses an LED epitaxial wafer based on a silicon substrate, a preparation method thereof and an LED, and relates to the field of semiconductor photoelectric devices. The LED epitaxial wafer based on the silicon substrate comprises the silicon substrate, and a buffer layer, a resistance layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer which are sequentially arranged on the silicon substrate; the resistor layer is of a periodic structure, the period number is more than or equal to 2, and the resistor layer of each period comprises a ternary co-doped GaN layer, a P-type InAlN layer and a C-doped AlN layer which are sequentially laminated; wherein the doping elements in the ternary co-doped GaN layer are Y, mg and C. By implementing the LED epitaxial wafer, the reliability and the luminous efficiency of the LED device based on the LED epitaxial wafer can be improved.

Description

LED epitaxial wafer based on silicon substrate, preparation method of LED epitaxial wafer and LED
Technical Field
The invention relates to the field of semiconductor photoelectric devices, in particular to an LED epitaxial wafer based on a silicon substrate, a preparation method of the LED epitaxial wafer and an LED.
Background
The GaN-based light emitting diode has been industrially produced and has been used in backlight, illumination, landscape lamp, and the like. The substrate materials commonly used for GaN-based light emitting diodes today are sapphire, silicon carbide and monocrystalline silicon. The monocrystalline silicon substrate has the advantages of low price, high quality, high heat conductivity, high electric conductivity and the like, and has great market application potential.
However, the silicon substrate has high conductivity and high electron mobility, and electrons are likely to migrate along the silicon substrate to the epitaxial wafer, thereby forming a leakage path. In addition, the silicon substrate has a small breakdown voltage and is easily broken down electrostatically.
Disclosure of Invention
The invention aims to solve the technical problem of providing an LED epitaxial wafer based on a silicon substrate and a preparation method thereof, which can improve the reliability of a light emitting diode.
The invention also solves the technical problem of providing an LED based on a silicon substrate.
In order to solve the problems, the invention discloses an LED epitaxial wafer based on a silicon substrate, which comprises the silicon substrate, and a buffer layer, a resistance layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer which are sequentially arranged on the silicon substrate; the resistor layer is of a periodic structure, the period number is more than or equal to 2, and the resistor layer of each period comprises a ternary co-doped GaN layer, a P-type InAlN layer and a C-doped AlN layer which are sequentially laminated; wherein, doping elements in the ternary co-doped GaN layer are Y, mg and C.
As an improvement of the technical scheme, the doping concentration of Y in the ternary co-doped GaN layer is 5 multiplied by 10 15 cm -3 ~5×10 18 cm -3 The doping concentration of C is 1×10 16 cm -3 ~5×10 18 cm -3 The doping concentration of Mg is 1×10 14 cm -3 ~5×10 16 cm -3 The thickness of the ternary co-doped GaN layer is 1 nm-5 nm.
As an improvement of the technical scheme, the P-type doping element in the P-type InAlN layer is Mg, and the doping concentration is 1 multiplied by 10 16 cm -3 ~2×10 17 cm -3 The In component accounts for 0.01-0.2, and the thickness of the P-type InAlN layer is 1-5 nm.
As an improvement of the technical scheme, the C doping concentration in the C-doped AlN layer is 1 multiplied by 10 17 cm -3 ~2×10 18 cm -3 The thickness of the C-doped AlN layer is 10 nm-15 nm.
As an improvement of the technical scheme, the doping concentration of Y in the ternary co-doped GaN layer is 1 multiplied by 10 18 cm -3 ~5×10 18 cm -3 And the In component In the InAlN layer is 0.05-0.1, so that the lattice constant of the ternary co-doped GaN layer is larger than that of the P-type InAlN layer, and the lattice constant of the P-type InAlN layer is larger than that of the C-doped AlN layer.
Correspondingly, the invention also discloses a preparation method of the LED epitaxial wafer based on the silicon substrate, which is used for preparing the LED epitaxial wafer based on the silicon substrate and comprises the following steps:
providing a silicon substrate, and sequentially growing a buffer layer, a resistor layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer on the silicon substrate; the resistor layer is of a periodic structure, the period number is more than or equal to 2, and the resistor layer of each period comprises a ternary co-doped GaN layer, a P-type InAlN layer and a C-doped AlN layer which are sequentially laminated; wherein the doping elements in the ternary co-doped GaN layer are Y, mg and C.
As an improvement of the technical scheme, the growth temperature of the ternary co-doped GaN layer is 800-850 ℃, and the growth pressure is 50-300 torr.
As an improvement of the technical scheme, the growth temperature of the P-type InAlN layer is 750-850 ℃, and the growth pressure is 50-300 torr.
As an improvement of the technical scheme, the growth temperature of the C-doped AlN layer is 700-800 ℃, and the growth pressure is 50-300 torr.
Correspondingly, the invention also discloses an LED based on the silicon substrate, which comprises the LED epitaxial wafer based on the silicon substrate.
The implementation of the invention has the following beneficial effects:
1. in the LED epitaxial wafer based on the silicon substrate, a resistance layer is arranged between a buffer layer and a non-doped GaN layer, the resistance layer is of a periodic structure, and each period comprises a ternary co-doped GaN layer, a P-type InAlN layer and a C-doped AlN layer which are sequentially laminated; wherein the doping elements in the ternary co-doped GaN layer are Y, mg and C. The ternary co-doped GaN layer has a large forbidden bandwidth, can limit electron movement, and simultaneously generates holes and consumes electrons, so that the number of electrons upwards migrating along a silicon substrate is greatly reduced, the generation of electric leakage is reduced, and the reliability and the luminous efficiency are improved. The P-type InAlN layer may also provide holes to further consume electrons. In addition, the P-type InAlN layer and the ternary co-doped GaN layer form a heterojunction material, so that the reverse voltage effect of the LED in high-voltage operation is eliminated, and the reliability of the LED device in long-time high-voltage operation is improved. The C-doped AlN layer can prevent the P-type doping element of the P-type InAlN layer from migrating upwards to cause non-radiative recombination.
2. According to the LED epitaxial wafer based on the silicon substrate, the doping concentration of Y in the GaN layer is controlled to be 1 multiplied by 10 18 cm -3 ~5×10 18 cm -3 The In component In the InAlN layer is 0.05-0.1, so that the lattice constant of the ternary co-doped GaN layer is larger than that of the P-type InAlN layer and larger than that of the C-doped AlN layer. The P-type InAlN layer provides compressive stress for the ternary co-doped GaN layer, the C-doped AlN layer provides compressive stress for the P-type InAlN layer, tensile stress between the silicon substrate and the epitaxial structure is effectively relieved, crystal quality of the epitaxial structure is improved, non-radiative composite centers are reduced, and luminous efficiency is improved.
Drawings
Fig. 1 is a schematic structural diagram of an LED epitaxial wafer based on a silicon substrate in an embodiment of the present invention;
FIG. 2 is a schematic diagram of a resistor layer according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for preparing an LED epitaxial wafer based on a silicon substrate according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail below in order to make the objects, technical solutions and advantages of the present invention more apparent.
Referring to fig. 1-2, the invention discloses an LED epitaxial wafer based on a silicon substrate, which comprises a silicon substrate 1, and a buffer layer 2, a resistive layer 3, an undoped GaN layer 4, an N-type GaN layer 5, a multiple quantum well layer 6, an electron blocking layer 7 and a P-type GaN layer 8 which are sequentially arranged on the silicon substrate 1. Wherein, the resistance layer 3 is of a periodic structure, and the period number is more than or equal to 2. The resistive layer 3 of each cycle includes a ternary co-doped GaN layer 31, a p-type InAlN layer 32, and a C-doped AlN layer 33, which are sequentially stacked. Preferably, the number of cycles of the resistive layer 3 is 3 to 10, more preferably 6 to 9.
Wherein, doping elements in the ternary co-doped GaN layer 31 are Y, mg and C. Mg dopingHoles can be generated by impurities, electrons generated by the bottom layer are consumed, and electrons migrating upwards are reduced. C doping is favorable for opening Mg-H bonds, reducing complex generation, improving the incorporation efficiency of Mg, improving hole concentration and improving the consumption of electrons. Meanwhile, Y, mg and C ternary codoping can effectively improve the forbidden bandwidth of GaN, so that electrons can be effectively limited from upwards migrating, electric leakage is avoided, and the reliability and luminous efficiency of the device are improved. Specifically, the doping concentration of Mg in the ternary co-doped GaN layer 31 is 1×10 14 cm -3 ~1×10 17 cm -3 Preferably 1X 10 14 cm -3 ~5×10 16 cm -3 More preferably 1X 10 15 cm -3 ~7×10 15 cm -3 Because the invention introduces C, relatively high hole concentrations can be generated at lower Mg doping concentrations. The doping concentration of C in the ternary co-doped GaN layer 31 was 5×10 15 cm -3 ~9×10 18 cm -3 Preferably 1X 10 16 cm -3 ~5×10 18 cm -3 Further preferably 5X 10 16 cm -3 ~5×10 17 cm -3 . The doping concentration of Y in the ternary co-doped GaN layer 31 was 1×10 15 cm -3 ~1×10 19 cm -3 When the doping concentration is too low, it is difficult to effectively increase the forbidden bandwidth of the layer, and when the doping concentration is too high, the preparation efficiency is low. Preferably, the doping concentration of Y in the ternary co-doped GaN layer 31 is 5×10 15 cm -3 ~5×10 18 cm -3 More preferably 1X 10 18 cm -3 ~5×10 18 cm -3 . Based on the doping concentration, not only can the forbidden bandwidth of the ternary co-doped GaN layer 31 be increased, but also electrons can be retarded; meanwhile, the layer has relatively larger lattice constant, so that compressive stress is applied to the P-type InAlN layer 32 which grows subsequently, tensile stress from the silicon substrate 1 is partially counteracted, the quality of each subsequent layer is improved, the non-radiative recombination center in the multi-quantum well layer 6 is reduced, and the luminous efficiency is improved.
Wherein, the thickness of the ternary co-doped GaN layer 31 is 0.5nm to 10nm, preferably 1nm to 5nm, more preferably 1nm to 3nm. The thinner layer structure can distort interface stress, reduce dislocation extension, improve lattice quality, and further improve luminous efficiency.
The P-type InAlN layer 32 can generate holes by P-type doping, further consume electrons from the silicon substrate 1, and prevent electrons from migrating upward. Meanwhile, the P-type InAlN layer 32 and the ternary co-doped GaN layer 31 form a heterojunction material, the inverse piezoelectric effect of high-voltage operation of the LED is eliminated, and the reliability of the LED device based on the LED epitaxial wafer during long-time operation under high voltage is improved.
Specifically, the P-type doping element in the P-type InAlN layer 32 is Mg, be or Zn, but is not limited thereto. Mg is preferred. The P-type doping concentration in the P-type InAlN layer 32 is 5×10 15 cm -3 ~5×10 17 cm -3 Preferably 1X 10 16 cm -3 ~2×10 17 cm -3 More preferably 2X 10 17 cm -3 ~5×10 17 cm -3 。
The introduction of In component In the P-type InAlN layer 32 can improve the incorporation efficiency of Mg to a certain extent, and can also adjust the lattice constant of the P-type InAlN layer 32 to be larger than that of the C-doped AlN layer 33, so that the C-doped AlN layer 33 provides compressive stress to the C-doped AlN layer, and the luminous efficiency is improved. Specifically, the In component In the P-type InAlN layer 32 has a ratio of 0.01 to 0.25, preferably 0.01 to 0.2, and more preferably 0.05 to 0.1, and the lattice constant of the P-type InAlN layer 32 based on the In component is smaller than that of the ternary co-doped GaN layer 31, so that compressive stress can be provided, and the light emitting efficiency is improved.
The thickness of the P-type InAlN layer 32 is 0.5nm to 10nm, preferably 1nm to 5nm, more preferably 1nm to 3nm. The thinner layer structure can distort interface stress, reduce dislocation extension, improve lattice quality, and further improve luminous efficiency.
Wherein, the C-doped AlN layer 33 is introduced with C-doping, which can prevent the P-doped element of the P-type InAlN layer 32 from migrating upward to the undoped GaN layer 4 and the N-type GaN layer 5, so as to cause non-radiative recombination of electrons generated by the N-type GaN layer 5, thereby improving the light emitting efficiency. In addition, the C-doped AlN layer 33 also provides compressive stress for the P-type InAlN layer 32, so that the overall tensile stress is relieved, and the luminous efficiency is improved.
Specifically, the doping concentration of C in the C-doped AlN layer 33 is6×10 16 cm -3 ~5×10 18 cm -3 Preferably 1X 10 17 cm -3 ~2×10 18 cm -3 More preferably 5X 10 17 cm -3 ~2×10 18 cm -3 。
The thickness of the C-doped AlN layer 33 is 10nm to 20nm, and when the thickness is too thin, it is difficult to effectively block upward migration of the P-type element. Preferably, the thickness of the C-doped AlN layer 33 is 10nm to 15nm.
Wherein the buffer layer 2 comprises an AlN layer and Al sequentially laminated on the silicon substrate 1 x Ga 1-x N layer (x=0.1-0.2), wherein the AlN layer has a thickness of 10-20 nm, al x Ga 1-x The thickness of the N layer is 20 nm-90 nm.
The thickness of the undoped GaN layer 4 is 1 μm to 3 μm, and exemplary thicknesses are 1.1 μm, 1.3 μm, 1.7 μm, 2.1 μm, or 2.4 μm, but not limited thereto.
Among them, the doping element of the N-type GaN layer 5 is Si or Ge, but is not limited thereto, and Si is preferable. The doping concentration of the N-type GaN layer 5 is 5×10 18 cm -3 ~5×10 19 cm -3 Exemplary is 6X 10 18 cm -3 、9×10 18 cm -3 、3×10 19 cm -3 Or 4X 10 19 cm -3 But is not limited thereto. The thickness of the N-type GaN layer 5 is 1 μm to 3 μm, and exemplary thicknesses are 1.2 μm, 1.6 μm, 2 μm, 2.4 μm, 2.8 μm, or 2.9 μm, but not limited thereto.
The multiple quantum well layer 6 is an InGaN quantum well layer and an AlGaN quantum barrier layer which are alternately stacked, and the stacking period is 3-15. The thickness of the single InGaN quantum well layer is 3nm to 5nm, and exemplary is 3.3nm, 3.7nm, 4.1nm, 4.5nm, or 4.9nm, but is not limited thereto. The thickness of the single AlGaN quantum barrier layer is 5nm to 15nm, and is exemplified by, but not limited to, 6nm, 8nm, 10nm, 12nm, or 14nm.
The electron blocking layer 7 is an AlGaN layer or an AlInGaN layer, but is not limited thereto. An AlInGaN layer is preferred. The thickness is 10nm to 40nm, and is exemplified by 15nm, 20nm, 25nm, 30nm or 35nm, but not limited thereto.
Wherein the P-type doping element in the P-type GaN layer 8 is Mg, be or ZnBut is not limited thereto. Mg is preferred. The P-type doping concentration in the P-type GaN layer 8 is 1×10 19 cm -3 ~1×10 21 cm -3 Exemplary is 3×10 19 cm -3 、7×10 19 cm -3 、1×10 20 cm -3 、4×10 20 cm -3 Or 8X 10 20 cm -3 But is not limited thereto. The thickness of the P-type GaN layer 8 is 10nm to 50nm, and is exemplified by, but not limited to, 15nm, 17nm, 22nm, 24nm, 30nm, 40nm, or 45 nm.
Correspondingly, referring to fig. 3, the invention also discloses a preparation method of the silicon substrate-based LED epitaxial wafer, which is used for preparing the silicon substrate-based LED epitaxial wafer, and comprises the following steps:
s1: providing a silicon substrate;
s2: sequentially growing a buffer layer, a resistor layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer on a silicon substrate;
specifically, step S2 includes:
s21: growing a buffer layer on a silicon substrate;
wherein, an Al layer is grown by PVD, then transferred into an MOCVD reaction chamber, and then is formed in NH 3 Nitriding at 1000-1200 ℃ in the atmosphere to form an AlN layer, and regrowing Al x Ga 1-x And N layers, namely obtaining the buffer layer. Wherein Al is x Ga 1-x The growth temperature of the N layer is 900-1000 ℃ and the growth pressure is 100-300 torr.
S22: growing a resistor layer on the buffer layer;
specifically, in one embodiment of the present invention, the ternary co-doped GaN layer, the P-type InAlN layer, and the C-doped AlN layer are periodically grown by MOCVD until a resistive layer is obtained.
The growth temperature of the ternary co-doped GaN layer is 800-850 ℃, and the growth pressure is 50-300 torr. During growth, TEGa is used as a C source and a Ga source, and Cp is used as Cp 2 Mg as a source of Mg, in order (MeCp) 3 Y is used as a Y source.
The growth temperature of the P-type InAlN layer is 750-850 ℃, and the growth pressure is 50-300 torr.
Wherein the growth temperature of the C-doped AlN layer is 700-900 ℃ and the growth pressure is 50-300 torr. During growth, TEAL is used as a C source and an Al source. Preferably, the growth temperature of the C-doped AlN layer is 700-800 ℃, and the lower growth temperature can ensure that the P-type doped element in the P-type InAlN layer can not obtain enough energy to migrate upwards, and particularly can inhibit the memory effect of the P-type doped element Mg.
S23: growing an undoped GaN layer on the resistor layer;
in one embodiment of the invention, an undoped GaN layer is grown in MOCVD at 1050-1150 ℃ and 100-500 torr.
S24: growing an N-type GaN layer on the undoped GaN layer;
in one embodiment of the invention, an N-type GaN layer is grown in MOCVD at 1100-1200 ℃ and at 100-500 torr.
S25: growing a multi-quantum well layer on the N-type GaN layer;
wherein, in one embodiment of the present invention, inGaN quantum well layers and AlGaN quantum barrier layers are periodically grown in MOCVD to form a multi-quantum well layer. The growth temperature of the InGaN quantum well layer is 750-900 ℃, and the growth pressure is 100-300 torr. The growth temperature of the AlGaN quantum barrier layer is 800-900 ℃, and the growth pressure is 100-300 torr.
S26: growing an electron blocking layer on the multiple quantum well layer;
wherein in one embodiment of the invention, an AlInGaN layer is grown by MOCVD as an electron blocking layer. The growth temperature is 900-1000 ℃, and the growth pressure is 100-300 torr.
S27: growing a P-type GaN layer on the electron blocking layer;
wherein, in one embodiment of the invention, the P-type GaN layer is grown by MOCVD. The growth temperature is 1000-1100 ℃, and the growth pressure is 100-300 torr.
The invention is further illustrated by the following examples:
example 1
Referring to fig. 1-2, the embodiment provides a silicon substrate-based LED epitaxial wafer, which includes a silicon substrate 1, and a buffer layer 2, a resistive layer 3, an undoped GaN layer 4, an N-type GaN layer 5, a multiple quantum well layer 6, an electron blocking layer 7 and a P-type GaN layer 8 sequentially disposed on the silicon substrate 1.
Wherein the buffer layer 2 comprises an AlN layer and Al sequentially laminated on the silicon substrate 1 x Ga 1-x N layer (x=0.12), alN layer 15nm thick, al x Ga 1-x The thickness of the N layer was 40nm.
Wherein the resistive layer 3 has a periodic structure, and the number of periods is 10. The resistive layer 3 of each cycle includes a ternary co-doped GaN layer 31, a p-type InAlN layer 32, and a C-doped AlN layer 33, which are sequentially stacked. The doping elements in the ternary co-doped GaN layer 31 are Y, mg and C. The doping concentration of Mg is 8 multiplied by 10 16 cm -3 The doping concentration of C is 7×10 18 cm -3 The doping concentration of Y is 4X 10 15 cm -3 The thickness was 2nm. The P-type doping element in the P-type InAlN layer 32 is Mg, and the doping concentration is 8 multiplied by 10 15 cm -3 The In component was 0.22 In ratio and 3nm In thickness. The C doping concentration of the C-doped AlN layer 33 was 4X 10 18 cm -3 The thickness was 18nm.
Wherein the thickness of the undoped GaN layer 4 is 1.5 μm. The thickness of the N-type GaN layer 5 is 2 μm, the doping element is Si, and the doping concentration of Si is 2×10 19 cm -3 。
The multiple quantum well layer 6 has a periodic structure, and the number of periods is 10, and each period includes an InGaN quantum well layer and an AlGaN quantum barrier layer which are sequentially stacked. Wherein the thickness of the single InGaN quantum well layer is 3nm, and the thickness of the single AlGaN quantum barrier layer is 11nm.
The electron blocking layer 7 is an AlInGaN layer, and the thickness thereof is 35nm. The thickness of the P-type GaN layer 8 is 45nm, the doping element is Mg, and the doping concentration is 5 multiplied by 10 20 cm -3 。
The preparation method for the LED epitaxial wafer based on the silicon substrate in the embodiment comprises the following steps:
(1) Providing a silicon substrate;
(2) Growing a buffer layer on a silicon substrate;
wherein, an Al layer is grown by PVD, then transferred into an MOCVD reaction chamber, and then is formed in NH 3 Nitriding at 1100 ℃ in the atmosphere to form an AlN layer, and regrowing Al x Ga 1-x And N layers, namely obtaining the buffer layer. Wherein Al is x Ga 1-x The growth temperature of the N layer is 980 ℃, and the growth pressure is 200torr.
(3) Growing a resistor layer on the buffer layer;
and periodically growing a ternary co-doped GaN layer, a P-type InAlN layer and a C-doped AlN layer through MOCVD until a resistor layer is obtained.
Wherein, the growth temperature of the ternary co-doped GaN is 820 ℃, and the growth pressure is 200torr. The growth temperature of the P-type InAlN layer is 780 ℃ and the growth pressure is 200torr. The growth temperature of the C-doped AlN layer is 820 ℃, and the growth pressure is 200torr.
(4) Growing an undoped GaN layer on the resistor layer;
wherein, the undoped GaN layer is grown in MOCVD, the growth temperature is 1120 ℃, and the growth pressure is 300torr.
(5) Growing an N-type GaN layer on the undoped GaN layer;
wherein, the N-type GaN layer is grown in MOCVD, the growth temperature is 1130 ℃, and the growth pressure is 300torr.
(6) Growing a multi-quantum well layer on the N-type GaN layer;
wherein the InGaN quantum well layer and the AlGaN quantum barrier layer are periodically grown in MOCVD to form a multi-quantum well layer. The growth temperature of the InGaN quantum well layer is 780 ℃ and the growth pressure is 200torr. The growth temperature of the AlGaN quantum barrier layer is 880 ℃, and the growth pressure is 200torr.
(7) An electron blocking layer on the multiple quantum well layer;
wherein an AlInGaN layer is grown by MOCVD as an electron blocking layer. The growth temperature was 930℃and the growth pressure was 150torr.
(8) Growing a P-type GaN layer on the electron blocking layer;
wherein the P-type GaN layer is grown by MOCVD. The growth temperature is 1050 ℃, and the growth pressure is 200torr.
Example 2
The present embodiment provides a silicon substrate-based LED epitaxial wafer, which differs from embodiment 1 in that:
wherein the number of cycles of the resistive layer 3 is 8. The doping concentration of Mg in the ternary co-doped GaN layer 31 was 5×10 15 cm -3 The doping concentration of C is 2X 10 18 cm -3 The doping concentration of Y is 4X 10 17 cm -3 . The P-type doping element in the P-type InAlN layer 32 is Mg, and the doping concentration is 8 multiplied by 10 15 cm -3 The In component was 0.12 In ratio. The C doping concentration of the C-doped AlN layer 33 was 1X 10 18 cm -3 The thickness was 14nm.
The remainder was the same as in example 1.
Example 3
The present embodiment provides a silicon substrate-based LED epitaxial wafer, which differs from embodiment 2 in that: the doping concentration of Y in the ternary co-doped GaN layer 31 was 4×10 18 cm -3 。
The remainder was the same as in example 2.
Example 4
The present embodiment provides a silicon substrate-based LED epitaxial wafer, which differs from embodiment 2 in that: the In composition ratio In the P-type InAlN layer 32 was 0.08.
The remainder was the same as in example 3.
Comparative example 1
This comparative example provides a silicon substrate-based LED epitaxial wafer which differs from example 1 in that it does not include a resistive layer, and accordingly, does not include a step of preparing the layer. The remainder was the same as in example 1.
Comparative example 2
This comparative example provides a silicon substrate-based LED epitaxial wafer, which differs from example 1 in that it does not include a ternary co-doped GaN layer, and correspondingly, does not include a step of preparing the layer. The remainder was the same as in example 1.
Comparative example 3
This comparative example provides a silicon substrate-based LED epitaxial wafer, which differs from example 1 in that it does not include a P-type InAlN layer, and correspondingly, does not include a preparation step of the layer. The remainder was the same as in example 1.
Comparative example 4
This comparative example provides a silicon substrate-based LED epitaxial wafer which differs from example 1 in that it does not include a C-doped AlN layer, and, correspondingly, does not include a step of preparing the layer. The remainder was the same as in example 1.
Comparative example 5
This comparative example provides a silicon substrate-based LED epitaxial wafer, which is different from example 1 in that an AlN layer is used instead of a C-doped AlN layer in the resistive layer; the AlN layer is made by PVD. The remainder was the same as in example 1.
Processing the LED epitaxial wafers based on the silicon substrate obtained in the examples 1-4 and the comparative examples 1-5 into 10×24mil LED chips with vertical structures, and testing the light-emitting brightness and reliability; the specific test method comprises the following steps:
(1) Brightness: the brightness of the obtained chip was measured at 120mA current, 10 for each example and comparative example, and the average value was obtained. And calculating a luminance improvement ratio based on comparative example 1;
(2) Reliability: the LED chip was fixed to the bracket, continuously energized with a current of 100 μa, the test initiation voltage was adjusted to 5V, 2V was increased after each interval of 3s, and the voltage when the LED chip was turned off was EOS voltage for evaluation of reliability.
The specific results are as follows:
as can be seen from the table, when the resistive layer of the present invention was added to the conventional light emitting diode structure (comparative example 1), the light emitting efficiency and reliability were effectively improved.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that changes and modifications may be made without departing from the principles of the invention, such changes and modifications are also intended to be within the scope of the invention.

Claims (10)

1. The LED epitaxial wafer based on the silicon substrate is characterized by comprising the silicon substrate, and a buffer layer, a resistance layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer which are sequentially arranged on the silicon substrate; the resistor layer is of a periodic structure, the period number is more than or equal to 2, and the resistor layer of each period comprises a ternary co-doped GaN layer, a P-type InAlN layer and a C-doped AlN layer which are sequentially laminated; wherein, doping elements in the ternary co-doped GaN layer are Y, mg and C;
the doping concentration of Y in the ternary co-doped GaN layer is 1 multiplied by 10 18 cm -3 ~5×10 18 cm -3 。
2. The LED epitaxial wafer on the basis of the silicon substrate according to claim 1, wherein the doping concentration of C in the ternary co-doped GaN layer is 1 x 10 16 cm -3 ~5×10 18 cm -3 The doping concentration of Mg is 1×10 14 cm -3 ~5×10 16 cm -3 The thickness of the ternary co-doped GaN layer is 1 nm-5 nm.
3. The silicon substrate-based LED epitaxial wafer of claim 1, wherein the P-type doping element in the P-type InAlN layer is Mg with a doping concentration of 1 x 10 16 cm -3 ~2×10 17 cm -3 The In component accounts for 0.01-0.2, and the thickness of the P-type InAlN layer is 1-5 nm.
4. The silicon substrate-based LED epitaxial wafer of claim 1, wherein the C-doped AlN layer has a C-doping concentration of 1 x 10 17 cm -3 ~2×10 18 cm -3 The thickness of the C-doped AlN layer is 10 nm-15 nm.
5. The LED epitaxial wafer on the basis of the silicon substrate according to any one of claims 1 to 4, wherein the In composition In the P-type InAlN layer is 0.05 to 0.1, so that the lattice constant of the ternary co-doped GaN layer is larger than that of the P-type InAlN layer, and the lattice constant of the P-type InAlN layer is larger than that of the C-doped AlN layer.
6. A method for preparing a silicon substrate-based LED epitaxial wafer, for preparing the silicon substrate-based LED epitaxial wafer according to any one of claims 1 to 5, comprising:
providing a silicon substrate, and sequentially growing a buffer layer, a resistor layer, an undoped GaN layer, an N-type GaN layer, a multiple quantum well layer, an electron blocking layer and a P-type GaN layer on the silicon substrate; the resistor layer is of a periodic structure, the period number is more than or equal to 2, and the resistor layer of each period comprises a ternary co-doped GaN layer, a P-type InAlN layer and a C-doped AlN layer which are sequentially laminated; wherein the doping elements in the ternary co-doped GaN layer are Y, mg and C;
the doping concentration of Y in the ternary co-doped GaN layer is 1 multiplied by 10 18 cm -3 ~5×10 18 cm -3 。
7. The method for preparing the LED epitaxial wafer based on the silicon substrate according to claim 6, wherein the growth temperature of the ternary co-doped GaN layer is 800-850 ℃, and the growth pressure is 50-300 torr.
8. The method for preparing the LED epitaxial wafer based on the silicon substrate as claimed in claim 6, wherein the growth temperature of the P-type InAlN layer is 750-850 ℃, and the growth pressure is 50-300 torr.
9. The method for preparing the LED epitaxial wafer based on the silicon substrate according to claim 6, wherein the growth temperature of the C-doped AlN layer is 700-800 ℃ and the growth pressure is 50-300 torr.
10. A silicon substrate-based LED comprising the silicon substrate-based LED epitaxial wafer according to any one of claims 1 to 5.
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