CN116705797A - Transistor structure and preparation method thereof - Google Patents

Transistor structure and preparation method thereof Download PDF

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Publication number
CN116705797A
CN116705797A CN202310692215.3A CN202310692215A CN116705797A CN 116705797 A CN116705797 A CN 116705797A CN 202310692215 A CN202310692215 A CN 202310692215A CN 116705797 A CN116705797 A CN 116705797A
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layer
channel
transistor
gate
forming
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乔梦竹
全钟声
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present disclosure provides a transistor structure and a method of making the same. The structure comprises: a substrate; the grid structure is arranged on the substrate and is provided with a first grid part, a second grid part and a third grid part which are sequentially arranged in the direction vertical to and far away from the substrate; a first channel arranged on the substrate and surrounding the outer surface of the first grid part; the first source-drain electrode layer is arranged on the substrate and connected with two opposite sides of the first channel; the isolation layer is covered on the first channel and the first source drain electrode layer and surrounds the outer surface of the second grid electrode part; the second channel is arranged on the isolation layer and surrounds the outer surface of the third grid part; the second source-drain electrode layer is arranged on the isolation layer and connected with two opposite sides of the second channel; the first grid electrode part, the first channel and the first source drain electrode layer form a first transistor, the third grid electrode part, the second channel and the second source drain electrode layer form a second transistor, one of the transistors is an N-type transistor, and the other transistor is a P-type transistor. The present disclosure enables halving the footprint of a transistor structure.

Description

Transistor structure and preparation method thereof
Technical Field
The disclosure relates to the technical field of semiconductor manufacturing, and in particular relates to a transistor structure and a manufacturing method thereof.
Background
With the continuous maturity of semiconductor technology, the size of integrated circuits is continuously reduced, so that the length of a channel in a transistor is continuously shortened, and short channel effect is easy to generate. In the related art, in order to solve this problem, a vertical ring channel structure (Channel all around, CAA), i.e., a structure in which a channel surrounds a gate in a transistor, is used to provide more strict control over charge carriers in the channel, thereby alleviating short channel effects.
However, the structure of the channel surrounding gate is generally applied to CMOS (Complementary Metal Oxide Semiconductor ) which includes N-type transistors
N Metal Oxide Semiconductor, NMOS) and P-type transistors (P Metal Oxide Semiconductor, PMOS), CMOS technology standards have heretofore placed NMOS and PMOS side by side in the horizontal direction, with a large footprint, which is detrimental to further density improvement.
The above information disclosed in the background section is only for enhancement of understanding of the background of the disclosure and thus it may include information that does not form a related art that is already known to a person of ordinary skill in the art.
Disclosure of Invention
The embodiment of the disclosure provides a transistor structure and a preparation method thereof, which can halve the occupied area of an N-type transistor and a P-type transistor and increase the density by one time.
The embodiment of the disclosure provides a transistor structure, which comprises a substrate, a gate structure, a first channel, a first source-drain electrode layer, an isolation layer, a second channel and a second source-drain electrode layer. The grid structure is arranged on the substrate and is provided with a first grid part, a second grid part and a third grid part which are sequentially arranged in the direction vertical to and far away from the substrate. The first channel is arranged on the substrate and surrounds the outer surface of the first grid part. The first source drain electrode layer is arranged on the substrate and connected with two opposite sides of the first channel. The isolation layer covers the first channel and the first source drain layer and surrounds the outer surface of the second grid part. The second channel is arranged on the isolation layer and surrounds the outer surface of the third grid electrode part. The second source drain electrode layer is arranged on the isolation layer and connected with two opposite sides of the second channel. The first gate part, the first channel and the first source drain layer of the gate structure form a first transistor, and the third gate part, the second channel and the second source drain layer of the gate structure form a second transistor. One of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor.
The embodiment of the disclosure also provides a preparation method of the transistor structure, which comprises the following steps: providing a substrate; forming a first gate part, a first channel surrounding the first gate part and first source-drain electrode layers positioned on two opposite sides of the first channel on the substrate to form a first transistor; forming an isolation layer having a first via on the first channel and the first source-drain layer, the first via corresponding to the first gate portion in a vertical direction; forming a second gate portion in the first via hole; forming a third gate part on the second gate part, forming a second channel surrounding the third gate part and second source-drain layers positioned on two opposite sides of the second channel on the isolation layer, and forming a second transistor; one of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor.
According to the technical scheme, the transistor structure of the embodiment of the disclosure has the following beneficial effects:
in the embodiment of the disclosure, the first transistor and the second transistor are distributed in the vertical direction and share the same gate structure, so that the first transistor and the second transistor are prevented from being placed side by side in the horizontal direction, the occupied area is reduced by half, the density of the transistor structure is doubled, and the electrical performance of the transistor structure is improved.
Drawings
Fig. 1 is a top view of a transistor structure having a first insulating layer formed over a substrate and a first trench formed in the first insulating layer, as shown in some embodiments of the present disclosure;
FIGS. 2a and 2B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 1;
fig. 3 is a top view of a transistor structure having a first polysilicon layer formed in a first trench and doped therein, as shown in some embodiments of the present disclosure;
FIGS. 4a and 4B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 3;
fig. 5 is a top view of a transistor structure with an initial mask layer having an initial via pattern formed over a first insulating layer as shown in some embodiments of the present disclosure;
FIGS. 6a and 6B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 5;
fig. 7 is a top view of a transistor structure with initial vias formed after patterning a first doped polysilicon layer and a first insulating layer, as shown in some embodiments of the present disclosure;
FIGS. 8a and 8B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 7;
fig. 9 is a top view of a transistor structure with a second polysilicon layer and a first gate dielectric layer formed sequentially on an inner wall of an initial via, according to some embodiments of the present disclosure;
FIGS. 10a and 10B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 9;
Fig. 11 is a top view of a transistor structure for forming a first source drain layer and a first channel, respectively, by heat treating a first doped polysilicon layer and a second polysilicon layer, as shown in some embodiments of the present disclosure;
FIGS. 12a and 12B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 11;
fig. 13 is a top view of a transistor structure with a first gate formed in an initial via as shown in some embodiments of the present disclosure;
FIGS. 14a and 14B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 13;
figure 15 is a top view of a transistor structure forming an isolation layer shown in some embodiments of the present disclosure;
FIGS. 16a and 16B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 15;
fig. 17 is a top view of a transistor structure shown in some embodiments of the present disclosure forming a first mask layer having a first via pattern;
FIGS. 18a and 18B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 17;
fig. 19 is a top view of a transistor structure with a first via formed in an isolation layer, as shown in some embodiments of the present disclosure;
FIGS. 20a and 20B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 19;
fig. 21 is a top view of a transistor structure with a second gate dielectric layer formed in a first via as shown in some embodiments of the present disclosure;
FIGS. 22a and 22B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 21;
fig. 23 is a top view of a transistor structure with a second gate formed in a first via, as shown in some embodiments of the present disclosure;
FIGS. 24a and 24B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 23;
fig. 25 is a top view of a transistor structure with a second insulating layer formed and a second mask layer having a second trench pattern formed over the second insulating layer, as shown in some embodiments of the present disclosure;
FIGS. 26a and 26B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 25;
fig. 27 is a top view of a transistor structure with a second trench formed in a second insulating layer as shown in some embodiments of the present disclosure;
FIGS. 28a and 28B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 27;
fig. 29 is a top view of a transistor structure having a third polysilicon layer filled and doped in a second trench, as shown in some embodiments of the present disclosure;
FIGS. 30a and 30B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 29;
fig. 31 is a top view of a transistor structure with a third mask layer having a second via pattern formed over a second insulating layer, as shown in some embodiments of the present disclosure;
FIGS. 32a and 32B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 31;
Fig. 33 is a top view of a transistor structure with a second via formed by patterning a third doped polysilicon layer and a second insulating layer, as shown in some embodiments of the present disclosure;
FIGS. 34a and 34B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 33;
fig. 35 is a top view of a transistor structure in which a fourth polysilicon layer and a third gate dielectric layer are sequentially formed on an inner wall of a second via hole according to some embodiments of the present disclosure;
FIGS. 36a and 36B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 35;
fig. 37 is a top view of a transistor structure with a third gate filled in a second via as shown in some embodiments of the present disclosure;
FIGS. 38a and 38B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 37;
fig. 39 is a top view of a transistor structure having a third doped polysilicon layer and a fourth polysilicon layer heat treated to form a second source drain layer and a second channel, respectively, as shown in some embodiments of the present disclosure;
FIGS. 40a and 40B are cross-sectional views taken along line A-A and B-B, respectively, of FIG. 39;
fig. 41 is a flow chart of a method of fabricating a transistor structure shown in some embodiments of the present disclosure.
Reference numerals illustrate:
1. a substrate; 2. a first insulating layer; 201. a first trench; 3. a first polysilicon layer; 301. a first doped polysilicon layer; 302. a first source/drain layer; 4. an initial mask layer; 5. an initial through hole; 6. a second polysilicon layer; 601. a first channel; 7. an isolation layer; 8. a first mask layer; 9. a first through hole; 10. a second insulating layer; 1001. a second trench; 11. a second mask layer; 12. a third polysilicon layer; 1201. a third doped polysilicon layer; 1202. a second source/drain layer; 13. a third mask layer; 14. a second through hole; 15. a fourth polysilicon layer; 1501. a second channel; 20. a gate structure; 21. a first gate portion; 211. a first gate dielectric layer; 212. a first gate; 22. a second gate portion; 221. a second gate dielectric layer; 222. a second gate; 23. a third gate portion; 231. a third gate dielectric layer; 232. a third gate; x1, a first horizontal direction; x2, a second horizontal direction; y, vertical direction.
Detailed Description
The flow diagrams depicted in the figures of the present disclosure are exemplary only, and not necessarily all of the elements and operations/steps are included or performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
In addition, in the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless specifically defined otherwise.
As the size of integrated circuits continues to decrease, the length of the channel in the transistor continues to decrease, thereby facilitating the generation of short channel effects. The short channel effect makes the control capability of the gate to the channel worse, namely the difficulty of gate voltage pinch-off (pin off) channel becomes larger, so that subthreshold leakage (subthreshold leakage) phenomenon is easy to occur, thereby reducing the electrical performance of the transistor.
The structure of surrounding the grid by the channel is adopted in the CMOS, so that the short channel effect can be relieved. The CMOS includes NMOS and PMOS, but all CMOS technologies place NMOS and PMOS side by side on the horizontal plane, the occupation area is larger, and the density is not beneficial to further improvement.
Based on the above, the embodiments of the present disclosure provide a transistor structure, which can realize that an N-type transistor (NMOS) and a P-type transistor (PMOS) share a gate, and the N-type transistor (NMOS) and the P-type transistor (PMOS) are distributed in a vertical direction Y, so as to reduce a occupation area and improve a layout density of the transistor. The PMOS and NMOS are controlled to operate separately by adjusting voltages at terminals such as gate, source and drain terminals.
Specifically, as shown in fig. 39 to 40b, the transistor structure of the embodiment of the present disclosure includes a substrate 1, a gate structure 20, a first channel 601, a first source-drain layer 302, an isolation layer 7, a second channel 1501, and a second source-drain layer 1202. Wherein the first gate portion 21, the first channel 601 and the first source drain layer 302 of the gate structure 20 constitute a first transistor, the third gate portion 23, the second channel 1501 and the second source drain layer 1202 of the gate structure 20 constitute a second transistor, the first and second transistors being distributed in a direction perpendicular to the substrate 1 and being separated by the isolation layer 7.
Transistor structures according to embodiments of the present disclosure are described in detail below.
In the embodiments of the present disclosure, the material of the substrate 1 may be silicon, silicon carbide, silicon on insulator germanium, or germanium on insulator, etc. The substrate 1 may also be doped with certain doping particles to change electrical parameters according to design requirements.
Shallow trench isolations are formed on the substrate 1 with active regions between the shallow trench isolations. A word line structure and a bit line structure (not shown) may also be provided in the substrate 1, the word line structure and the bit line structure being provided at different heights of the substrate 1, and the word line structure and the bit line structure being connected to the active region. The transistor structure of the embodiments of the present disclosure is located in the active region of the substrate 1.
In the embodiment of the present disclosure, as shown in fig. 40a and 40b, the gate structure 20 is provided on the substrate 1, and the gate structure 20 has a first gate portion 21, a second gate portion 22, and a third gate portion 23 arranged in this order in a direction perpendicular to and away from the substrate 1. As shown in fig. 40a and 40b, the gate structure 20 includes a gate and a gate dielectric layer surrounding an outer surface of the gate. The gate includes a first gate 212, a second gate 222, and a third gate 232, and the gate dielectric layer includes a first gate dielectric layer 211, a second gate dielectric layer 221, and a third gate dielectric layer 231.
In some embodiments, the material of the gate dielectric layer may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-K dielectric.
In some embodiments, the gate may comprise any suitable conductive material, such as polysilicon, a metal (e.g., tungsten, aluminum, copper, etc.), a metal compound (e.g., titanium nitride, tantalum nitride), or a silicide, etc.
In the embodiment of the present disclosure, as shown in fig. 40a and 40b, the first channel 601 is disposed on the substrate 1 and surrounds the outer surface of the first gate portion 21, so that the first transistor in the embodiment of the present disclosure has a channel surrounding gate structure.
As shown in fig. 39, 40a and 40b, the first source/drain layer 302 is disposed on the substrate 1 and connected to opposite sides of the first channel 601.
The first source-drain layer 302 may include a first source portion and a first drain portion, the first source portion being connected to one side of the first channel 601, and the first drain portion being connected to the opposite side of the first channel 601.
In this manner, the first gate portion 21, the first channel 601, and the first source-drain layer 302 of the gate structure 20 constitute a first transistor. That is, the first source portion may be understood as the source of the first transistor, and the first drain portion may be understood as the drain of the first transistor, which is the transistor whose channel surrounds the gate structure 20.
In the embodiment of the present disclosure, as shown in fig. 40a and 40b, the isolation layer 7 covers the first channel 601 and the first source-drain layer 302, and is disposed around the outer surface of the second gate portion 22.
The isolation layer 7 is made of an insulating material, and in some embodiments, the material of the isolation layer 7 may be at least one of silicon oxide, silicon nitride, and silicon oxynitride. The isolation layer 7 is made of an insulating material, and can isolate the first transistor from the second transistor in an insulating manner.
In the embodiment of the present disclosure, as shown in fig. 40a and 40b, the second channel 1501 is disposed on the isolation layer 7 and surrounds the outer surface of the third gate portion 23, so that the second transistor in the embodiment of the present disclosure is also a channel surrounding gate structure.
Wherein, the material of the second channel 1501 may be the same as that of the first channel 601, for example, both may be monocrystalline silicon, so that the process can be simplified and the cost can be saved in the manufacturing process.
In the embodiment of the present disclosure, as shown in fig. 40a and 40b, the second source/drain layer 1202 is disposed on the isolation layer 7 and connected to opposite sides of the second channel 1501.
The second source/drain layer 1202 may include a second source portion and a second drain portion, the second source portion being connected to one side of the second channel 1501, and the second drain portion being connected to an opposite side of the second channel 1501.
In this manner, the third gate portion 23, the second channel 1501 and the second source drain layer 1202 of the gate structure 20 constitute a second transistor. That is, the second source portion may be understood as a source of the second transistor, and the second drain portion may be understood as a drain of the second transistor, which is a transistor with a channel surrounding the gate structure 20.
In an embodiment of the disclosure, one of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor. For example, the first transistor may be an N-type transistor (NMOS), then the second transistor is a P-type transistor (PMOS), the first transistor may be a P-type transistor, and then the second transistor is an N-type transistor.
In summary, in the embodiment of the disclosure, the first transistor and the second transistor are distributed in the vertical direction Y, share one gate structure 20, and are insulated and isolated by the isolation layer 7, so that the occupation area of the NMOS and the PMOS is halved while reducing the short channel effect, the density of the transistor structure is doubled, the electrical performance of the transistor structure is improved, and the limit of moore's law is further broken through.
The embodiment of the disclosure also provides a method for manufacturing a transistor structure, fig. 1 to 40b respectively show schematic structural diagrams of the transistor structure at different steps in the manufacturing process, and fig. 41 shows a flowchart of the method for manufacturing the transistor structure.
As shown in fig. 41, the method of manufacturing a transistor structure according to an embodiment of the present disclosure includes the following steps S411 to S415.
S411: a substrate 1 is provided.
S412: a first gate portion 21, a first channel 601 surrounding the first gate portion 21, and first source-drain layers 302 located on opposite sides of the first channel 601 are formed on the substrate 1, forming a first transistor.
S413: an isolation layer 7 having a first via hole 9 is formed on the first channel 601 and the first source-drain layer 302, the first via hole 9 corresponding to the first gate portion 21 in the vertical direction Y.
S414: a second gate portion 22 is formed in the first via hole 9.
S415: forming a third gate portion 23 on the second gate portion 22, and forming a second channel 1501 surrounding the third gate portion 23 and second source-drain layers 1202 located at opposite sides of the second channel 1501 on the isolation layer 7, forming a second transistor; one of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor.
In the method of the embodiment of the disclosure, the N-type transistors and the P-type transistors distributed in the vertical direction Y can be formed, and the two transistors share one gate, so that the occupied area of the transistor structure is reduced by half, the density is doubled, and the electrical performance of the transistor structure is further improved.
The following describes in detail the method for manufacturing the transistor structure according to the embodiment of the present disclosure.
S411: a substrate 1 is provided.
The material of the substrate 1 may be silicon, silicon carbide, silicon on insulator, silicon germanium on insulator, or the like. The substrate 1 may also be doped with certain doping particles to change electrical parameters according to design requirements. The substrate 1 is identical to the substrate 1 in the embodiment of the transistor structure and will not be described here again.
S412: a first gate portion 21, a first channel 601 surrounding the first gate portion 21, and first source-drain layers 302 located on opposite sides of the first channel 601 are formed on the substrate 1, forming a first transistor.
In some embodiments, S412 may include the following A1-A8.
A1: a first insulating layer 2 is formed on a substrate 1 as shown in fig. 1.
In some embodiments, the material of the first insulating layer 2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.
In some embodiments, the first insulating layer 2 having a certain thickness may be deposited on the substrate 1 using a deposition process. The deposition process may be at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process, and is not particularly limited herein. When the first insulating layer 2 is silicon oxide, the top portion of the silicon oxide substrate 1 may also be oxidized using a dry oxidation method or a wet oxidation method (e.g., in-situ steam generation process, in-situ steam generation, ISSG) to form the first insulating layer 2 of silicon oxide.
A2: a first trench 201 extending in the first horizontal direction X1 is formed in the first insulating layer 2.
A mask layer (not shown) of a first trench pattern extending in the first horizontal direction X1 may be formed on the first insulating layer 2, the first insulating layer 2 is etched using the mask layer, and the first trench 201 is formed in the first insulating layer 2 to expose the substrate 1, as shown in fig. 1, 2a and 2 b.
In some embodiments, the first trench 201 may be etched on the first insulating layer 2 using a dry etching process or a wet etching process, and those skilled in the art may select according to practical situations, which is not limited herein.
A3: a first polysilicon layer 3 is formed in the first trench 201.
As shown in fig. 3, 4a and 4b, a first polysilicon layer 3 may be deposited in the first trench 201 using a deposition process, the first polysilicon layer 3 filling the first trench 201. After forming the first polysilicon layer 3, the first polysilicon layer 3 higher than the top surface of the first insulation layer 2 may be removed using a chemical mechanical polishing process such that the top surface of the first polysilicon layer 3 is flush with the top surface of the first insulation layer 2.
A4: one of N-type doping ions and P-type doping ions is doped into the first polysilicon layer 3 to form a first doped polysilicon layer 301.
As shown in fig. 4a and 4b, the first polysilicon layer 3 is used to form the source and drain of the first transistor, and thus the first polysilicon layer 3 needs to be doped. If the first transistor is an N-type transistor, the first polysilicon layer 3 may be N-doped, the dopant may be phosphorus (P) or arsenic (As), and if the first transistor is a P-type transistor, the first polysilicon layer 3 may be P-doped, the dopant may be boron (B) or gallium (Ga). The doping may be performed by an ion implantation process or a thermal diffusion process, and is not particularly limited herein.
A5: the first doped polysilicon layer 301 and the first insulating layer 2 are patterned to the substrate 1, forming an initial via 5, the diameter of the initial via 5 being larger than the size of the first doped polysilicon layer 301 in the second horizontal direction X2, the second horizontal direction X2 being perpendicular to the first horizontal direction X1.
As shown in fig. 5, 6a and 6b, an initial mask layer 4 having an initial via 5 pattern is formed on the first insulating layer 2 and the first doped polysilicon layer 301, and the first insulating layer 2 and the first doped polysilicon layer 301 are patterned using the initial mask layer 4.
As shown in fig. 7, 8a and 8b, the first doped polysilicon layer 301 and the first insulating layer 2 are patterned to the substrate 1, i.e., the surface of the substrate 1 is exposed, forming the initial via 5. The diameter of the initial via 5 is larger than the dimension of the first doped polysilicon layer 301 in the second horizontal direction X2, which is also understood to mean that the diameter of the initial via 5 is larger than the width of the first doped polysilicon layer 301. The first horizontal direction X1 and the second horizontal direction X2 are perpendicular, and the first horizontal direction X1 and the second horizontal direction X2 are perpendicular to the vertical direction Y.
Setting the diameter of the initial via 5 to be larger than the width of the first doped polysilicon layer 301 can ensure that the first source-drain layer 302 formed in the subsequent process is located at opposite sides of the first channel 601, avoiding source-drain interconnection in the first source-drain layer 302.
A6: a second polysilicon layer 6 and a first gate dielectric layer 211 are sequentially formed on the inner wall of the initial via hole 5.
As shown in fig. 9, 10a and 10b, a second polysilicon layer 6 may be formed on the inner wall of the initial via 5, the first insulating layer 2 and the first doped polysilicon layer 301 using a deposition process, a first gate dielectric layer 211 may be formed on the second polysilicon layer 6, i.e., the second polysilicon layer 6 surrounds the first gate dielectric layer 211, and then the second polysilicon layer 6 and the first gate dielectric layer 211 on the first insulating layer 2 and the first doped polysilicon layer 301 may be removed using a chemical mechanical polishing process, leaving only the second polysilicon layer 6 and the first gate dielectric layer 211 on the inner wall of the initial via 5.
A7: the first doped polysilicon layer 301 and the second polysilicon layer 6 are heat treated to form a first source drain layer 302 and a first channel 601, respectively.
As shown in fig. 11, 12a and 12b, the first doped polysilicon layer 301 and the second polysilicon layer 6 are heat treated so that the polysilicon is formed as single crystal silicon, that is, the first doped polysilicon layer 301 is formed as a first doped single crystal silicon layer and further formed as a first source drain layer 302, and the second polysilicon layer 6 is formed as a second single crystal silicon layer and further formed as a first channel 601.
In some embodiments, the temperature of the heat treatment is 900 ℃ to 1200 ℃, specifically, in addition to the above two end values, the temperature of the heat treatment may be 950 ℃, 1000 ℃, 1050 ℃, 1100 ℃, 1150 ℃, and the person skilled in the art may adjust according to the actual situation, and is not particularly limited herein.
A8: the first gate electrode 212 is filled in the initial via hole 5 in which the first gate dielectric layer 211 is formed, and the first gate electrode 212 and the first gate dielectric layer 211 form a first gate portion 21.
As shown in fig. 13, 14a and 14b, the initial via 5 where the first gate dielectric layer 211 is formed may be filled with the first gate electrode 212 using a deposition process. For the first gate 212 higher than the surface of the first insulating layer 2 and deposited on the surface of the first insulating layer 2, the first gate 212 on the surface of the first insulating layer 2 may be removed by a chemical mechanical polishing process after the deposition process is completed, and the top surface of the first gate 212 in the initial via 5 may be treated to be flush with the surface of the first insulating layer 2. The first gate electrode 212 and the first gate dielectric layer 211 form a first gate electrode portion 21.
In some embodiments, the material of the first gate 212 may include at least one of polysilicon, tungsten, titanium nitride, tantalum nitride, and silicide, which is not limited herein.
As shown in fig. 14a and 14b, after the above process, the first gate portion 21, the first channel 601 surrounding the first gate portion 21, and the first source-drain layer 302 located at opposite sides of the first channel 601 are formed as a first transistor, which may be one of an N-type transistor and a P-type transistor.
In other embodiments, S412 may include the following B1-B8.
B1: a first insulating layer 2 is formed on a substrate 1 as shown in fig. 1.
The first insulating layer 2 may be formed on the substrate 1 using a deposition process or a dry silicon oxide method or a wet oxidation method. The material and specific forming process of the first insulating layer 2 may be the same as those of the first insulating layer 2 in the above embodiment A1, and will not be described here again.
B2: a first trench 201 extending in the first horizontal direction X1 is formed in the first insulating layer 2.
As shown in fig. 1, 2a and 2b, a first trench 201 extending in a first horizontal direction X1 may be etched in the first insulating layer 2 using an etching process. The process of forming the first trench 201 may be the same as A2 in the above embodiment, and will not be described here again.
B3: a first single crystal silicon layer is epitaxially grown in the first trench 201.
In this embodiment, the substrate 1 is a single crystal silicon substrate. After the first trench 201 is formed in the first insulating layer 2, the first trench 201 exposes the surface of the substrate 1, at which time a single crystal silicon layer may be grown on the exposed surface of the substrate 1 using an epitaxial growth technique until the epitaxially grown single crystal silicon layer stops after filling the first trench 201, thereby forming a first single crystal silicon layer in the first trench 201. The first monocrystalline silicon layer is used for forming the first source/drain electrode layer 302 in a subsequent process, and compared with the above embodiment, the heat treatment of the first monocrystalline silicon layer is not needed, thereby saving the process.
B4: one of N-type doping ions and P-type doping ions is doped into the first monocrystalline silicon layer, so that the first doped monocrystalline silicon layer is formed.
Since the first single crystal silicon layer is used to form the source and drain electrodes of the first transistor, the first single crystal silicon layer needs to be doped. If the first transistor is an N-type transistor, the first polysilicon layer 3 may be N-doped, the dopant may be phosphorus (P) or arsenic (As), and if the first transistor is a P-type transistor, the first single crystal silicon layer may be P-doped, the dopant may be boron (B) or gallium (Ga). The doping may be performed by an ion implantation process or a thermal diffusion process, and is not particularly limited herein.
B5: the first doped monocrystalline silicon layer and the first insulating layer 2 are patterned to the substrate 1 to form an initial via 5, the first doped monocrystalline silicon layer is formed as the first source-drain layer 302, the diameter of the initial via 5 is larger than the size of the first doped monocrystalline silicon layer in the second horizontal direction X2, and the second horizontal direction X2 is perpendicular to the first horizontal direction X1.
An initial mask layer 4 having an initial via 5 pattern is formed on the first insulating layer 2 and the first doped monocrystalline silicon, and the first insulating layer 2 and the first doped monocrystalline silicon layer are patterned using the initial mask layer 4.
The first doped monocrystalline silicon layer and the first insulating layer 2 are patterned to the substrate 1, i.e. the surface of the substrate 1 is exposed, forming an initial via 5. The diameter of the initial via 5 is larger than the dimension of the first doped monocrystalline silicon layer in the second horizontal direction X2, which is also understood to mean that the diameter of the initial via 5 is larger than the width of the first doped monocrystalline silicon layer.
Setting the diameter of the initial via 5 to be larger than the width of the first doped monocrystalline silicon can ensure that the first source-drain layer 302 formed in the subsequent process is located at opposite sides of the first channel 601, and avoid source-drain interconnection in the first source-drain layer 302.
B6: a second polysilicon layer 6 and a first gate dielectric layer 211 are sequentially formed on the inner wall of the initial via hole 5.
In some embodiments, the second polysilicon layer 6 and the first gate dielectric layer 211 may be sequentially formed on the inner wall of the initial via hole 5 using a deposition process such that the second polysilicon layer 6 surrounds the first gate dielectric layer 211. The formation process of the second polysilicon layer 6 and the first gate dielectric layer 211 is the same as the process of the A6 in the above embodiment, and will not be repeated here.
B7: the second polysilicon layer 6 is heat treated to form a first channel 601.
In some embodiments, the temperature of the heat treatment is 900 to 1200 ℃, specifically, in addition to the above two end values, the temperature of the heat treatment may be 950 ℃, 1000 ℃, 1050 ℃, 1100 ℃, 1150 ℃, and the person skilled in the art may adjust the temperature according to the actual situation, and the present invention is not limited thereto.
In other embodiments, the second polysilicon layer 6 may not be formed, and the first channel 601 may be directly formed by continuing epitaxial growth on the surface of the first single crystal silicon layer, so that a subsequent heat treatment process may be omitted.
B8: the first gate electrode 212 is filled into the initial via hole 5 where the first gate dielectric layer 211 is formed, and the first gate electrode 212 and the first gate dielectric layer 211 form a first gate portion 21.
The material and the process for forming the first gate 212 may be the same as those in A8 in the above embodiment, and will not be described here again.
After the above process, the first gate portion 21, the first channel 601 surrounding the first gate portion 21, and the first source-drain layer 302 located at opposite sides of the first channel 601 are formed as a first transistor, which may be one of an N-type transistor and a P-type transistor.
In other embodiments, S412 may include the following C1-C9.
C1: a first trench extending in a first horizontal direction X1 is formed in the substrate 1.
Specifically, a mask layer having a first trench pattern may be formed on the substrate 1, the substrate 1 is etched using the mask layer, and a first trench extending in the first horizontal direction X1 is formed in the substrate 1.
C2: a first polysilicon layer is formed in the first trench.
After the first trench is formed, the mask layer is not removed first, a first polysilicon layer is deposited in the first trench by a deposition process, the first trench is filled, and then the mask layer is removed.
And C3: and doping one of N-type doping ions and P-type doping ions into the first polysilicon layer to form the first doped polysilicon layer.
The first polysilicon layer is used to form the source and drain of the first transistor, and thus the first polysilicon layer needs to be doped. If the first transistor is an N-type transistor, the first polysilicon layer may be N-doped, the dopant may be phosphorus (P) or arsenic (As), and if the first transistor is a P-type transistor, the first polysilicon layer 3 may be P-doped, the dopant may be boron (B) or gallium (Ga). The doping may be performed by an ion implantation process or a thermal diffusion process, and is not particularly limited herein.
And C4: and removing the parts of the substrate 1 positioned at the two sides of the first doped polysilicon layer, so that the first doped polysilicon layer protrudes out of the rest of the substrate.
A mask layer is formed on the surface of the substrate 1, the mask layer covers a portion of the first doped polysilicon layer, an etching process may be used to remove the uncovered portion of the substrate 1, that is, the portion of the substrate 1 located at two sides of the first doped polysilicon layer, the remaining portion of the substrate 1 is lower than the first doped polysilicon layer in the vertical direction Y, and the surface of the remaining portion of the substrate 1 may be flush with the bottom surface of the first doped polysilicon layer, that is, the first doped polysilicon layer protrudes from the remaining substrate 1.
C5: a first insulating layer is formed on the remaining substrate 1 on both sides of the first doped polysilicon layer, the top surface of the first insulating layer being flush with the top surface of the first doped polysilicon layer.
Masking the first doped polysilicon layer, for example, a mask layer in C4 may be used, or another mask layer that masks the first doped polysilicon layer may be reformed, and a deposition process may be used to form a first insulating layer on the remaining substrate 1. The mask layer is removed and a portion of the first insulating layer above the first doped polysilicon layer may be removed using a chemical mechanical polishing process such that a top surface of the first insulating layer is level with a top surface of the first doped polysilicon layer.
C6: patterning the first doped polysilicon layer and the first insulating layer to the surface of the remaining substrate 1 to form an initial via hole, wherein the diameter of the initial via hole is larger than the dimension of the first doped polysilicon layer in the second horizontal direction X2, and the second horizontal direction X2 is perpendicular to the first horizontal direction X1.
Referring to fig. 7, 8a and 8b, the first doped polysilicon layer 301 and the first insulating layer 2 may be patterned to the remaining substrate 1, i.e., to expose the surface of the substrate 1, to form the initial via 5. The diameter of the initial via 5 is larger than the dimension of the first doped polysilicon layer 301 in the second horizontal direction X2, which is also understood to mean that the diameter of the initial via 5 is larger than the width of the first doped polysilicon layer 301.
Setting the diameter of the initial via 5 to be larger than the width of the first doped polysilicon can ensure that the first source-drain layer 302 formed in the subsequent process is located at opposite sides of the first channel 601, avoiding source-drain interconnection in the first source-drain layer 302.
C7: a second polysilicon layer 6 and a first gate dielectric layer 211 are sequentially formed on the inner wall of the initial via hole 5.
And C8: the first doped polysilicon layer 301 and the second polysilicon layer 6 are heat treated to form a first source drain layer 302 and a first channel 601, respectively.
C9: the first gate electrode 212 is filled in the initial via hole 5 in which the first gate dielectric layer 211 is formed, and the first gate electrode 212 and the first gate dielectric layer 211 form a first gate portion 21.
The process of C7 to C9 in this embodiment may be the same as the process of A6 to A8 in the above embodiment, and will not be described here again.
After the above process, the first gate portion 21, the first channel 601 surrounding the first gate portion 21, and the first source-drain layer 302 located at opposite sides of the first channel 601 are formed as a first transistor, which may be one of an N-type transistor and a P-type transistor.
In other embodiments, S412 may include the following D1-D8.
D1: a first block mask layer having a first trench pattern extending in a first horizontal direction X1 is formed on the substrate 1, where the substrate 1 is exposed.
Specifically, a first shadow mask layer and a photoresist layer stacked in sequence may be formed on the substrate 1, a first trench pattern is formed on the photoresist layer using a photolithography process, and then the first shadow mask layer is patterned using an etching process, the first trench pattern is transferred into the first shadow mask layer, and the substrate 1 is exposed.
D2: one of the N-type doping ions and the P-type doping ions is doped into the exposed substrate 1 to form a doped substrate.
After exposing the substrate 1, the first blocking mask layer is reserved to block other parts of the substrate 1, and one of N-type doping ions and P-type doping ions is doped on the exposed part of the substrate 1. The partially doped substrate 1 is used to form the first source drain layer 302 in a subsequent process, and thus, in this embodiment, the material of the substrate 1 may be monocrystalline silicon. The exposed substrate 1 is doped to form a first doped monocrystalline silicon layer.
Doping can be performed by using an ion implantation process or a thermal diffusion process, and the implantation depth can be adjusted by adjusting the concentration of implanted ions and process parameters.
D3: the portions of the substrate 1 on both sides of the first doped monocrystalline silicon layer are removed so that the first doped monocrystalline silicon layer protrudes beyond the remaining substrate 1.
Specifically, the first shielding mask layer is removed, and a second shielding mask layer is formed on the first doped monocrystalline silicon layer so as to shield the first doped monocrystalline silicon layer. The exposed portion of the substrate 1 may be etched using an etching process, and the surface of the remaining substrate 1 may be flush with the bottom surface of the first doped monocrystalline silicon layer, i.e., the first doped monocrystalline silicon layer protrudes from the remaining substrate 1.
D4: a first insulating layer 2 is formed on the remaining substrate 1 on both sides of the first doped monocrystalline silicon layer, the top surface of the first insulating layer 2 being flush with the top surface of the first doped monocrystalline silicon layer.
The second blocking mask layer is left to block the first doped monocrystalline silicon layer, and the first insulating layer 2 may be formed on the remaining substrate 1 using a deposition process. And then removing the second blocking mask layer, the part of the first insulating layer 2 higher than the first doped monocrystalline silicon layer can be removed by using a chemical mechanical polishing process, so that the top surface of the first insulating layer 2 is flush with the top surface of the first doped monocrystalline silicon.
D5: the first doped monocrystalline silicon layer and the first insulating layer 2 are patterned to the surface of the remaining substrate 1, forming an initial via 5, the diameter of the initial via 5 being larger than the dimension of the first doped polycrystalline silicon layer 301 in the second horizontal direction X2.
The first doped monocrystalline silicon layer and the first insulating layer 2 are patterned to the remaining substrate 1, i.e. the surface of the remaining substrate 1 is exposed, forming an initial via 5. The diameter of the initial via 5 is larger than the dimension of the first doped monocrystalline silicon layer in the second horizontal direction X2, which is also understood to mean that the diameter of the initial via 5 is larger than the width of the first doped monocrystalline silicon layer.
Setting the diameter of the initial via 5 to be larger than the width of the first doped monocrystalline silicon can ensure that the first source-drain layer 302 formed in the subsequent process is located at opposite sides of the first channel 601, and avoid source-drain interconnection in the first source-drain layer 302.
D6: a second polysilicon layer 6 and a first gate dielectric layer 211 are sequentially formed on the inner wall of the initial via hole 5.
D7: the second polysilicon layer 6 is heat treated to form a first channel 601.
D8: the first gate electrode 212 is filled in the initial via hole 5 in which the first gate dielectric layer 211 is formed, and the first gate electrode 212 and the first gate dielectric layer 211 form a first gate portion 21.
The process in D6 to D8 in this embodiment may be the same as B6 to B8 in the above embodiment, and will not be described here again. After the above process, the first gate portion 21, the first channel 601 surrounding the first gate portion 21, and the first source-drain layer 302 located at opposite sides of the first channel 601 are formed as a first transistor, which may be one of an N-type transistor and a P-type transistor.
The above-described different embodiments can form the first transistor, and those skilled in the art may choose according to practical situations, which are not particularly limited herein.
S413: an isolation layer 7 having a first via hole 9 is formed on the first channel 601 and the first source-drain layer 302, the first via hole 9 corresponding to the first gate portion 21 in the vertical direction Y.
Specifically, S413 includes the following contents E1 to E2.
E1: an isolation layer 7 is formed on the first gate portion 21, the first channel 601, the first source-drain layer 302, and the first insulating layer 2.
After the formation of the first transistor, an isolation layer 7 is deposited over the first transistor to isolate the first transistor from a subsequently formed second transistor. Specifically, as shown in fig. 15, 16a and 16b, the isolation layer 7 may be formed on the first insulating layer 2 and the first transistor using a deposition process.
In some embodiments, the material of the isolation layer 7 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.
E2: the isolation layer 7 is patterned to the first gate portion 21, forming the first via hole 9.
As shown in fig. 17, 18a and 18b, a first mask layer 8 having a first via pattern is formed on the isolation layer 7, and an edge of the first via pattern is aligned with an outer edge of the first gate dielectric layer 211 in the vertical direction Y. As shown in fig. 19, 20a and 20b, the isolation layer 7 is patterned to form the first via hole 9, and the first via hole 9 corresponds to the first gate portion 21 in the vertical direction Y, exposing the first gate 212 and the first gate dielectric layer 211.
Of course, after patterning the isolation layer 7, the first via hole 9 may also expose the first channel 601, after which an insulating layer is formed over the first channel 601 in the first via hole 9. The material of the insulating layer may be the same as or different from that of the insulating layer 7, and the thinner insulating layer is formed alone, so that the insulating layer is denser, which is beneficial to forming the second gate dielectric layer 221 in the subsequent process.
S414: a second gate portion 22 is formed in the first via hole 9.
Specifically, S414 includes the following contents F1 to F2.
F1: a second gate dielectric layer 221 is formed on the inner wall of the first via hole 9.
As shown in fig. 21, 22a and 22b, a second gate dielectric layer 221 may be formed on the inner wall of the first via hole 9 and the isolation layer 7 using a deposition process.
F2: the second gate electrode 222 is filled in the first via hole 9 in which the second gate dielectric layer 221 is formed, and the second gate dielectric layer 221 and the second gate electrode 222 form the second gate electrode portion 22.
As shown in fig. 23, 24a and 24b, the first via hole 9 where the second gate dielectric layer 221 is formed is filled with the second gate electrode 222 using a deposition process. The second gate dielectric layer 221 and the second gate electrode 222 located on the surface of the isolation layer 7 may be removed by using a chemical mechanical polishing process, and the top surfaces of the second gate dielectric layer 221 and the second gate electrode 222 in the first via hole 9 may be flush with the top surface of the isolation layer 7. The second gate dielectric layer 221 and the second gate 222 are formed as the second gate portion 22. The second gate portion 22 is connected to the first gate portion 21 and subsequently to the third gate portion 23 of the second transistor to form the gate structure 20.
In some embodiments, the second gate dielectric layer 221 may be the same as the first gate dielectric layer 211, and the second gate 222 may be the same as the first gate 212, so as to avoid material replacement during the manufacturing process, simplify the process, and save cost.
S415: forming a third gate portion 23 on the second gate portion 22, and forming a second channel 1501 surrounding the third gate portion 23 and second source-drain layers 1202 located at opposite sides of the second channel 1501 on the isolation layer 7, forming a second transistor; one of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor.
Specifically, S415 may include the following contents G1 to G8.
G1: a second insulating layer 10 is formed on the isolation layer 7 and on the second gate portion 22.
In some embodiments, as shown in fig. 25, 26a and 26b, the second insulating layer 10 may be formed using a deposition process, and a material of the second insulating layer 10 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the second insulating layer 10 may be the same as that of the first insulating layer 2, avoiding material replacement in the manufacturing process, thereby simplifying the process and saving costs.
And G2: a second trench 1001 extending in the first horizontal direction X1 is formed in the second insulating layer 10, exposing the second gate electrode 222.
As shown in fig. 25, 26a and 26b, a second mask layer 11 of a second trench pattern extending in the first horizontal direction X1 may be formed on the second insulating layer 10, and as shown in fig. 27, 28a and 28b, the second insulating layer 10 may be etched using the second mask layer 11, and a second trench 1001 may be formed in the second insulating layer 10, exposing the second gate electrode 222.
And G3: the second trench 1001 is filled with a third polysilicon layer 12.
As shown in fig. 29, 30a and 30b, a third polysilicon layer 12 may be deposited in the second trench 1001 using a deposition process, the third polysilicon layer 12 filling the first trench 201. After forming the third polysilicon layer 12, the third polysilicon layer 12 higher than the surface of the second insulating layer 10 may be removed using a chemical mechanical polishing process such that the top surface of the third polysilicon layer 12 is flush with the top surface of the second insulating layer 10.
And G4: the third doped polysilicon layer 1201 is formed by doping the third polysilicon layer 12 with the other of the N-type doping ion and the P-type doping ion.
As shown in fig. 30a and 30b, the third polysilicon layer 12 is used to form the source and drain of the second transistor, and thus the third polysilicon layer 12 needs to be doped. If the second transistor is an N-type transistor, the third polysilicon layer 12 may be N-doped, the dopant may be phosphorus (P) or arsenic (As), and if the second transistor is a P-type transistor, the third polysilicon layer 12 may be P-doped, the dopant may be boron (B) or gallium (Ga). The doping may be performed by an ion implantation process or a thermal diffusion process, and is not particularly limited herein.
And G5: the third doped polysilicon layer 1201 and the second insulating layer 10 are patterned to the second gate portion 22 and the isolation layer 7, forming a second via hole 14, the diameter of the second via hole 14 being larger than the size of the third doped polysilicon layer 1201 in the second horizontal direction X2.
As shown in fig. 31, 32a and 32b, a third mask layer 13 having a second via pattern is formed on the second insulating layer 10 and the third doped polysilicon layer 1201, and the second insulating layer 10 and the third doped polysilicon layer 1201 are patterned using the third mask layer 13.
As shown in fig. 33, 34a and 34b, the third doped polysilicon layer 1201 and the second insulating layer 10 are patterned to the second gate portion 22 and the isolation layer 7, forming the second via hole 14. The diameter of the second via 14 is larger than the dimension of the third doped polysilicon layer 1201 in the second horizontal direction X2, which is also understood as the diameter of the second via 14 being larger than the width of the third doped polysilicon layer 1201.
Setting the diameter of the second through hole 14 to be larger than the width of the third doped polysilicon can ensure that the second source-drain layer 1202 formed in the subsequent process is located at two opposite sides of the second channel 1501, avoiding source-drain interconnection in the second source-drain layer 1202.
G6: a fourth polysilicon layer 15 and a third gate dielectric layer 231 are sequentially formed on the inner wall of the second via hole 14.
As shown in fig. 35, 36a and 36b, a fourth polysilicon layer 15 may be formed on the inner wall of the second via hole 14, the second insulating layer 10 and the third doped polysilicon layer 1201 using a deposition process, a third gate dielectric layer 231 may be formed on the fourth polysilicon layer 15, i.e., the fourth polysilicon layer 15 surrounds the third gate dielectric layer 231, and then the fourth polysilicon layer 15 and the third gate dielectric layer 231 on the second insulating layer 10 and the third doped polysilicon layer 1201 may be removed using a chemical mechanical polishing process, leaving only the fourth polysilicon layer 15 and the third gate dielectric layer 231 on the inner wall of the second via hole 14.
And G7: the second via hole 14 having the third gate dielectric layer 231 formed therein is filled with the third gate electrode 232, and the third gate electrode 232 and the third gate dielectric layer 231 form the third gate portion 23.
As shown in fig. 37, 38a and 38b, the second via hole 14 formed with the third gate dielectric layer 231 may be filled with the third gate electrode 232 using a deposition process. For the third gate electrode 232 that is higher than the surface of the second insulating layer 10 and is deposited on the surface of the second insulating layer 10, the third gate electrode 232 on the surface of the second insulating layer 10 may be removed by a chemical mechanical polishing process after the deposition process is completed, and the top surface of the third gate electrode 232 in the second via hole 14 may be treated to be flush with the surface of the second insulating layer 10. The third gate 232 and the third gate dielectric layer 231 form the third gate portion 23.
In some embodiments, the material of the third gate 232 may include at least one of polysilicon, tungsten, aluminum, copper, titanium nitride, tantalum nitride, and silicide, which is not limited herein. The material of the third gate 232 may be the same as the material of the first gate 212 and the second gate 222, and the material of the third gate dielectric layer 231 may be the same as the material of the first gate dielectric layer 211 and the second gate dielectric layer 221, so as to avoid material replacement in the preparation process, simplify the process, and save the cost.
G8: the third doped polysilicon layer 1201 and the fourth polysilicon layer 15 are heat treated to form a second source drain layer 1202 and a second channel 1501, respectively.
As shown in fig. 39, 40a and 40b, the third doped polysilicon layer 1201 and the fourth polysilicon layer 15 are heat treated so that the polysilicon is formed as single crystal silicon, that is, the third doped polysilicon layer 1201 is formed as a third doped single crystal silicon layer and further formed as the second source drain layer 1202, and the fourth polysilicon layer 15 is formed as a fourth single crystal silicon layer and further formed as the second channel 1501.
In some embodiments, the temperature of the heat treatment is 900 to 1200 ℃, specifically, in addition to the above two end values, the temperature of the heat treatment may be 950 ℃, 1000 ℃, 1050 ℃, 1100 ℃, 1150 ℃, and the person skilled in the art may adjust the temperature according to the actual situation, and the present invention is not limited thereto.
Alternatively, G8 may be performed first, and G7 may be performed after that, that is, the third doped polysilicon layer 1201 and the fourth polysilicon layer 15 are subjected to heat treatment to form the second source/drain layer 1202 and the second channel 1501, respectively, and then the third gate 232 is filled into the second via hole 14 formed with the third gate dielectric layer 231, so that the third gate 232 and the third gate dielectric layer 231 form the third gate portion 23. Those skilled in the art can choose according to the actual circumstances, and are not particularly limited herein.
As shown in fig. 40a and 40b, after the above process, the third gate portion 23, the second channel 1501 surrounding the third gate portion 23, and the second source-drain layer 1202 located at opposite sides of the second channel 1501 are formed as a second transistor, which may be one of an N-type transistor and a P-type transistor. The embodiment of the disclosure provides a channel surrounding grid structure, which realizes that the NMOS and the PMOS share the grid and the channel in the same area, and realizes that the NMOS and the PMOS work respectively by adjusting the voltage of each end, thereby effectively halving the occupied area of the transistor, doubling the area density and further breaking through the limit of moore's law.
In summary, in the transistor structure manufactured by the manufacturing method of the embodiment of the present disclosure, the first transistor and the second transistor are distributed in the vertical direction Y and share the same gate structure 20, so that the first transistor and the second transistor are prevented from being placed side by side in the horizontal direction, the occupied area is reduced by half, the density of the transistor structure is doubled, and the electrical performance of the transistor structure is improved.
It is to be understood that the disclosure is not limited in its application to the details of construction and the arrangement of components set forth in the disclosure. The disclosure is capable of other embodiments and of being practiced and carried out in various ways. The foregoing variations and modifications are within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined herein extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for carrying out the disclosure and will enable those skilled in the art to utilize the disclosure.

Claims (11)

1. A transistor structure, comprising:
a substrate;
the grid structure is arranged on the substrate and is provided with a first grid part, a second grid part and a third grid part which are sequentially arranged in the direction vertical to and far away from the substrate;
a first channel arranged on the substrate and surrounding the outer surface of the first grid part;
the first source-drain electrode layer is arranged on the substrate and connected with two opposite sides of the first channel;
The isolation layer is covered on the first channel and the first source-drain electrode layer and surrounds the outer surface of the second grid electrode part;
the second channel is arranged on the isolation layer and surrounds the outer surface of the third grid part;
the second source-drain electrode layer is arranged on the isolation layer and connected with two opposite sides of the second channel;
wherein the first gate portion, the first channel, and the first source drain layer of the gate structure constitute a first transistor, and the third gate portion, the second channel, and the second source drain layer of the gate structure constitute a second transistor;
one of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor.
2. The transistor structure of claim 1, wherein the gate structure comprises a gate and a gate dielectric layer surrounding an outer surface of the gate.
3. The transistor structure of claim 1, wherein the first source-drain layer comprises a first source portion and a first drain portion, the first source portion connecting one side of the first channel and the first drain portion connecting an opposite side of the first channel;
The second source-drain layer comprises a second source electrode part and a second drain electrode part, wherein the second source electrode part is connected with one side of the second channel, and the second drain electrode part is connected with the opposite side of the second channel.
4. A method of fabricating a transistor structure, comprising:
providing a substrate;
forming a first gate part, a first channel surrounding the first gate part and first source-drain electrode layers positioned on two opposite sides of the first channel on the substrate to form a first transistor;
forming an isolation layer having a first via on the first channel and the first source-drain layer, the first via corresponding to the first gate portion in a vertical direction;
forming a second gate portion in the first via hole;
forming a third gate part on the second gate part, forming a second channel surrounding the third gate part and second source-drain layers positioned on two opposite sides of the second channel on the isolation layer, and forming a second transistor; one of the first transistor and the second transistor is an N-type transistor, and the other is a P-type transistor.
5. The method of claim 4, wherein forming a first gate portion, a first channel surrounding the first gate portion, and first source-drain layers on opposite sides of the first channel on the substrate, forming a first transistor, comprises:
Forming a first insulating layer on the substrate;
forming a first trench extending in a first horizontal direction in the first insulating layer;
forming a first polysilicon layer in the first trench;
doping one of N-type doping ions and P-type doping ions into the first polysilicon layer to form a first doped polysilicon layer;
patterning the first doped polysilicon layer and the first insulating layer to the substrate to form an initial through hole, wherein the diameter of the initial through hole is larger than the dimension of the first doped polysilicon layer in a second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction;
sequentially forming a second polysilicon layer and a first gate dielectric layer on the inner wall of the initial through hole;
heat treating the first doped polysilicon layer and the second polysilicon layer to form a first source drain layer and a first channel respectively;
and filling a first grid electrode in the initial through hole formed with the first grid dielectric layer, wherein the first grid electrode and the first grid dielectric layer form the first grid electrode part.
6. The method of claim 4, wherein forming a first gate portion, a first channel surrounding the first gate portion, and first source-drain layers on opposite sides of the first channel on the substrate, forming a first transistor, comprises:
Forming a first insulating layer on the substrate;
forming a first trench extending in a first horizontal direction in the first insulating layer;
epitaxially growing a first monocrystalline silicon layer in the first trench;
doping one of N-type doping ions and P-type doping ions into the first monocrystalline silicon layer to form a first doped monocrystalline silicon layer;
patterning the first doped monocrystalline silicon layer and the first insulating layer to the substrate to form an initial through hole, wherein the first doped monocrystalline silicon layer is formed into the first source-drain electrode layer, the diameter of the initial through hole is larger than the dimension of the first doped monocrystalline silicon layer in a second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction;
sequentially forming a second polysilicon layer and a first gate dielectric layer on the inner wall of the initial through hole;
heat treating the second polysilicon layer to form a first channel;
and filling a first grid electrode into the initial through hole formed with the first grid dielectric layer, wherein the first grid electrode and the first grid dielectric layer form the first grid electrode part.
7. The method of claim 4, wherein forming a first gate portion, a first channel surrounding the first gate portion, and first source-drain layers on opposite sides of the first channel on the substrate, forming a first transistor, comprises:
Forming a first trench extending in a first horizontal direction in the substrate;
forming a first polysilicon layer in the first trench;
doping one of N-type doping ions and P-type doping ions into the first polysilicon layer to form a first doped polysilicon layer;
removing the parts of the substrate positioned at the two sides of the first doped polysilicon layer, so that the first doped polysilicon layer protrudes out of the rest of the substrate;
forming a first insulating layer on the rest of the substrate on two sides of the first doped polysilicon layer, wherein the top surface of the first insulating layer is flush with the top surface of the first doped polysilicon layer;
patterning the first doped polysilicon layer and the first insulating layer to the rest of the substrate surface to form an initial through hole, wherein the diameter of the initial through hole is larger than the dimension of the first doped polysilicon layer in a second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction;
sequentially forming a second polysilicon layer and a first gate dielectric layer on the inner wall of the initial through hole;
heat treating the first doped polysilicon layer and the second polysilicon layer to form a first source drain layer and a first channel respectively;
And filling a first grid electrode in the initial through hole formed with the first grid dielectric layer, wherein the first grid electrode and the first grid dielectric layer form the first grid electrode part.
8. The method of any of claims 5 to 7, wherein forming an isolation layer with a first via over the first channel and the first source drain layer comprises:
forming an isolation layer on the first gate portion, the first channel, the first source-drain layer, and the first insulating layer;
and patterning the isolation layer to the first grid electrode part to form the first through hole.
9. The method of claim 4, wherein forming a second gate portion in the first via comprises:
forming a second gate dielectric layer on the inner wall of the first through hole;
and filling a second grid electrode in the first through hole formed with the second grid dielectric layer, wherein the second grid dielectric layer and the second grid electrode form the second grid electrode part.
10. The method of claim 9, wherein forming a third gate portion on the second gate portion and forming a second channel surrounding the third gate portion and second source-drain layers on opposite sides of the second channel on the spacer layer, forming a second transistor, comprises:
Forming a second insulating layer on the isolation layer and on the second gate portion;
forming a second trench extending in the first horizontal direction in the second insulating layer to expose the second gate electrode;
filling a third polysilicon layer in the second groove;
doping the other of the N-type doping ions and the P-type doping ions into the third polysilicon layer to form a third doped polysilicon layer;
patterning the third doped polysilicon layer and the second insulating layer to the second gate portion and the isolation layer to form a second via hole, the diameter of the second via hole being larger than the dimension of the third doped polysilicon layer in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction;
sequentially forming a fourth polysilicon layer and a third gate dielectric layer on the inner wall of the second through hole;
filling a third grid electrode in the second through hole formed with the third grid dielectric layer, wherein the third grid electrode and the third grid dielectric layer form a third grid electrode part;
and thermally treating the third doped polysilicon layer and the fourth polysilicon layer to form a second source-drain electrode layer and a second channel respectively.
11. The method according to any one of claims 5 to 7 and 10, wherein the temperature of the heat treatment is 900-1200 ℃.
CN202310692215.3A 2023-06-09 2023-06-09 Transistor structure and preparation method thereof Pending CN116705797A (en)

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