CN116702666A - IP verification method and device and electronic equipment - Google Patents
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Abstract
The present application relates to the field of integrated circuits, and in particular, to an IP verification method, apparatus, and electronic device. The IP verification method comprises the following steps: determining a target program corresponding to the IP verification service, wherein the IP verification service at least comprises function verification and problem analysis, and the target program is written by a script language in a preset format; sequentially executing each program instruction in the target program; when the program interrupt mode is single instruction interrupt, executing a single program instruction in the target program, and triggering interrupt when executing and completing one program instruction; or when the program interrupt mode is offset instruction interrupt, triggering interrupt when the offset instruction in the execution target program reaches N instruction offsets. Based on the method, verification of each IP core is achieved through running the target program written by the script language with the preset format, and the method is efficient and quick.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to an IP verification method, apparatus, and electronic device.
Background
With the continuous development and popularization of modern electronic technologies, system On Chip (SOC) designs are more and more complex and functions are more and more, so that the number and complexity of intellectual property (Intellectual Property, IP) cores required for implementing these functions are gradually increased, and accordingly, the difficulty of verifying each IP core is gradually increased.
At this stage, the IP core is designed mainly by integrated circuit (integrated circuit, IC) designers. When the design of the IP core is completed, a software person writes a verification program corresponding to the IP core, wherein the verification program mainly comprises a Field programmable gate array (Field-Programmable Gate Array, FPGA) verification program and a simulation program. Finally, the software personnel verify the IP core based on the FPGA verification program, and the IC designer verifies the IP core based on the simulation program.
In the process, when the software personnel write the verification program corresponding to the IP core, the software personnel are not familiar with the related knowledge of the IP core, so that the IP core designed by the IC designer is not understood, and further the IP core verification work is difficult to be efficiently completed.
Disclosure of Invention
The application provides an IP verification method, an IP verification device and electronic equipment, which realize verification of each IP core by running a target program written by a script language with a preset format, and are efficient and quick.
In a first aspect, the present application provides an IP verification method, the method comprising:
determining a target program corresponding to an IP verification service, wherein the IP verification service at least comprises function verification and problem analysis, and the target program is written by a script language in a preset format;
when the running mode of the target program is the debugging mode, judging the interrupt mode of the current running
When the interrupt mode is single instruction interrupt, executing a single instruction in the target program, and triggering interrupt when executing one single instruction;
when the interrupt mode is offset instruction interrupt, triggering interrupt when the offset instructions in the execution target program reach N, wherein N is an integer greater than or equal to 2.
By the method, the target program written by the script language with the preset format is operated, so that function verification and problem analysis of each IP core are realized, the problem that the IP core verification efficiency is reduced because software staff is not familiar with the related knowledge of the IP core is avoided, and the method is efficient and quick.
In one possible design, before the determining the target program corresponding to the IP verification service, the method further includes:
before executing the IP verification service, loading a first preset program into a memory;
and configuring a first preset program instruction starting address for the IPTC to obtain the target program.
By the method, the IP verification process can be controlled based on the start address of the preset program configuration instruction, and the IP verification efficiency is improved.
In one possible design, the executing each single instruction in the target program and triggering an interrupt when the execution of the single instruction is completed includes:
loading the target program into a first preset memory;
executing each single instruction in the first preset memory, and triggering an interrupt when the execution of the single instruction is completed.
In one possible design, the loading the target program into the first preset memory includes:
burning the target program in a second preset storage space;
reading the target program from the second preset storage space and loading the target program into the first preset memory; and/or
Downloading the target program into the first preset memory through preset software; and/or
And reading the target program into the first preset memory through a preset peripheral interface.
By the method, the target program for IP core verification is loaded into the preset memory, so that the IP core verification service can be conveniently unfolded in the later period.
In one possible design, the triggering an interrupt when the execution of the offset instruction in the target program reaches N includes:
judging whether to trigger interruption when the instruction execution is completed;
if no interrupt is triggered, judging whether the instruction triggers an offset instruction or not;
if the offset instruction is triggered, judging whether the execution number of the offset instruction reaches N;
if the execution number of the offset instruction reaches N, triggering an interrupt;
if the execution number of the offset instruction does not reach N, continuing to execute the instruction.
By the method, interruption in the execution process of the target program is processed, and the control of the IP verification flow is realized.
In a second aspect, the present application provides an IP verification apparatus, the apparatus comprising:
the IP verification system comprises a determination IP module and a verification module, wherein the determination IP module is used for determining a target program corresponding to an IP verification service, the IP verification service at least comprises function verification and problem analysis, and the target program is written by a script language in a preset format;
the interrupt processing module is used for judging the currently operated interrupt mode when the operation mode of the target program is a debugging mode; the processing module is used for executing a single instruction in the target program when the interrupt mode is single instruction interrupt, and triggering interrupt when the execution of one single instruction is completed; when the interrupt mode is offset instruction interrupt, triggering interrupt when the offset instructions in the execution target program reach N, wherein N is an integer greater than or equal to 2.
In one possible design, the interrupt module is specifically configured to:
judging whether to trigger interruption when the instruction execution is completed;
if no interrupt is triggered, judging whether the instruction triggers an offset instruction or not;
if the offset instruction is triggered, judging whether the execution number of the offset instruction reaches N;
if the execution number of the offset instruction reaches N, triggering an interrupt;
if the number of execution of the offset instruction does not reach N, continuing to determine the number of execution of the offset instruction. In a third aspect, the present application provides an electronic device, comprising:
a memory for storing a computer program;
and the processor is used for realizing the steps of the IP verification method when executing the computer program stored in the memory.
In a fourth aspect, the present application provides a computer readable storage medium having stored therein a computer program which when executed by a processor implements the above-described IP verification method steps.
Based on the IP verification method, the function verification and the problem analysis of each IP core are realized by executing the target program written by the script language with the preset format, and the problem that the IP verification efficiency is reduced because software staff is not familiar with the related knowledge of the IP core is avoided.
The technical effects of each of the second to fourth aspects and the technical effects that may be achieved by each aspect are described above with reference to the first aspect or the technical effects that may be achieved by each possible aspect in the first aspect, and the description is not repeated here.
Drawings
FIG. 1 is a flow chart of an IP verification method provided by the application;
fig. 2 is a schematic diagram of a functional module for implementing an IP verification service according to the present application;
fig. 3 is a schematic structural diagram of an IP verification apparatus according to the present application;
fig. 4 is a schematic structural diagram of an electronic device according to the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings. The specific method of operation in the method embodiment may also be applied to the device embodiment or the system embodiment. In the description of the present application, "a plurality of" means "at least two". "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. A is connected with B, and can be represented as follows: both cases of direct connection of A and B and connection of A and B through C. In addition, in the description of the present application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not be construed as indicating or implying a relative importance or order.
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
At present, when a software person writes a verification program corresponding to an IP core, the software person is not familiar with the related knowledge of the IP core and does not understand the IP core designed by IC design personnel, so that the IP core verification work is difficult to be efficiently completed.
In order to solve the problems, the embodiment of the application realizes the function verification and problem analysis of each IP core through the target program written by the script language running the preset format, thereby avoiding the reduction of the IP verification efficiency because software staff is not familiar with the related knowledge of the IP core, and being efficient and quick. The method and the device according to the embodiments of the present application are based on the same technical concept, and because the principles of the problems solved by the method and the device are similar, the embodiments of the device and the method can be referred to each other, and the repetition is not repeated.
As shown in fig. 1, a flowchart of an IP verification method provided by the present application specifically includes the following steps:
s11, determining a target program corresponding to the IP verification service;
in the embodiment of the application, the IP verification service at least comprises function verification and problem analysis, wherein the function verification comprises all function verification and part of function verification. The completion of the IP core verification service is mainly completed based on the target program and the execution of the IP core.
In the above process, the target program is written by a scripting language T language in a preset format, and each T language instruction corresponding to the scripting language in the preset format is composed of 12 bytes of bytes, and at least includes functions of waiting and delaying, and functions of returning, setting a register value and the like, so that the IP verification work is more accurate and efficient. The executing IP core is used for running the target program, so that the IP core verification service is realized.
As shown in fig. 2, a schematic diagram of a functional module for implementing an IP verification service mainly includes:
a central processing unit (Central Processing Unit/Processor, CPU) module, at least comprising a CPU core;
a digital signal processing (Digital Signal Process, DSP) module, primarily for implementing high-speed digital signal processing functions;
the direct memory access (Direct Memory Access, DMA) host Master module can effectively replace loading and storing instructions of a CPU, and improves the parallel processing capacity of the system;
the ITPC module is used for executing the IP core in the embodiment of the application, analyzing the verification script program of the Memory and realizing verification of other IP cores, such as DSP, DMAMaster, memory and other IP cores;
the high-speed bus Cross Bar module is mainly used for meeting the bandwidth requirement between the CPU and the memory; a system bus (Advanced High performance Bus, AHB) -peripheral bus (Advanced Peripheral Bus, APB) primarily to enable bridging between high-speed buses and low-speed devices;
memory, mainly implementing Memory functions, including Double Data Rate (DDR), synchronous dynamic random access Memory (synchronous dynamic random-access Memory, SDRAM), etc.;
the AHB IP1 module is an optional IP core such as USB, SDIO and the like which is mounted on the high-speed bus;
the AHB IPn module is an optional IP core mounted on the high-speed bus;
a universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART) module for serial communication IP core;
TIMER is a TIMER IP core;
I2C module, a simple low-speed bus;
the watchdog module Watch Dog is used for resetting a System On Chip (SOC) when the System does not work normally;
a General-purpose input/output (GPIO) module is mainly used for inputting and outputting signals or simulating specific devices.
Based on the above functional module, before the IP verification service is started, the power is first turned on for the IP verification system, and then, CPU initialization, double Data Rate (DDR) initialization, system initialization, and IP core initialization are completed. After the above-mentioned initialization processes are completed, if the IP verification service is to be started, the target program corresponding to the IP verification service is first determined, specifically:
before executing the IP verification service, loading a first preset program into a memory, wherein the first preset program is a script language T language with a specific format, and configuring a first preset program configuration instruction starting address T instruction Addr for IPTC according to different IP core service types to obtain a target program.
For example, when the IP core service type is full function verification or problem analysis, the instruction start address is a first instruction in a first preset program; when the IP core service type is partial function verification, the instruction starting address is an instruction in the middle position in the first preset program, and finally, according to the instruction starting position, the target program can be determined in the first preset program.
Alternatively, a single instruction interrupt may be set to the target program and/or an instruction interrupt offset may be set to the target program.
S12, judging the running mode of the target application program;
after the target application program is started, the operation mode corresponding to the target application program is first determined, in this embodiment of the present application, the operation mode corresponding to the target application program may be a normal mode and a debug mode, and if the operation mode of the target application program is the normal mode, step S13 is executed. If the running mode of the target application is the debug mode, step S14 is executed.
S13, gradually executing the program instruction until the execution of the program instruction is finished.
S14, judging an interruption mode of the current operation;
in the embodiment of the application, different interrupt modes are set in the system, and after the system runs the IP verification function, the system can select the different interrupt modes to realize the interrupt. In the embodiment of the application, two different interrupt modes are provided, one interrupt mode is single instruction interrupt, and the other interrupt mode is offset instruction interrupt. If the current operation is a single instruction interrupt, step S15 is executed, and if the current operation is an offset instruction interrupt, step S16 is executed.
S15, when the interrupt mode is single instruction interrupt, executing a program instruction in the target program, and triggering interrupt when executing and completing one program instruction;
after the target program corresponding to the IP verification service is obtained, a Start register corresponding to the IP verification service can be configured. Then, the target program is loaded into a first preset storage space, in this embodiment of the present application, the first preset storage space may be a double rate Synchronous Dynamic Random Access Memory (SDRAM), or may be other storage devices, and the method for loading the target program is not specifically limited herein:
the target program is burnt in a second preset storage space, and in the embodiment of the application, the second preset storage space can be a FLASH memory, or can be other memory or external memory equipment, and is not particularly limited herein; then, reading a target program from a second preset storage space and loading the target program into the first preset storage space; and/or
The target program is downloaded to the first preset storage space through preset software, and in the embodiment of the application, the preset software can be simulation software of a connection test group (JointTestActionGroup, JTAG) or simulation software of other interface forms, and is not particularly limited herein; and/or
The target program is read into the first preset storage space through a preset peripheral interface, and in the embodiment of the application, the preset peripheral interface can be a peripheral interface such as a universal asynchronous receiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART), a universal serial bus (Universal Serial Bus, USB) or the like.
After the target program is loaded into the first preset storage space by the method, further, executing a program instruction corresponding to the target program in the first preset storage space, triggering an interrupt by the system after execution of one program instruction is completed, and displaying the IP state of each current module after triggering the interrupt, so that a user performs expansion operation in the interrupt, such as checking a module or external input that a certain IP cannot be connected to IPTC, checking the running state of the system, and the like. Through the mode, IP verification can be realized.
S16, when the interrupt mode is offset instruction interrupt, when the offset instructions in the execution target program reach N, the interrupt is triggered.
In the process of executing each program instruction corresponding to the target program in the first preset storage space, if the current program instruction is an offset instruction, interrupt processing is required to be performed on the IP verification service, specifically:
judging whether the current program instruction triggers single instruction interrupt or not;
if the single instruction interrupt is not triggered, judging whether the current instruction triggers an offset instruction or not;
if the single instruction interrupt is triggered, after the interrupt processing is carried out on the IP verification service, the IP core is configured to execute continuously, and whether the current instruction triggers an offset instruction is judged;
after the target program is loaded into the first preset memory by the method, further, executing the offset instruction corresponding to the target program in the first preset memory, and triggering the interrupt by the system after the offset instruction in the target program is executed for N.
For example, the Offset instruction is an Offset instruction. The Offset instruction interrupts, i.e., counts each time an Offset instruction is executed, when a set amount is reached, an interrupt occurs. For example, if the offset is set to 8, an interrupt occurs when the 8 th offset instruction is executed. In the embodiment of the present application, the offset may be set according to an actual application scenario, for example, set to 5/9/12/33/45/99, which is 6 offset interrupts.
By the method, the target program written by the script language with the preset format is operated, so that function verification and problem analysis of each IP core are realized, the problem that the IP core verification efficiency is reduced because software staff is not familiar with the related knowledge of the IP core is avoided, and the method is efficient and quick.
Based on the same inventive concept, the present application also provides an IP verification apparatus, as shown in fig. 3, which is a schematic structural diagram of an IP verification apparatus in the embodiment of the present application, including:
the determining IP module 31 is configured to determine an object program corresponding to an IP verification service, where the IP verification service includes at least function verification and problem analysis, and the object program is written in a scripting language with a preset format;
an interrupt processing module 32, configured to determine an interrupt mode of current operation when the operation mode of the target program is a debug mode; the processing module 33 is configured to execute a single instruction in the target program when the interrupt mode is a single instruction interrupt, and trigger an interrupt when executing one of the single instructions; when the interrupt mode is offset instruction interrupt, triggering interrupt when the offset instructions in the execution target program reach N, wherein N is an integer greater than or equal to 2.
In one possible design, the apparatus further comprises:
the loading module is used for loading a first preset program into the memory before the IP verification service is executed;
and the configuration module is used for configuring an instruction starting address for the first preset program to obtain the target program.
In one possible design, the processing module 32 is specifically configured to load the target program into a first preset storage space;
executing each program instruction in the first preset storage space, and triggering an interrupt when the execution of the program instruction is completed.
In one possible design, the processing module 32 is specifically configured to:
loading the target program into a first preset storage space;
and executing each program instruction corresponding to the target program in the first preset storage space in sequence.
In one possible design, the interrupt module 32 is further configured to:
judging whether to trigger interruption when the program instruction execution is completed;
if no interrupt is triggered, judging whether the program instruction triggers an offset instruction or not;
if the offset instruction is triggered, judging whether the execution number of the offset instruction reaches N;
if the execution number of the offset instruction reaches N, triggering an interrupt;
if the number of execution of the offset instruction does not reach N, continuing to determine the number of execution of the offset instruction.
In one possible design, the interrupt module 32 is further configured to:
judging whether the current instruction is an ending instruction or not;
if yes, stopping the IP verification service;
if not, continuing to execute the next program instruction. Through the device, the target program written by the script language with the preset format is operated, so that function verification and problem analysis on each IP core are realized, the problem that the IP core verification efficiency is reduced because software staff is not familiar with the related knowledge of the IP core is avoided, and the device is efficient and quick.
Based on the same inventive concept, the embodiment of the present application further provides an electronic device, where the electronic device may implement the function of the IP verification apparatus, and referring to fig. 4, the electronic device includes:
at least one processor 41, and a memory 42 connected to the at least one processor 41, the specific connection medium between the processor 41 and the memory 42 is not limited in the embodiment of the present application, and the connection between the processor 41 and the memory 42 through the bus 40 is exemplified in fig. 4. The connection between the other components of bus 40 is shown in bold lines in fig. 4, and is merely illustrative and not limiting. The bus 40 may be divided into an address bus, a data bus, a control bus, etc., and is represented by only one thick line in fig. 4 for convenience of illustration, but does not represent only one bus or one type of bus. Alternatively, the processor 41 may be referred to as a controller, and the names are not limited.
In the embodiment of the present application, the memory 42 stores instructions executable by the at least one processor 41, and the at least one processor 41 can perform the IP verification method as previously discussed by executing the instructions stored in the memory 42. The processor 41 may implement the functions of the respective modules in the apparatus shown in fig. 3.
The processor 41 is a control center of the apparatus, and various interfaces and lines can be used to connect various parts of the entire control device, and by executing or executing instructions stored in the memory 42 and invoking data stored in the memory 42, various functions of the apparatus and processing data, thereby performing overall monitoring of the apparatus.
In one possible design, processor 41 may include one or more processing units, and processor 41 may integrate an application processor and a modem processor, wherein the application processor primarily processes operating systems, user interfaces, application programs, and the like, and the modem processor primarily processes wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 41. In some embodiments, processor 41 and memory 42 may be implemented on the same chip, and in some embodiments they may be implemented separately on separate chips.
The processor 41 may be a general-purpose processor such as a Central Processing Unit (CPU), digital signal processor, application specific integrated circuit, field programmable gate array or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, and may implement or perform the methods, steps and logic blocks disclosed in embodiments of the application. The general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the IP verification method disclosed in connection with the embodiments of the present application may be directly embodied in a hardware processor for execution, or may be executed in a combination of hardware and software modules in the processor.
The memory 42 is used as a non-volatile computer readable storage medium for storing non-volatile software programs, non-volatile computer executable programs, and modules. The Memory 42 may include at least one type of storage medium, and may include, for example, flash Memory, hard disk, multimedia card, card Memory, random access Memory (Random Access Memory, RAM), static random access Memory (Static Random Access Memory, SRAM), programmable Read-Only Memory (Programmable Read Only Memory, PROM), read-Only Memory (ROM), charged erasable programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), magnetic Memory, magnetic disk, optical disk, and the like. Memory 42 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The memory 42 in embodiments of the present application may also be circuitry or any other device capable of performing memory functions for storing program instructions and/or data.
By programming the processor 41, the code corresponding to the IP verification method described in the foregoing embodiment can be cured into the chip, so that the chip can execute the steps of the IP verification method of the embodiment shown in fig. 1 at runtime. How to design and program the processor 41 is a technique well known to those skilled in the art, and will not be described in detail herein.
Based on the same inventive concept, embodiments of the present application also provide a storage medium storing computer instructions that, when run on a computer, cause the computer to perform the IP verification method as previously discussed.
In some possible embodiments, aspects of the IP verification method provided by the present application may also be implemented in the form of a program product comprising program code for causing the control apparatus to carry out the steps in the IP verification method according to the various exemplary embodiments of the application as described in the present specification when the program product is run on a device.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A method of IP verification, the method comprising:
determining a target program corresponding to an IP verification service, wherein the IP verification service at least comprises function verification and problem analysis, and the target program is written by a script language in a preset format;
when the running mode of the target program is a debugging mode, judging an interruption mode of current running;
when the interrupt mode is single instruction interrupt, executing a single instruction in the target program, and triggering interrupt when executing one single instruction;
when the interrupt mode is offset instruction interrupt, triggering interrupt when the offset instructions in the execution target program reach N, wherein N is an integer greater than or equal to 2.
2. The method of claim 1, further comprising, prior to said determining the target program to which the IP verification service corresponds:
before executing the IP verification service, loading a first preset program into a memory;
and configuring a first preset program instruction starting address for IPTC to obtain the target program.
3. The method of claim 1, wherein the executing each single instruction in the target program and triggering an interrupt when single instruction execution is complete comprises:
loading the target program into a first preset memory;
executing each single instruction in the first preset memory, and triggering an interrupt when the execution of the program instruction is completed.
4. The method of claim 3, wherein loading the target program into the first predetermined memory comprises:
burning the target program in a second preset storage space;
reading the target program from the second preset storage space and loading the target program into the first preset memory; and/or
Downloading the target program into the first preset memory through preset software; and/or
And reading the target program into the first preset memory through a preset peripheral interface.
5. The method of claim 1, wherein triggering an interrupt when the execution of the offset instructions in the target program reaches N comprises:
judging whether to trigger interruption when the instruction execution is completed;
if no interrupt is triggered, judging whether the instruction triggers an offset instruction or not;
if the offset instruction is triggered, judging whether the execution number of the offset instruction reaches N;
if the execution number of the offset instruction reaches N, triggering an interrupt;
if the execution number of the offset instruction does not reach N, continuing to execute the instruction.
6. The method of claim 1, wherein after the triggering an interrupt, the method further comprises:
judging whether the current instruction is an ending instruction or not;
if yes, stopping the IP verification service;
if not, continuing to execute the next instruction.
7. An IP verification apparatus, the apparatus comprising:
the IP verification system comprises a determination IP module and a verification module, wherein the determination IP module is used for determining a target program corresponding to an IP verification service, the IP verification service at least comprises function verification and problem analysis, and the target program is written by a script language in a preset format;
the interrupt processing module is used for judging the currently operated interrupt mode when the operation mode of the target program is a debugging mode;
the processing module is used for executing a single instruction in the target program when the interrupt mode is single instruction interrupt, and triggering interrupt when the execution of one single instruction is completed; when the interrupt mode is offset instruction interrupt, triggering interrupt when the offset instructions in the execution target program reach N, wherein N is an integer greater than or equal to 2.
8. The apparatus of claim 7, wherein the interrupt module is specifically configured to:
judging whether to trigger interruption when the instruction execution is completed;
if no interrupt is triggered, judging whether the instruction triggers an offset instruction or not;
if the offset instruction is triggered, judging whether the execution number of the offset instruction reaches N;
if the execution number of the offset instruction reaches N, triggering an interrupt;
if the number of execution of the offset instruction does not reach N, continuing to determine the number of execution of the offset instruction.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for carrying out the method steps of any one of claims 1-6 when executing a computer program stored on said memory.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored therein a computer program which, when executed by a processor, implements the method steps of any of claims 1-6.
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