CN116686431A - Ferroelectric Random Access Memory (FRAM) capacitor and method of construction - Google Patents

Abstract

The application provides Ferroelectric Random Access Memory (FRAM) capacitors and methods of forming FRAM capacitors. The FRAM capacitor may be formed between adjacent metal interconnect layers or between a silicided active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The FRAM capacitor may be formed by a damascene process that includes forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode, forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element. The FRAM capacitor may form a component of a FRAM memory cell. For example, a FRAM memory cell may include one FRAM capacitor and one transistor (1T 1C configuration) or two FRAM capacitors and two transistors (2T 2C configuration).

Description

Ferroelectric Random Access Memory (FRAM) capacitor and method of construction

Related patent application

The present application claims priority from commonly owned U.S. provisional patent application 63/208,531 filed on 6/9 of 2021, the entire contents of which are hereby incorporated by reference for all purposes.

Technical Field

The present disclosure relates to non-volatile memory (NVM), and more particularly to Ferroelectric Random Access Memory (FRAM) capacitors and methods of construction and FRAM memory cells including FRAM capacitors.

Background

Nonvolatile memory (NVM) refers to memory that can hold data without external power supply. NVM is useful for many applications, for example as a microcontroller component. In contrast, a Static Random Access Memory (SRAM), which is typically composed of six transistors, requires external power to hold data. Similarly, dynamic Random Access Memory (DRAM), which typically includes one transistor and one capacitor, also requires external power to hold and refresh data.

Currently, the most common form of NVM is flash memory, which includes floating gate based memory cells. NOR-type flash memory is generally used to store codes, while NAND-type flash memory is generally used to store data. However, flash memory has various limitations and drawbacks. For example, it is difficult to continue to reduce the critical dimensions of flash memory. In addition, flash memory typically requires high voltages (typically about 20V) for programming and erasing. In addition, adding flash memory cells to a typical CMOS process flow as an embedded memory requires several additional photomask layers, e.g., 5 or more mask layers. This adds significantly to the cost of flash memory in embedded applications.

Accordingly, other types of NVM memories have been developed in recent years, including Ferroelectric Random Access Memories (FRAMs). The FRAM memory cell includes at least one transistor and at least one capacitor ("FRAM capacitor"). Typical FRAM memory cells are constructed of either a 1T1C (one transistor, one capacitor) architecture including a transistor (e.g., a metal oxide semiconductor field effect transistor, or MOSFET) and a FRAM capacitor or a 2T2C (two transistor, two capacitor) architecture including two transistors (e.g., MOSFET) and two FRAM capacitors.

FRAM capacitors include a ferroelectric element disposed between two electrodes, thereby defining a capacitor having an electrode-ferroelectric element-electrode structure, referred to herein as an EFE structure. The ferroelectric element comprises a crystal that can be spontaneously polarized to one of two defined states by an external electric field and can be polarized to the other of the two defined states by reversing the external electric field. The polarization state is maintained (i.e., the non-volatile data storage device is defined) after the external electric field is removed. The change in polarization state does not involve atomic collisions; thus, FRAM memory cells typically exhibit high read and write speeds, ultra-low power consumption, and nearly infinite write cycles. FRAM memory is therefore particularly suited to storage device memory in certain systems, such as for frequent reading and writing of data between different subsystems.

In addition, FRAM has unique advantages for Microcontroller (MCU) applications. For example, FRAM generally does not require high voltage devices, uses significantly less power, can provide faster write performance, and can provide greater maximum read/write endurance than flash memory.

However, typical FRAM capacitors have various drawbacks or disadvantages. For example, some FRAM capacitor constructions require at least two additional mask layers compared to the relevant background integrated circuit fabrication processes. Also, some FRAM capacitors are formed as stacked capacitors, which are often difficult to etch. For example, conventional Reactive Ion Etching (RIE) may not be suitable because the noble metals typically used for both the top and bottom electrodes of FRAM capacitors are not reactive and the vapor pressure of the by-products from the ferroelectric material is extremely low. Thus, it may be desirable to employ physically assisted RIE by using an argon mixed etching gas, which generally poses a significant challenge for etching chamber maintenance. Moreover, FRAM capacitors may be subject to the risk of hydrogen exposure, as hydrogen reacts with ferroelectric materials, which may result in a permanent decrease in their polarization capability.

There is a need to construct FRAM capacitors that reduce or eliminate any one or more of the above-described drawbacks and challenges. There is a need to construct FRAM capacitors at lower cost (e.g., by reducing or eliminating the added masking layer) and with improved manufacturing processes (e.g., by eliminating the above-described extraneous electrode metal etch).

Disclosure of Invention

The present disclosure provides FRAM capacitors and methods of construction, and FRAM memory cells including FRAM capacitors. As used herein, FRAM capacitor refers to a capacitor formed from ferroelectric elements. The FRAM capacitor may include an electrode-ferroelectric element-electrode or "EFE" structure formed between adjacent metal interconnect layers or between an active layer (e.g., including MOSFET devices) and a first metal interconnect layer. The EFE structure of the FRAM capacitor may be formed by a damascene process including forming a tub opening in a dielectric region, forming a cup-shaped bottom electrode in the tub opening, forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode, and forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element. In some embodiments, the cup-shaped bottom electrode may be formed simultaneously with at least one interconnect via, for example, by depositing tungsten or other conformal metal into a corresponding opening formed in the dielectric region. In some examples, the FRAM capacitor may be formed without adding any photomask process to the background integrated circuit fabrication process (e.g., a typical CMOS fabrication process).

One aspect provides a method of forming an integrated circuit structure that includes a FRAM capacitor. The method comprises the following steps: forming a tub opening in the dielectric region; forming a cup-shaped bottom electrode in the tub opening; forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode; forming a top electrode in an interior opening defined by the cup-shaped ferroelectric element; and forming an upper metal layer over the dielectric region, the upper metal layer including a capacitor contact in conductive contact with the top electrode. The cup-shaped bottom electrode, cup-shaped ferroelectric element, and top electrode define the FRAM capacitor.

In some examples, the FRAM capacitor is formed by a damascene process. The FRAM capacitor may be formed without adding any photomask process to the background integrated circuit fabrication process.

In one example, the method includes forming a cup-shaped bottom electrode contact in the tub opening and forming a cup-shaped bottom electrode in an interior opening defined by the cup-shaped bottom electrode contact. In one example, the method includes depositing a conformal metal to simultaneously form (a) the cup-shaped bottom electrode contact in the tub opening and (b) a via in a via opening in the dielectric region spaced apart from the tub opening. In one example, forming the upper metal layer over the dielectric region includes simultaneously forming the capacitor contact in contact with the top electrode and an upper interconnect element in contact with the via.

In one example, a top surface of the cup-shaped ferroelectric element is planarized with a top surface of the dielectric region prior to forming the upper metal layer over the dielectric region, and a diffusion barrier layer is deposited to cover the planarized top surface of the cup-shaped ferroelectric element.

In one example, a top surface of the cup-shaped bottom electrode, a top surface of the cup-shaped ferroelectric element, and a top surface of the top electrode are planarized before forming the upper metal layer over the dielectric region, and a diffusion barrier layer is deposited to cover the planarized top surfaces of the cup-shaped bottom electrode, the cup-shaped ferroelectric element, and the top electrode.

In one example, the top electrode is cup-shaped, and the method includes forming a top electrode contact in an interior volume defined by the cup-shaped top electrode, and the capacitor contact is formed in conductive contact with the top electrode contact.

In some examples, each of the bottom electrode and the top electrode includes at least one noble metal. For example, each of the bottom electrode and the top electrode may include iridium or platinum. In one example, each of the bottom electrode and the top electrode includes iridium and iridium oxide.

In one example, the ferroelectric element includes lead zirconate titanate (PZT). In other examples, the ferroelectric element includes strontium bismuth tantalate niobate (SBNT), strontium Bismuth Tantalate (SBT), or lanthanum-substituted bismuth titanate (BLT).

Another aspect provides an integrated circuit structure comprising: a dielectric region including a tub opening; a FRAM capacitor formed in the tub opening; and an upper metal layer formed over the FRAM capacitor. The FRAM capacitor includes a cup-shaped bottom electrode, a cup-shaped ferroelectric element, and a top electrode. The upper metal layer formed over the dielectric region may include a capacitor contact in conductive contact with the top electrode of the FRAM capacitor.

In one example, the dielectric region is formed over the lower metal interconnect layer, and the upper metal layer includes the upper metal interconnect layer.

In one example, the dielectric region is formed over a transistor including a doped source region and a doped drain region, and the cup-shaped bottom electrode is conductively coupled to the doped source region or the doped drain region of the transistor.

In some examples, the integrated circuit structure includes a cup-shaped bottom electrode contact formed on a silicide region on a top side of the doped source region or the doped drain region of the transistor, wherein the cup-shaped bottom electrode is formed on the cup-shaped bottom electrode contact. In one example, the upper metal layer includes a metal-1 interconnect layer.

In one example, the top electrode is cup-shaped, the integrated circuit structure includes a top electrode contact formed at least partially in an interior volume defined by the cup-shaped top electrode, and the capacitor contact is in conductive contact with the top electrode contact for conductive contact with the top electrode.

In one example, the integrated circuit structure includes a via formed in a via opening laterally spaced from the tub opening in the dielectric region, and the upper metal layer includes an interconnect element in contact with the via.

Another aspect provides a Ferroelectric Random Access Memory (FRAM) memory cell comprising (a) a transistor comprising a gate, a doped source region, and a doped drain region; and (b) a FRAM capacitor coupled to the transistor and including a cup-shaped bottom electrode, a cup-shaped ferroelectric element formed in an interior opening defined by the cup-shaped bottom electrode, and a top electrode formed in an interior opening defined by the cup-shaped ferroelectric element.

In one example, the FRAM capacitor includes a cup-shaped bottom electrode contact formed on a silicide region on a top side of the doped source or drain region of the transistor, and the cup-shaped bottom electrode is formed in an interior volume defined by the cup-shaped bottom electrode contact.

In one example, the FRAM capacitor includes a cup-shaped bottom electrode contact formed on a lower interconnect element of a metal interconnect layer, and the cup-shaped bottom electrode is formed in an interior volume defined by the cup-shaped bottom electrode contact.

In one example, the FRAM capacitor is formed in a common via layer having at least one interconnect via or contact via.

In one example, the FRAM memory cell has a transistor-capacitor (1T 1C) configuration. As another example, the FRAM memory cell has a transistor-two capacitor (2T 2C) configuration that includes the transistor, an additional transistor, the FRAM capacitor, and an additional FRAM capacitor.

Drawings

Example aspects of the disclosure are described below in conjunction with the following drawings, in which:

FIG. 1A illustrates an exemplary integrated circuit structure including an exemplary FRAM capacitor and an exemplary interconnect structure formed between two metal interconnect layers;

FIG. 1B illustrates an exemplary integrated circuit structure including an exemplary FRAM capacitor formed between two metal interconnect layers;

FIGS. 2A-2I illustrate an exemplary process for forming the integrated circuit structure shown in FIG. 1A, including an exemplary FRAM capacitor and an exemplary interconnect structure;

FIG. 3 illustrates an exemplary integrated circuit structure including the exemplary FRAM capacitor of FIG. 1A or FIG. 1B formed between a silicided active region including a MOSFET transistor and a first metal interconnect layer;

FIG. 4A illustrates an exemplary FRAM memory cell having a 1T1C architecture including one transistor (e.g., MOSFET) and one FRAM capacitor as disclosed herein; and is also provided with

Fig. 4B illustrates an exemplary FRAM memory cell having a 2T2C architecture including two transistors (e.g., MOSFETs) and two FRAM capacitors as disclosed herein.

It will be appreciated that the reference numerals of any illustrated element appearing in a plurality of different figures have the same meaning in the plurality of figures, and that any illustrated element mentioned or discussed herein in the context of any particular figure is also applicable to every other figure (if any), where the same illustrated element is shown.

Detailed Description

The present disclosure provides Ferroelectric Random Access Memory (FRAM) capacitors and methods of construction, and FRAM memory cells including FRAM capacitors. The FRAM capacitor may include a capacitor formed on two metal layers (e.g., lower metal layer M _x And an upper metal layer M _x+1 ) A cup-shaped "electrode-ferroelectric element-electrode" or "EFE" structure in between. In contrast to the background CMOS fabrication process, such FRAM capacitors may be formed according to the present disclosure without any added masking layers.

As used herein, for example, in the lower metal layer M _x And an upper metal layer M _x+1 In the context of (a), "metal layer" may include any metal layer or metallization layer including:

(a) Metal interconnect layers, e.g. comprising copper, aluminum or other metals formed by damascene processes or deposited by subtractive patterning processes such as deposition, patterning and etching of metal layers, or

(b) Including a plurality of silicided structures (having a structure with a metal silicide layer formed thereon), such as silicided source regions, drain regions, or polysilicon gates of MOSFETs.

For example, FRAM capacitors may be constructed at any depth in the integrated circuit structure at two adjacent metal interconnect layers M _x And M is as follows _x+1 Between them. As another example, FRAM capacitors may be constructed on silicided active regions, particularly on silicon transistors having a metal silicide layer formed on selected transistor elements, and under a first metal interconnect layer (commonly referred to as metal-1); in such an example, the silicided active region defines a lower metal layer M _x Where x=0 (i.e., M ₀ ) And the first metal interconnection layer (metal-1) defines an upper metal layer M _x+1 (i.e., M ₁ )。

In some examples, at least one component of the FRAM capacitor may be formed simultaneously with certain interconnect structures (e.g., interconnect vias) separate from the FRAM capacitor. For example, a cup-shaped bottom electrode contact of a FRAM capacitor may be formed simultaneously with an interconnect via by depositing a conformal metal layer (e.g., tungsten or cobalt) into the respective openings for the cup-shaped bottom electrode and the interconnect via. For example, fig. 1A, 2A-2I, and 3 illustrate an exemplary FRAM capacitor formed simultaneously with an interconnect via.

In other examples, FRAM capacitors may be formed differently (i.e., not simultaneously) than interconnect structures (e.g., interconnect vias). For example, fig. 1B shows a FRAM capacitor formed differently (not simultaneously) with an interconnect via. The exemplary FRAM capacitor shown in fig. 3 may be similarly formed differently (not simultaneously) than an interconnect structure (e.g., an interconnect via).

As discussed below with reference to fig. 2A-2I, in some examples, FRAM capacitors may be constructed without adding any masking operations to the background integrated circuit fabrication process. FRAM capacitors may be built using a damascene process, which may avoid plasma etching problems associated with some conventional FRAM capacitor manufacturing processes. In some examples, the FRAM capacitor may be surrounded by a hydrogen diffusion barrier, e.g., to protect the ferroelectric material from degradation caused by hydrogen exposure.

FIG. 1A shows a capacitor 102 including an exemplary FRAM capacitorAnd an exemplary integrated circuit structure 100a of an interconnect structure 104. FRAM capacitor 102 is formed on lower metal layer M _x And upper layer M _x+1 Between them. In the example shown in fig. 1A (and fig. 2A to 2I), the lower metal layer M _x And an upper metal layer M _x+1 Is two adjacent metal interconnect layers such that FRAM capacitor 102 is formed at two adjacent metal interconnect layers M _x And M is as follows _x+1 Between via layers V _x Is a kind of medium. In other examples, FRAM capacitor 102 is formed in a silicided active region (comprising one or more silicon-based transistors including a silicided structure), M, for example, as shown in fig. 3, discussed below ₀ Interconnect with metal layer M ₁ (commonly referred to as metal-1) via layer V ₀ (commonly referred to as a contact layer). Through-hole layer V _x Various conductive structures formed in inter-metal dielectric (IMD) regions 108, such as oxide regions, may be included.

As shown in fig. 1A, the interconnect structure 104 may include a metal layer M formed on a lower portion _x (e.g., where x=0 for the silicided active layer as discussed above) lower interconnect element 110 in and formed in upper metal layer M _x+1 Upper interconnect element 160 in (e.g., metal-1) and is formed in via layer V by depositing a conformal metal (e.g., tungsten or cobalt) into the respective via openings 115 _x Is connected to the lower interconnect element 110. Each of the lower and upper interconnecting elements 110, 160 may include wires or other laterally elongated structures (e.g., elongated in the y-axis direction), or discrete pads (e.g., having a square, circular, or substantially square or circular shape in the x-y plane), or any other suitable shape and structure.

FRAM capacitor 102 includes a capacitor formed in via layer V _x A three-dimensional (3D) electrode-ferroelectric element-electrode (EFE) structure 126 in the barrel opening 113. The 3D EFE structure 126 includes (a) a cup-shaped bottom electrode 132 formed in an interior opening 131 defined by the cup-shaped bottom electrode contact 130, (b) a cup-shaped ferroelectric element 134 formed in an interior opening 133 defined by the cup-shaped bottom electrode 132, and (c) a cup-shaped ferroelectric element 134 formed in an interior defined by the cup-shaped ferroelectric element 134A top electrode 136 in the opening 135. Cup-shaped bottom electrode contact 130 is formed on lower metal layer M _x Is in contact with the lower interconnect element 112. The lower interconnect element 112 may include conductive wires or other laterally elongated structures (e.g., elongated in the y-axis direction), or discrete pads (e.g., having a square, circular, or substantially square or circular shape in the x-y plane), or any other suitable shape and structure.

In some examples, FRAM capacitor 102 includes a cup-shaped bottom electrode contact 130, which cup-shaped bottom electrode contact 130 is formed in tub opening 113 before cup-shaped bottom electrode 132. Additionally, in some examples, top electrode 136 is formed as a cup-shaped top electrode 136, and FRAM capacitor 102 includes a top electrode contact 138 formed in an interior opening 137 defined by cup-shaped top electrode 136.

Each of the cup-shaped bottom electrode contact 130, the cup-shaped bottom electrode 132, the cup-shaped ferroelectric element 134, and the cup-shaped top electrode 136 includes a respective laterally extending base and a plurality of vertically extending sidewalls extending upwardly from the laterally extending base (e.g., four vertically extending sidewalls extending upwardly from the respective laterally extending base to define a cup-shaped structure). In some examples, the respective laterally extending base of each cup-shaped member 130, 132, 134, 136 can have a rectangular perimeter (e.g., having a square or non-square rectangular shape) that defines four lateral sides when viewed from above, with four vertically extending sidewalls extending upwardly from the perimeter of the respective laterally extending base. Due to the cup-shaped structure of the components of FRAM capacitor 102, cup-shaped bottom electrode 132 may also be referred to as an outer electrode, and top electrode 136 may also be referred to as an inner electrode.

As discussed below with reference to fig. 2A and 2B, by depositing a conformal metal (e.g., tungsten or cobalt) to the via layer V _x In the tub opening 113 and the via opening 115, the cup-shaped bottom electrode contact 130 may be formed simultaneously with the interconnection via 114. In some examples, a glue layer 142 (e.g., comprising titanium nitride (TiN)) is deposited in the tub opening 113 and the via opening 115 prior to the conformal metal to improve adhesion between the conformal metal and the IMD region 108.

In some examples, each of the cup-shaped bottom electrode 132 and the top electrode 136 may be formed of a noble metal. For example, cup-shaped bottom electrode 132 and top electrode 136 may each comprise iridium or platinum. In one example, cup-shaped bottom electrode 132 and top electrode 136 each comprise a mixture of iridium and iridium oxide.

In one example, cup-shaped ferroelectric element 134 comprises lead zirconate titanate (PZT). In other examples, cup-shaped ferroelectric element 134 includes, but is not limited to, strontium bismuth tantalate (SBNT), strontium Bismuth Tantalate (SBT), or lanthanum-substituted bismuth titanate (BLT).

The top electrode contact 138 may comprise titanium nitride (TiN), tungsten (W), or a combination thereof. In other examples, the top electrode contact 138 may include aluminum (Al), titanium (Ti), titanium Tungsten (TiW), cobalt (Co), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or any combination thereof.

A diffusion barrier 182 may be formed over FRAM capacitor 102, which may include a dielectric material such as silicon nitride (SiN), silicon carbide (SiC), or aluminum oxide (Al ₂ O ₃ ) But is not limited thereto. The diffusion barrier 182 may act as a hydrogen diffusion barrier to protect the cup-shaped ferroelectric element 134 from degradation caused by hydrogen exposure. In addition, the diffusion barrier 182 may be formed on the upper metal layer M _x+1 During the construction of (e.g. for the upper metal layer M _x+1 During damascene etching of the metal element).

At the via layer V _x (Via layer V) _x Including interconnect via 114 and 3D EFE structure 126) _x+1 ) Including capacitor contacts 158 in electrical contact with the top electrode 136 (via the top electrode contacts 138) and upper interconnect elements 160 in electrical contact with the interconnect vias 114 and thus with the lower interconnect elements 110. In some embodiments, the capacitor contacts 158 and the upper interconnect element 160 comprise damascene elements formed by a damascene process (e.g., using copper, tungsten, aluminum, or cobalt). For example, the capacitor contacts 158 and the upper interconnect element 160 may comprise copper damascene elements formed over a barrier layer 159 (e.g., a TaN/Ta bilayer).

Each of the capacitor contacts 158 and the upper interconnect element 160 may include wires or other laterally elongated structures (e.g., elongated in the y-axis direction), or discrete pads (e.g., having a square, circular, or substantially square or circular shape in the x-y plane), or any other suitable shape and structure.

Thus, according to the exemplary process described above, the 3D EFE structure 126 may be formed at the common via layer V simultaneously with the interconnect via 114 _x Is a kind of medium. In some embodiments, cup-shaped bottom electrode contact 130 may be formed simultaneously with via 114, for example, by conformal tungsten fill.

Fig. 1B illustrates an exemplary integrated circuit structure 100B including an exemplary FRAM capacitor 102, wherein a 3D EFE structure 126 is formed differently (not simultaneously) with an interconnect via. The exemplary FRAM capacitor 102 shown in fig. 3 may similarly be formed differently (not simultaneously) than an interconnect structure (e.g., an interconnect via).

Fig. 2A-2I illustrate an exemplary process for forming the integrated circuit structure 100a shown in fig. 1A, including the exemplary FRAM capacitor 102 and the exemplary interconnect structure 104 shown in fig. 1A. Those skilled in the art will recognize that the same process (without reference to interconnect structure 104) may be used to form integrated circuit structure 100B shown in fig. 1B. First, as shown in FIG. 2A, which includes a top view (x-y plane) and side-section vias (x-z plane) of the integrated circuit structure 100a formed, an inter-metal dielectric (IMD) region 108 (e.g., comprising an oxide) is formed on a lower metal layer M that includes lower interconnect elements 110 and 112 formed in dielectric region 200 _x Above. The lower interconnect elements 110 and 112 may comprise copper elements formed by a damascene process. Lower metal layer M _x The lower interconnect elements 110 and 112 of (a) may include wires or other laterally elongated structures (e.g., elongated in the y-axis direction), or discrete pads (e.g., having a square, circular, or substantially square or circular shape in the x-y plane), or any other suitable shape and structure.

A photoresist layer 202 may be deposited and patterned to form a photoresist opening, and the underlying IMD region 108 etched through the photoresist opening to form a tub opening 113 and IMD region 108 for forming the 3D EFE structure 126Through-hole openings 115 of the substrate. Fig. 2A shows one via opening 115. The via openings 115 may each have a square, circular, or other suitable shape, or, for example, wherein the width (or diameter or Critical Dimension (CD)) W, as viewed from a top view (x-y plane) _{Through hole} In the range of 0.1 μm to 0.35 μm in both the x-direction and the y-direction.

In contrast, the width W of the tub opening 113 in the x-direction _{Bucket_x} And width W in y direction _{Bucket_y} May be significantly larger than the via opening 115. The shape and size of the tub opening 113 may be selected based on various parameters, such as for efficient fabrication of the 3D EFE structure 126 and/or for desired performance characteristics of the resulting FRAM capacitor 102. In one example, the tub opening 113 may have a square or rectangular shape in the x-y plane. In other examples, the tub opening 113 may have a circular or oval shape in the x-y plane.

Width of the tub opening 113 in the x direction (W _{Bucket_x} ) Width in y direction (W _{Bucket_y} ) Or width in both x-direction and y-direction (W _{Bucket_x} And W is _{Bucket_y} ) May be substantially greater than the width W of the via opening 115 in the x-direction _{Through hole} And width W of the via opening 115 in the y direction _{Through hole} . For example, in some examples, W of drum opening 113 _{Bucket_x} And W is _{Bucket_y} Is the width W of the via opening 115 _{Through hole} Is at least twice as large. In a particular example, each width W of the tub opening 113 _{Bucket_x} And W is _{Bucket_y} Is the width W of the via opening 215 _{Through hole} Is at least five times larger. Each width (W of the tub opening 113 _{Bucket_x} And W is _{Bucket_y} ) It may be sufficient to allow FRAM capacitor 102 to be constructed within tub opening 113 by a damascene process, for example, to allow construction of (a) cup-shaped bottom electrode contact 130, (b) cup-shaped bottom electrode 132 formed in interior opening 131 of cup-shaped bottom electrode contact 130, (c) cup-shaped ferroelectric element 134 formed in interior opening 133 of cup-shaped bottom electrode 132, (d) top electrode 136 formed in interior opening 135 of cup-shaped ferroelectric element 134, and (e) top electrode contact 138 formed in interior opening 137 of top electrode 136. In some examples, W _{Bucket_x} And W is _{Bucket_y} Each in the range of 0.5 μm to 100. Mu.m, for example in the range of 0.5 μm to 10. Mu.m.

In addition, the tub opening 113 may be formed to have an aspect ratio in both the x-direction and the y-direction of less than or equal to 2.0, for example, to allow the tub opening 113 to be efficiently filled with a conformal material. For example, the tub openings 113 may be formed to have aspect ratios H each in the range of 0.1-2.0, such as in the range of 0.5-2.0 _{Barrel (barrel)} /W _{Bucket_x} And H _{Barrel (barrel)} /W _{Bucket_y} . In some examples, aspect ratio H _{Barrel (barrel)} /W _{Bucket_x} And H _{Barrel (barrel)} /W _{Bucket_y} Each less than or equal to 1.5, for example, to effectively fill the tub opening 113 with a conformal material (e.g., tungsten, cobalt, or aluminum). For example, the tub openings 113 may be formed to have aspect ratios H each in the range of 0.5-1.5, or more specifically in the range of 0.8-1.2 _{Barrel (barrel)} /W _{Bucket_x} And H _{Barrel (barrel)} /W _{Bucket_y} 。

Next, as shown in fig. 2B, photoresist layer 202 is removed and a glue layer 142 (e.g., comprising TiN) is deposited over IMD region 108 and extends down into tub opening 113 and via opening 115. The glue layer 142 may be deposited using a reactive Physical Vapor Deposition (PVD) process or a Chemical Vapor Deposition (CVD) process. In some examples, the glue layer 142 may have a thickness of 50- Within a range of (2).

A conformal metal layer 212 is then deposited over the glue layer 142 and extends down into the tub opening 113 and the via opening 115. As shown, the deposited conformal metal layer 212 (a) fills the interconnect via openings 115 to form interconnect vias 114, and (b) covers the interior surfaces of the tub openings 113 to form cup-shaped bottom electrode contacts 130 defining interior openings 131. As described above, the cup-shaped bottom electrode contact 130 includes a laterally extending bottom electrode contact cup base 230 and a plurality (in this example, four) vertically extending bottom electrode contact sidewalls 232 extending upwardly from the periphery of the laterally extending bottom electrode contact cup base 230. In some examples, conformal metal layer 212 comprises tungsten, cobalt, aluminum or is deposited asTo the point ofOther conformal metals of the thickness of (a). The conformal metal layer 212 may be deposited by a conformal Chemical Vapor Deposition (CVD) process or other suitable deposition process. The glue layer 142 (e.g., comprising TiN) may increase or enhance the adhesion of the conformal metal layer 212 to the interior surfaces of the tub opening 113 (including the vertical sidewall surfaces of the tub opening 113) to facilitate the formation of the cup-shaped bottom electrode contact 130.

Next, as shown in fig. 2C, a bottom electrode layer 220 is deposited over the conformal metal layer 212 and extends down into the tub opening 113 to define a cup-shaped bottom electrode 132 formed in the interior opening 131 of the cup-shaped bottom electrode contact 130. The cup-shaped bottom electrode 132 defines an interior opening 133. Similar to the cup-shaped bottom electrode contact 130, the cup-shaped bottom electrode 132 includes a laterally extending bottom electrode cup base and a plurality of vertically extending bottom electrode sidewalls (in this example, four sidewalls) extending upwardly from the periphery of the laterally extending bottom electrode cup base.

In some examples, the bottom electrode layer 220 may include a noble metal, such as iridium (Ir) or platinum (Pt). For example, the bottom electrode may include iridium oxide (IrO) and iridium (Ir) deposited by a PVD process to form a silicon oxide film on the bottom electrodeWithin (1), or->Within (1), or about->Is used for the layer thickness of the layer.

Next, as shown in fig. 2D, a ferroelectric layer 230 is deposited or formed over the bottom electrode layer 220 and extends down to the interior defined by the cup-shaped bottom electrode 132In the opening 133 to define a cup-shaped ferroelectric element 134 having an interior opening 135. In some examples, ferroelectric layer 230 may be deposited using Metal Organic Chemical Vapor Deposition (MOCVD). For example, ferroelectric layer 230 may include a layer deposited to have an active layerPZT (lead zirconate titanate, pbZr) of a thickness in the range of _x Ti _1-x O3). As another example, ferroelectric layer 230 may include (a) strontium bismuth niobate tantalate, srBi ₂ Nb ₂ O ₉ (SBNT), (b) strontium bismuth tantalate, sr _1-y Bi _2+x Ta ₂ O ₉ (SBT), (c) lanthanum substituted bismuth titanate, bi _4-x La _x Ti ₃ O ₁₂ (BLT), or any other suitable ferroelectric material.

Next, as shown in fig. 2E, a top electrode layer 240 may be deposited over the ferroelectric layer 230 and extend down into the interior opening 135 defined by the cup-shaped ferroelectric element 134 to define a top electrode 136 having an interior opening 137. In one example, the top electrode 136 is cup-shaped. The top electrode layer 240 may include a noble metal, such as iridium (Ir) or platinum (Pt). For example, the top electrode layer 240 may include iridium oxide (IrO) and iridium (Ir) deposited by a PVD process to form a silicon oxide film on the top electrode layer Within (1), or->Within (1), or about->Is used for the layer thickness of the layer.

Next, as shown in fig. 2F, a top electrode contact layer 250 may be deposited to form the top electrode contact 138 in the interior volume 137 defined by the top electrode 136 (e.g., cup-shaped top electrode 136). In some examples, the top electrode contact layer 250 may include titanium nitride (TiN), tungsten (W), or a combination thereof. For example, titanium nitride (TiN) may be deposited by a reactive Physical Vapor Deposition (PVD) process or a Chemical Vapor Deposition (CVD) process. For example, a CVD process may be used to deposit tungsten (W). In other examples, the top electrode contact layer 250 may include aluminum (Al), titanium (Ti), titanium Tungsten (TiW), cobalt (Co), tantalum (Ta), tantalum nitride (TaN), copper (Cu), or any combination thereof.

Next, as shown in fig. 2G, a Chemical Mechanical Planarization (CMP) process may be performed to remove portions of previously deposited layers extending outside of the tub opening 113 or the via opening 115, including the glue layer 142, the conformal metal layer 212, the bottom electrode layer 220, the ferroelectric film 230, the top electrode layer 240, and the top electrode contact layer 250 outside of the tub opening 113 or the via opening 115. As shown in fig. 2G, the CMP process effectively planarizes the top surfaces of cup-shaped bottom electrode contact 130, cup-shaped bottom electrode 132, cup-shaped ferroelectric element 134, top electrode 136, top electrode contact 138, and via 114 with surrounding IMD regions 108. The cup-shaped bottom electrode 132, cup-shaped ferroelectric element 134, and top electrode 136 collectively define the 3D EFE structure 126.

Forming FRAM capacitor 102 using such a damascene process (referred to herein as "damascene integration") allows FRAM capacitor 102 to be formed without metal etching, which may be advantageous compared to other processes for forming FRAM capacitors that require one or more metal etches. For example, during plasma etching of prior art processes, certain foreign materials such as (a) iridium (Ir) (which may be used for bottom and/or top electrodes) and (b) PZT or other exemplary ferroelectric materials forming ferroelectric elements do not form volatile byproducts (i.e., removable gaseous byproducts) in the plasma etch chamber, resulting in solid byproducts remaining in the etch chamber, which may be problematic due to particle generation and degradation of etch chamber performance (e.g., etch rate, non-uniformity within the wafer, and selectivity). The damascene integration disclosed above allows the use of foreign materials such as iridium and PZT (or other disclosed ferroelectric materials) in FRAM capacitor 102 while avoiding the problems associated with etching such materials.

Next, as shown in fig. 2H, a diffusion barrier 182 may be deposited over the integrated circuit structure 100 a. Diffusion barrier 182 may act as a hydrogen diffusion barrier To protect the cup-shaped ferroelectric element 134 from degradation caused by hydrogen exposure. Thus, the diffusion barrier 182 may completely cover the exposed top surface of the cup-shaped ferroelectric element 134. In some examples, the diffusion barrier 182 may include a thickness in the range of Within (1), e.g. in +.>Dielectric materials such as silicon nitride (SiN) or silicon carbide (SiC) within the scope of (a). In some embodiments, the diffusion barrier 182 may be deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD), high Density Plasma (HDP), or Low Pressure Chemical Vapor Deposition (LPCVD).

Furthermore, in some examples, the diffusion barrier 182 also acts as an etch barrier for damascene trench etching (e.g., cu trench etching) during formation of the overlying metal structure, as discussed below.

Next, as shown in fig. 2I, the upper metal layer M is formed, for example, by a damascene process _x+1 (including capacitor contact 158 and upper interconnect element 160) is formed over via layer Vx including via 114 and FRAM capacitor 102. In one example, an upper metal layer M _x+1 Including copper interconnect layers formed by a copper damascene process.

To form the upper metal layer M _x+1 A dielectric layer 270 is first deposited over the diffusion barrier 182. In some examples, dielectric layer 270 may include silicon oxide, FSG (fluorosilicate glass), OSG (organosilicate glass), or porous OSG. The dielectric layer 270 may be patterned and etched to form capacitor contact openings 260 over the top electrode contacts 138 and interconnect openings 262 (e.g., trench openings) over the vias 114, wherein etching proceeds through the diffusion barrier 182 through the capacitor contact openings 260 and the interconnect openings 262. Barrier layer (e.g., taN/Ta bilayer) and copper seed layer indicated at 159 May be deposited over dielectric layer 270 and extend down into etched capacitor contact openings 260 and interconnect openings 262. A copper plating process may then be performed that fills the capacitor contact openings 260 and interconnect openings 262 with copper. A copper anneal may be performed followed by a copper CMP process to remove a portion of the copper over capacitor contact opening 260 and interconnect opening 262, thereby defining capacitor contact 158 in electrical contact with top electrode contact 138 of FRAM capacitor 102 and upper interconnect element 160 in electrical contact with via 114. In other examples, other metals (other than copper) may be used to form the capacitor contacts 158 and the upper interconnect element 160, such as tungsten (W), cobalt (Co), or aluminum (Al).

Forming an upper metal layer M as discussed above _x+1 Thereafter, the process may be continued to build additional interconnect structures, for example, by building additional metal layers separated by respective dielectric layers.

Fig. 3 illustrates an exemplary integrated circuit structure 300 that includes an exemplary FRAM capacitor 102 formed over a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) 306 and an interconnect structure 304.FRAM capacitor 102 and MOSFET 306 may be components of a FRAM memory cell, such as a 1t1c FRAM memory cell (discussed below) as shown in fig. 4A or a 2t2c FRAM memory cell (discussed below) as shown in fig. 4B.

Unlike the example shown in fig. 1A and 1B, in which FRAM capacitor 102 is formed at two adjacent metal interconnect layers M _x And M is as follows _x+1 In between, in the example shown in fig. 3, FRAM capacitor 102 is formed in (a) a silicide active region M that includes silicide structures 320 (e.g., silicide transistor components) ₀ (i.e., M _x Where x=0) and (b) a first metal interconnect layer M, commonly referred to as metal-1 ₁ (i.e., M _x+1 Where x=0).

As shown in fig. 3, the active region M is silicided ₀ Including a MOSFET 306 formed on a silicon substrate 308. MOSFET 306 may include a polysilicon gate 310 formed over a silicon substrate 308 and separated from the silicon substrate by a gate oxide layer 312, and doped source and drain regions 314, 316 formed in silicon substrate 308. In this exampleThe polysilicon gate 310 and the doped drain region 316 include a silicidation structure 320. Specifically, a metal silicide layer 324 is formed on the top surface of the polysilicon gate 310, and a metal silicide layer 326 is formed on the top surface of the doped drain region 316. Metal silicide layers 324 and 326 may be includedAny suitable metal silicide layer, such as titanium silicide (TiSi 2), cobalt silicide (CoSi 2), or nickel silicide (NiSi), of a thickness within the range of (a) or other suitable thickness. For purposes of this disclosure, metal silicide layers 324 and 326 define a metal structure such that active region M is silicided ₀ May be considered a metal layer.

In the example shown in fig. 3, FRAM capacitor 102 is formed on top of doped drain region 316 on a metal silicide layer 326 that is used to provide a conductive connection between FRAM capacitor 102 and doped drain region 316. As described above, FRAM capacitor 102 is contacted from above by capacitor contact 158. In addition, vias 114 (also commonly referred to as contacts) are formed on a metal silicide layer 324 on top of the polysilicon gate 310, which is used to provide a conductive connection between the polysilicon gate 310 and the upper interconnect element 160. Although FRAM capacitor 102 is shown between doped drain region 316 and capacitor contact 158, FRAM capacitor 102 may similarly be formed between doped source region 314 and capacitor contact 158, or between polysilicon gate 310 and capacitor contact 158. The capacitor contact 158 and the upper interconnect element 160 comprise a first metal interconnect layer M formed, for example, by a damascene process ₁ Is a metal element of the group (C).

Fig. 4A shows an exemplary FRAM memory cell 400a having a 1T1C architecture including one transistor (e.g., MOSFET) 402 and one FRAM capacitor 102 (e.g., constructed as described herein). The gate of transistor 402 is connected to a word line, one end of FRAM capacitor 102 is connected to a plate line, a second end of FRAM capacitor 102 is connected to a first terminal of transistor 402, and a second terminal of transistor 402 is connected to a bit line.

Fig. 4B shows an exemplary FRAM memory cell 400B having a 2T2C architecture including two transistors (e.g., MOSFETs) 402a and 402B, each of the transistors 402a and 402B being supplied with a respective bit line, and two FRAM capacitors 102a and 102B connected to a pair of bit lines, word lines, and plate lines as described above with respect to exemplary FRAM memory cell 400 a. Each FRAM capacitor 102a and 102b may correspond to an exemplary FRAM capacitor 102 constructed as described herein above.

Claims (28)

1. A method of forming an integrated circuit structure including a ferroelectric random access memory capacitor, the method comprising:

forming a tub opening in the dielectric region;

forming a cup-shaped bottom electrode in the tub opening;

forming a cup-shaped ferroelectric element in an interior opening defined by the cup-shaped bottom electrode;

forming a top electrode in an interior opening defined by the cup-shaped ferroelectric layer; and

forming an upper metal layer over the dielectric region, the upper metal layer including a capacitor contact in conductive contact with the top electrode;

wherein the cup-shaped bottom electrode, cup-shaped ferroelectric element and top electrode define the ferroelectric random access memory capacitor.

2. The method of claim 1, wherein the ferroelectric random access memory capacitor is formed by a damascene process.

3. The method of any of claims 1-2, wherein the ferroelectric random access memory capacitor is formed without adding any photomask process to a background integrated circuit fabrication process.

4. A method according to any one of claims 1 to 3, comprising forming a cup-shaped bottom electrode contact in the tub opening; and

the cup-shaped bottom electrode is formed in an interior opening defined by the cup-shaped bottom electrode contact.

5. The method of claim 4, comprising depositing a conformal metal to simultaneously form (a) the cup-shaped bottom electrode contact in the tub opening and (b) a via in a via opening in the dielectric region spaced apart from the tub opening.

6. The method of claim 5, wherein forming the upper metal layer over the dielectric region comprises simultaneously forming the capacitor contact in contact with the top electrode and an upper interconnect element in contact with the via.

7. The method of any of claims 1-6, comprising, prior to forming the upper metal layer over the dielectric region:

planarizing a top surface of the cup-shaped ferroelectric element with a top surface of the dielectric region; and

A diffusion barrier layer is deposited to cover the planarized top surface of the cup-shaped ferroelectric element.

8. The method of any of claims 1-6, comprising, prior to forming the upper metal layer over the dielectric region:

planarizing a top surface of the cup-shaped bottom electrode, a top surface of the cup-shaped ferroelectric element, and a top surface of the top electrode; and

a diffusion barrier layer is deposited to cover the planarized top surfaces of the cup-shaped bottom electrode, the cup-shaped ferroelectric element, and the top electrode.

9. The method of any one of claims 1 to 8, wherein

The top electrode is cup-shaped;

the method includes forming a top electrode contact in an interior volume defined by the cup-shaped top electrode; and is also provided with

The capacitor contact is formed in conductive contact with the top electrode contact such that the capacitor contact is in conductive contact with the top electrode.

10. The method of any one of claims 1-9, wherein each of the bottom electrode and the top electrode comprises at least one noble metal.

11. The method of any one of claims 1-9, wherein each of the bottom electrode and the top electrode comprises iridium or platinum.

12. The method of any one of claims 1-9, wherein each of the bottom electrode and the top electrode comprises iridium and iridium oxide.

13. The method of any of claims 1-11, wherein the ferroelectric element comprises lead zirconate titanate (PZT).

14. The method of any of claims 1-13, wherein the ferroelectric element comprises strontium bismuth tantalate niobate, strontium bismuth tantalate, or lanthanum-substituted bismuth titanate.

15. An integrated circuit structure, the integrated circuit structure comprising:

a dielectric region comprising a tub opening;

a ferroelectric random access memory capacitor formed in the tub opening and comprising:

a cup-shaped bottom electrode;

a cup-shaped ferroelectric element; and

a top electrode; and

an upper metal layer over the dielectric region and including a capacitor contact in conductive contact with the top electrode.

16. The integrated circuit structure of claim 15, wherein:

the dielectric region is formed over the lower metal interconnect layer; and is also provided with

The upper metal layer includes an upper metal interconnect layer.

17. The integrated circuit structure of any of claims 15 to 16, wherein:

The dielectric region is formed over a transistor including a doped source region and a doped drain region; and is also provided with

The cup-shaped bottom electrode is conductively coupled to the doped source region or the doped drain region of the transistor.

18. The integrated circuit structure of claim 17, the integrated circuit structure comprising:

a cup-shaped bottom electrode contact formed on a silicide region on a top side of the doped source region or the doped drain region of the transistor,

wherein the cup-shaped bottom electrode is formed in an interior volume defined by the cup-shaped bottom electrode contact.

19. The integrated circuit structure of claim 17, the integrated circuit structure comprising:

a cup-shaped bottom electrode contact formed on a lower interconnect element formed in a lower metal layer,

wherein the cup-shaped bottom electrode is formed in an interior volume defined by the cup-shaped bottom electrode contact.

20. The integrated circuit structure of any of claims 17-19, wherein the upper metal layer comprises a metal-1 interconnect layer.

21. The integrated circuit structure of any of claims 15 to 20, wherein:

the top electrode is cup-shaped;

the integrated circuit structure includes a top electrode contact formed at least partially in an interior volume defined by the cup-shaped top electrode; and is also provided with

Wherein the capacitor contact is in conductive contact with the top electrode contact so as to be in conductive contact with the top electrode.

22. The integrated circuit structure of any of claims 15-21, comprising a via formed in a via opening laterally spaced from the tub opening in the dielectric region; and is also provided with

Wherein the upper metal layer includes an interconnect element in contact with the via.

23. A Ferroelectric Random Access Memory (FRAM) memory cell, the FRAM memory cell comprising:

a transistor comprising a gate, a doped source region, and a doped drain region; and

a FRAM capacitor coupled to the transistor and comprising:

a cup-shaped bottom electrode;

a cup-shaped ferroelectric element formed in an interior opening defined by the cup-shaped bottom electrode; and

A top electrode formed in an interior opening defined by the cup-shaped ferroelectric element.

24. The FRAM memory cell of claim 23, wherein:

the FRAM capacitor includes a cup-shaped bottom electrode contact formed on a silicide region on a top side of the doped source region or the doped drain region of the transistor; and is also provided with

The cup-shaped bottom electrode is formed in an interior volume defined by the cup-shaped bottom electrode contact.

25. The FRAM memory cell of any one of claims 23 to 24, wherein:

the FRAM capacitor includes a cup-shaped bottom electrode contact formed on a lower interconnect element formed in a metal interconnect layer; and is also provided with

The cup-shaped bottom electrode is formed in an interior volume defined by the cup-shaped bottom electrode contact.

26. The FRAM memory cell of any one of claims 23 to 25, wherein the FRAM capacitor is formed in a common via layer having at least one interconnect via or contact via.

27. The FRAM memory cell of any one of claims 23 to 26, wherein the FRAM memory cell has a transistor-capacitor (1T 1C) configuration in which:

The gate of the transistor is connected to a word line;

the first end of the FRAM capacitor is connected to a plate line,

a second end of the FRAM capacitor is connected to the first terminal of the transistor and a second terminal of the transistor is connected to a bit line.

28. The FRAM memory cell of any one of claims 23 to 27, wherein the FRAM memory cell has a transistor including the transistor, an additional transistor, the transistor

A two transistor capacitor (2T 2C) configuration of a FRAM capacitor and an additional FRAM capacitor, wherein:

the FRAM capacitor is connected to the transistor and the additional FRAM capacitor is connected to the additional transistor;

the gates of the transistors and the gates of the additional transistors are connected to a common word line;

the transistor is connected to a first bit line and the additional transistor is connected to a second bit line; and is also provided with

The FRAM capacitor and the additional FRAM capacitor are connected to a common plate line.