CN116684541A - Method for converting 4x3G-SDI into HDMI video signal - Google Patents
Method for converting 4x3G-SDI into HDMI video signal Download PDFInfo
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- CN116684541A CN116684541A CN202310753470.4A CN202310753470A CN116684541A CN 116684541 A CN116684541 A CN 116684541A CN 202310753470 A CN202310753470 A CN 202310753470A CN 116684541 A CN116684541 A CN 116684541A
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 63
- 230000015654 memory Effects 0.000 claims abstract description 25
- 101100498818 Arabidopsis thaliana DDR4 gene Proteins 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 abstract description 4
- 239000000872 buffer Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 5
- 238000005457 optimization Methods 0.000 description 4
- 239000003086 colorant Substances 0.000 description 2
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- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/268—Signal distribution or switching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0125—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level one of the standards being a high definition standard
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The application relates to a method for converting 4x3G-SDI into HDMI video signals, and belongs to the technical field of video signal conversion. The method for converting 4x3G-SDI into HDMI video signal comprises inputting SDI data frame into FPGA unit, wherein the SDI data frame is 3G-SDI differential signal of 4 channels; generating data in YCbCr format from SDI data frames; caching the data in the YCbCr format into an external memory; the FPGA unit reads the data in the YCbCr format in the external memory and converts the data into the data in the RGB format; and the FPGA unit performs parallel-serial conversion on the RGB format data to generate HDMI signals. The application realizes the conversion of the 4x3G-SDI video signal and the HDMI video signal by the video signal conversion system, utilizes the FPGA unit as an execution main body of the transmission buffer, the video signal type conversion, the serial-parallel conversion process and the parallel-serial conversion, has lower delay in the video signal conversion process, and simplifies the circuit structure.
Description
Technical Field
The application belongs to the technical field of video signal conversion, and particularly relates to a method for converting 4x3G-SDI into HDMI video signals.
Background
The 4x3G-SDI interface is a four-channel digital serial interface, the data transmission rate of the interface is 3Gbit per second, and the interface can support an HD signal of 60 frames per second. The HDMI interface is a high definition multimedia interface and is mostly installed on DVD players, televisions, game hosts, computers and other devices. In the field of optical-end transmission using an HDMI interface, industries such as broadcasting, video, monitoring, and the like, it is necessary to convert a 3G-SDI video signal into an HDMI video signal using a signal conversion device. In the prior art, an SDI signal is converted through an SDI-HDMI adjustable frequency converter, a video signal conversion process has time delay, and a conversion circuit structure is complex, so that signal conversion equipment has a large space occupation ratio.
Disclosure of Invention
The present application has been made to solve the above-mentioned problems, and an object of the present application is to provide a method for converting 4x3G-SDI into HDMI video signals, which reduces the delay phenomenon during the video signal conversion process and simplifies the circuit structure.
The application realizes the above purpose through the following technical scheme:
a video signal conversion system comprises an FPGA unit, an external memory and a clock circuit for providing clock signals to the FPGA unit, wherein the FPGA unit is a Zynq UltraScale+MPSoC MZU04A-4EV chip of XILINX company, and the FPGA unit comprises:
the 3G-SDI receiving module is used for receiving an SDI data frame outside the FPGA unit, generating serial data in a YCbCr format, and inputting the serial data in the YCbCr format into the external memory;
the 3G-SDI-HDMI conversion module is used for reading serial data in a YCbCr format in an external memory, carrying out serial-to-parallel conversion on the serial data, and converting the serial-to-parallel converted data into data in an RGB format, wherein YCbCr is one of color spaces and is usually used for continuous processing of images in films, or is a brightness component of colors in a digital photographic system, and Cb and Cr are concentration offset components of blue and red respectively;
and the HDMI output module is used for carrying out parallel-serial conversion on data in an RGB format to generate an HDMI signal, wherein the RGB format is a common video encoding and decoding format, and RGB is the color representing three channels of red, green and blue.
As a further optimization scheme of the application, the 3G-SDI receiving module includes 4 3G-SDI interfaces for receiving SDI data frames and a YCbCr data output module, where the 4 3G-SDI interfaces are used for receiving 3G-SDI differential signals of the 4 channels to obtain YCbCr format data, the YCbCr data output module is used for buffering the YCbCr format data into an external memory, and the external memory is 4 pieces of DDR4 memory.
As a further optimization scheme of the application, the 3G-SDI-HDMI conversion module comprises a GTX module, an SDI IP core and a signal conversion module, wherein the GTX module is a high-speed transceiver of an FPGA unit, the IP core is an independent hardware module reusable in the FPGA unit and can realize serial-parallel conversion of video signals, the GTX module is used for reading and serial-parallel converting data in a YCbCr format in an external memory, the SDI IP core is used for decoding data obtained by deserializing, solving a line field, a control signal and pixel data, transmitting the control signal to the signal conversion module, and the signal conversion module is used for converting the pixel data into data in an RGB format.
As a further optimization scheme of the application, the HDMI output module includes a differential signal-to-HDMI interface signal module, and the differential signal-to-HDMI interface signal module is configured to convert RGB format data into an HDMI signal, where the HDMI signal is a serial low voltage differential RMDS signal.
As a further optimization scheme of the application, the HDMI output module further comprises an HDMI interface and a feedback signal receiving module, the HDMI interface is electrically connected with the HDMI driving assembly, the output end of the HDMI driving assembly is connected with the input end of the display, the HDMI interface is used for transmitting HDMI signals to the HDMI driving assembly, the HDMI driving assembly is used for converting HDMI signals into analog signals, outputting the analog signals to the display, and sending feedback signals to the feedback signal receiving module, the feedback signal receiving module is used for judging whether the HDMI signals are successfully transmitted or not, the HDMI driving assembly sends feedback signals to the HDMI output module after detecting the HDMI signals, the HDMI output module sends next packet of data when receiving the feedback signals, and otherwise, the HDMI driving assembly repeatedly sends the previous packet of data.
A method for converting 4x3G-SDI into HDMI video signal, comprising the steps of:
step one: inputting an SDI data frame into the FPGA unit, wherein the SDI data frame is a 3G-SDI differential signal of 4 channels, a 3G-SDI receiving module receives the SDI data frame and generates serial data in a YCbCr format, and the 3G-SDI receiving module inputs the serial data in the YCbCr format into an external memory;
step two: reading serial data in a YCbCr format in an external memory through a 3G-SDI-HDMI conversion module, carrying out serial-parallel conversion on the serial data to obtain parallel data in the YCbCr format, and converting the parallel data into data in an RGB format;
step three: and performing parallel-to-serial conversion on the RGB format data through the HDMI output module to generate an HDMI signal.
In the second step, the 3G-SDI to HDMI module decodes the parallel data in YCbCr format, decodes the line field, the control signal and the pixel data, and converts the pixel data into RGB format data.
The application has the beneficial effects that:
1) The application realizes the conversion of the 4x3G-SDI video signal and the HDMI video signal by the video signal conversion system, and utilizes the FPGA unit as an execution main body of the transmission buffer, the video signal type conversion, the serial-parallel conversion process and the parallel-serial conversion, so that the video signal conversion process has almost no delay, the circuit structure is effectively simplified, and the space occupation ratio of the signal conversion equipment is reduced;
2) The FPGA unit further comprises an HDMI interface and a feedback signal receiving module, the HDMI interface packages HDMI signals and transmits the HDMI signals to the HDMI driving assembly, the HDMI driving assembly sends feedback signals to the feedback signal receiving module after detecting the HDMI signals, the feedback signal receiving module sends next package data when receiving the feedback signals, otherwise, the HDMI interface repeatedly sends previous package data, and the HDMI driving assembly can be ensured to successfully receive video signals.
Drawings
FIG. 1 is a system block diagram of the present application;
FIG. 2 is a flow chart of the operational state of the present application;
FIG. 3 is a schematic diagram of the 3G-SDI receiving module structure of the present application;
FIG. 4 is a schematic diagram of a 3G-SDI-to-HDMI module according to the present application;
fig. 5 is a schematic structural diagram of an HDMI output module according to the present application;
fig. 6 is a schematic structural diagram of an HDMI driving assembly according to the present application.
Detailed Description
The present application will be described in further detail with reference to the accompanying drawings, wherein it is to be understood that the following detailed description is for the purpose of further illustrating the application only and is not to be construed as limiting the scope of the application, as various insubstantial modifications and adaptations of the application to those skilled in the art can be made in light of the foregoing disclosure.
Examples
As shown in fig. 1 to 6, a method for converting 4x3G-SDI into HDMI video signals, the method realizes conversion of 4x3G-SDI video signals and HDMI video signals by a video signal conversion system, uses an FPGA unit as an execution body of a transfer buffer, video signal type conversion, serial-parallel conversion process and parallel-serial conversion, and the video signal conversion process has almost no delay, thereby effectively simplifying a circuit structure, the system includes the FPGA unit, an external memory and a clock circuit, the method specifically includes the following steps:
step one:
inputting an SDI data frame into an FPGA unit, wherein the SDI data frame is a 3G-SDI differential signal of 4 channels, the FPGA unit comprises a 3G-SDI receiving module, the 3G-SDI receiving module comprises 4 3G-SDI interfaces and a YCbCr data output module, the 4 3G-SDI interfaces are used for receiving the 3G-SDI differential signal of the 4 channels, and the resolution ratio and the refresh rate of the received video signal are 1080P@30Hz;
after the 3G-SDI interface receives the 3G-SDI differential signal, the 3G-SDI receiving module obtains the data in the YCbCr format, and buffers the data in the YCbCr format into an external memory through a YCbCr data output module, wherein YCbCr is one of color spaces and is usually used for continuous processing of images in films or in a digital photographing system, Y is the brightness component of colors, cb and Cr are the concentration offset components of blue and red respectively, the external memory is 4 DDR4 memories, DDR is a double rate synchronous dynamic random access memory, and DDR4 is a fourth generation double rate synchronous dynamic random access memory;
step two:
the method comprises the steps that in an FPGA unit, serial-to-parallel conversion is carried out on YCbCr format data, parallel data obtained after conversion are converted into RGB format data, the FPGA unit further comprises a 3G-SDI-to-HDMI module, the 3G-SDI-to-HDMI module comprises a GTX module, an SDI IP core and a signal conversion module, the GTX module is a high-speed transceiver of the FPGA unit, the IP core is a reusable independent hardware module in the FPGA unit and can realize serial-to-parallel conversion of video signals, the GTX module carries out serial-to-parallel conversion on YCbCr format data in an external memory, the SDI IP core decodes the parallel data obtained by deserializing, a line field, a control signal and pixel data are decoded, the SDI IP core transmits the control signal to the signal conversion module, the signal conversion module converts the pixel data into RGB format data, the RGB format is a common video coding and decoding format, and RGB is the color representing red, green and blue channels;
step three: the FPGA unit performs parallel-serial conversion on the RGB format data to generate an HDMI signal, the FPGA unit further comprises an HDMI output module, the HDMI output module comprises a differential signal-to-HDMI interface signal module, the differential signal-to-HDMI interface signal module converts the RGB format data into an HDMI signal, and the HDMI signal is a serial low-voltage differential RMDS signal;
further, the video signal conversion system further comprises a clock circuit, wherein clock signals are provided for the 3G-SDI receiving module, the 3G-SDI to HDMI module and the HDMI output module through the clock circuit;
further, in the third step, after the HDMI output module generates the HDMI signal, the HDMI signal is packaged and transmitted to the HDMI driving component, after the HDMI driving component detects the HDMI signal, the HDMI driving component sends a feedback signal to the HDMI output module, when the HDMI output module receives the feedback signal, the HDMI output module sends the next packet of data, otherwise, the HDMI output module repeatedly sends the previous packet of data;
the HDMI driving component performs digital-to-analog conversion on the HDMI signal to obtain an HDMI analog signal, and outputs the HDMI analog signal to the display.
Specifically, the HDMI output module of the FPGA unit further comprises an HDMI interface and a feedback signal receiving module, the HDMI interface is electrically connected with the HDMI driving component, the output end of the HDMI driving component is connected with the input end of the display, the HDMI interface packages HDMI signals and transmits the HDMI signals to the HDMI driving component, the HDMI driving component comprises an HDMI signal detection module and a feedback signal transmitting module, after the HDMI signal detection module of the HDMI driving component detects HDMI signals, the feedback signal transmitting module transmits feedback signals to the feedback signal receiving module, when the feedback signal receiving module receives the feedback signals, the HDMI interface transmits next package data, otherwise, the HDMI interface repeatedly transmits the previous package data; the HDMI driving assembly further comprises a digital-to-analog conversion module, the HDMI signal is converted into an analog signal through the digital-to-analog conversion module of the HDMI driving assembly, and the analog signal is output to the display.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application.
Claims (7)
1. A video signal conversion system, characterized by: the clock circuit comprises an FPGA unit, an external memory and a clock circuit for providing clock signals for the FPGA unit, wherein the FPGA unit comprises:
the 3G-SDI receiving module is used for receiving an SDI data frame outside the FPGA unit, generating serial data in a YCbCr format, and inputting the serial data in the YCbCr format into the external memory;
the 3G-SDI-HDMI conversion module is used for reading serial data in a YCbCr format in an external memory, carrying out serial-to-parallel conversion on the serial data, and converting the serial-to-parallel converted data into data in an RGB format; and
and the HDMI output module is used for carrying out parallel-serial conversion on the RGB format data so as to generate HDMI signals.
2. The system according to claim 1, wherein: the 3G-SDI receiving module comprises 4 3G-SDI interfaces for receiving SDI data frames and a YCbCr data output module, wherein the 4 3G-SDI interfaces are used for receiving 3G-SDI differential signals of 4 channels so as to obtain data in a YCbCr format, the YCbCr data output module is used for caching the data in the YCbCr format into an external memory, and the external memory is 4 DDR4 memories.
3. The system according to claim 1, wherein: the 3G-SDI-HDMI conversion module comprises a GTX module, an SDI IP core and a signal conversion module, wherein the GTX module is used for reading and converting the YCbCr format data in an external memory into serial and parallel data, the SDI IP core is used for decoding the data obtained by the deserialization, solving the line field, the control signal and the pixel data, transmitting the control signal to the signal conversion module, and the signal conversion module is used for converting the pixel data into the RGB format data.
4. The system according to claim 1, wherein: the HDMI output module comprises a differential signal-to-HDMI interface signal module, wherein the differential signal-to-HDMI interface signal module is used for converting RGB format data into HDMI signals, and the HDMI signals are serial low-voltage differential RMDS signals.
5. The system according to claim 1, wherein: the HDMI output module further comprises an HDMI interface and a feedback signal receiving module, the HDMI interface is electrically connected with the HDMI driving assembly, the output end of the HDMI driving assembly is connected with the input end of the display, the HDMI interface is used for transmitting HDMI signals to the HDMI driving assembly, the HDMI driving assembly is used for converting HDMI signals into analog signals, the analog signals are output to the display, the feedback signal receiving module is used for sending feedback signals to the feedback signal receiving module, and the feedback signal receiving module is used for judging whether the HDMI signals are successfully transmitted.
6. A method for converting 4x3G-SDI into HDMI video signal, comprising: a video signal conversion system as claimed in any one of claims 1 to 5, comprising the steps of:
step one: inputting an SDI data frame into the FPGA unit, wherein the SDI data frame is a 3G-SDI differential signal of 4 channels, a 3G-SDI receiving module receives the SDI data frame and generates serial data in a YCbCr format, and the 3G-SDI receiving module inputs the serial data in the YCbCr format into an external memory;
step two: reading serial data in a YCbCr format in an external memory through a 3G-SDI-HDMI conversion module, carrying out serial-parallel conversion on the serial data to obtain parallel data in the YCbCr format, and converting the parallel data into data in an RGB format;
step three: and performing parallel-to-serial conversion on the RGB format data through the HDMI output module to generate an HDMI signal.
7. The method according to claim 6, wherein: in the second step, the 3G-SDI-to-HDMI module decodes the parallel data in YCbCr format, decodes the line field, the control signal and the pixel data, and converts the pixel data into RGB format data.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310753470.4A CN116684541A (en) | 2023-06-26 | 2023-06-26 | Method for converting 4x3G-SDI into HDMI video signal |
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| CN202310753470.4A CN116684541A (en) | 2023-06-26 | 2023-06-26 | Method for converting 4x3G-SDI into HDMI video signal |
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