CN116683873B - Harmonic suppression up-converter circuit, chip and pulse generator - Google Patents
Harmonic suppression up-converter circuit, chip and pulse generator Download PDFInfo
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Abstract
The invention discloses a harmonic suppression up-converter circuit, a chip and a pulse generator, wherein the circuit inputs four groups of two intermediate frequency baseband signals with 180 DEG phase difference in each group into four buffer units respectively, each buffer unit outputs three voltage signals with 45 DEG phase difference in one group respectively, and the amplitude ratio of the three voltage signals is strictly equal to that of theoryThen, the voltage signal output from the buffer unit is up-converted by the two mixer units and output as a differential signal. Because resistor or transistor array stacking is not needed, mismatch errors caused by factors such as process, voltage and temperature PVT can be avoided, and the harmonic suppression capability of the up-converter is affected. Therefore, the invention can restrain various harmonic waves in the up-conversion signal band, and improves the harmonic wave restraining capability of the up-converter, thereby further improving the spurious-free dynamic range of the up-converter.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a harmonic suppression up-converter circuit, a chip and a pulse generator.
Background
The quantum computer is composed of a quantum chip and a control/reading system, and the control/reading system is used for controlling or reading the quantum state of the quantum bit formed on the quantum chip under low-temperature operation, so as to realize quantum calculation. Because the quantum chip needs to work in the very low temperature area in the low temperature refrigeration box, if the control/reading system needs a large amount of signal cables and is connected to the quantum chip across the temperature area, a large amount of noise is introduced and the complexity of interconnection is increased, so that the quantum computer is unreliable in work and high in manufacturing cost, and therefore, the quantum chip is placed in the 1-4K temperature area, and the integration with the same temperature area of the control/reading system is realized, so that the method becomes an important development direction of the current quantum computer.
The control system of the quantum computer is actually equivalent to a pulse generator and consists of a digital part and an analog part, wherein the digital part is formed by a digital controller through a DAC and a filter to generate a baseband signal for controlling the quantum bit; the analog part is used for converting the baseband signal into microwave pulses in a high-frequency band through an up-converter so as to generate the microwave pulses to control the quantum bit; in the control of qubits, spurious Free Dynamic Range (SFDR) of the control system is critical to low temperature quantum gate control using Frequency division multiplexing (Frequency-division multiplexing, FDM), unwanted Spurious waves can significantly reduce the fidelity of the qubit, and limited SFDR (30-40 dBc) can make the fidelity of the qubit lower than 99.99%, so in order to achieve the fidelity performance limit of the qubit of 99.99%, further improvement of the SFDR of the control system of the quantum computer is required.
At present, an effective means for improving the SFDR of a control system of a quantum computer is to improve the performance of an up-converter; the SFDR of the up-converter takes the worst local oscillation suppression, image suppression and harmonic suppression capability of stray wave suppression in the concerned frequency band; because more mature technical means exist in the prior art, the local oscillation suppression capability and the image suppression capability of the up-converter can be improved to a higher level, and the harmonic suppression capability becomes a bottleneck for limiting the SFDR of the up-converter.
Disclosure of Invention
In a first aspect of the present invention, a harmonic rejection up-converter circuit is provided that can reject harmonics in the up-converted signal band, improving the harmonic rejection capability of the up-converter, and further improving the spurious-free dynamic range of the up-converter.
In a first aspect of the present invention, there is provided a harmonic rejection up-converter circuit comprising: four buffer units and two mixing units; wherein,
the first buffer unit is configured to output three voltage signals with phases of 0 DEG, 45 DEG and 90 DEG according to two paths of baseband signals with the input phases of 180 DEG and 270 DEG respectively; the second buffer unit is configured to output three voltage signals with the phases of 90 DEG, 135 DEG and 180 DEG according to two paths of baseband signals with the input phases of 270 DEG and 360 DEG respectively; the third buffer unit is configured to output three voltage signals with phases of 180 DEG, 225 DEG and 270 DEG according to two paths of baseband signals with phases of 0 DEG and 90 DEG respectively; the fourth buffer unit is configured to output three voltage signals with the phases of 270 DEG, 315 DEG and 360 DEG respectively according to two paths of baseband signals with the input phases of 90 DEG and 180 DEG respectively;
the first mixing unit is configured to output a variable frequency signal through a first output end and a second output end of the first mixing unit according to three paths of voltage signals output by the first buffering unit, a voltage signal with the phase of 180 degrees output by the second buffering unit, two paths of voltage signals with the phases of 225 degrees and 270 degrees output by the third buffering unit and two paths of local oscillation signals with the phases of 0 degrees and 180 degrees respectively; the second mixing unit is configured to output a variable frequency signal through a first output end and a second output end of the second mixing unit according to two paths of voltage signals with phases of 90 degrees and 135 degrees respectively output by the second buffering unit, a voltage signal with a phase of 180 degrees output by the third buffering unit, three paths of voltage signals output by the fourth buffering unit and two paths of local oscillation signals with phases of 90 degrees and 270 degrees respectively input; and the variable frequency signals output by the first output end of the first frequency mixing unit and the first output end of the second frequency mixing unit are converged into one path of signal, and the variable frequency signals output by the second output end of the first frequency mixing unit and the second output end of the second frequency mixing unit are converged into the other path of signal, so that differential signal output is formed.
In some possible embodiments, the buffer unit is composed of three identical gain circuits; moreover, the gain circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; wherein the drain of the first transistor is connected to the source of the third transistor, the source thereof is grounded through a ground impedance, and the gate thereof is configured to be connected to a first bias voltage or a baseband signal; the drain electrode of the third is connected with the working voltage through load impedance, and the grid electrode of the third is configured to be connected with a second bias voltage; the drain electrode of the second transistor is connected to the source electrode of the fourth transistor, the source electrode of the second transistor is grounded through a grounding impedance, and the grid electrode of the second transistor is configured to be connected with a first bias voltage or a baseband signal; the drain electrode of the fourth transistor is connected with the working voltage through load impedance, and the grid electrode of the fourth transistor is configured to be connected with a second bias voltage; the drains of the third transistor and the fourth transistor are commonly connected to an output end of a voltage signal;
in the buffer unit, one gain circuit is configured to access the first bias voltage and the first baseband signal, one gain circuit is configured to access the first bias voltage and the second baseband signal, and one gain circuit is configured to access the first baseband signal and the second baseband signal.
In some possible embodiments, the mixing unit is composed of three identical mixing subunits; furthermore, the mixing subunit comprises: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth transistor, and a sixth transistor; wherein sources of the first and second switching transistors are commonly connected to a drain of the fifth transistor, sources of the third and fourth switching transistors are commonly connected to a drain of the sixth transistor, and drains of the first and third switching transistors are connected to a first output terminal; drains of the second switching transistor and the fourth switching transistor are connected to a second output terminal; sources of the fifth transistor and the sixth transistor are grounded;
moreover, the gates of the first switching transistor and the fourth switching transistor are configured to access the same voltage signal, and the second switching transistor and the third switching transistor are configured to access the same voltage signal, wherein the phase difference of the voltage signals accessed by the gates of the first switching transistor and the second switching transistor is 180 degrees; the grid electrode of the fifth transistor is configured to be connected with the first local oscillation signal, and the grid electrode of the sixth transistor is configured to be connected with the second local oscillation signal.
In some possible embodiments, the phase of the baseband signal is characterized as a relative phase to the absolute phase of the baseband signal; wherein the absolute phase of the baseband signal may be configured to any angle.
In some possible embodiments, the local oscillator signal has a frequency range of 4G to 12G.
In a second aspect of the present invention, there is provided a chip comprising:
a substrate; and the harmonic suppression up-converter circuit provided in the first aspect of the invention is manufactured on the substrate.
In a third aspect the invention provides a pulse generator comprising the harmonic rejection up-converter circuit provided in the first aspect of the invention or employing the chip provided in the second aspect of the invention.
Compared with the prior art, in the harmonic suppression up-converter circuit provided by the invention, four groups of two intermediate frequency baseband signals with the phase difference of 180 DEG in each group are respectively input into four buffer units, each buffer unit respectively outputs three voltage signals with the phase difference of 45 DEG in one group, and the amplitude ratio of the three voltage signals is strictly equal to that of theoryThen, the voltage signal output from the buffer unit is up-converted by the two mixer units and output as a differential signal. Because resistor or transistor array stacking is not needed, mismatch errors caused by factors such as process, voltage and temperature PVT can be avoided, and the harmonic suppression capability of the up-converter is affected. Therefore, the invention can restrain various harmonic waves in the up-conversion signal band, and improves the harmonic wave restraining capability of the up-converter, thereby further improving the spurious-free dynamic range of the up-converter.
Description of the drawings:
FIG. 1 is a schematic diagram of a harmonic rejection up-converter circuit according to the present invention;
FIG. 2 is a schematic diagram of a buffer unit in a harmonic rejection up-converter circuit according to the present invention;
FIG. 3 is a schematic diagram of a mixer unit in a harmonic rejection up-converter circuit according to the present invention;
FIG. 4 is a simulation plot of various types of harmonic rejection for a harmonic rejection up-converter circuit of the present invention at room temperature;
FIG. 5 is a simulation plot of various types of harmonic rejection at low temperature for a harmonic rejection up-converter circuit of the present invention;
fig. 6 is a schematic structural diagram of a pulse generator according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings and specific examples. It should not be construed that the scope of the above subject matter of the present invention is limited to the following embodiments, and all techniques realized based on the present invention are within the scope of the present invention.
As shown in fig. 1, the harmonic-rejection up-converter circuit of the present invention includes: four Buffer units Buffer 1-Buffer 4 and two Mixer units Mixer1, mixer2.
Wherein the first Buffer unit Buffer1 is configured to output a baseband signal I with an input phase of 180 DEG BB,- And a baseband signal Q with a phase of 270 DEG BB,- And outputs three voltage signals with phases of 0 DEG, 45 DEG and 90 DEG respectively; the second Buffer unit Buffer2 is configured to output a baseband signal Q with an input phase of 270 DEG BB,- And a baseband signal I with a phase of 360 DEG BB,+ And outputs three voltage signals with phases of 90 DEG, 135 DEG and 180 DEG respectively; the third Buffer unit Buffer3 is configured to input a baseband signal with a phase of 0 degree (a baseband signal with a phase of 0 degree and a baseband signal I with a phase of 360 degrees) BB,+ Equivalent) and a baseband signal Q with a phase of 90 deg BB,+ And outputs three voltage signals with phases of 180 DEG, 225 DEG and 270 DEG respectively; the fourth Buffer unit Buffer4 is configured to output a baseband signal Q with an input phase of 90 DEG BB,+ And a baseband signal I with a phase of 180 DEG BB,- Three voltage signals with the phases of 270 DEG, 315 DEG and 360 DEG are output; in addition, the amplitude ratio of the three voltage signals output by the four Buffer units Buffer 1-Buffer 4 is strictly equal to the theoretical value
Through four Buffer units Buffer 1-BufferAfter er4 generates 12 voltage signals in total, the first Mixer1 is configured to output two voltage signals with phases of 180 ° and 225 ° and 270 ° respectively according to the three voltage signals output by the first Buffer unit Buffer1, the voltage signal with phase of 180 ° output by the second Buffer unit Buffer2, the two voltage signals with phase of 0 ° output by the third Buffer unit Buffer3, and the local oscillator signal I with phase of 0 ° input LO,+ And a local oscillation signal I with 180 DEG phase LO,- And outputs a frequency conversion signal through the first output end and the second output end respectively; the second mixing unit Mixer2 is configured to output three voltage signals with phases of 90 degrees and 135 degrees according to the two voltage signals output by the second Buffer unit Buffer2, the voltage signal with a phase of 180 degrees output by the third Buffer unit Buffer3, the three voltage signals output by the fourth Buffer unit Buffer4, and the input local oscillation signal Q with a phase of 90 degrees LO,+ And local oscillation signal Q with 270 DEG phase LO,- And outputs a frequency conversion signal through the first output end and the second output end respectively; the variable frequency signals output by the first output end of the first frequency mixing unit and the first output end of the second frequency mixing unit are converged into one path of signal to be output through the OUTN, and the variable frequency signals output by the second output end of the first frequency mixing unit and the second output end of the second frequency mixing unit are converged into the other path of signal to be output so as to form differential signal output.
Specifically, as shown in fig. 2, four Buffer units Buffer1 to Buffer4 have the same circuit structure, and in the present invention, the circuit structure of each Buffer unit is composed of three identical gain circuits; taking the first Buffer unit Buffer1 as an example, it has three identical gain circuits 100a, 100b and 100c; taking the gain circuit 100a as an example, it includes: a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4; wherein the drain of the first transistor M1 is connected to the source of the third transistor M3, the source thereof is grounded through a ground resistance Rs, and the gate thereof is configured to be connected to the first bias voltage VB1; the third drain passes through the load impedance R L The grid electrode of the working voltage is connected with a second bias voltage VB2; the drain of the second transistor M2 is connected to the fourthThe source of transistor M4, whose source is grounded via ground impedance Rs, and whose gate is configured to access baseband signal I with 180 DEG phase BB,- The method comprises the steps of carrying out a first treatment on the surface of the The drain of the fourth transistor M4 passes through the load impedance R L The grid electrode of the working voltage is connected with a second bias voltage VB2; the drains of the third transistor M1 and the fourth transistor M2 are commonly connected to an output terminal of a voltage signal, that is, a voltage signal if_0 having a phase of 0 °. Similarly, the gain circuit 100b differs from the gain circuit 100a in that: the first transistor in gain circuit 100b has access to a 180 baseband signal I BB,- The fourth transistor is connected to the baseband signal Q with 270 DEG phase BB,- And outputs a voltage signal if_45 having a phase of 45 °; the difference between the gain circuit 100c and the gain circuit 100a is that: the first transistor in the gain circuit 100c is connected to the baseband signal Q with a phase of 270 deg BB,- The method comprises the steps of carrying out a first treatment on the surface of the The fourth transistor is connected to the first bias voltage VB1 and outputs a voltage signal IF_90 with a phase of 90 degrees.
Thus, in the buffer unit of the present invention, one of the gain circuits is configured to access the first bias voltage and the first baseband signal, one of the gain circuits is configured to access the first bias voltage and the second baseband signal, and one of the gain circuits is configured to access the first baseband signal and the second baseband signal.
In fact, since the gain circuit in the buffer unit of the present invention adopts the Casecode structure, in which Rs is used as the source load impedance, it can play a role of good linearity, all input signals assume that the amplitude is 1, and the baseband signal I BB,- Is 180 DEG, VB2 is a constant bias voltage, and the current signal is applied to the load impedance R L The voltage signal is converted into a voltage signal to be output; the circuit mirror side has the same circuit structure and the baseband signal Q BB,- The phase of (2) is 270 DEG amplitude coincident with 180 DEG; because the local oscillator with the Casecode structure has a 180-degree phase inversion function, the local oscillator inputs a baseband signal I BB,- The output voltage phase is flipped to 0 °; at baseband signal Q BB,- The output voltage phase is inverted to 90 DEG, since the two are the same in amplitude butDifferent phases, namely the phase is 45 DEG and the amplitude is the following principle of vector superpositionIs provided. And by analogy, when baseband signals with other phases are input, the phase and the amplitude of the voltage signal output by each gain circuit can be obtained.
Specifically, as shown in fig. 3, the mixing units Mixer1 and Mixer2 have the same circuit structure, and each mixing unit in the invention is composed of three identical mixing subunits; taking the first Mixer1 as an example, it has three identical Mixer subunits 100A, 100B and 100C; taking the mixing subunit 100A as an example, it includes: a first switching transistor m1, a second switching transistor m2, a third switching transistor m3, a fourth switching transistor m4, a fifth transistor m5, and a sixth transistor m6; wherein sources of the first switching transistor m1 and the second switching transistor m2 are commonly connected to a drain of the fifth transistor m5, sources of the third switching transistor m3 and the fourth switching transistor m4 are commonly connected to a drain of the sixth transistor m6, and drains of the first switching transistor m1 and the third switching transistor m3 are connected to a first output terminal of the first mixing unit Mixer 1; drains of the second switching transistor m2 and the fourth switching transistor m4 are connected to a second output terminal of the first mixing unit Mixer 1; sources of the fifth transistor m5 and the sixth transistor m6 are grounded.
Moreover, the gates of the first switching transistor m1 and the fourth switching transistor m4 are configured to be connected to the same voltage signal if_0, where the voltage signal if_0 is a voltage signal output by the first Buffer unit Buffer1 and having a phase of 0 °; the second switching transistor m2 and the third switching transistor m3 are configured to access the same voltage signal if_180, where the voltage signal if_0 is a voltage signal output by the second Buffer unit Buffer2 and having a phase of 180 °; thus, the phase difference of the voltage signals of the gate access of the first switching transistor m1 and the second switching transistor m2 is 180 degrees; meanwhile, the gate access phase of the fifth transistor m5 is 0 degree local oscillation signal I LO,+ Gate of the sixth transistor m6Local oscillation signal I with incoming phase of 180 DEG LO,- . By analogy, mixer subunits 100A, 100B, and 100C differ in that: the phase combinations of the connected voltage signals of the corresponding first switching transistor and the second switching transistor in the frequency mixing subunit are different; in the mixing subunit 100B, a first switching transistor is connected to a voltage signal with a phase of 45 ° output by the first Buffer unit Buffer1, and a second switching transistor is connected to a voltage signal with a phase of 225 ° output by the third Buffer unit Buffer 3; in the mixing subunit 100C, a first switching transistor is connected to a voltage signal with a phase of 90 ° output by the first Buffer unit Buffer1, and a second switching transistor is connected to a voltage signal with a phase of 270 ° output by the first Buffer unit Buffer 1.
And so on, in the second mixing unit Mixer2, the gate access phase of the fifth transistor of each mixing subunit is 90 ° local oscillation signal Q LO,+ The grid access phase of the sixth transistor is 270 DEG local oscillation signal Q LO,- . Among the three mixing subunits, a first switching transistor of the first mixing subunit is connected with a voltage signal with the phase of 90 degrees output by a second Buffer unit Buffer2, and a second switching transistor of the first mixing subunit is connected with a voltage signal with the phase of 270 degrees output by a fourth Buffer unit Buffer 4; the first switching transistor of the second mixing subunit is connected to a voltage signal with the phase of 135 degrees output by the second Buffer unit Buffer2, and the second switching transistor of the second mixing subunit is connected to a voltage signal with the phase of 315 degrees output by the fourth Buffer unit Buffer 4; the first switching transistor of the third mixing subunit is connected to the voltage signal with the phase of 180 ° output by the third Buffer unit Buffer3, and the second switching transistor is connected to the voltage signal with the phase of 0 ° output by the fourth Buffer unit Buffer4 (the voltage signal with the phase of 0 ° is identical to the voltage signal with the phase of 360 °).
Therefore, in the mixing unit of the present invention, the gates of the first switching transistor and the fourth switching transistor are configured to access the same voltage signal, and the second switching transistor and the third switching transistor are configured to access the same voltage signal, wherein the phase difference of the voltage signals accessed by the gates of the first switching transistor and the second switching transistor is 180 °; the grid electrode of the fifth transistor is configured to be connected with the first local oscillation signal, and the grid electrode of the sixth transistor is configured to be connected with the second local oscillation signal.
In fact, the mixer unit of the present invention is improved based on the double-balanced gilbert structure, and the input position of the local oscillation signal is interchanged with the input signal position, the local oscillation signal is input from the lower transistors (the transistors m5 and m 6), the output signal of the buffer unit is input from the upper transistors (the switch transistors m1 to m 4), and the suppression of the in-band intermediate frequency can be realized by the above mode.
It should be noted that, as those skilled in the art will appreciate, in the present invention, the phase of the baseband signal actually characterizes the relative phase to the absolute phase (original phase) of the baseband signal; moreover, the absolute phase of the baseband signals may be configured to any angle as long as the phase difference requirement between the baseband signals is satisfied.
In one embodiment of the present invention, there is also provided a chip including:
a substrate; and the harmonic suppression up-converter circuit provided by the invention is manufactured on the substrate.
In practice, the chip provided by the invention can be manufactured by a mature semiconductor chip manufacturing process, such as a CMOS process; in order to verify the frequency conversion performance index of the up-converter chip manufactured by adopting the CMOS process, the local oscillation suppression capability, the image suppression capability and the harmonic suppression capability are tested at normal temperature and low temperature respectively.
As shown in fig. 4, the capability of the local oscillation suppression degree, the mirror image suppression degree and the harmonic suppression degree of the up-converter at normal temperature are sequentially described, the baseband (BB) signal is 100M-400M in the wide frequency range of 4G-12G, the three types of harmonic suppression capability are all above 68dB, and the intermediate frequency third harmonic suppression capability is more than 70dB in the whole frequency band.
As shown in fig. 5, the local oscillation suppression degree, the mirror image suppression degree and the harmonic suppression capability of the up-converter at low temperature are sequentially described, and by using the existing method for simulating the low-temperature environment, various harmonic suppression capabilities can be achieved to a very high level by changing the bias voltage. Thanks to the structure of the intermediate frequency harmonic suppression up-converter, the local oscillation suppression degree of the up-converter is more than 64dB, the mirror image suppression degree is more than 81dB and the third harmonic suppression degree is more than 75dB in the local oscillation range of 4G-12G.
Therefore, the invention can restrain various harmonic waves in the up-conversion signal band, and improves the harmonic wave restraining capability of the up-converter, thereby further improving the spurious-free dynamic range of the up-converter.
In one embodiment of the present invention, there is also provided a pulse generator comprising the harmonic rejection up-converter circuit provided by the present invention or the up-converter chip provided by the present invention.
Specifically, as shown in fig. 6, the pulse generator 1 includes: a digital controller (Digital Controller), two digital-to-analog converters (DACs), two filtering modules, an up-conversion chip 10 and a local oscillation signal generating module; the digital controller generates analog signals with certain frequency through the output control digital-to-analog converter, generates four paths of baseband signals with the phases being different by 90 degrees in sequence through the filtering module, inputs the four paths of baseband signals into the up-conversion chip 10, outputs a group of differential signals through the up-conversion chip 10, and finally outputs pulse signals after sequentially passing through the attenuator and the transformer.
In view of the fact that the up-conversion chip provided by the invention has better harmonic suppression capability under the low-temperature condition, the whole spurious-free dynamic range (SFDR) of the pulse generator is improved by choosing and separating the local oscillation suppression capability, the image suppression capability and the harmonic suppression capability.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (7)
1. A harmonic rejection up-converter circuit, comprising: four buffer units and two mixing units; wherein,
the first buffer unit is configured to output three voltage signals with phases of 0 DEG, 45 DEG and 90 DEG according to two paths of baseband signals with the input phases of 180 DEG and 270 DEG respectively; the second buffer unit is configured to output three voltage signals with the phases of 90 DEG, 135 DEG and 180 DEG according to two paths of baseband signals with the input phases of 270 DEG and 360 DEG respectively; the third buffer unit is configured to output three voltage signals with phases of 180 DEG, 225 DEG and 270 DEG according to two paths of baseband signals with phases of 0 DEG and 90 DEG respectively; the fourth buffer unit is configured to output three voltage signals with the phases of 270 DEG, 315 DEG and 360 DEG respectively according to two paths of baseband signals with the input phases of 90 DEG and 180 DEG respectively;
the first mixing unit is configured to output a variable frequency signal through a first output end and a second output end of the first mixing unit according to three paths of voltage signals output by the first buffering unit, a voltage signal with the phase of 180 degrees output by the second buffering unit, two paths of voltage signals with the phases of 225 degrees and 270 degrees output by the third buffering unit and two paths of local oscillation signals with the phases of 0 degrees and 180 degrees respectively; the second mixing unit is configured to output a variable frequency signal through a first output end and a second output end of the second mixing unit according to two paths of voltage signals with phases of 90 degrees and 135 degrees respectively output by the second buffering unit, a voltage signal with a phase of 180 degrees output by the third buffering unit, three paths of voltage signals output by the fourth buffering unit and two paths of local oscillation signals with phases of 90 degrees and 270 degrees respectively input; and the variable frequency signals output by the first output end of the first frequency mixing unit and the first output end of the second frequency mixing unit are converged into one path of signal, and the variable frequency signals output by the second output end of the first frequency mixing unit and the second output end of the second frequency mixing unit are converged into the other path of signal, so that differential signal output is formed.
2. The harmonic rejection up-converter circuit as in claim 1 wherein the buffer unit is comprised of three identical gain circuits; moreover, the gain circuit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; wherein the drain of the first transistor is connected to the source of the third transistor, the source thereof is grounded through a ground impedance, and the gate thereof is configured to be connected to a first bias voltage or a baseband signal; the drain electrode of the third is connected with the working voltage through load impedance, and the grid electrode of the third is configured to be connected with a second bias voltage; the drain electrode of the second transistor is connected to the source electrode of the fourth transistor, the source electrode of the second transistor is grounded through a grounding impedance, and the grid electrode of the second transistor is configured to be connected with a first bias voltage or a baseband signal; the drain electrode of the fourth transistor is connected with the working voltage through load impedance, and the grid electrode of the fourth transistor is configured to be connected with a second bias voltage; the drains of the third transistor and the fourth transistor are commonly connected to an output end of a voltage signal;
in the buffer unit, one gain circuit is configured to access the first bias voltage and the first baseband signal, one gain circuit is configured to access the first bias voltage and the second baseband signal, and one gain circuit is configured to access the first baseband signal and the second baseband signal.
3. The harmonic rejection up-converter circuit of claim 2 wherein said mixing unit is comprised of three identical mixing subunits; furthermore, the mixing subunit comprises: a first switching transistor, a second switching transistor, a third switching transistor, a fourth switching transistor, a fifth transistor, and a sixth transistor; wherein sources of the first and second switching transistors are commonly connected to a drain of the fifth transistor, sources of the third and fourth switching transistors are commonly connected to a drain of the sixth transistor, and drains of the first and third switching transistors are connected to a first output terminal; drains of the second switching transistor and the fourth switching transistor are connected to a second output terminal; sources of the fifth transistor and the sixth transistor are grounded;
moreover, the gates of the first switching transistor and the fourth switching transistor are configured to access the same voltage signal, and the second switching transistor and the third switching transistor are configured to access the same voltage signal, wherein the phase difference of the voltage signals accessed by the gates of the first switching transistor and the second switching transistor is 180 degrees; the grid electrode of the fifth transistor is configured to be connected with the first local oscillation signal, and the grid electrode of the sixth transistor is configured to be connected with the second local oscillation signal.
4. A harmonic rejection upconverter circuit as claimed in any one of claims 1 to 3 wherein the phase of the baseband signal is characterised by a relative phase to the absolute phase of the baseband signal; wherein the absolute phase of the baseband signal is at any angle.
5. The harmonic rejection up-converter circuit of claim 4 wherein the local oscillator signal has a frequency range of 4G to 12G.
6. A chip, comprising:
a substrate; a harmonic-rejection up-converter circuit as claimed in any one of claims 1 to 5 fabricated on said substrate.
7. A pulse generator comprising a harmonic rejection up-converter circuit as claimed in any one of claims 1 to 5 or employing a chip as claimed in claim 6.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522952A (en) * | 2011-12-30 | 2012-06-27 | 广州市广晟微电子有限公司 | Harmonic suppression mixer and GSM (Global System for Mobile) radio-frequency chip |
| CN105594120A (en) * | 2013-09-27 | 2016-05-18 | 高通股份有限公司 | Harmonic rejective passive frequency up converter |
| CN111211737A (en) * | 2020-03-03 | 2020-05-29 | 芯原微电子(上海)股份有限公司 | High harmonic rejection ratio mixer circuit |
| CN112260651A (en) * | 2020-09-28 | 2021-01-22 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Broadband programmable harmonic rejection mixer |
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2023
- 2023-05-26 CN CN202310603751.1A patent/CN116683873B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522952A (en) * | 2011-12-30 | 2012-06-27 | 广州市广晟微电子有限公司 | Harmonic suppression mixer and GSM (Global System for Mobile) radio-frequency chip |
| CN105594120A (en) * | 2013-09-27 | 2016-05-18 | 高通股份有限公司 | Harmonic rejective passive frequency up converter |
| CN111211737A (en) * | 2020-03-03 | 2020-05-29 | 芯原微电子(上海)股份有限公司 | High harmonic rejection ratio mixer circuit |
| CN112260651A (en) * | 2020-09-28 | 2021-01-22 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Broadband programmable harmonic rejection mixer |
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