CN116682475A - Voltage offset determining method, voltage offset adjusting method, and storage medium - Google Patents

Voltage offset determining method, voltage offset adjusting method, and storage medium Download PDF

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Publication number
CN116682475A
CN116682475A CN202310596831.9A CN202310596831A CN116682475A CN 116682475 A CN116682475 A CN 116682475A CN 202310596831 A CN202310596831 A CN 202310596831A CN 116682475 A CN116682475 A CN 116682475A
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voltage offset
target
voltage
candidate
offsets
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CN116682475B (en
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郭梦奇
贺乐
赖鼐
龚晖
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Zhuhai Miaocun Technology Co ltd
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Zhuhai Miaocun Technology Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The application provides a voltage offset determining method, a voltage offset adjusting method and a storage medium, comprising the following steps: acquiring a plurality of operation scenes, a plurality of page types and a plurality of voltage offsets; determining a target operation scene from a plurality of operation scenes, and determining a target page type from a plurality of page types; for each chip, extracting the maximum codeword max_cw and the average codeword mean_cw of the target page type of the chip under the target operation scene and each voltage offset, and screening candidate optimal voltage offsets from a plurality of voltage offsets according to the maximum codeword max_cw and the average codeword mean_cw; and screening all candidate optimal voltage offsets of all chips under the target operation scene and the target page type to obtain target optimal voltage offsets corresponding to the target operation scene and the target page type. The application can quickly adjust and obtain the optimal voltage offset of a plurality of chips according to the operation scene and the page type, and can simultaneously ensure the correction success rate and correction speed of the plurality of chips, so that the chip performance is greatly improved.

Description

Voltage offset determining method, voltage offset adjusting method, and storage medium
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a voltage offset determining method, a voltage offset adjusting method, and a storage medium.
Background
In the related art, for a chip related product, several sets of voltage offsets are often set during shipment; however, in actual various different operation scenarios, the chip related product is difficult to completely cover data or has slow data reading speed under the condition of partial voltage offset, so that the voltage offset of the current chip related product is difficult to well match with the operation scenario, and the chip performance cannot be improved better.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the application provides a voltage offset determining method, a voltage offset adjusting method and a storage medium, which aim to improve the performance of a chip.
In a first aspect, an embodiment of the present application provides a method for determining a voltage offset, including:
acquiring a plurality of operation scenes, a plurality of page types and a plurality of voltage offsets;
determining a target operation scene from a plurality of operation scenes, and determining a target page type from a plurality of page types;
Extracting a maximum codeword max_cw and an average codeword mean_cw of the target page type of each chip under the target operation scene and each voltage offset, and screening candidate optimal voltage offsets from a plurality of voltage offsets according to the maximum codeword max_cw and the average codeword mean_cw;
and screening all candidate optimal voltage offsets of all chips under the target operation scene and the target page type to obtain target optimal voltage offsets corresponding to the target operation scene and the target page type.
In some embodiments, said selecting a candidate best voltage offset from a plurality of said voltage offsets based on said maximum codeword max_cw and said average codeword mean_cw comprises:
screening a plurality of candidate voltage offset values from a plurality of voltage offset values according to the maximum codeword max_cw of the target page type of the chip under the target operation scene and each voltage offset value;
and screening candidate optimal voltage offset from a plurality of candidate voltage offset according to average code words mean_cw of the target page type of the chip under the target operation scene and each candidate voltage offset.
In some embodiments, the selecting a number of candidate voltage offsets from the plurality of voltage offsets according to the maximum codeword max_cw of the target page type of the chip under the target operation scenario and each voltage offset includes:
acquiring an error correction capability limit value;
and screening a plurality of candidate voltage offsets according to the maximum codeword max_cw corresponding to the voltage offset and the error correction capability limit value.
In some embodiments, the filtering a plurality of candidate voltage offsets according to the maximum codeword max_cw corresponding to the voltage offset and the error correction capability limit value includes at least one of:
discarding the voltage offset when the maximum codeword max_cw corresponding to the voltage offset is greater than or equal to the error correction capability limit value;
and when the maximum codeword max_cw corresponding to the voltage offset is smaller than the error correction capability limit value, reserving the voltage offset, and taking the voltage offset as a candidate voltage offset.
In some embodiments, the selecting a candidate optimal voltage offset from a plurality of candidate voltage offsets according to an average codeword mean_cw of the target page type of the chip under the target operation scenario and each candidate voltage offset includes:
Sorting average code words mean_cw of the target page type of the chip under the target operation scene and each candidate voltage offset according to the numerical value, and obtaining a plurality of sorted average code words mean_cw;
and screening the average codeword mean_cw with the smallest value from the plurality of average codewords mean_cw, and taking the candidate voltage offset corresponding to the average codeword mean_cw with the smallest value as the candidate optimal voltage offset.
In some embodiments, before the extracting the maximum codeword max_cw and the average codeword mean_cw of the target page type of the chip under the target operation scenario and the respective voltage offsets, the voltage offset determining method further includes:
acquiring a voltage offset limit value;
when the voltage offset is smaller than the voltage offset limit value, reserving the voltage offset;
and discarding the voltage offset when the voltage offset is greater than or equal to the voltage offset limit value.
In some embodiments, the filtering all the candidate optimal voltage offsets of all the chips under the target operation scene and the target page type to obtain target optimal voltage offsets corresponding to the target operation scene and the target page type includes:
Counting the occurrence times of the candidate optimal voltage offset of all chips under the target operation scene and the target page type;
and selecting the candidate optimal voltage offset with the largest occurrence number as a target optimal voltage offset corresponding to the target operation scene and the target page type.
In some embodiments, after the acquiring the plurality of operation scenes, the plurality of page types, and the plurality of voltage offsets, the voltage offset determining method further includes:
preprocessing the data of each chip to convert unstructured data into structured data.
In a second aspect, an embodiment of the present application provides a voltage offset adjustment method, including:
acquiring current running scenes and current page types of a plurality of chips;
determining a corresponding target optimal voltage offset according to the current running scene and the current page type, wherein the target optimal voltage offset is determined by the voltage offset determining method according to the first aspect;
and adjusting the voltage offset of all the chips to be the target optimal voltage offset.
In a third aspect, an embodiment of the present application provides a computer-readable storage medium storing computer-executable instructions for performing the voltage offset determining method of the first aspect or the voltage offset adjusting method of the second aspect.
According to the technical scheme provided by the embodiment of the application, the method has at least the following beneficial effects: firstly, the embodiment of the application can acquire a plurality of operation scenes, a plurality of page types and a plurality of voltage offsets; then, the embodiment of the application determines a target operation scene from a plurality of operation scenes and determines a target page type from a plurality of page types; then, for each chip, the embodiment of the application extracts the maximum codeword max_cw and the average codeword mean_cw of the target page type of the chip under the target operation scene and each voltage offset, and screens the candidate optimal voltage offset from a plurality of voltage offsets according to the maximum codeword max_cw and the average codeword mean_cw; finally, the embodiment of the application screens all candidate optimal voltage offsets of all chips under the target operation scene and the target page type to obtain the target optimal voltage offset corresponding to the target operation scene and the target page type. The embodiment of the application can determine different optimal voltage offset from a plurality of voltage offset based on different operation scenes and different page types, so that the optimal voltage offset of a plurality of chips can be quickly adjusted according to the operation scenes and the page types in practical application, and further, the correction success rate and correction speed of the plurality of chips can be simultaneously ensured, and the chip performance is greatly improved.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and do not limit the application.
FIG. 1 is a flow chart of steps of a voltage offset determination method according to an embodiment of the present application;
FIG. 2 is a flow chart illustrating steps of a voltage offset determination method according to another embodiment of the present application;
FIG. 3 is a flowchart illustrating steps of a voltage offset determination method according to another embodiment of the present application;
FIG. 4 is a flowchart illustrating steps of a voltage offset determination method according to another embodiment of the present application;
FIG. 5 is a flowchart illustrating steps of a voltage offset determination method according to another embodiment of the present application;
FIG. 6 is a flow chart illustrating steps of a voltage offset determination method according to another embodiment of the present application;
FIG. 7 is a flowchart illustrating steps of a voltage offset determination method according to another embodiment of the present application;
FIG. 8 is a flow chart illustrating steps of a method for determining a voltage offset according to another embodiment of the present application;
FIG. 9 is a flowchart illustrating steps of a voltage offset determination method according to another embodiment of the present application;
FIG. 10 is a flowchart illustrating the overall steps of a voltage offset determination method according to one embodiment of the present application;
FIG. 11 is a flowchart illustrating a voltage offset adjustment method according to an embodiment of the present application;
fig. 12 is a schematic structural diagram of an electronic device for performing a voltage offset determining method or a voltage offset adjusting method according to an embodiment of the present application;
FIG. 13 is a schematic diagram of a voltage offset determining apparatus according to an embodiment of the present application;
fig. 14 is a schematic structural diagram of a voltage offset adjustment device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
In the description of the present application, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
In the description of the present application, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present application, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present application can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
In some cases, for chip related products, several sets of voltage offsets are often set during shipment; however, in actual various different operation scenarios, the chip related product is difficult to completely cover data or has slow data reading speed under the condition of partial voltage offset, so that the voltage offset of the current chip related product is difficult to well match with the operation scenario, and the chip performance cannot be improved better.
Based on the above situation, the embodiments of the present application provide a voltage offset determining method, a voltage offset adjusting method, an electronic device, a voltage offset determining apparatus, a voltage offset adjusting apparatus, and a computer readable storage medium, which aim to improve chip performance.
The voltage offset determining method according to the embodiment of the application is further described below with reference to the accompanying drawings.
As shown in fig. 1, fig. 1 is a flowchart illustrating steps of a voltage offset determining method according to an embodiment of the present application. The voltage offset determining method of the embodiment of the application includes, but is not limited to, step S110, step S120, step S130 and step S140.
Step S110, acquiring a plurality of operation scenes, a plurality of page types and a plurality of voltage offsets;
Step S120, determining a target operation scene from a plurality of operation scenes, and determining a target page type from a plurality of page types;
step S130, extracting a maximum codeword max_cw and an average codeword mean_cw of a target page type of the chip under a target operation scene and each voltage offset for each chip, and screening candidate optimal voltage offsets from a plurality of voltage offsets according to the maximum codeword max_cw and the average codeword mean_cw;
step S140, screening all candidate optimal voltage offsets of all chips under the target operation scene and the target page type to obtain target optimal voltage offsets corresponding to the target operation scene and the target page type.
In an embodiment, the embodiment of the application can screen each voltage offset under each operation scene and each page type, thereby obtaining the corresponding target optimal voltage offset. For example, the embodiment of the application can select one target operation scene from a plurality of operation scenes and select one target page type from a plurality of page types for experiments, and then the embodiment of the application can extract the maximum codeword max_cw and the average codeword mean_cw of the target page type of each chip under the target operation scene and each voltage offset, wherein the voltage offset with high correction success rate can be screened out through the maximum codeword max_cw, and meanwhile, the voltage offset with high correction speed can be screened out through the average codeword mean_cw, so that the embodiment of the application can screen out the candidate optimal voltage offset of each chip under the target operation scene and the target page type, and can ensure the correction success rate and the correction speed at the same time; finally, because the more samples the number of chips are, the more accurate the obtained experimental data is, so the embodiment of the application can screen out a plurality of candidate optimal voltage offsets of a plurality of chips under the target operation scene and the target page type, which can ensure the correction success rate and the correction speed at the same time, and screen out the most suitable target optimal voltage offset from the plurality of candidate optimal voltage offsets, and then the target optimal voltage offset is the most suitable voltage offset of all chips under the selected target operation scene and target page type.
It is worth noting that, because the embodiment of the application can determine different optimal voltage offset from a plurality of voltage offset based on different operation scenes and different page types, the optimal voltage offset of a plurality of chips can be quickly adjusted according to the operation scenes and the page types in practical application, and further, the correction success rate and correction speed of the plurality of chips can be simultaneously ensured, so that the chip performance is greatly improved.
It should be noted that, regarding the above operation scenario, the above operation scenario may be a high-temperature writing scenario, a high Wen Douqu scenario, a high-refresh-rate scenario, a low-refresh-rate scenario, or other types of operation scenarios, and the type of the above operation scenario is not particularly limited in the embodiment of the present application.
In addition, regarding the above-mentioned page type, the present application is not limited to the above-mentioned page type, and may be of FLC type, MLC type, SLC type, SMLC type, TLC type, or other types.
In addition, it should be noted that, regarding the above voltage offset, reference is made to Retry, where a plurality of groups of voltage offsets are pre-stored during the factory, where the number of voltage offsets may be 5 groups or 10 groups, and the number of pre-stored voltage offsets is not specifically limited in the embodiment of the present application.
In addition, regarding the maximum codeword max_cw, if the value is larger, the correction complexity is higher; if the value is smaller, the correction complexity is lower.
In addition, regarding the average codeword mean_cw, if the value is larger, it indicates that the correction speed is slower; if the value is smaller, the higher the correction speed is indicated.
It should be noted that, in order to obtain the target optimal voltage offset under different operation scenarios and different page types, the embodiments of the present application need to test combinations of various operation scenarios and various page types continuously, for example: testing the operation scene A1 and the page type B1 to obtain a target optimal voltage offset C1; testing the operation scene A1 and the page type B2 to obtain a target optimal voltage offset C2; testing the operation scene A2 and the page type B1 to obtain a target optimal voltage offset C3; and testing the operation scene A2 and the page type B2 to obtain a target optimal voltage offset C4. Therefore, after a series of combination tests are completed, the embodiment of the application obtains a mapping table corresponding to the operation scene, the page type and the target optimal voltage offset one by one, and pre-stores the mapping table, so that the optimal voltage offset can be quickly found for the current operation scene and the current page type during actual operation.
In addition, as shown in fig. 2, fig. 2 is a flowchart illustrating steps of a voltage offset determining method according to another embodiment of the present application. Regarding the above-described selection of the candidate optimal voltage offset from the plurality of voltage offsets according to the maximum codeword max_cw and the average codeword mean_cw in step S130, including but not limited to step S210 and step S220.
Step S210, a plurality of candidate voltage offset values are screened out from a plurality of voltage offset values according to the maximum codeword max_cw of the target page type of the chip under the target operation scene and each voltage offset value;
step S220, selecting a candidate optimal voltage offset from a plurality of candidate voltage offsets according to an average codeword mean_cw of a target page type of the chip under a target operation scene and each candidate voltage offset.
In an embodiment of the present application, a plurality of candidate voltage offsets with a correction success rate of 100% may be screened from a plurality of voltage offsets by using a maximum codeword max_cw, and then the candidate voltage offsets are screened, and specifically, a candidate voltage offset with a highest error correction speed may be screened from the plurality of candidate voltage offsets by using an average codeword mean_cw as a candidate optimal voltage offset.
It is to be understood that, regarding the number of candidate voltage offsets in the step S210, there may be one or more candidate voltage offsets, and the number of candidate voltage offsets is not specifically limited in the embodiment of the present application.
In addition, as shown in fig. 3, fig. 3 is a flowchart illustrating steps of a voltage offset determining method according to another embodiment of the present application. Regarding the maximum codeword max_cw of the target page type of the chip under the target operation scenario and the respective voltage offsets in the above step S210, a plurality of candidate voltage offsets are selected from the plurality of voltage offsets, including but not limited to step S310 and step S320.
Step S310, obtaining an error correction capability limit value;
step S320, a plurality of candidate voltage offsets are screened out according to the maximum codeword max_cw corresponding to the voltage offset and the error correction capability limit value.
In an embodiment, the embodiment of the application can compare the maximum codeword max_cw corresponding to the voltage offset with the error correction capability limit value to obtain a numerical comparison result, and then screen a plurality of candidate voltage offsets from a plurality of voltage offsets according to the numerical comparison result.
The error correction capability limit value refers to the maximum error correction capability; the maximum codeword max_cw is the correction complexity, so that the embodiment of the application can screen a plurality of candidate voltage offsets with the correction success rate of 100% through the comparison result of the error correction capability limit value and the value of the maximum codeword max_cw.
It should be noted that, regarding the filtering of the plurality of candidate voltage offsets according to the maximum codeword max_cw and the error correction capability limit value corresponding to the voltage offset in the step S320, the filtering may include, but is not limited to, two implementation cases in fig. 4 or fig. 5, specifically, the following steps respectively:
as shown in fig. 4, fig. 4 is a flowchart illustrating steps of a voltage offset determining method according to another embodiment of the present application. Regarding the above step S320, including but not limited to step S410 and step S420.
Step S410, when the maximum codeword max_cw corresponding to the voltage offset is greater than or equal to the error correction capability limit value;
step S420, discard the voltage offset.
As shown in fig. 5, fig. 5 is a flowchart illustrating steps of a voltage offset determining method according to another embodiment of the present application. Regarding the above step S320, including but not limited to step S510 and step S520.
Step S510, when the maximum codeword max_cw corresponding to the voltage offset is smaller than the error correction capability limit value;
step S520, the voltage offset is reserved, and the voltage offset is used as a candidate voltage offset.
In an embodiment, if the maximum codeword max_cw corresponding to the voltage offset is greater than or equal to the error correction capability limit value, it indicates that the correction complexity is greater than or equal to the maximum error correction capability, and the correction success rate cannot be guaranteed to be 100%, and then the embodiment of the application discards the voltage offset; if the maximum codeword max_cw corresponding to the voltage offset is smaller than the error correction capability limit value, the correction complexity is smaller than the maximum error correction capability, and the correction success rate can be ensured to be 100%, then the voltage offset is reserved, and the voltage offset is taken as a candidate voltage offset.
In addition, as shown in fig. 6, fig. 6 is a flowchart illustrating steps of a voltage offset determining method according to another embodiment of the present application. Regarding the average codeword mean_cw of the target page type of the chip under the target operation scene and each candidate voltage offset in the above step S220, candidate optimal voltage offsets are selected from a plurality of candidate voltage offsets, including but not limited to step S610 and step S620.
Step S610, sorting average code words mean_cw of target page types of the chip under the target operation scene and each candidate voltage offset according to the numerical value, and obtaining a plurality of sorted average code words mean_cw;
step S620, the average codeword mean_cw with the smallest value is screened out from the plurality of average codewords mean_cw, and the candidate voltage offset corresponding to the average codeword mean_cw with the smallest value is used as the candidate optimal voltage offset.
In an embodiment, the embodiment of the application can sort the values of the average code words mean_cw, and the larger the value of the average code word mean_cw is, the slower the correction speed is indicated; the smaller the value of the average codeword mean_cw, the faster the correction speed is indicated; then, the embodiment of the application can screen the average codeword mean_cw with the smallest value from the plurality of average codewords mean_cw after sequencing, and takes the candidate voltage offset corresponding to the average codeword mean_cw with the smallest value as the candidate optimal voltage offset, so that the candidate optimal voltage offset can be ensured to be capable of achieving 100% error correction success and achieve the fastest error correction speed.
In addition, as shown in fig. 7, fig. 7 is a flowchart illustrating steps of a voltage offset determining method according to another embodiment of the present application. Before performing the above-mentioned maximum codeword max_cw and average codeword mean_cw of the target page type of the extraction chip in step S130 under the target operation scene and each voltage offset, the voltage offset determining method according to the embodiment of the present application further includes, but is not limited to, step S710, step S720 and step S730.
Step S710, obtaining a voltage offset limit value;
step S720, when the voltage offset is smaller than the voltage offset limit value, reserving the voltage offset;
step S730, discarding the voltage offset when the voltage offset is greater than or equal to the voltage offset limit value.
In one embodiment, the voltage offset is compared with the voltage offset limit value, and if the voltage offset is smaller than the voltage offset limit value, the voltage offset can be used normally, and then the voltage offset is reserved; if the voltage offset is greater than or equal to the voltage offset limit value, indicating that the voltage offset cannot be used normally, embodiments of the present application discard the voltage offset.
In addition, as shown in fig. 8, fig. 8 is a flowchart illustrating steps of a voltage offset determining method according to another embodiment of the present application. Regarding the above-mentioned step S140, all candidate optimal voltage offsets of all chips under the target operation scene and the target page type are filtered to obtain target optimal voltage offsets corresponding to the target operation scene and the target page type, including but not limited to step S810 and step S820.
Step 810, counting the occurrence times of each candidate optimal voltage offset of all chips under a target operation scene and a target page type;
step S820, selecting the candidate optimal voltage offset with the largest occurrence number as the target optimal voltage offset corresponding to the target operation scene and the target page type.
In an embodiment, the more the number of chips is, the more accurate the obtained experimental data is, so that the embodiment of the application can screen out a plurality of candidate optimal voltage offsets of a plurality of chips under the target operation scene and the target page type, which can ensure the correction success rate and the correction speed at the same time; then, in order to screen out the target optimal voltage offset with the highest degree of adaptation with all chips, the embodiment of the application can count the occurrence times of each candidate optimal voltage offset, and then select the candidate optimal voltage offset with the highest occurrence times as the target optimal voltage offset. Since the target optimum voltage offset occurs most frequently, it is indicated that the target optimum voltage offset matches more chips.
In addition, as shown in fig. 9, fig. 9 is a flowchart illustrating steps of a voltage offset determining method according to another embodiment of the present application. After the step S110 is performed to obtain a plurality of operation scenes, a plurality of page types, and a plurality of voltage offsets, the voltage offset determining method according to the embodiment of the present application further includes, but is not limited to, step S900.
Step S900, preprocessing the data of each chip to convert unstructured data into structured data.
Based on the voltage offset determination methods of the respective embodiments described above, overall embodiments of the voltage offset determination method of the present application are presented below.
As shown in fig. 10, fig. 10 is a flowchart illustrating overall steps of a voltage offset determining method according to an embodiment of the present application. The overall embodiment of the voltage offset determination method of the present application includes, but is not limited to, steps S1001 to S1014.
Step S1001, start;
step S1002, acquiring read data through different scene experiments;
step S1003, preprocessing data, namely converting unstructured data into structured data;
step S1004, extracting max_cw of all pages of each chip;
step S1005, repeating the following operations one by one according to the page type of the nand:
Step S1006, judging that retry < retry_limit;
step S1007, discarding the retry;
step S1008, solving the max_cw and the mean_cw of the current chip and the current retry;
step S1009, judging that max_cw is less than ecc_limit;
step S1010, the retry cannot completely correct the data and discard the data;
step S1011, the retry success rate is 100%, and the retry success rate is used as a candidate retry of the best retry;
step S1012, taking the retry with the minimum mean_cw of the candidate retry as the best retry of the page type of the chip and recording;
step S1013, selecting the same optimal retry of the most chips from the same page type of all chips in the same scene as the optimal retry of the page type of the scene;
step S1014, end.
Based on the voltage offset determination methods of the respective embodiments described above, the respective embodiments of the voltage offset adjustment method of the present application are set forth below.
FIG. 11 is a flowchart showing steps of a voltage offset adjustment method according to an embodiment of the present application; the voltage offset adjustment method according to the embodiment of the application includes, but is not limited to, step S1110, step S1120, and step S1130.
Step S1110, obtaining current running scenes and current page types of a plurality of chips;
Step S1120, determining a corresponding target optimal voltage offset according to the current operation scene and the current page type, wherein the target optimal voltage offset is determined by the voltage offset determining method in any embodiment;
step S1130, adjust the voltage offsets of all chips to the target optimal voltage offset.
In an embodiment, by the voltage offset determining method of the above embodiment, a mapping table corresponding to the operation scene, the page type and the target optimal voltage offset one to one may be obtained, so during the actual operation, the embodiment of the present application may acquire the current operation scenes and the current page types of the plurality of chips, then quickly find the target optimal voltage offset corresponding to the current operation scenes and the current page types according to the pre-stored mapping table, and finally adjust the voltage offsets of all chips to the target optimal voltage offset.
It is worth noting that, because the embodiment of the application can determine different optimal voltage offset from a plurality of voltage offset based on different operation scenes and different page types, the optimal voltage offset of a plurality of chips can be quickly adjusted according to the operation scenes and the page types in practical application, and further, the correction success rate and correction speed of the plurality of chips can be simultaneously ensured, so that the chip performance is greatly improved.
Based on the voltage offset determination method and the voltage offset adjustment method of the respective embodiments described above, respective embodiments of the electronic device, the voltage offset determination apparatus, the voltage offset adjustment apparatus, and the computer-readable storage medium of the present application are respectively presented below.
As shown in fig. 12, fig. 12 is a schematic structural diagram of an electronic device for performing a voltage offset determining method or a voltage offset adjusting method according to an embodiment of the present application. The electronic device 100 according to the present application includes: processor 110, memory 120, and a computer program stored on memory 120 and executable on processor 110, where one processor 110 and one memory 120 are illustrated in fig. 12.
The processor 110 and the memory 120 may be connected by a bus or otherwise, which is illustrated in fig. 12 as a bus connection.
Memory 120, as a non-transitory computer-readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer-executable programs. In addition, memory 120 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some implementations, the memory 120 optionally includes memory 120 remotely located relative to the processor 110, the remote memory 120 being connectable to the electronic device 100 through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Those skilled in the art will appreciate that the apparatus structure shown in fig. 12 is not limiting of the electronic device 100 and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
In the electronic device 100 shown in fig. 12, the processor 110 may be configured to invoke the voltage offset determining program or the voltage offset adjusting program stored in the memory 120, thereby implementing the above-described voltage offset determining method or voltage offset adjusting method. Specifically, a non-transitory software program and instructions required to implement the voltage offset determination method or the voltage offset adjustment method of the above-described embodiments are stored in the memory 120, which when executed by the processor 110, perform the voltage offset determination method or the voltage offset adjustment method of the above-described embodiments.
It should be noted that, since the electronic device 100 according to the embodiment of the present application is capable of executing the voltage offset determining method or the voltage offset adjusting method according to any of the embodiments described above, the specific implementation and the technical effect of the electronic device 100 according to the embodiment of the present application may refer to the specific implementation and the technical effect of the voltage offset determining method or the voltage offset adjusting method according to any of the embodiments described above.
Further, as shown in fig. 13, fig. 13 is a schematic diagram of a structure of a voltage offset determining apparatus according to an embodiment of the present application. The voltage offset determining apparatus 200 implemented by the present application includes, but is not limited to, a first acquisition unit 210, a type determining unit 220, a first filtering unit 230, and a second filtering unit 240.
Specifically, the first obtaining unit 210 is configured to obtain a plurality of operation scenes, a plurality of page types, and a plurality of voltage offsets; the type determining unit 220 is configured to determine a target running scene from a plurality of running scenes, and determine a target page type from a plurality of page types; the first filtering unit 230 is configured to extract, for each chip, a maximum codeword max_cw and an average codeword mean_cw of a target page type of the chip under a target operation scene and each voltage offset, and to filter a candidate optimal voltage offset from a plurality of voltage offsets according to the maximum codeword max_cw and the average codeword mean_cw; the second filtering unit 240 is configured to filter all candidate optimal voltage offsets of all chips under the target operation scene and the target page type, so as to obtain a target optimal voltage offset corresponding to the target operation scene and the target page type.
In an embodiment, the first filtering unit 230 is further configured to filter a plurality of candidate voltage offsets from the plurality of voltage offsets according to a maximum codeword max_cw of the target page type of the chip under the target operation scene and each voltage offset, and filter a candidate optimal voltage offset from the plurality of candidate voltage offsets according to an average codeword mean_cw of the target page type of the chip under the target operation scene and each candidate voltage offset.
In an embodiment, the first filtering unit 230 is further configured to obtain an error correction capability limit value, and filter a plurality of candidate voltage offsets according to the maximum codeword max_cw corresponding to the voltage offset and the error correction capability limit value.
In an embodiment, when the maximum codeword max_cw corresponding to the voltage offset is greater than or equal to the error correction capability limit value, the first filtering unit 230 is further configured to discard the voltage offset; when the maximum codeword max_cw corresponding to the voltage offset is smaller than the error correction capability limit value, the first filtering unit 230 is further configured to reserve the voltage offset, and take the voltage offset as the candidate voltage offset.
In an embodiment, the first filtering unit 230 is further configured to sort the average codeword mean_cw of the target page type of the chip under the target operation scene and each candidate voltage offset according to the value size, to obtain a plurality of sorted average codewords mean_cw; and screening the average codeword mean_cw with the smallest value from the plurality of average codewords mean_cw, and taking the candidate voltage offset corresponding to the average codeword mean_cw with the smallest value as the candidate optimal voltage offset.
In an embodiment, the voltage offset determining apparatus 200 of the present application further includes, but is not limited to, a third filtering unit 250, where the third filtering unit 250 is configured to obtain a voltage offset limit value; when the voltage offset is smaller than the voltage offset limit value, the third filtering unit 250 retains the voltage offset; when the voltage offset is greater than or equal to the voltage offset limit value, the third filtering unit 250 discards the voltage offset.
In an embodiment, the second filtering unit 240 is further configured to count the occurrence times of each candidate optimal voltage offset of all chips under the target operation scene and the target page type, and select the candidate optimal voltage offset with the largest occurrence times as the target optimal voltage offset corresponding to the target operation scene and the target page type.
In an embodiment, the voltage offset determining apparatus 200 of the present application further includes, but is not limited to, a preprocessing unit 260, where the preprocessing unit 260 is configured to preprocess data of each chip to convert unstructured data into structured data.
It should be noted that, since the voltage offset determining apparatus 200 according to the embodiment of the present application corresponds to the voltage offset determining method according to any of the embodiments described above, reference may be made to the specific implementation and technical effects of the voltage offset determining apparatus 200 according to any of the embodiments described above.
In addition, as shown in fig. 14, fig. 14 is a schematic structural diagram of a voltage offset adjustment device according to an embodiment of the present application. The voltage offset adjustment apparatus 300 implemented by the present application includes, but is not limited to, a second acquisition unit 310, an offset determination unit 320, and an offset adjustment unit 330.
Specifically, the second obtaining unit 310 is configured to obtain a current running scenario and a current page type of the plurality of chips; the offset determining unit 320 is configured to determine a corresponding target optimal voltage offset according to the current running scenario and the current page type, where the target optimal voltage offset is determined by the voltage offset determining method in any of the foregoing embodiments; the offset adjustment unit 330 is used for adjusting the voltage offsets of all chips to the target optimal voltage offset.
It should be noted that, since the voltage offset adjustment device 300 according to the embodiment of the present application corresponds to the voltage offset adjustment method according to any of the embodiments described above, the specific implementation and technical effects of the voltage offset adjustment device 300 according to the embodiment of the present application can be referred to the specific implementation and technical effects of the voltage offset adjustment method according to any of the embodiments described above.
The apparatus embodiments described above are merely illustrative, in which modules illustrated as separate components may or may not be physically separate, i.e., may be located in one place, or may be distributed over multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In the several embodiments provided by the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the modules described above is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.
The modules described above as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in software functional modules.
In addition, an embodiment of the present application also provides a computer-readable storage medium storing computer-executable instructions for performing the above-described voltage offset determination method or voltage offset adjustment method. Illustratively, the method steps in fig. 1-11 described above are performed.
It should be noted that, since the computer readable storage medium according to the embodiment of the present application can perform the voltage offset determining method or the voltage offset adjusting method according to any of the embodiments described above, reference may be made to the specific implementation and technical effects of the voltage offset determining method or the voltage offset adjusting method according to any of the embodiments described above.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and may include any information delivery media.
The voltage offset determining method, the voltage offset adjusting method, the electronic device, the voltage offset determining device, the voltage offset adjusting device and the storage medium provided by the embodiment of the application can determine different optimal voltage offsets from a plurality of voltage offsets based on different operation scenes and different page types, so that the optimal voltage offsets of a plurality of chips can be quickly adjusted according to the operation scenes and the page types in practical application, and further, the correction success rate and correction speed of the plurality of chips can be simultaneously ensured, and the chip performance is greatly improved.
The embodiments described in the embodiments of the present application are for more clearly describing the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application, and those skilled in the art can know that, with the evolution of technology and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.
It will be appreciated by persons skilled in the art that the embodiments of the application are not limited by the illustrations, and that more or fewer steps than those shown may be included, or certain steps may be combined, or different steps may be included.
Those of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.
The terms "first," "second," "third," "fourth," and the like in the description of the application and in the above figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
While the preferred embodiment of the present application has been described in detail, the present application is not limited to the above embodiments, and those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit and scope of the present application, and these equivalent modifications or substitutions are included in the scope of the present application as defined in the appended claims.

Claims (10)

1. A voltage offset determination method, comprising:
acquiring a plurality of operation scenes, a plurality of page types and a plurality of voltage offsets;
determining a target operation scene from a plurality of operation scenes, and determining a target page type from a plurality of page types;
extracting a maximum codeword max_cw and an average codeword mean_cw of the target page type of each chip under the target operation scene and each voltage offset, and screening candidate optimal voltage offsets from a plurality of voltage offsets according to the maximum codeword max_cw and the average codeword mean_cw;
and screening all candidate optimal voltage offsets of all chips under the target operation scene and the target page type to obtain target optimal voltage offsets corresponding to the target operation scene and the target page type.
2. The method of claim 1, wherein said selecting a candidate optimal voltage offset from a plurality of said voltage offsets based on said maximum codeword max_cw and said average codeword mean_cw comprises:
screening a plurality of candidate voltage offset values from a plurality of voltage offset values according to the maximum codeword max_cw of the target page type of the chip under the target operation scene and each voltage offset value;
And screening candidate optimal voltage offset from a plurality of candidate voltage offset according to average code words mean_cw of the target page type of the chip under the target operation scene and each candidate voltage offset.
3. The method for determining voltage offset according to claim 2, wherein the step of screening a plurality of candidate voltage offsets from the plurality of voltage offsets according to a maximum codeword max_cw of the target page type of the chip under the target operation scene and each voltage offset comprises:
acquiring an error correction capability limit value;
and screening a plurality of candidate voltage offsets according to the maximum codeword max_cw corresponding to the voltage offset and the error correction capability limit value.
4. The method of claim 3, wherein the screening a plurality of candidate voltage offsets according to the maximum codeword max_cw and the error correction capability limit value corresponding to the voltage offset includes at least one of:
discarding the voltage offset when the maximum codeword max_cw corresponding to the voltage offset is greater than or equal to the error correction capability limit value;
And when the maximum codeword max_cw corresponding to the voltage offset is smaller than the error correction capability limit value, reserving the voltage offset, and taking the voltage offset as a candidate voltage offset.
5. The method for determining a voltage offset according to claim 2, wherein the selecting a candidate optimal voltage offset from a plurality of candidate voltage offsets according to an average codeword mean_cw of the target page type of the chip under the target operation scene and each of the candidate voltage offsets comprises:
sorting average code words mean_cw of the target page type of the chip under the target operation scene and each candidate voltage offset according to the numerical value, and obtaining a plurality of sorted average code words mean_cw;
and screening the average codeword mean_cw with the smallest value from the plurality of average codewords mean_cw, and taking the candidate voltage offset corresponding to the average codeword mean_cw with the smallest value as the candidate optimal voltage offset.
6. The voltage offset determination method according to any one of claims 1 to 5, characterized in that before the extracting the maximum codeword max_cw and the average codeword mean_cw of the target page type of the chip under the target operation scene and the respective voltage offsets, the voltage offset determination method further comprises:
Acquiring a voltage offset limit value;
when the voltage offset is smaller than the voltage offset limit value, reserving the voltage offset;
and discarding the voltage offset when the voltage offset is greater than or equal to the voltage offset limit value.
7. The method of determining a voltage offset according to claim 1, wherein the filtering all candidate optimal voltage offsets of all chips under the target operation scene and the target page type to obtain target optimal voltage offsets corresponding to the target operation scene and the target page type includes:
counting the occurrence times of the candidate optimal voltage offset of all chips under the target operation scene and the target page type;
and selecting the candidate optimal voltage offset with the largest occurrence number as a target optimal voltage offset corresponding to the target operation scene and the target page type.
8. The voltage offset determination method according to claim 1, wherein after the acquiring of the plurality of operation scenes, the plurality of page types, and the plurality of voltage offsets, the voltage offset determination method further comprises:
Preprocessing the data of each chip to convert unstructured data into structured data.
9. A voltage offset adjustment method, comprising:
acquiring current running scenes and current page types of a plurality of chips;
determining a corresponding target optimal voltage offset according to the current running scene and the current page type, wherein the target optimal voltage offset is determined by the voltage offset determining method according to any one of claims 1 to 8;
and adjusting the voltage offset of all the chips to be the target optimal voltage offset.
10. A computer-readable storage medium storing computer-executable instructions for performing the voltage offset determination method according to any one of claims 1 to 8 or the voltage offset adjustment method according to claim 9.
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