CN116680140A - Verification method, system, device and storage medium for processor - Google Patents
Verification method, system, device and storage medium for processor Download PDFInfo
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- CN116680140A CN116680140A CN202310801612.XA CN202310801612A CN116680140A CN 116680140 A CN116680140 A CN 116680140A CN 202310801612 A CN202310801612 A CN 202310801612A CN 116680140 A CN116680140 A CN 116680140A
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Abstract
The present disclosure provides an authentication method, system, device and storage medium for a processor, the method comprising: acquiring a page conversion table for access operation; fetching a generate instruction item, the generate instruction item comprising an operation mask determined by a value in a mask register and at least one instruction attribute item for a memory operation; acquiring a first access instruction based on the generated instruction item; acquiring an instruction injection page table requirement for a first access instruction, wherein the instruction injection page table requirement comprises that a page table error is injected for the first access instruction or that a page table error is not injected for the first access instruction; and acquiring a second target instruction based on the instruction injection page table requirement and the first access instruction, wherein the second target instruction is used for verifying whether the access page table conversion table is abnormal. The verification method can realize verification of page table exception scenes including operation mask attributes in the access instruction, so that test excitation is quite abundant, and a verification space is continuously expanded.
Description
Technical Field
Embodiments of the present disclosure relate to an authentication method, system, device, and storage medium for a processor.
Background
The processor, as a specialized unit of operation and logic control, refines and packages the commonly used computation or logic control into a single instruction, and when a user develops a program based on a specific processor platform, the user can directly use the instruction to achieve a specific target without paying attention to hardware implementation, and the combination of the instructions is called an instruction set.
With the development of technology, the operation requirement of software on a processor is higher, and the implementation of some common algorithms on the software level cannot meet the requirement on the speed, and the speed can be increased by converting the implementation into hardware. Thus, these algorithms are refined and added to instructions that integrate one direction of processor evolution.
At present, some instruction set architectures belonging to the complex instruction set operation series exist, and with the continuous development of corresponding architecture processors, the instructions in the complex instruction set are also increasing, and the instructions included in the complex instruction set can be divided according to different types, such as general instructions, system instructions, high-level vector expansion instructions, or expansion instructions for expanding the high-level vector expansion instructions, and the like. For these complex instruction sets, adequate verification and fast verification by efficient methods become necessary.
Disclosure of Invention
At least one embodiment of the present disclosure provides an authentication method for a processor, including: acquiring a page conversion table for access operation; obtaining at least one generated instruction item, wherein the at least one generated instruction item comprises an operation mask determined by a value in a mask register and at least one instruction attribute item for the memory access operation; acquiring a first access instruction based on the at least one generated instruction item; obtaining an instruction injection page table requirement for the first access instruction, wherein the instruction injection page table requirement comprises either injecting a page table error for the first access instruction or not injecting a page table error for the first access instruction; and acquiring a second target instruction based on the instruction injection page table requirement and the first access instruction, wherein the second target instruction is used for verifying whether the access to the page table conversion table is abnormal.
For example, an authentication method provided in at least one embodiment of the present disclosure further includes: the mask register is initialized to determine a value in the mask register.
For example, in an authentication method provided by at least one embodiment of the present disclosure, initializing the mask register includes: a first random variable is obtained, and the mask register is initialized through a data storage mask register instruction by using the first random variable.
For example, in an authentication method provided in at least one embodiment of the present disclosure, obtaining a page translation table for a memory access operation includes: a plurality of first page tables are created such that portions of the plurality of first page tables serve as reserved address spaces to obtain the page translation table for the memory access operation, wherein the reserved address spaces are configured to generate page table exceptions when pointed to an access.
For example, in one verification method provided by at least one embodiment of the present disclosure, the at least one instruction attribute item includes at least one of: the instruction type of the access operation, the source operand of the access, the destination operand of the access, the size of the access range, the access base address, the access address offset, the access index and the granularity of the access element.
For example, in a verification method provided in at least one embodiment of the present disclosure, based on the at least one generated instruction item, obtaining a first access instruction includes: and carrying out randomization on the at least one generated instruction item by utilizing a randomization function to acquire the first memory access instruction.
For example, in an authentication method provided in at least one embodiment of the present disclosure, obtaining an instruction injection page table requirement for the first access instruction includes: a second random variable is obtained and based on the second random variable, the first memory instruction is caused to be randomly injected with or without a page table error.
For example, an authentication method provided in at least one embodiment of the present disclosure further includes: and acquiring a valid bit signal of the mask register based on the size of the access range and the granularity of the access element in the first access instruction, wherein the valid bit signal of the mask register is used for determining whether the first access instruction supports exception suppression.
For example, in a verification method provided in at least one embodiment of the present disclosure, obtaining a second target instruction based on the instruction injection page table requirement and the first memory access instruction includes: responding to the instruction injection page table requirement that a page table error is not injected into the first access instruction, and acquiring the second target instruction which is normal; or, in response to the instruction injection page table requirement being a page table error injection for the first access instruction, acquiring the abnormal second target instruction.
For example, in a verification method provided in at least one embodiment of the present disclosure, responding to the instruction injection page table requirement to inject a page table error for the first access instruction, obtaining the abnormal second target instruction includes: responding to the instruction injection page table requirement to inject a page table error to the first access instruction, adjusting the access address offset and/or the access base address, and pointing to a reserved address space in the page conversion table, wherein the reserved address space is configured to generate a page table exception when pointed to access; acquiring a page table abnormality influence result based on the valid bit signal of the mask register; responding to the page table abnormality influence result to be the non-influence, and acquiring the abnormal second target instruction; or, in response to the page table exception effect result being an effect, fetching the page table exception pre-processing subroutine and fetching the second target instruction of the exception.
At least one embodiment of the present disclosure provides an authentication system for a processor, comprising: the page conversion table acquisition module is configured to acquire a page conversion table for access operation; a generate instruction item acquisition module configured to acquire at least one generate instruction item, wherein the at least one generate instruction item includes an operation mask determined by a value in a mask register and at least one instruction attribute item for the memory access operation; a first instruction acquisition module configured to acquire a first memory instruction based on the at least one generated instruction item; an instruction injection page table requirement acquisition module configured to acquire an instruction injection page table requirement for the first memory instruction, wherein the instruction injection page table requirement includes injecting a page table error for the first memory instruction or not injecting a page table error for the first memory instruction; and a second instruction acquisition module configured to acquire a second target instruction based on the instruction injection page table requirement and the first access instruction, wherein the second target instruction is used for verifying whether accessing the page table conversion table is abnormal.
At least one embodiment of the present disclosure provides an electronic device, including: a processor and a memory, wherein the memory has stored thereon a computer program which, when executed by the processor, implements a verification method as claimed in any one of the preceding claims.
At least one embodiment of the present disclosure provides a computer-readable storage medium, in which a computer program is stored, which when executed by a processor, implements a verification method as described in any of the examples above.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
FIG. 1 is a flow chart of a verification method for a processor provided by some embodiments of the present disclosure;
FIG. 2 is a flow chart of step S52 provided by some embodiments of the present disclosure;
FIG. 3 is a flow chart of a method for randomly generating instructions in a verification method for a processor provided by some embodiments of the present disclosure;
FIG. 4 is a schematic diagram of generating a test stimulus source file provided by some embodiments of the present disclosure;
FIG. 5 is a block diagram of a verification system provided by some embodiments of the present disclosure;
Fig. 6 is a block diagram of an electronic device provided by some embodiments of the present disclosure.
Detailed Description
The following description of the technical solutions in the embodiments of the present disclosure will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
Unless defined otherwise, all terms (including technical and scientific terms) used in the embodiments of the disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined by the presently disclosed embodiments.
The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Nor does the terms "a," "an," or "the" or similar terms mean a limitation of quantity, but rather that at least one is present. Likewise, the word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. A flowchart is used in the embodiments of the present disclosure to illustrate the steps of a method according to embodiments of the present disclosure. It should be understood that the steps that follow or before do not have to be performed in exact order. Rather, the various steps may be processed in reverse order or simultaneously. Also, other operations may be added to or removed from these processes.
Currently, some instructions that extend a range of native instruction sets (e.g., AVX-512 instructions, corresponding to the set advanced vector extension instructions described below, a simplified description of which is available herein) may include corresponding base instructions, exponent and reciprocal instructions, conflict instructions, prefetch instructions, and newly added single instruction multiple data Stream (SIMD) extension instructions (e.g., 512bit SIMD extension instructions).
The inventors of the present disclosure have found that this instruction (the set advanced vector expansion instruction as described above) can also introduce architectural improvements such as: (1) A register set supporting 512bit wide vectors and single instruction multiple data streams; (2) 16 new 512-bit SIMD registers are supported in 64-bit mode; (3) 8 new operation mask registers (OpmaskRegisters, k0-k 7) are supported, mainly for conditional execution and efficient integration of destination operands; (4) A new instruction encoding prefix (EVEXPrefix) is introduced to expand the operand bit width to 512 bits.
Page table translation is a method of translating virtual addresses to physical addresses maintained and managed by operating system software in some architectures that can improve memory access security. In general, page table translation mechanisms may enable operating system software to open up separate address spaces for each process or program. The mechanism idea is that the operating system maintains a table of page table translations from virtual addresses to physical addresses. For example, taking the 4-KByte-sized physical address page table translation in 64-bit mode of an architecture as an example, a 64-bit virtual address is divided into 6 different domains, 4 of which are used as indexes for different levels of physical address lookup, e.g., one of the 6 different domains (e.g., bits11: 0) is used as a memory offset address for the 4-KByte physical page table, and the roles of the other five domains are not described here.
Page table errors are a scenario that occurs upon memory access. For example, page table errors are typically caused by non-creation of page table mappings from virtual addresses to physical addresses or by non-uniformity of the permissions that programs need to access and the currently existing page table attributes. The inventors of the present disclosure have found that the main causes of page table error generation include the following: first, the page table of the memory unit to be accessed does not exist in the page translation table; second, the processor attempts to read instructions from page tables that do not have executable rights; thirdly, a page table protection check failure is encountered during memory access; fourth, the reserved bit in the page table translation table is 1.
The inventors of the present disclosure have also found that under normal conditions, if a source operand or a destination operand in an instruction contains a memory access and a page table error exists in an address of a memory unit to be accessed, for example, the page table is not created, the memory access unit generates a page table error signal to microcode (Ucode), and the microcode enters a corresponding exception/pre-processing subroutine according to an interrupt vector table, to complete, for example, processing of an exception/interrupt. An instruction (e.g., the advanced vector expansion instruction described above) may not actually issue a memory access request due to the introduction of an operation mask, such that in the case of an operation mask of 0, even if there is a page table error in the memory access address of the source or destination operand, the memory location will not generate an error in the page table exception back to the microcode, thus eliminating the need to enter the exception pre-processing subroutine for processing. An operation mask is an attribute of an instruction. For example, for VPANDNQZMM0{ k1}, ZMM1, [ mem ], the Opmask register k1[7:0] is a valid operation mask, and each bit in the operation mask register k1 controls whether every 8 bytes in the memory access unit will be actually accessed. For the above instruction, if k1[7:0] =0, the Load (Load) or Store (Store) memory access unit will not generate a page table error signal to the microcode even if the accessed memory page table is not present, so that the microcode will not enter the interrupt subroutine for page table error handling. If k1[7:0] =1, indicating that 8 bytes of data elements need to be read from the memory starting address, the load unit or the store unit will initiate a real access request to the memory, a page table exception will be generated, the load unit or the store unit will send the exception error information to the microcode, and the microcode will perform further processing. Of course, this is merely exemplary and is not a limitation of the present application.
Verification test stimulus for top level (top level) of kernel cluster (coremaster) is an assembler based on instruction sequences. The inventor of the present disclosure also found that, because the instruction set is very complex, the test space is very large, while the top level verification platform focuses on the system level function verification, and needs to pay attention to whether the kernel functions correctly when encountering some instruction exceptions or interrupts. Therefore, the method for generating random instructions is particularly important in large-scale integrated circuit verification, and the randomness of test stimulus directly determines whether the coverage of the verification scene is comprehensive or not.
At least one embodiment of the present disclosure provides an authentication method for a processor, including: acquiring a page conversion table for access operation; obtaining at least one generated instruction item, the at least one generated instruction item comprising an operation mask determined by a value in a mask register and at least one instruction attribute item for a memory access operation; acquiring a first access instruction based on at least one generated instruction item; acquiring an instruction injection page table requirement for a first access instruction, wherein the instruction injection page table requirement comprises that a page table error is injected for the first access instruction or that a page table error is not injected for the first access instruction; and acquiring a second target instruction based on the instruction injection page table requirement and the first access instruction, wherein the second target instruction is used for verifying whether the access page table conversion table is abnormal.
The verification method of the embodiment of the disclosure can realize verification of the page table exception scene of the operation mask attribute included in the access instruction, so that test stimulus (also called verification stimulus) is enriched, and the verification space is continuously expanded. For example, in at least one embodiment of the present disclosure, the verification method may also combine the features of operation mask and exception suppression to achieve a comprehensive verification of page table exception scenarios with operation mask and different exception suppression attributes in memory access instructions (including, but not limited to, advanced vector expansion instructions), and some unexpected design flaws may be detected through different scenario combinations. The verification method of the embodiment of the present disclosure is also applicable to some page table error injection scenarios of other access instructions that do not support operation masks and exception suppression, other than the access instructions described above. Embodiments of the present disclosure are also capable of randomly combining instruction fragments generated with other test sequences to generate more complex, more comprehensive test stimuli for verification of the processor. The embodiment of the disclosure can be extended to multi-threading very simply and conveniently, and can provide test stimulus for single-core multi-threading and multi-core multi-threading.
Fig. 1 is a flow chart of a verification method for a processor provided in some embodiments of the present disclosure.
For example, as shown in fig. 1, at least one embodiment of the present disclosure provides a verification method for a processor including steps S1 to S5.
Step S1, acquiring a page conversion table for access operation.
Step S2, at least one generating instruction item is obtained, wherein the at least one generating instruction item comprises an operation mask determined by a value in a mask register and at least one instruction attribute item for a memory access operation.
And step S3, acquiring a first access instruction based on at least one generation instruction item.
Step S4, acquiring an instruction injection page table requirement for the first access instruction, wherein the instruction injection page table requirement comprises that a page table error is injected into the first access instruction or that a page table error is not injected into the first access instruction.
And S5, acquiring a second target instruction based on the instruction injection page table requirement and the first access instruction, wherein the second target instruction is used for verifying whether the access page table conversion table is abnormal.
According to the verification method of the embodiment of the disclosure, when verification of access abnormality of the page table (namely the page table conversion table) by the access instruction is realized, verification of page table abnormality scene including operation mask attribute in the access instruction can be realized, test excitation can be enriched, and verification space is continuously expanded.
The verification method of some embodiments of the present disclosure can also combine the characteristics of operation mask and exception suppression to realize comprehensive verification of page table exception scenes with operation mask and different exception suppression attributes in the memory access instruction, and some unexpected design defects can be detected through different scene combinations.
The verification method of the embodiment of the disclosure is also applicable to some page table error injection scenes of access instructions which do not support operation masks and exception suppression except the access instructions, and the verification is comprehensive.
The above embodiments of the present disclosure enable random combination of instruction fragments generated from other test sequences, generating more complex, more comprehensive test stimuli for verification of a processor.
The embodiment of the disclosure can be very simply and conveniently extended to multi-threads, and can provide test stimulus for single-core multi-thread and multi-core multi-thread.
Currently, the adoption of verification methodologies is one of the trends of processor verification, and Universal Verification Methodologies (UVM) are typical representatives thereof. UVM is a general verification methodology based on SystemVerilog class, with its reusable components, a functional verification environment with standardized hierarchies and interfaces, namely a UVM verification environment, can be built. The UVM verification environment specifies the basic classes (i.e., reusable components) in UVM. The verifier can expand the needed classes on the basis of the basic classes, and then the communication interfaces of the classes are connected by using the communication statement of the UVM standard. As such, embodiments of the present disclosure may implement a test stimulus (e.g., kernel cluster top test stimulus) generation process that generates a random access instruction (e.g., AVX-512 access instruction) and randomly injects page table errors through a random test generation module (RandomTest Generate, RTG). The random test generation module is a random instruction generation environment built based on a SystemVerilog language and a UVM verification method. It should be noted that, because this is not an important point for the description of the embodiments of the present disclosure, the description is omitted here.
In some examples, the first access instruction and/or the second target instruction of embodiments of the present disclosure is an instruction that includes a memory access operation, whereby verification of the context of a page table access exception may be achieved.
The first memory access instruction and/or the second target instruction of embodiments of the present disclosure may be an AVX-512 memory access instruction. It should be noted that, the following embodiments mainly take the first access instruction and/or the second target instruction as AVX-512 access instruction as an example, but the embodiments of the present disclosure are not limited thereto, and are not exhaustive or redundant herein.
In some examples, the verification method of embodiments of the present disclosure further includes the following process or step T1: the mask register is initialized to determine the values in the mask register (also referred to as the operation mask register).
The embodiment of the disclosure can control the value initialized by the mask register by adding a certain constraint through the SystemVerilog, so that a corresponding scene is constructed, the test stimulus of the embodiment of the disclosure is very abundant, and the verification is more comprehensive.
In some examples, for step T1, initializing the mask register to determine the value in the mask register includes the following process or step T11: the first random variable is obtained and the mask register is initialized by the data store mask register instruction using the first random variable.
For example, in step T11, the first random variable may be a 64bit variable. Of course, this is merely exemplary and is not limiting of the embodiments of the present disclosure.
For example, in step T11, the first random variable may be an immediate value or may be data in a memory, which is, of course, merely exemplary, and the embodiments of the present disclosure are not limited thereto, and are not exhaustive or redundant herein.
For example, for step T11, embodiments of the present disclosure may define a variable in SystemVerilog as bit [63:0] var1, i.e., var1 is a 64bit variable, and then recall the random function interface in SystemVerilog, which may randomize variable var 1. Thus, var1 becomes a randomly generated 64bit variable, i.e., the first random variable corresponding to the 64 bit. Of course, this is merely exemplary and is not limiting of the embodiments of the present disclosure.
For example, in step T11, the data store mask register instruction may be a KMOVW or KMOVB or KMOVQ or KMOVD instruction, which is an instruction supported in the set advanced vector expansion instruction set that may use the mask register as a destination address, thereby implementing loading data in an immediate or in memory into the mask register. Of course, this is merely exemplary and is not limiting of the embodiments of the present disclosure.
In some examples, the step T1 may be performed before the step S1, or after the step S1 or performed simultaneously with the step S1, which is not limited in this embodiment of the disclosure, and may be freely adjusted according to practical situations, which is not described herein.
In some examples, for step S1, acquiring the page translation table for the memory access operation includes the following process or step S11: the plurality of first page tables are created such that portions of the plurality of first page tables serve as a reserved address space configured to generate page table exceptions when pointed to an access to obtain a page translation table for the memory operation.
In some examples, in step S11, the plurality of first page tables may be page tables of a plurality of different attributes. For example, the created plurality of first page tables may be four consecutive 4K-byte page tables with virtual addresses mapped to physical addresses (e.g., each virtual address mapped to a physical address requiring 4 page table translations), and when the presentbit attribute in the page table of the last 4K-byte in the four 4K-byte page tables is 0 (presentbit=1 indicates present and presentbit=0 indicates absent), then the page table of the last 4K-byte is the reserved address space. Thus, if the virtual address in the memory access points to the last 4K-byte page table, a page table exception may occur due to the absence of the page table.
The generated instruction item of some embodiments of the present disclosure is used as a basic element of an instruction, and the generated instruction item may determine a specific instruction generated according to a random constraint based on a random test generation module.
In some examples, in step S2, the instruction attribute item includes at least one of: the instruction type of the access operation, the source operand of the access, the destination operand of the access, the size of the access range, the access base address, the access address offset, the access index and the granularity of the access element.
In some examples, for step S3, obtaining the first memory access instruction based on the at least one generated instruction item includes the following process or step: and (3) randomizing at least one generated instruction item by utilizing a randomizing function to acquire a first memory access instruction. Thus, the embodiment of the disclosure can realize the generation of the test case that the instruction generates the random access memory and randomly injects the page table error, thereby realizing the verification of whether the page table conversion table access is abnormal.
In some examples, the randomization function is a random constraint random () function of SystemVerilog. Of course, this is merely exemplary and is not limiting of the embodiments of the present disclosure.
In some examples, for step S4, fetching the instruction injection page table requirement for the first memory instruction includes the following process or steps: a second random variable is obtained and based on the second random variable, the page table error is either randomly injected or not injected for the first access instruction.
Embodiments of the present disclosure may increase the complexity of the test scenario, covering more random test scenarios, by randomly determining whether to inject page table errors for memory access instructions.
In some examples, embodiments of the present disclosure may determine whether to inject a page table error for a first memory instruction based on a second random variable whose random value is 1 (e.g., setting a 10% probability to have a value of 1) each time a memory instruction is generated. For example, if the random value of the second random variable is 1, the generation instruction of the access instruction is controlled to generate an access instruction (i.e., the second target instruction) that generates a page table access exception. Of course, this is merely exemplary and is not limiting of the embodiments of the present disclosure.
In some examples, the verification method of embodiments of the present disclosure further includes the following process or step T2: based on the memory range size in the first memory instruction and the granularity of the access elements, a valid bit signal of the mask register is obtained, e.g., the valid bit signal of the mask register is used to determine whether the first memory instruction supports exception suppression (faultsuppresion).
In some examples, in step T2, for a memory access instruction supporting exception suppression, the memory granule whose corresponding bit is 1 in the valid bit signal of the mask register is considered to be truly read and used for instruction computation.
According to the verification method of some embodiments of the present disclosure, the characteristics of operation mask and exception suppression can be combined, so that comprehensive verification of page table exception scenes with operation mask and different exception suppression attributes in the memory access instruction is realized, and some unexpected design defects can be detected through different scene combinations.
For example, for step S5, in some examples, fetching a second target instruction based on the instruction injection page table requirement and the first memory access instruction includes the following process or step S51: and responding to the instruction injection page table requirement that the page table error is not injected to the first access instruction, and acquiring a normal second target instruction.
For example, for step S5, in other examples, fetching a second target instruction based on the instruction injection page table requirement and the first memory access instruction includes the following process or step S52: and responding to the instruction injection page table requirement to inject page table errors into the first access instruction, and acquiring an abnormal second target instruction.
Fig. 2 is a flowchart of step S52 provided in some embodiments of the present disclosure.
For example, as shown in fig. 2, step S52 in the authentication method includes steps S521 to S523.
Step 521, in response to the instruction injection page table requirement, a page table error is injected to the first access instruction, and the access address offset and/or the access base address are adjusted to point to a reserved address space in the page translation table, wherein the reserved address space is configured to generate a page table exception when pointed to access.
Step S522, based on the valid bit signal of the mask register, obtaining the page table abnormal influence result.
Step S523, responding to the page table abnormality influence result as no influence, and acquiring an abnormal second target instruction; or, in response to the page table exception effect result being an effect, fetching the page table exception pre-processing subroutine and fetching the second target instruction of the exception.
In some examples, a page table exception error is generated in a first memory access instruction, and if no special handling is done in the instruction program, the program cannot continue to execute other instruction streams following the first memory access instruction. Therefore, the embodiment of the disclosure can inject the page table error in combination with the operation mask register in the instruction operand and whether the access instruction supports the exception suppression, judge whether the exception of the actual page table error is generated, and realize the subroutine for preprocessing the page table error, so that the embodiment of the disclosure can complete the processing of the exception through the exception preprocessing subroutine and return to the access instruction generating the exception (namely, the second target instruction of an exception) and then continue to execute the following instruction sequence (namely, the first access instruction corresponding to the random generation), thereby solving the problem that the test efficiency of the program is affected.
In some examples, the verification method of embodiments of the present disclosure further includes the following process or step T3: counting the acquired second target instructions, and judging whether the number of the acquired second target instructions is smaller than the total number of the random instructions expected to be generated or not: if yes, repeating the steps to continuously acquire other second target instructions until the number of the acquired second target instructions reaches the total number of the random instructions expected to be generated; if not, correspondingly generating a complete test excitation source file.
It should be noted that, the embodiments of the present disclosure do not limit the specific number of the total number of random instructions that are expected to be generated, and this may be freely adjusted according to practical situations, which are not exhaustive and not described herein.
Fig. 3 is a flow chart of a method for randomly generating instructions in a verification method for a processor provided by some embodiments of the present disclosure.
For example, as shown in fig. 3, the method for randomly generating instructions in the authentication method of a processor includes steps P1 to P11.
Step P1, obtain at least one generating instruction item, the generating instruction item comprising an operation mask determined by the value in the mask register and at least one instruction attribute item for the memory access operation.
And P2, acquiring a page conversion table for access operation.
Step P3, initializing the mask register to determine the value in the mask register.
And P4, randomizing at least one generated instruction item by utilizing a randomizing function to acquire a first access instruction.
And step P5, based on the size of the access range and the granularity of the access elements in the first access instruction, acquiring a valid bit signal of a mask register, wherein the valid bit signal of the mask register is used for determining whether the first access instruction supports abnormal suppression.
Step P6, obtaining an instruction injection page table requirement for the first access instruction, and judging whether the instruction injection page table requirement is an injection page table error for the first access instruction: if yes, the instruction injection page table requirement is that the first access instruction is injected with a page table error, and then the step P7 is continuously executed; if not, the instruction injection page table requirement is that the page table error is not injected for the first access instruction, and the process goes to step P11.
And P7, adjusting access address offset and/or access base address, and pointing to a reserved address space in the page translation table, wherein the reserved address space is configured to generate page table exception when pointed to access.
Step P8, obtaining a page table abnormality influence result based on the valid bit signal of the mask register, and judging whether a real page table abnormality is generated or not: if yes, namely the page table abnormality influence result is influence, continuing to execute the step P9; if not, the page table exception effect is not affected, go to step P10.
And step P9, acquiring a page table exception preprocessing subprogram, and continuing to execute step P10.
And step P10, acquiring a second abnormal target instruction.
And step P11, acquiring a normal second target instruction.
In some examples, the second target instruction of embodiments of the present disclosure is a random access instruction.
The verification method of the embodiment of the disclosure can realize the generation of random test excitation aiming at the random injection page table error with the operation mask in the instruction access memory, thereby completing the verification of the access memory instruction page table abnormality. The verification method of the embodiment of the disclosure not only can ensure that verification can cover the scene of randomly injecting some instruction exceptions, but also can ensure that a processor can continue to execute other instruction sequences in test excitation after entering into an exception processing program. The embodiment of the disclosure can be used for generating the page table error test excitation aiming at the high-level vector expansion instruction by a kernel cluster top stage of a processor access module, and can also be used for generating test excitation for generating other high-level vector expansion instruction exceptions in an expansion way. The random test excitation instruction sequences generated by the embodiment of the disclosure can be mixed with other random test excitation instruction sequences to construct and generate more complex assembler, so that more random test scenes are covered. The embodiment of the disclosure not only can ensure that verification can cover the scene of randomly injecting some instruction exceptions, but also can ensure that a processor can continue to execute other instruction sequences in test excitation after entering an exception processing program, and can avoid the influence on the program test efficiency.
For example, as shown in fig. 3, steps P1 to P11 are steps of a method for randomly generating the second target instruction in a sequence (for example, the sequence 0 shown in fig. 3 may be denoted as seq 0), and each sequence corresponds to generating a second target instruction.
For example, as shown in fig. 3, the verification method of the embodiment of the present disclosure further includes:
step P12, counting the second target instructions, and judging whether the counted instruction number is smaller than the total number N of the random instructions expected to be generated, wherein N is an integer greater than or equal to 1: if yes, jumping to the step P4 and circularly executing the step to continue to generate the next second target instruction until all the second target instructions are generated; if not, go to step P13.
And P13, generating a complete test excitation source file according to the acquired N second target instructions.
In some examples, the total number of random instructions N desired to be generated may be controlled and determined by the user and it is a condition of the loop ending mechanism of the method of randomly generating the second target instruction.
Fig. 4 is a schematic diagram of generating a test stimulus source file provided by some embodiments of the present disclosure.
In some examples, embodiments of the present disclosure can build more powerful test stimuli by randomly combining between sequences for different test scenarios, greatly enriching the complexity of the test stimuli.
For example, as shown in fig. 4, embodiments of the present disclosure may generate a complete test stimulus source file by random combination between sequence 0, sequence 1, sequence 2, and up to sequence N for different test scenarios, which may greatly enrich the complexity of the test stimulus, thereby helping the verification environment find more hidden design issues.
Fig. 5 is a block diagram of an authentication system for a processor provided in some embodiments of the present disclosure.
For example, as shown in fig. 5, at least one embodiment of the present disclosure provides a verification system 100 for a processor that includes a page translation table fetch module 101, a generate instruction item fetch module 102, a first instruction fetch module 103, an instruction injection page table requirement fetch module 104, and a second instruction fetch module 105.
The page translation table acquisition module 101 is configured to acquire a page translation table for a memory access operation. The generate instruction item acquisition module 102 is configured to acquire at least one generate instruction item including an operation mask determined by a value in a mask register and at least one instruction attribute item for a memory access operation. The first instruction fetch module 103 is configured to fetch a first memory instruction based on the generated instruction item. The instruction injection page table requirement retrieval module 104 is configured to retrieve an instruction injection page table requirement for the first memory instruction, the instruction injection page table requirement including injecting a page table error for the first memory instruction or not injecting a page table error for the first memory instruction. The second instruction fetch module 105 is configured to fetch a second target instruction based on the instruction injection page table requirement and the first memory access instruction, the second target instruction being used to verify whether the access page table translation table is abnormal.
It should be noted that in the embodiment of the present disclosure, the verification system 100 for a processor may include more or less modules, and the connection relationship between the respective modules is not limited and may be determined according to actual requirements. The specific constitution of each module is not limited. Regarding the technical effects of the verification system 100 for a processor, reference may be made to the technical effects of the verification method for a processor provided in the above-described embodiments of the present disclosure, and the description thereof will not be repeated here.
Each module in the above embodiments may be configured as software, hardware, firmware, or any combination thereof, respectively, that performs a specific function. For example, these modules may correspond to application specific integrated circuits, to pure software code, or to a combination of software and hardware.
It should be noted that, although the authentication system for a processor is described above as being divided into modules for executing the respective processes, it is apparent to those skilled in the art that the processes executed by the respective modules may be executed without any specific division of the modules or without explicit demarcation between the respective modules.
Fig. 6 is a schematic structural diagram of an electronic device according to at least one embodiment of the present disclosure. The terminal devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and the like, and stationary terminals such as digital TVs, desktop computers, and the like. The electronic device shown in fig. 6 is merely an example and should not be construed to limit the functionality and scope of use of the disclosed embodiments.
For example, as shown in fig. 6, in some examples, the electronic apparatus 200 includes a processing device (e.g., a central processor, a graphics processor, etc.) 201 that can perform the verification method as described above according to a program stored in a read-only memory (ROM) 202 or a program loaded from a storage device 208 into a Random Access Memory (RAM) 203. In the RAM203, various programs and data required for the operation of the computer system are also stored. The processing device 201, ROM202, and RAM203 are connected to each other through a bus 204. An input/output (I/O) interface 205 is also connected to bus 204.
For example, the following components may be connected to the I/O interface 205: input devices 206 including, for example, a touch screen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; an output device 207 including a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 208 including, for example, magnetic tape, hard disk, etc.; and a communication device 209 including a network interface card such as a LAN card, a modem, or the like. The communication means 209 may allow the electronic device 200 to perform wireless or wired communication with other devices to exchange data, performing communication processing via a network such as the internet. The drive 210 is also connected to the I/O interface 205 as needed. A removable medium 211 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is installed as needed on the drive 210, so that a computer program read therefrom is installed as needed into the storage device 209. While fig. 6 illustrates an electronic device 200 including various means, it is to be understood that not all illustrated means are required to be implemented or included. More or fewer devices may be implemented or included instead.
For example, the electronic device 200 may further include a peripheral interface (not shown), and the like. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning (lighting) interface, etc. The communication means 209 may communicate with networks and other devices by wireless communication, such as the internet, intranets and/or wireless networks such as cellular telephone networks, wireless Local Area Networks (LANs) and/or Metropolitan Area Networks (MANs). The wireless communication may use any of a variety of communication standards, protocols, and technologies including, but not limited to, global system for mobile communications (GSM), enhanced Data GSM Environment (EDGE), wideband code division multiple access (W-CDMA), code Division Multiple Access (CDMA), time Division Multiple Access (TDMA), bluetooth, wi-Fi (e.g., based on the ieee802.11a, ieee802.11b, ieee802.11g, and/or ieee802.11n standards), voice over internet protocol (VoIP), wi-MAX, protocols for email, instant messaging, and/or Short Message Service (SMS), or any other suitable communication protocol.
For example, the electronic device may be any device such as a mobile phone, a tablet computer, a notebook computer, an electronic book, a game console, a television, a digital photo frame, a navigator, or any combination of electronic devices and hardware, which is not limited in the embodiments of the present disclosure.
For example, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a non-transitory computer readable medium, the computer program comprising program code for performing the method shown in the flow chart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication means 209, or from the storage means 208, or from the ROM 202. The above-described authentication function for the processor defined in the method of the embodiment of the present disclosure is performed when the computer program is executed by the processing device 201.
It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In an embodiment of the present disclosure, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. Whereas in embodiments of the present disclosure, the computer-readable signal medium may comprise a data signal propagated in baseband or as part of a carrier wave, with computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.
In some implementations, the clients, servers may communicate using any currently known or future developed network protocol, such as HTTP (HyperText TransferProtocol ), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), the internet (e.g., the internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed networks.
The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.
It should be noted that, in the embodiments of the present disclosure, specific functions and technical effects of the electronic device 200 may refer to the above description about the verification method for the processor, which is not repeated herein.
The following points need to be described:
(1) The drawings of the embodiments of the present disclosure relate only to the structures to which the embodiments of the present disclosure relate, and reference may be made to the general design for other structures.
(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.
The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.
Claims (13)
1. A method of authentication for a processor, comprising:
acquiring a page conversion table for access operation;
obtaining at least one generated instruction item, wherein the at least one generated instruction item comprises an operation mask determined by a value in a mask register and at least one instruction attribute item for the memory access operation;
acquiring a first access instruction based on the at least one generated instruction item;
obtaining an instruction injection page table requirement for the first access instruction, wherein the instruction injection page table requirement comprises either injecting a page table error for the first access instruction or not injecting a page table error for the first access instruction;
and acquiring a second target instruction based on the instruction injection page table requirement and the first access instruction, wherein the second target instruction is used for verifying whether the access to the page table conversion table is abnormal.
2. The authentication method of claim 1, further comprising:
the mask register is initialized to determine a value in the mask register.
3. The authentication method of claim 2, wherein initializing the mask register comprises:
a first random variable is obtained, and the mask register is initialized through a data storage mask register instruction by using the first random variable.
4. The authentication method of claim 3, wherein obtaining the page translation table for the memory access operation comprises:
a plurality of first page tables are created such that portions of the plurality of first page tables serve as reserved address spaces to obtain the page translation table for the memory access operation, wherein the reserved address spaces are configured to generate page table exceptions when pointed to an access.
5. The authentication method of claim 1, wherein the at least one instruction attribute item comprises at least one of:
the instruction type of the access operation, the source operand of the access, the destination operand of the access, the size of the access range, the access base address, the access address offset, the access index and the granularity of the access element.
6. The authentication method of claim 1, wherein based on the at least one generated instruction item, obtaining a first memory instruction comprises:
and carrying out randomization on the at least one generated instruction item by utilizing a randomization function to acquire the first memory access instruction.
7. The authentication method of claim 1, wherein fetching instruction injection page table requirements for the first access instruction comprises:
a second random variable is obtained and based on the second random variable, the first memory instruction is caused to be randomly injected with or without a page table error.
8. The authentication method of claim 5, further comprising:
and acquiring a valid bit signal of the mask register based on the size of the access range and the granularity of the access element in the first access instruction, wherein the valid bit signal of the mask register is used for determining whether the first access instruction supports exception suppression.
9. The validation method of claim 8, wherein fetching a second target instruction based on the instruction injection page table requirement and the first memory access instruction comprises:
responding to the instruction injection page table requirement that a page table error is not injected into the first access instruction, and acquiring the second target instruction which is normal; or alternatively, the process may be performed,
and responding to the instruction injection page table requirement to inject a page table error into the first access instruction, and acquiring the abnormal second target instruction.
10. The validation method of claim 9, wherein the fetching of the second target instruction of the exception in response to the instruction injection page table requirement being a page table error for the first access instruction comprises:
Responding to the instruction injection page table requirement to inject a page table error to the first access instruction, adjusting the access address offset and/or the access base address, and pointing to a reserved address space in the page conversion table, wherein the reserved address space is configured to generate a page table exception when pointed to access;
acquiring a page table abnormality influence result based on the valid bit signal of the mask register;
responding to the page table abnormality influence result to be the non-influence, and acquiring the abnormal second target instruction; or, in response to the page table exception effect result being an effect, fetching the page table exception pre-processing subroutine and fetching the second target instruction of the exception.
11. A verification system for a processor, comprising:
the page conversion table acquisition module is configured to acquire a page conversion table for access operation;
a generate instruction item acquisition module configured to acquire at least one generate instruction item, wherein the at least one generate instruction item includes an operation mask determined by a value in a mask register and at least one instruction attribute item for the memory access operation;
a first instruction acquisition module configured to acquire a first memory instruction based on the at least one generated instruction item;
An instruction injection page table requirement acquisition module configured to acquire an instruction injection page table requirement for the first memory instruction, wherein the instruction injection page table requirement includes injecting a page table error for the first memory instruction or not injecting a page table error for the first memory instruction;
and a second instruction acquisition module configured to acquire a second target instruction based on the instruction injection page table requirement and the first access instruction, wherein the second target instruction is used for verifying whether accessing the page table conversion table is abnormal.
12. An electronic device, comprising:
a processor and a memory are provided for the processor,
wherein the memory has stored thereon a computer program which, when executed by the processor, implements the authentication method of any of claims 1 to 10.
13. A computer readable storage medium, wherein the storage medium has stored therein a computer program which, when executed by a processor, implements the authentication method of any one of claims 1 to 10.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117076330A (en) * | 2023-10-12 | 2023-11-17 | 北京开源芯片研究院 | Access verification method, system, electronic equipment and readable storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117076330A (en) * | 2023-10-12 | 2023-11-17 | 北京开源芯片研究院 | Access verification method, system, electronic equipment and readable storage medium |
| CN117076330B (en) * | 2023-10-12 | 2024-02-02 | 北京开源芯片研究院 | Access verification method, system, electronic equipment and readable storage medium |
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