CN116667849A

CN116667849A - Background calibration of digital-to-analog converters

Info

Publication number: CN116667849A
Application number: CN202310167565.8A
Authority: CN
Inventors: G·恩格尔; P·S·维金斯
Original assignee: Analog Devices Inc
Current assignee: Analog Devices Inc
Priority date: 2022-02-28
Filing date: 2023-02-27
Publication date: 2023-08-29

Abstract

The present disclosure relates to background calibration of digital-to-analog converters. Techniques for background calibration of digital-to-analog converters (DACs) with minimal processing overhead. Errors between bits may be calibrated using a single frequency bin. The low frequency feedback path may be included in a low frequency low power ADC to determine the error signal present in the calibration window. When this error signal is minimized, the bits are calibrated. The background calibration technique described provides very efficient and optimal static and dynamic error calibration at the DAC output.

Description

Background calibration of digital-to-analog converters

Priority claim

The present application claims priority from U.S. provisional patent application Ser. No. 63/314,614, entitled "background calibration of digital TO analog converter (BACKGROUND CALIBRATION OF DIGITAL-TO-ANALOG CONVERTERS)" filed by Gil Engel et al at 28, 2, 2022, which is incorporated herein by reference in its entirety.

Background

Integrated circuits process electrical signals for a rich electronic application. The data converter is an important component of the electronic device responsible for converting signals between the digital and analog domains. However, a circuit inside the data converter or a circuit driving the data converter is not perfect, and thus the converted output may not be perfect. The imperfections or non-idealities may cause unwanted noise or spikes (spurs) to appear at the output and degrade the performance of the data converter. Noise or spikes may even affect other parts of the signal chain if not removed or calibrated.

Disclosure of Invention

The present disclosure describes various techniques to implement background calibration of digital-to-analog converters (DACs) with minimal processing overhead. Errors between bits may be calibrated using a single frequency bin. The low frequency feedback path may be included in a low frequency low power ADC to determine the error signal present in the calibration window. When the error signal is minimized, the bits are calibrated. The background calibration technique described provides very efficient and optimal static and dynamic error calibration at the DAC output.

In some aspects, the present disclosure relates to a background method for measuring non-idealities of a DAC, the DAC having a plurality of DAC cells and a plurality of redundant DAC cells, the outputs of the DAC cells being summed to produce an analog output of the DAC, the method comprising: providing digital data to the DAC cell to produce an output spectrum at an analog output of the DAC; generating a first digitally encoded calibration stimulus having a first baseband energy at a first frequency window; scaling the first digitally encoded calibration stimulus by a first weighting factor and providing a first weighted calibration stimulus to a first subset of the redundant DAC cells while the DAC cells are producing the output spectrum to produce a first analog tone; scaling the first digitally encoded calibration stimulus by a first weighting factor and providing a first weighted calibration stimulus to a first subset of the redundant DAC cells while the DAC cells are producing the output spectrum to produce a first analog tone, wherein the second weighting factor is selected such that the first analog tone and the second analog tone have opposite polarities; in an analog output of the DAC, an error tone at the first frequency bin generated by the first analog tone and the second analog tone is detected.

In some aspects, the present disclosure relates to a background method for measuring non-idealities of a DAC, the DAC having a plurality of DAC cells and a plurality of redundant DAC cells, the outputs of the DAC cells being summed to produce an analog output of the DAC, the method comprising: generating a first digitally encoded calibration stimulus having a first baseband energy at a first frequency window; scaling the first digitally encoded calibration stimulus by a first weighting factor to produce a first weighted calibration stimulus; providing the first weighted calibration stimulus to the redundant DAC cell to generate a first analog tone; providing digital data and an inverse version of the first weighted calibration stimulus to the DAC unit to produce an output spectrum and a first analog tone while providing the first weighted calibration stimulus to the redundant DAC unit; and detecting error tones produced by the first analog tone and the second analog tone in the analog output of the DAC.

In some aspects, the present disclosure relates to a background method for measuring one or both of static errors between DAC cells and timing errors between DAC cells of a multi-gigabit per second DAC, the DAC having a plurality of DAC cells and a plurality of redundant DAC cells, the outputs of the DAC cells summed to produce an analog output of the DAC, the method comprising: providing digital data to the DAC unit to generate an output spectrum at the analog output of the DAC; generating a first digitally encoded calibration stimulus having a first baseband energy at a first frequency window; scaling the first digitally encoded calibration stimulus by a first weighting factor and providing a first weighted calibration stimulus to a first subset of the redundant DAC cells while the DAC cells are producing the output spectrum to produce a first analog tone; scaling the first digitally encoded calibration stimulus by a first weighting factor and providing a first weighted calibration stimulus to a first subset of the redundant DAC cells while the DAC cells produce the output spectrum to produce a first analog tone, wherein the second weighting factor is selected such that the first analog tone and the second analog tone have opposite polarities, wherein summing the first analog tone and the second analog tone produces the error tone; and detecting, in the analog output of the DAC, an error tone at the first frequency bin produced by the first analog tone and the second analog tone by detecting energy in the analog output of the DAC at the first frequency bin.

In some aspects, the present disclosure relates to a digital-to-analog converter (DAC) with background calibration, the digital-to-analog converter comprising: a plurality of DAC units for receiving digital data and generating an output frequency spectrum; an excitation generator to generate a first digitally encoded calibration excitation having a first baseband energy at a first frequency window; one or more reference DAC cells for receiving a weighted version of the first digitally encoded calibration stimulus to generate a first analog tone; one or more calibration DAC units to receive a further weighted version of the first digitally encoded calibration stimulus to generate a first analog tone, wherein the second analog tone has an opposite polarity to the first analog tone; wherein the outputs of the DAC unit, the reference DAC unit and the calibration DAC unit are summed to form an analog output of the DAC; a sensing ADC at the analog output of the DAC to sense error tones produced by the first analog tone and the second analog tone.

In some aspects, the present disclosure relates to a digital-to-analog converter (DAC) with background calibration, the digital-to-analog converter comprising: an excitation generator to generate a first digitally encoded calibration excitation having a first baseband energy at a first frequency window; a plurality of DAC cells to receive digital data and a weighted version of the first digitally encoded calibration stimulus and to generate an output spectrum and a first analog tone at an analog output of the DAC; one or more calibration DAC units to receive a further weighted version of the first digitally encoded calibration stimulus to generate a first analog tone, wherein the second analog tone has an opposite polarity to the first analog tone; wherein the outputs of the DAC cell and the calibration DAC cell are summed to form an analog output of the DAC; and a sensing ADC at the analog output of the DAC to sense an error tone generated by the first analog tone and the second analog tone.

Drawings

In order to provide a more complete understanding of the present disclosure, and features and advantages thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts, and in which:

FIG. 1 is an exemplary segmented digital-to-analog converter (DAC) according to some embodiments of the present disclosure;

FIG. 2 is an exemplary DAC with background calibration using a reference DAC unit and a calibration DAC unit according to some embodiments of the present disclosure;

FIG. 3 is an exemplary DAC with background calibration relative to a master DAC according to some embodiments of the present disclosure;

FIG. 4 is another exemplary DAC with background calibration relative to the master DAC according to some embodiments of the present disclosure; and

fig. 5 is an exemplary DAC with background calibration and correction according to some embodiments of the present disclosure.

Detailed Description

Overview of the invention

The DAC maps a digital word (digital word) to an analog output. The DAC bits may have amplitude and timing errors (timing errors). Such errors (sometimes referred to as "non-idealities") can lead to dynamic range distortion and degradation in the DAC. Background calibration of static and dynamic errors (dynamic errors) and a flexible method of generating test patterns as stimuli (stinmulus) are described.

Basic knowledge of DAC

Real-world analog signals (real-world analog signal), such as temperature, pressure, sound or images, are typically converted into digital representations (digital representation) that are easy to process in modern digital systems. In many systems, this digital information must be converted back to analog form to perform some real world function. The circuit performing this step is a DAC, and the output of the circuit can be used to drive various devices. Speakers, video displays, motors, mechanical servos, radio Frequency (RF) transmitters, and temperature controls are just a few different examples.

A DAC is a circuit, device, or system that can generate a quantized (discrete step) analog output in response to a digital input code. Digital inputs are generated in the digital domain (e.g., from transistor logic (TTL), emitter-coupled logic (ECL), complementary Metal Oxide Semiconductor (CMOS) circuits or Low Voltage Differential Signaling (LVDS), digital logic, processors, etc.). The DAC converts the digital input to an analog output. The analog output of the DAC may be a voltage or a current. In some cases, the digital input may include binary coded bits or thermometer coded bits. The bits of the digital input are provided to drive or control circuitry in the DAC to produce an analog output.

To produce an output, the reference quantity (reference quantity) is divided into binary and/or linear fractions. One or more DAC cells are implemented for each of those scores. The digital inputs drive the switches of the individual DAC cells with appropriate weights corresponding to those scores. The respective portions of the digital inputs drive the respective DAC cells to deliver an aggregate output (aggregate output) of the DAC cells representing the digital inputs. The DAC cell may include a current source, a voltage source, a resistor, a capacitor, and the like. The DAC cell may be driven by a digital input (i.e., a digital input code) to produce an analog output. In some embodiments, the outputs of the DAC units are summed or combined to produce a collective output.

In some cases, the segmented DAC may use different circuit architectures and/or encodings for different segments of the digital input. In a segmented architecture, the full resolution (full resolution) of the converter is distributed across two or more sub-DACs, which architecture can be used for both current output DACs and voltage output DACs. The sub-DACs of the entire DAC need not have the same resolution. In some cases, redundant circuitry may also be provided in a DAC in which additional circuitry or DAC cells are included in the design.

FIG. 1 shows a schematic diagram according to the present disclosureThe exemplary segmented DAC 100 of some embodiments. As shown in fig. 1, the digital input signal or digital input code may be provided to a segmentation unit that divides the digital input signal/code into its most significant bits d _MSB Intermediate significant bit d _ISB And least significant bit d _LSB . Most significant bit d _MSB May be provided to decoder block 102. Intermediate significant bit d _ISB May be provided to decoder block 104. Decoder block 102 and decoder block 104 may use the most significant bit d _MSB And intermediate significant bit d _ISB Decoding from binary to thermometer coding so that the unitary DAC units of MSB and ISB sections (i.e., DAC units having the same bit weight) can decode the most significant bit d _MSB And intermediate significant bit d _ISB Converted to the respective analog outputs of the MSB section and the ISB section. Least significant bit d _LSB May be provided to delay block 106 (to provide or simulate the delay of decoder blocks 102 and 104). The binary weighted DAC unit can use the least significant bit d _LSB Converted to an analog output of the LSB segment. Assume that the full resolution of the segmented DAC 100 is b=b _MSB +B _ISB +B _LSB And there is B for the most significant bit section _MSB Number of bits, B exists for the middle significant bit _ISB Number of bits, B exists for the least significant bit _LSB A number of bits. The unary DAC unit 108 of the most significant bit section may comprise at least 2 ^BMSB-1 A plurality of DAC units, each of the DAC units having the same (ideal) bit weight w _MSB ＝2 ^(BLSB+BISB) . The unitary DAC unit 110 of the middle significant bit section may comprise at least 2 ^BISB-1 A plurality of DAC units, each of the DAC units having the same (ideal) bit weight w _ISB ＝2 ^BLSB . Binary DAC unit 112 may have B _LSB A number of DAC units having different binary bit weights w _LSB[k] ＝2 ^k ，k＝[0:B _LSB -1]. The different segments produce respective analog outputs based on respective digital inputs to the different segments. Combiner 114 combines the respective outputs of the segments with DAC cells (e.g., segments with unitary DAC cells 108, unitary DAC cells 110, or binary DAC cells 112),Summed or added to produce the analog output of the entire DAC 100.

In some cases, the decoder blocks 102 and 104 (one or both) may implement additional logic to shuffle the unitary DAC cells 108 and 110 to average out the mismatch between the cells, thereby reducing distortion at the analog output.

A segmented DAC (such as the segmented DAC shown in fig. 1) balances the accuracy and design complexity of the converter. One benefit of segmentation is to reduce the number of resistors (or current sources) required to achieve a given resolution by allowing different DAC architectures to be used for different sections of the digital input code, thereby allowing for smaller die sizes. Thus, a high resolution DAC typically requires segmentation. To achieve high speed, a current steering DAC cell (current-steering DAC cell) is typically used.

Errors in DAC

Segmented DACs or overall DACs are not perfect and calibrating a unitary or binary DAC cell presents challenges to the designer. As with many other devices fabricated using complex manufacturing processes, various imperfections/non-idealities may affect the performance of the DAC.

One example includes circuit imperfections that affect the performance of individual components of a DAC (referred to herein as a "DAC cell"). The imperfections may be due to manufacturing variations, commonly referred to as "static mismatch" or "DC error". For example, static mismatch may be caused by the size of the devices (e.g., resistors, current sources, transistors) being different from the ideal size. Thus, the "bit weights" of the DAC cells may deviate from the ideal value, resulting in an "amplitude error".

Another example includes timing errors, commonly referred to as "AC errors" (AC stands for alternating current) or "dynamic errors", which may be caused by, for example, frequency jitter, switching mismatch, and driver mismatch. The timing errors may be global (e.g., associated with a global frequency signal), or they may be local to a particular DAC cell. When a transition in the analog output of the DAC cell occurs before or relative to the ideal time, or the transition deviates from the ideal transition, a timing error may result in an "erroneous" amount of "bit weight" being delivered to the analog output. In some cases, frequency jitter may affect the time that a particular DAC cell is turned on relative to a reference DAC cell (i.e., when two DAC cells are expected to be turned on simultaneously, the two DAC cells are not turned on simultaneously). In that case, the DAC cells are turned on and off earlier or later than ideal time, resulting in errors in the analog output. In some cases, the DAC cell itself may have a transition asymmetry in which the rising and falling of the analog output behave differently. For example, transition asymmetry due to switch mismatch (e.g., mismatch of a pair of differential switches (differential switch) responsible for directing current to a particular one of the outputs) may affect the performance of a particular DAC cell, resulting in rising and falling transitions behaving differently. In another example, transition asymmetry due to driver mismatch (e.g., timing mismatch in signal paths driving a pair of differential switches responsible for directing current to a particular one of the outputs) may also affect the performance of the particular DAC cell, again resulting in rising and falling transitions deviating from ideal values. The timing related imperfections may also lead to duty cycle errors (duty cycle error) in which the DAC cells are turned "on" for a period of time that differs from the ideal period of time (e.g., too long or too short compared to the reference or ideal period of time).

Another example includes drift, such as thermal drift, aging, etc., that changes the characteristics of the device over time and deviates the device from ideal.

Many of the examples mentioned above result in distortion at the analog output, affecting the performance of the entire DAC. For some errors, designers have chosen to use larger devices to reduce some of the errors. However, increasing the device size and thus increasing area and power consumption is not always desirable. Designers do not attempt to add devices, but rather address performance issues through calibration.

Adverse aspects of certain calibration techniques

Various schemes have been proposed to measure and calibrate errors in DACs. For example, a square wave of a particular frequency and an inverse version of such a square wave may be used as calibration stimulus to control (1) the reference DAC cell and (2) the calibration DAC cell (and more calibration cells if the desired weights are pre-implemented to balance the reference DAC cell), and the analog output may be measured to determine timing skew. However, this approach may be limited and may be impractical for some applications. One reason that a square wave is undesirable as a calibration stimulus is that it can generate even harmonics (even harmonics) at the output of the DAC. Such even harmonics and/or images thereof may affect the actual signal being generated by the DAC and may severely degrade the performance of the DAC if the square wave is applied in the background (i.e., during normal operation of the DAC).

In some techniques, uncorrelated pseudo-random sequences are used as calibration stimulus to a reference DAC cell and a calibration DAC cell. Although such a sequence does not produce a tone at the output, a broadband observation analog-to-digital converter (ADC) is required to observe the analog output of the DAC, and the digital processing to extract the errors exposed using such excitation is too computationally intensive to be practical.

In some techniques, delta-sigma patterns may be generated as calibration stimuli. However, delta-sigma converters used to generate graphics have feedback loops (feedback loops) and are too slow for some applications. Furthermore, those techniques are not necessarily suitable for background calibration.

Extracting errors in the background

To calibrate static or dynamic errors within the DAC in the background, one or more reference bits (e.g., one or more reference DAC cells) may be excited with a pattern (or excitation) to produce a reference tone (reference tone) at the analog output of the DAC. Each reference DAC cell will receive the same pattern. The same pattern may be applied to one or more calibration bits (e.g., one or more calibration DAC cells) to generate a calibration tone having an opposite polarity to the reference tone.

The goal is to generate a reference tone and a calibration tone that can cancel each other if there is no mismatch between the reference bit and the calibration bit. One of the applied graphics may be reversed (e.g., scaled by a negative amount). One or more of the patterns may be weighted to ensure that the reference tone and the calibration tone are ideally the same size. Each calibration DAC cell will receive the same pattern.

If the reference DAC cell and the calibration DAC cell match each other (or have no error relative to each other), the reference tone and the calibration tone are intended to have the same magnitude but opposite polarities. If there is a mismatch, an error tone is generated and can be observed to compensate/correct the mismatch. Depending on the bit weights of the reference DAC cells and the bit weights of the calibration DAC cells, the patterns may be weighted accordingly to produce reference tones and calibration tones of similar size.

Note that in parallel, the normal DAC cell operates to convert digital data to the desired analog output spectrum (as in normal operation), and the reference DAC cell and the calibration DAC cell are redundant DAC cells of the DAC that receive the pattern at the same time as the normal DAC cell. There are typically redundant DAC cells located in the DAC architecture and/or a set of (redundant) DAC cells that can produce a droop output. In many applications, the calibration technique is generated during normal operation of the DAC, and the error tones do not have a significant effect on the DAC. The ability to perform the calibration technique in the background is due to the very small signal amplitude of the error tones.

Once the outputs of the DAC cells are summed, the analog output of the DAC will have an error tone resulting from the summation of the reference tone and the calibration tone. The error tones will correspond to difference errors between the one or more reference bits and the one or more calibration bits. Since the reference tone, the calibration tone, and the resulting error tone all occupy a single frequency bin, processing/examining the energy at that single frequency bin can extract the difference/mismatch error.

In some cases, the DAC may be iteratively modified (in the digital or analog domain) using a least mean square algorithm or a binary search (binary search) algorithm to minimize the amplitude of the error tone. Thus, the algorithm may drive the discrepancy/mismatch error to be smaller and smaller.

To expose the static error, the pattern preferably causes the DAC cell to produce a tone with fundamental energy (fundamental energy) (or zero frequency) at or near DC. To expose the dynamic error, the pattern preferably causes the DAC cell to produce a tone having fundamental energy at or near Nyquist.

The pattern need not be a delta-sigma generated pattern, as it may be impractical to provide an excitation generator that includes a delta-sigma converter with a feedback loop. Instead, the pattern may be a 1-bit sequence that approximates a sine wave, such that DAC cells excited by the 1-bit sequence will output a tone having fundamental energy at the signal frequency window. The component of the error tone not associated with the fundamental tone (fundamental tone) is even lower than the fundamental energy.

As calibration progresses, the error tones become smaller and smaller, thereby reducing the impact of the error tones on the normal operation of the DAC.

Exemplary DAC for background calibration Using redundant DAC units as reference DAC Unit and calibration DAC Unit

Fig. 2 is an exemplary DAC with background calibration using a reference DAC unit and a calibration DAC unit according to some embodiments of the disclosure. The DAC has a (normal or main) DAC cell 202 and a redundant DAC cell. The redundant DAC cells are not used to generate the desired output spectrum (e.g., for a specified period of time). The same cells may be used to produce the desired output spectrum at different points in time, and some of the DAC cells 202 become redundant DAC cells (e.g., role swap or rotation) at that point in time. A subset of the redundant DAC cells is labeled as reference DAC cells 204 and another subset of the redundant DAC cells is labeled as calibration DAC cells 206. The outputs of the DAC cells of the DAC are summed to form the final analog output.

The normal DAC unit 202 receives digital data D _data [k]And operates normally to produce the desired output spectrum f (t). Digital data D _data [k]And/or D _data [k]May be shuffled to achieve dynamic component matching such that the mismatch in DAC cell 202 is averaged.

Generating calibration stimulus D _cal [k]For calibration. Before providing the calibration stimulus to each reference DAC unit 204, a first weighting factor w may be passed ₁ To a certain proportionScaling the calibration stimulus. The calibration stimulus causes the reference DAC unit 204 to generate a first analog tone u ₁ (t). At the point of calibrating the excitation D _cal [k]Before being provided to each calibration DAC unit, the first weighting factor w can be used for ₂ The calibration stimulus is scaled. The calibration stimulus causes the calibration DAC unit 206 to generate a first analog tone u ₂ (t)。

The (weighted) calibration stimulus is applied in the background to the reference DAC unit 204 and the calibration DAC unit 206, while the digital data is applied to the normal DAC unit 202.

An appropriate number of reference DAC cells 204 and an appropriate number of calibration DAC cells 206 may be selected to receive the calibration stimulus. Selecting a first weighting factor w ₁ And a second weighting factor w ₂ So that the first analog tone u ₁ (t) and a second analog tone u ₂ (t) have substantially the same size and opposite polarity. When the first analog tone u ₁ (t) and a second analog tone u ₂ (t), when summed, produces an error tone e (t) that represents the difference between the reference DAC unit 204 and the calibration DAC unit 206.

Since the outputs of the DAC cells are summed, the analog output has the desired output spectrum and error tones: f (t) +e (t).

Exemplary DAC for background calibration Using redundant DAC units as calibration DAC units

Instead of comparing subsets of redundant DAC cells to each other (as shown in fig. 3), one or more redundant DAC cells are compared to a normal DAC cell (i.e., the main DAC). This variation creates another background calibration technique that can be performed while the DAC is operating. One or more calibration bits may be excited with the calibration tone and the calibration tone itself or its derivative (derivative) may be subtracted from the autonomous DAC output spectrum signal path. If there is no error between the calibration bit and the main DAC cell, no error tones will occur at the analog output of the DAC. One advantage of this technique is that the number of redundant DAC cells required for the calibration technique is reduced.

Fig. 3 is an exemplary DAC with background calibration relative to a master DAC according to some embodiments of the disclosure. The DAC has a (normal or main) DAC cell 302 and a redundant DAC cell 304. The redundant DAC cells are not used to produce the desired output spectrum. The redundant DAC cell 304 is used as a calibration DAC cell. The outputs of the DAC cells of the DAC are summed to form the final analog output.

Generating calibration stimulus D _cal [k]For calibration. Before providing the calibration stimulus to each calibration DAC unit 304, a weighting factor W may be used ₁ The calibration stimulus is scaled. The calibration stimulus causes the calibration DAC unit 206 to generate an analog tone u ₂ (t)。

Providing a weighted calibration stimulus D _cal [k]*w ₁ Digitally modifying digital data D _data [k]. If the bit weights of the calibration DAC cell 304 do not match the cells in the main DAC cell 302, the calibration stimulus may be scaled by different weighting factors, where appropriate. In the example shown, from D _data [k]The weighted calibration stimulus D is subtracted _cal [k]*w ₁ . The normal DAC unit 302 receives the modified digital data D _data [k]-(D _cal [k]*w ₁ ) And operates normally to produce a desired output spectrum f (t) and another analog tone u ₁ (t) or f (t) +u ₁ (t). The one or more DAC cells 302 are thus effectively used as one or more reference DAC cells.

DAC unit 302 and/or modified digital data D _data [k]-(D _cal [k]*w ₁ ) May be shuffled to achieve dynamic element matching such that the mismatch in DAC cell 302 is averaged.

Applying the calibration stimulus in the background to the calibration DAC unit 304 while the modified digital data D _data [k]-(D _cal [k]*w ₁ ) Applied to the normal DAC cell 302.

An appropriate number of calibration DAC cells 304 may be selected to receive the calibration stimulus. Selecting a weighting factor w ₁ And possibly another weighting factor such that the first analog tone u ₁ (t) and a second analog tone u ₂ (t) have substantially the same size and opposite polarity. When the first analog tone u ₁ (t) and a second analog tone u ₂ (t) when summed, produce a representation of the main DAC unit 302 andthe error tone e (t) of the difference between DAC cells 304 is calibrated.

Exemplary DAC for Multi-tone background calibration Using redundant DAC units as calibration DAC units

Fig. 4 is another exemplary DAC with background calibration relative to a master DAC according to some embodiments of the disclosure. The DAC has a (normal or main) DAC cell 402, a first redundant DAC cell 404 and a second redundant DAC cell 406. The redundant DAC cells are not used to produce the desired output spectrum. The first redundant DAC cell 404 and the second redundant DAC cell 406 are used as calibration DAC cells to receive different calibration stimuli having fundamental energy in different frequency windows. The outputs of the DAC cells of the DAC are summed to form the final analog output. Errors of different calibration DAC cells can be extracted simultaneously.

Generating a first calibration stimulus D _cal1 [k]For calibration. At the time of exciting the first calibration D _cal1 [k]Before being provided to each calibration DAC unit 404, a weighting factor w may be used ₁ The first calibration stimulus is scaled. The first calibration stimulus causes the calibration DAC unit 404 to generate an analog tone u ₂ (t)。

Generating a first calibration stimulus D _cal2 [k]For calibration, wherein the fundamental energy is excited D with a first calibration _cal1 [k]In different frequency windows. At the time of exciting the second calibration D _cal2 [k]Before being provided to each calibration DAC unit 406, the calibration DAC units may be weighted by another weighting factor w ₂ To scale the second calibration stimulus. The second calibration stimulus causes the calibration DAC unit 406 to generate another analog tone u ₄ (t)。

Providing a first weighted calibration stimulus D _cal1 [k]*W ₁ And a second weighted calibration stimulus D _cal2 [k]*W ₂ Digitally modifying digital data D _data [k]. If the bit weights of the calibration DAC cells 404/406 do not match the cells in the main DAC cell 402, the corresponding calibration stimulus may be scaled by different weighting factors, where appropriateAnd (5) placing. In the example shown, from D _data [k]Subtracting the first weighted calibration stimulus D _cal1 [k]*W ₁ And a second weighted calibration stimulus D _cal2 [k]*w ₂ . The normal DAC unit 402 receives the modified digital data D _data [k]-(D _cal1 [k]*w ₁ )-(D _cal2 [k]*w ₂ ) And operates normally to produce a desired output spectrum f (t), analog tone u ₁ (t) and another analog tone u ₃ (t) or f (t) +u ₁ (t)+u ₃ (t). The one or more DAC cells 402 are thus effectively used as one or more reference DAC cells.

DAC cell 402 and/or modified digital data D _data [k]-(D _cal1 [k]*w ₁ )-(D _cal2 [k]*w ₂ ) May be shuffled to achieve dynamic element matching such that the mismatch in DAC cell 402 is averaged.

The first calibration stimulus is applied to the calibration DAC unit 404 and the second calibration stimulus is applied to the calibration DAC unit 406 in the background while the modified digital data D _data [k]-(D _cal1 [k]*w ₁ )-(D _cal2 [k]*w ₂ ) Applied to the normal DAC cell 402.

An appropriate number of calibration DAC cells 404 may be selected to receive the calibration stimulus. Selecting a weighting factor W ₁ And possibly another weighting factor, such that the tone u is simulated ₁ (t) and analog tone u ₂ (t) have substantially the same size and opposite polarity. When simulating tone u ₁ (t) and analog tone u ₂ (t) when summed, produces an error tone e representing the difference between the main DAC unit 402 and the calibration DAC unit 404 ₁ (t)。

An appropriate number of calibration DAC cells 406 may be selected to receive the calibration stimulus. Selecting a weighting factor w ₂ And possibly another weighting factor, such that the tone u is simulated ₃ (t) and analog tone u ₄ (t) have substantially the same size and opposite polarity. When the first analog tone u ₃ (t) and analog tone u ₄ (t) when summed, produces an error tone e representing the difference between the main DAC unit 402 and the calibration DAC unit 406 ₂ (t)。

Since the outputs of the DAC cells are summed, the analog output has the desired output spectrum and two error tones: f (t) +e ₁ (t)+e ₂ (t)。

Exemplary DAC with background calibration and correction

Fig. 5 is an exemplary DAC with background calibration and correction according to some embodiments of the present disclosure. DAC 502 shows any of the DACs seen in fig. 2-4. Regarding DAC 502, a stimulus generator 504, a sensing ADC 506, and error extraction logic 508 are provided. The excitation generator 504 may generate one or more digitally encoded calibration excitation as described herein. Because the error tones are in only a single frequency bin, sensing ADC 506 may be bandwidth limited (not necessarily a wideband ADC). Error extraction logic 508 may observe the energy in the frequency window (which represents the error in the calibrated DAC cell) and perform a correction to reduce the observed energy. One way to perform correction is to use the distortion logic 510 to distort the digital data to compensate for errors in the digital domain. Another way to perform the correction is to tune the circuitry in DAC 502 in the analog domain to compensate for the error.

Variations and implementations

Note that the activities discussed above with reference to the figures apply to any integrated circuit involving background calibration of DAC cells of a DAC. The technique may be repeated by selecting certain DAC cells as calibration DAC cells. The embodiments described herein may be used for background calibration of DACs with different architectures. Preferably, embodiments are applicable to DACs that correspond to individual components or cells controlling the input bit lines summing directly at the output, as current steering or potentially parallel capacitor DACs (which are in fact most signal processing DACs). Other architectures such as resistor strings (precision applications) or pipelined capacitive DACs perform partial summation before reaching the output and are therefore unsuitable for this approach.

The performance of the DAC, i.e. a measure of distortion at the output, is critical for some applications. The calibration scheme of the present disclosure provides a flexible and efficient way to measure errors in the background (i.e., when the main DAC is processing real-time signals). In certain contexts, features discussed herein may be applied to medical systems, scientific instruments, wireless and wired communications, radar, industrial process control, audio and video equipment, current sensing, instrumentation (which may be highly sophisticated), cable infrastructure, military applications (e.g., radar), and other systems where reducing distortion at the output of a DAC is important to an application.

Portions of the various devices used in the background calibration DAC unit may include digital or circuitry to perform the functions described herein. In some cases, one or more portions of the apparatus may be provided by a processor (e.g., an on-chip processor, an on-chip microprocessor, an on-chip digital signal processor, an off-chip microprocessor, and an off-chip digital signal processor) that is specifically configured to perform the functions described herein. For example, a processor may include one or more application-specific components, or may include programmable logic gates configured to perform the functions described herein. Circuitry may operate in the analog domain, digital domain, or mixed signal domain. In some cases, the processor may be configured to perform the functions described herein by executing one or more instructions stored on a non-transitory computer medium.

In one exemplary embodiment, any number of the circuits in the figures may be implemented on a board of an associated electronic device. The board may be a universal circuit board that may house various components of the internal electronic system of the electronic device and further provide connectors for other interface devices. More specifically, the board may provide electrical connections through which other components of the system may be in electrical communication. Any suitable processor (including digital signal processors, microprocessors, supporting chipsets, etc.), computer-readable non-transitory storage components, etc. may be coupled to the board in a suitable manner based on particular configuration requirements, processing requirements, computer designs, etc. Other components such as external storage, additional sensors, controllers for audio/video displays and peripherals may be attached to the board via cables as plug-in cards or integrated into the board itself. In various embodiments, the functions described herein may be implemented in emulation form as software or firmware running within one or more configurable (e.g., programmable) components arranged in a structure supporting the functions. The software or firmware that provides the emulation can be provided on a non-transitory computer readable storage medium containing instructions that allow the processor to implement those functions.

In another exemplary embodiment, the circuitry of the figures may be implemented as stand-alone modules (e.g., devices having associated components and circuitry configured to perform specific applications or functions), or as plug-in modules in application specific hardware of an electronic device. Note that particular embodiments of the present disclosure may readily be included, in part or in whole, in a system on a chip (SOC) package. SOC refers to ICs that integrate components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed signal and usual RF functions: all of the functions may be provided on a single chip substrate. Other embodiments may include a multi-chip module (MCM) in which a plurality of individual ICs are located within a single electronic package and are configured to closely interact with each other through the electronic package. In various other embodiments, the calibration functions may be implemented in one or more silicon cores in Application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs), and other semiconductor chips.

It must also be noted that all of the specifications, dimensions and relationships (e.g., number of processors, logical operations, etc.) outlined herein are provided for purposes of example and teaching only. Such information may vary considerably without departing from the spirit of the present disclosure and/or examples. The description is applicable to only one non-limiting example, and thus, they should be construed as such. In the foregoing specification, exemplary embodiments have been described with reference to specific processor and/or component arrangements. Various modifications and changes may be made to such embodiments without departing from the scope of the disclosure and/or examples. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Note that for many of the examples provided herein, interactions may be described in terms of two, three, four, or more electronic components. However, this is for clarity and illustration only. It should be appreciated that the system may be incorporated in any suitable manner. Any of the components, modules, and assemblies shown in the figures may be combined in a variety of possible configurations along similar design alternatives, all of which are apparent within the broad scope of this specification. In some cases, it may be easier to describe one or more of the functions of a given set of flows by referencing only a limited number of electronic components. It should be understood that the circuitry of the drawings and its teachings are readily scalable and can accommodate a large number of components, as well as more complex/sophisticated arrangements and configurations. Accordingly, the examples provided should not limit the scope or inhibit the broad teachings of circuits potentially applied to a myriad of other architectures.

Note that in this specification, references to various features (e.g., components, structures, modules, components, steps, operations, features, etc.) are included in "one embodiment," "an example embodiment," "another embodiment," "some embodiments," "various embodiments," "other embodiments," "alternative embodiments," etc., which are intended to mean that any such feature is included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

It is also important to note that the functions related to calibration are only illustrative of some of the possible functions that may be performed by or within the system shown in the figures. Some of the operations may be deleted or removed where appropriate, or considerable modification or change may be made without departing from the scope of the present disclosure. Furthermore, the timing of the operations may be significantly altered. The foregoing operational flows have been provided for purposes of illustration and discussion. The embodiments described herein provide considerable flexibility in that any suitable arrangement, order of occurrence, configuration, and timing mechanism may be provided without departing from the teachings of the present disclosure.

Numerous other changes, substitutions, variations, alterations, and modifications may be ascertained by those skilled in the art and it is intended that the present disclosure encompass all such changes, substitutions, variations, alterations, and modifications as falling within the scope of the present disclosure. Note that all optional features of the apparatus described above may also be implemented with respect to the methods or processes described herein, and that details in the examples may be used anywhere in one or more embodiments.

Examples

Example 1. A background method for measuring non-idealities of a DAC, the DAC having a plurality of DAC cells and a plurality of redundant DAC cells, the outputs of the DAC cells being summed to produce an analog output of the DAC, the method comprising: providing digital data to the DAC unit to generate an output spectrum at the analog output of the DAC; generating a first digitally encoded calibration stimulus having a first baseband energy at a first frequency window; scaling the first digitally encoded calibration stimulus by a first weighting factor and providing a first weighted calibration stimulus to a first subset of the redundant DAC cells while the DAC cells are producing the output spectrum to produce a first analog tone; scaling the first digitally encoded calibration stimulus by a first weighting factor and providing a first weighted calibration stimulus to a first subset of the redundant DAC cells while the DAC cells are producing the output spectrum to produce a first analog tone, wherein the second weighting factor is selected such that the first analog tone and the second analog tone have opposite polarities; in an analog output of the DAC, an error tone at the first frequency bin generated by the first analog tone and the second analog tone is detected.

Example 2. Background method according to example 1, wherein the digital data is shuffled to average non-idealities of the DAC cell.

Example 3. The background method of any of the above examples, wherein the DAC cells are shuffled to average non-idealities of the DAC cells.

Example 4. The background method of any of the above examples, wherein the redundant DAC cells comprise a set of DAC cells having least significant bit weights.

Example 5. The background method of any one of examples 1-4, wherein the first subset of the redundant DAC cells includes a plurality of redundant DAC cells and the second subset of the redundant DAC cells includes a plurality of redundant DAC cells.

Example 6. The background method of any of examples 1-4, wherein the first subset of the redundant DAC cells includes a single redundant DAC cell and the second subset of the redundant DAC cells includes a plurality of redundant DAC cells.

Example 7. The background method of any one of examples 1-4, wherein the first subset of the redundant DAC cells includes a plurality of redundant DAC cells and the second subset of the redundant DAC cells includes a single redundant DAC cell.

Example 8. The background method of any of examples 1-4, wherein the first subset of the redundant DAC cells includes a single redundant DAC cell and the second subset of the redundant DAC cells includes a single redundant DAC cell.

Example 9. The background method of any of the above examples, wherein one or more redundant DAC cells are to receive a portion of the digital data, and a subset of the DAC cells become one or more redundant DAC cells to receive a weighted calibration stimulus.

Example 10. The background method of any of the preceding examples, wherein the first weighting factor and the second weighting factor have opposite polarities.

Example 11. The background method of any of the above examples, wherein the first weighting factor and the second weighting factor have the same size.

Example 12. The background method of any of the preceding examples, wherein the first weighting factor and the second weighting factor have different sizes.

Example 14. The background method of any of the above examples, wherein the first weighting factor and the second weighting factor are selected from the group consisting of: +1, -1, positive weight value, and negative weight value.

Example 15. The background method of any of the preceding examples, wherein summing the first analog tone and the second analog tone produces the error tone.

Example 16. The background method of any of the above examples, wherein detecting the error tone includes detecting energy in an analog output of the DAC at the first frequency window.

Example 15. The background method of any of the above examples, further comprising: the error tones are iteratively minimized by pre-distorting the digital data.

Example 16. The background method of any of the above examples, further comprising: the error tones are iteratively minimized by adjusting the first subset of the redundant DAC cells or the second subset of the redundant DAC cells in the analog domain.

Example 17. The background method of any of the preceding examples, wherein the first digitally encoded calibration stimulus is a 1-bit sequence that approximates a sine wave.

Example 18. The background method of any of the preceding examples, wherein generating the first digitally encoded calibration stimulus involves no feedback.

Example 19. The background method of any of the preceding examples, wherein generating the first digitally encoded calibration stimulus comprises filtering a multi-bit sequence of encoded sine waves to generate a 1-bit sequence of approximation to the sine waves.

Example 20. The background method of any of the preceding examples, wherein generating the first digitally encoded calibration stimulus comprises low pass filtering a multi-bit sequence of encoded sine waves.

Example 21. The background method of any of the preceding examples, wherein the first frequency bin is not within a frequency band of the output spectrum.

Example 22. The background method of any of the preceding examples, wherein selecting the first frequency bin does not interfere with the output spectrum.

Example 23. The background process of example 1, further comprising: generating a first digitally encoded calibration stimulus, the second digitally encoded calibration stimulus having a first baseband energy at a first frequency bin, wherein the second frequency bin is different from the first frequency bin; scaling the second digitally encoded calibration stimulus by a third weighting factor and providing a third weighted calibration stimulus to a third subset of the redundant DAC cells while the DAC cells are producing the output spectrum to produce a third analog tone; scaling the third digitally encoded calibration stimulus by a fourth weighting factor and providing a fourth weighted calibration stimulus to a fourth subset of the redundant DAC cells while the DAC cells are producing the output spectrum to produce a fourth analog tone, wherein the fourth weighting factor is selected such that the third analog tone and the fourth analog tone have opposite polarities; further error tones produced by the third analog tone and the fourth analog tone are detected in the analog output of the DAC.

Example 24. The background method of any of the above examples, wherein the DAC is a multi-gigabit per second DAC.

Example 25. The background method of any of the above examples, wherein the non-ideality factor comprises a static error between DAC cells.

Example 26. The background method of any of the above examples, wherein the non-ideality factor comprises a timing error between DAC cells.

Example 100. A background method for measuring non-idealities of a DAC, the DAC having a plurality of DAC cells and a plurality of redundant DAC cells, outputs of the DAC cells being summed to produce an analog output of the DAC, the method comprising: generating a first digitally encoded calibration stimulus having a first baseband energy at a first frequency window; scaling the first digitally encoded calibration stimulus by a first weighting factor to produce a first weighted calibration stimulus; providing the first weighted calibration stimulus to the redundant DAC cell to generate a first analog tone; providing digital data and an inverse version of the first weighted calibration stimulus to the DAC unit to produce an output spectrum and a first analog tone while providing the first weighted calibration stimulus to the redundant DAC unit; and detecting error tones produced by the first analog tone and the second analog tone in the analog output of the DAC.

Example 101. The background method of example 100, further comprising: generating a first digitally encoded calibration stimulus, the second digitally encoded calibration stimulus having a first baseband energy at a first frequency window; scaling the second digitally encoded calibration stimulus by a first weighting factor to produce a first weighted calibration stimulus; providing the second weighted calibration stimulus to a further redundant DAC cell to produce a third analog tone; wherein an inverse version of said second weighted calibration stimulus is further provided to said DAC unit having said digital data and said inverse version of said first weighted calibration stimulus to further produce a fourth analog tone having said output spectrum and said second analog tone; and detecting in the analog output of the DAC another error tone produced by the third analog tone and the fourth analog tone.

Example 102 any of examples 2-26 may be an optional feature of examples 100 or 101.

Example 200. A digital-to-analog converter (DAC) with background calibration, the digital-to-analog converter comprising: a plurality of DAC units for receiving digital data and generating an output frequency spectrum; an excitation generator to generate a first digitally encoded calibration excitation having a first baseband energy at a first frequency window; one or more reference DAC units for receiving a weighted version of the first digitally encoded calibration stimulus to generate a first analog tone; one or more calibration DAC units to receive a further weighted version of the first digitally encoded calibration stimulus to generate a first analog tone, wherein the second analog tone has an opposite polarity to the first analog tone; wherein the outputs of the DAC unit, the reference DAC unit and the calibration DAC unit are summed to form an analog output of the DAC; a sensing ADC at the analog output of the DAC to sense error tones produced by the first analog tone and the second analog tone.

Example 201. The DAC with background calibration of example 200, further comprising: distortion logic to distort the digital data before it is provided to the DAC cell.

Example 202. The DAC with background calibration of examples 200 or 201, wherein the reference DAC unit and/or the calibration DAC unit are tunable in response to the sensed error tone.

Example 203. The DAC with background calibration of any of embodiments 200-202, wherein the excitation generator comprises a low pass filter to receive a multi-bit sine wave signal and to generate a sequence of unit cells approximating the sine wave.

Example 204 the DAC with background calibration of any of examples 200-203, wherein the excitation generator has no feedback.

Example 205 the DAC with background calibration of any one of examples 200-204, further comprising: error extraction logic to measure energy at the first frequency window.

Example 206. The DAC with background calibration according to any of examples 200-205 may implement any of the methods of examples 1-26.

Example 300. A digital-to-analog converter (DAC) with background calibration, the digital-to-analog converter comprising: an excitation generator to generate a first digitally encoded calibration excitation having a first baseband energy at a first frequency window; a plurality of DAC cells for receiving digital data and a weighted version of the first digitally encoded calibration stimulus and producing an output spectrum and a first analog tone at an analog output of the DAC; one or more calibration DAC units to receive a further weighted version of the first digitally encoded calibration stimulus to generate a first analog tone, wherein the second analog tone has an opposite polarity to the first analog tone; wherein the outputs of the DAC cell and the calibration DAC cell are summed to form an analog output of the DAC; and a sensing ADC at the analog output of the DAC to sense an error tone generated by the first analog tone and the second analog tone.

Example 301. A DAC with background calibration according to example 300, wherein: the excitation generator is further to generate a first digitally encoded calibration excitation having a first baseband energy at a second frequency bin different from the first frequency bin; the DAC unit is to further receive a weighted version of the second digitally encoded calibration stimulus and further generate a third analog tone at the analog output of the DAC; the DAC further comprises one or more further calibration DAC cells to receive a further weighted version of the second digitally encoded calibration stimulus and further generate a fourth analog tone; and the sensing ADC is used for sensing another error tone generated by the third analog tone and the fourth analog tone.

Example 302. A DAC with background calibration according to example 300 or example 301 may implement any of the methods according to examples 100-102.

Claims

1. A background method for measuring non-idealities of a DAC, the DAC having a plurality of DAC cells and a plurality of redundant DAC cells, outputs of the DAC cells being summed to produce an analog output of the DAC, the method comprising:

providing digital data to the DAC unit to generate an output spectrum at the analog output of the DAC;

generating a first digitally encoded calibration stimulus having a first baseband energy at a first frequency window;

scaling the first digitally encoded calibration stimulus by a first weighting factor and providing a first weighted calibration stimulus to a first subset of the redundant DAC cells while the DAC cells are producing the output spectrum to produce a first analog tone;

scaling the first digitally encoded calibration stimulus by a first weighting factor and providing a first weighted calibration stimulus to a first subset of the redundant DAC cells while the DAC cells are producing the output spectrum to produce a first analog tone, wherein the second weighting factor is selected such that the first analog tone and the second analog tone have opposite polarities; and

In the analog output of the DAC, an error tone at the first frequency bin generated by the first analog tone and the second analog tone is detected.

2. The background method of claim 1, wherein the digital data or the DAC cell is shuffled to average non-idealities of the DAC cell.

3. The background method of claim 1, wherein the first subset of the redundant DAC units includes a plurality of redundant DAC units and the second subset of the redundant DAC units includes a plurality of redundant DAC units.

4. The background method of claim 1, wherein the first subset of the redundant DAC units includes a single redundant DAC unit and the second subset of the redundant DAC units includes a plurality of redundant DAC units.

5. The background method of claim 1, wherein the first subset of the redundant DAC units includes a plurality of redundant DAC units and the second subset of the redundant DAC units includes a single redundant DAC unit.

6. The background method of claim 1, wherein the first subset of the redundant DAC units includes a single redundant DAC unit and the second subset of the redundant DAC units includes a single redundant DAC unit.

7. The background method of claim 1, wherein one or more redundant DAC units are to receive a portion of the digital data and a subset of the DAC units become one or more redundant DAC units to receive weighted calibration stimulus.

8. The background method of claim 1, wherein summing the first analog tone and the second analog tone produces the error tone.

9. The background method of claim 1, wherein detecting the error tone includes detecting energy in the analog output of the DAC at the first frequency window.

10. The background method of claim 1, further comprising:

the error tones are iteratively minimized by pre-distorting the digital data.

11. The background method of claim 1, further comprising:

the error tones are iteratively minimized by adjusting the first subset of the redundant DAC cells or the second subset of the redundant DAC cells in the analog domain.

12. The background method of claim 1, wherein the first digitally encoded calibration stimulus is a 1-bit sequence that approximates a sine wave.

13. A background method according to claim 1, wherein generating the first digitally encoded calibration stimulus comprises filtering a multi-bit sequence of encoded sine waves to generate a 1-bit sequence approximating the sine waves.

14. A background method according to claim 1, wherein generating the first digitally encoded calibration stimulus comprises low pass filtering a multi-bit sequence of encoded sine waves.

15. The background method of claim 1, further comprising:

generating a first digitally encoded calibration stimulus, the second digitally encoded calibration stimulus having a first baseband energy at a first frequency bin, wherein the second frequency bin is different from the first frequency bin;

scaling the second digitally encoded calibration stimulus by a third weighting factor and providing a third weighted calibration stimulus to a third subset of the redundant DAC cells while the DAC cells are producing the output spectrum to produce a third analog tone;

scaling the third digitally encoded calibration stimulus by a fourth weighting factor and providing a fourth weighted calibration stimulus to a fourth subset of the redundant DAC cells while the DAC cells are producing the output spectrum to produce a fourth analog tone, wherein the fourth weighting factor is selected such that the third analog tone and the fourth analog tone have opposite polarities; and

Further error tones produced by the third analog tone and the fourth analog tone are detected in the analog output of the DAC.

16. A background method for measuring non-idealities of a DAC, the DAC having a plurality of DAC cells and a plurality of redundant DAC cells, outputs of the DAC cells being summed to produce an analog output of the DAC, the method comprising:

scaling the first digitally encoded calibration stimulus by a first weighting factor to produce a first weighted calibration stimulus;

providing the first weighted calibration stimulus to the redundant DAC cell to generate a first analog tone;

providing digital data and an inverse version of the first weighted calibration stimulus to the DAC unit to produce an output spectrum and a first analog tone while providing the first weighted calibration stimulus to the redundant DAC unit; and

error tones produced by the first analog tone and the second analog tone are detected in the analog output of the DAC.

17. The background method of claim 16, further comprising:

Generating a first digitally encoded calibration stimulus, the second digitally encoded calibration stimulus having a first baseband energy at a first frequency window;

scaling the second digitally encoded calibration stimulus by a first weighting factor to produce a first weighted calibration stimulus;

providing the second weighted calibration stimulus to a further redundant DAC cell to produce a third analog tone, wherein an inverse version of the second weighted calibration stimulus is further provided to the DAC cell having the digital data and the inverse version of the first weighted calibration stimulus to further produce a fourth analog tone having the output spectrum and the second analog tone; and

18. A background method for measuring one or both of a static error between DAC cells and a timing error between DAC cells of a multi-gigabit per second DAC, the DAC having a plurality of DAC cells and a plurality of redundant DAC cells, the outputs of the DAC cells being summed to produce an analog output of the DAC, the method comprising:

Providing digital data to the DAC cell to produce an output spectrum at the analog output of the DAC;

scaling the first digitally encoded calibration stimulus by a first weighting factor and providing a first weighted calibration stimulus to a first subset of the redundant DAC cells while the DAC cells produce the output spectrum to produce a first analog tone, wherein the second weighting factor is selected such that the first analog tone and the second analog tone have opposite polarities, wherein summing the first analog tone and the second analog tone produces the error tone; and

by detecting energy in the analog output of the DAC at the first frequency bin, error tones at the first frequency bin produced by the first analog tone and the second analog tone are detected in the analog output of the DAC.

19. The background method of claim 18, further comprising:

the error tones are iteratively minimized by pre-distorting the digital data.

20. The background method of claim 18, further comprising: