CN116667826A - Correction circuit and correction method - Google Patents

Abstract

The invention provides a correction circuit and a correction method. The correction circuit can be used for carrying out built-in self test on the delay line and comprises a delay reference circuit, a comparator and an adjusting circuit. The delay reference circuit can generate a first clock signal and a second clock signal with preset delay according to an external clock signal, wherein the delay line is controlled by the control signal to generate a third clock signal according to the first clock signal. The comparator is coupled to the delay reference circuit. The comparator can compare the second clock signal with the third clock signal to judge whether the second clock signal leads or lags the third clock signal, and generate a comparison result. The adjusting circuit is coupled to the delay line and the comparator, and adjusts the control signal provided to the delay line according to the comparison result.

Description

Correction circuit and correction method

Technical Field

The present invention relates to a circuit and a method, and more particularly, to a correction circuit and a correction method.

Background

With the increase of circuit performance, the demand for high frequency clock signals for electronic devices is increasing. However, compared to low frequency operation, the same clock error results in a larger error rate at high frequency operation, and thus the fine-scale requirements of the electronic system for clock signals are also increased with the increase of the driving frequency.

Disclosure of Invention

The invention provides a correction circuit and a correction method for performing built-in self-test on a clock of a delay line.

The correction circuit of the invention can be used for carrying out built-in self-test on the delay line and comprises a delay reference circuit, a comparator and an adjusting circuit. The delay reference circuit can generate a first clock signal and a second clock signal with preset delay with the first clock signal according to an external clock signal, wherein the delay line generates a third clock signal according to the first clock signal, and the delay between the first clock signal and the third clock signal is controlled by a control signal received by the delay line. The comparator is coupled to the delay reference circuit. The comparator can compare the second clock signal with the third clock signal to judge whether the second clock signal leads or lags the third clock signal, and generate a comparison result. The adjusting circuit is coupled to the delay line and the comparator, and adjusts the control signal provided to the delay line according to the comparison result.

The calibration method of the present invention can be used to perform built-in self-test (BIST) on a delay line. The correction method comprises the following steps: generating a first clock signal and a second clock signal with a preset delay with the first clock signal according to an external clock signal by a delay reference circuit; providing a first clock signal to the delay line to generate a third clock signal, wherein the delay between the first clock signal and the third clock signal is controlled by a control signal received by the delay line; comparing the second clock signal with the third clock signal by a comparator to judge whether the second clock signal is a leading or trailing third clock signal and generating a comparison result; and adjusting the control signal provided to the delay line by an adjusting circuit according to the comparison result.

Based on the above, the correction circuit and the correction method can perform built-in self-test, and perform accurate clock correction without additional pads, thereby effectively improving the accuracy of clock signals provided to the circuit.

Drawings

FIG. 1 is a circuit block diagram of a calibration circuit according to an embodiment of the invention.

FIG. 2 is a circuit block diagram of a calibration circuit according to an embodiment of the invention.

Fig. 3 is a waveform diagram illustrating an operation of a delay reference circuit according to an embodiment of the present invention.

FIG. 4A is a block diagram of a progressive approximation register according to an embodiment of the present invention.

Fig. 4B is a circuit diagram of a digital-to-analog converter according to an embodiment of the invention.

Fig. 4C is a schematic waveform diagram of a control signal generated by an adjusting circuit according to an embodiment of the invention.

Fig. 5 is a waveform diagram illustrating an operation of a correction circuit according to an embodiment of the invention.

[ symbolic description ]

1. 2: correction circuit

10. 20: delay reference circuit

11. 21: comparator with a comparator circuit

12. 22: adjusting circuit

220: progressive approximation register

221: digital-to-analog converter

43: multiplexer

44: d-type trigger

A. B: control signal terminal

B0 to Bn-1: bit position

clk: clock input terminal

Clke: external clock signal

Clkey: inverse clock signal

Clk1: first clock signal

Clk2: second clock signal

Clk3: third clock signal

cmp: comparison result input terminal

CR, CR1 to CR3: comparison result

D: data input terminal

DIV1: first frequency divider

DIV2: second frequency divider

DL: delay line

En: enable signal

INV1: first inverter

INV2: second inverter

out: an output terminal

P1 to P4: time interval

Q: data output terminal

rst: reset terminal

SAR0 to SARn-1: approximation circuit

sel: select input terminal

set: setting end

shift: displacement input end

TD1: first delay

TD2: second delay

TD3: third delay

Vc: control signal

Vref: reference voltage

Vtar: target voltage

X-Z: data input terminal

Detailed Description

In many circuit applications requiring fine clock control, such as memory control, universal serial bus (universal serial bus, USB) transmission, phase Locked Loop (PLL), delay Locked Loop (DLL), clock data recovery circuit (clock and data recovery, CDR), etc., or other high-speed circuit applications requiring fine clock control, many fine clock signals are often required for circuit control. If all the clock signals are obtained from the outside of the circuit, the same number of pads on the chip are required to receive the clock signals, which results in an increase in the area of the chip and the manufacturing cost.

Therefore, in these circuit applications, a delay line (delay line) or a ring oscillator (ring oscillator) is often provided to generate one or more clock signals required for the operation of the system in the internal circuit of the circuit, so as to reduce the dependence on external clock signals. Generally, a delay line is formed by a plurality of delay cells (e.g., buffers) connected in series. The delay line may receive an external clock signal input from the outside and generate sequentially delayed multi-stage clock signals between delay cells of each stage. Similarly, a ring oscillator is generally formed by connecting a plurality of delay units in a ring-type manner, with their heads and tails connected in series. The ring oscillator may generate a multi-stage clock signal by self-oscillation after being enabled in a cyclic manner without an external clock signal.

Further, the delay unit may adjust the delay amount by receiving a digital or analog control signal. Therefore, in some cases, the delay lines or the ring oscillators can receive the clock signals generated by the delay lines or the ring oscillators through the test circuits, so as to adjust the control signals provided to the delay units to adjust the delay amounts to a preset range, thereby preferably overcoming the non-ideal effects generated in the manufacturing process.

However, when the clock signal generated inside the circuit is verified, if the clock signal generated inside the chip is to be provided to the test machine outside the chip for measurement, the signal path includes the delay generated by the delay unit, the delay generated by the internal signal trace of the chip connected to the pad, and the delay generated by the signal trace (trace) of the chip connected to the external test machine. Therefore, when the clock signal generated inside the chip is tested by the external test machine, the clock signal is often affected by the addition of the above factors, and the delay generated by the delay unit cannot be accurately determined.

Fig. 1 is a circuit block diagram of a correction circuit 1 according to an embodiment of the invention. The correction circuit 1 may be used to perform built-in self-test (BIST) on the delay line DL. For example, the built-in self-test is performed on the delay generated by the delay line DL through a circuit provided in the chip, and the control signal Vc is generated to control the delay cells in the delay line DL, so that the delay generated by the delay line DL can be adjusted to a predetermined range according to the built-in self-test. In some implementations, built-in self-testing may have advantages such as, for example, reduced test cost, reduced test time, improved test convenience, improved test accuracy, and the like.

In general, the correction circuit 1 includes a delay reference circuit 10, a comparator 11, and an adjustment circuit 12. The delay reference circuit 10 may receive the external clock signal Clk to generate the first clock signal Clk1 and the second clock signal Clk2 according to the external clock signal Clk. Further, the first clock signal Clk1 may be provided to the delay line DL, so that the delay line DL generates the third clock signal Clk3 according to the first clock signal Clk1. Next, the comparator 11 is coupled to the delay reference circuit 10 and the delay line DL. The comparator 10 can compare the second clock signal Clk2 with the third clock signal Clk3 and determine whether the second clock signal Clk2 leads or lags the third clock signal Clk3, and generate the comparison result CR. Finally, the adjusting circuit 12 is coupled to the delay line DL and the comparator 11. The adjusting circuit 12 can adjust the control signal Vc provided to the delay line DL according to the comparison result CR.

In detail, the delay reference circuit 10 generates a first clock signal Clk1 and a second clock signal Clk2 having a predetermined first delay TD1 therebetween. The delay line DL has a second delay TD2 between the received first clock signal Clk1 and the third clock signal Clk3 generated thereby. When the correction circuit 1 performs the built-in self-test, the correction circuit 1 can determine the phase relationship between the second clock signal Clk2 and the third clock signal Clk3 through the comparator 11, and adjust the control signal Vc provided to the delay line DL through the adjusting circuit 12, so that the phase of the third clock signal Clk3 gradually approaches the phase of the second clock signal Clk2, and further adjust the delay amount (i.e., the second delay TD 2) generated by the delay line DL to a predetermined range.

In other words, in the correction circuit 1, the first delay TD1 between the first clock signal Clk1 and the second clock signal Clk2 generated by the delay reference circuit 10 can be used as a reference to correct the delay line DL, so that the second delay TD2 between the second clock signal Clk2 and the first clock signal Clk1 generated by the delay line DL can approach the first delay TD1 generated by the delay reference circuit 10. As the second delay TD2 is advanced to the first delay TD1, the third delay TD3 between the second clock signal Clk2 and the third clock signal Clk3 received by the comparator 11 also approaches zero.

In short, when the correction circuit 1 performs the built-in self-test, the correction circuit 1 can generate the first clock signal Clk1 and the second clock signal Clk2 by using the external clock signal Clk e, and correct the delay line DL by using the first delay TD1 between the first clock signal Clk1 and the second clock signal Clk2 as a reference, so that the second delay TD2 between the third clock signal Clk3 and the first clock signal Clk1 generated by the delay line DL can be approximated or approximated to the first delay TD1 used as the reference.

Fig. 2 is a circuit block diagram of a correction circuit 2 according to an embodiment of the invention. The calibration circuit 2 can be used to perform a built-in self-test on the delay line DL. In general, the correction circuit 2 includes a delay reference circuit 20, a comparator 21, and an adjustment circuit 22. The delay reference circuit 20 may receive the external clock signal Clk to generate the first clock signal Clk1 and the second clock signal Clk2 according to the external clock signal Clk. Further, the first clock signal Clk1 may be provided to the delay line DL, so that the delay line DL generates the third clock signal Clk3 according to the first clock signal Clk1. Next, the comparator 21 is coupled to the delay reference circuit 20 and the delay line DL. The comparator 10 can compare the second clock signal Clk2 with the third clock signal Clk3 and determine whether the second clock signal Clk2 leads or lags the third clock signal Clk3, and generate the comparison result CR. Finally, the adjusting circuit 22 is coupled to the delay line DL and the comparator 21. The adjusting circuit 22 can adjust the control signal Vc provided to the delay line DL according to the comparison result CR.

In the present embodiment, the control signal Vc provided by the adjusting circuit 22 to each delay cell in the delay line DL may be in the form of an analog voltage. That is, as the analog voltage value of the control signal Vc changes, each delay cell in the delay line DL may correspondingly change the amount of delay it generates.

The delay reference circuit 20 includes a first frequency divider DIV1, a second frequency divider DIV2, and an inverter INV1. The first frequency divider DIV1 receives the enable signal En and the external clock signal clk. The first frequency divider DIV1 may be enabled by the enable signal En to divide the external clock signal Clk e to generate the first clock signal Clk1. The inverter INV1 inverts the external clock signal Clke to generate an inverted clock signal Clkeb, and supplies the inverted clock signal Clkeb to the second frequency divider DIV2. The second frequency divider DIV2 is coupled to the inverter IV1, and the second frequency divider DIV2 divides the inverted clock signal Clk eb to generate the second clock signal Clk2.

Fig. 3 is a waveform diagram illustrating an operation of the delay reference circuit 20 according to an embodiment of the present invention. In this embodiment, the first frequency divider DIV1 and the second frequency divider DIV2 are divide-by-two circuits, and the first frequency divider DIV1 and the second frequency divider DIV2 have the same triggering mode, for example, both positive edge triggering and both negative edge triggering.

Next, please refer to fig. 2 and 3 together to understand the operation of the delay reference circuit 20 in the following description. First, the external clock signal Clk is provided to the first frequency divider DIV1, and the first frequency divider DIV1 is triggered every time the positive edge of the external clock signal Clk is triggered to transition the voltage level of the first clock signal Clk1 from the high voltage level to the low voltage level or vice versa. The first frequency divider DIV1 generates the first clock signal Clk1 having a frequency half of the external clock signal Clk as shown in fig. 3 according to the external clock signal Clk. Further, the external clock signal clk is converted by the first inverter INV1 to generate an inverted clock signal clk_b, and the second frequency divider DIV2 is triggered every positive edge of the inverted clock signal clk_b after receiving the inverted clock signal clk_b, so as to convert the voltage level of the inverted clock signal clk_b from a high voltage level to a low voltage level or from the low voltage level to the high voltage level. The second frequency divider DIV2 generates a second clock signal Clk2 having a frequency half of the external clock signal Clk as shown in fig. 3 according to the inverted clock signal Clk eb.

In addition, since the first clock signal Clk1 is in the positive-edge transition of the external clock signal Clk and the second clock signal Clk2 is in the positive-edge transition of the inverted clock signal Clk b, the first delay TD1 between the first clock signal Clk1 and the second clock signal Clk2 is a half cycle of the external clock signal Clk or a quarter cycle of the first clock signal Clk1 and the second clock signal Clk2. In this way, the delay reference circuit 20 can generate the first clock signal Clk1 and the second clock signal Clk2 with the first delay TD1 information through the connection and operation of the first frequency divider DIV1, the second frequency divider DIV2 and the first inverter INV1.

In some embodiments, since the first delay TD1 generated by the delay reference circuit 20 is an operation period related to the external clock signal clk, a person skilled in the art can, of course, change the delay amount of the first delay TD1 by adjusting the period of the external clock signal clk input to the delay reference circuit 20, thereby increasing the application range and design flexibility of the correction circuit 2.

Next, as shown in fig. 2, the first clock signal Clk1 may be provided to the delay line DL to generate the third clock signal Clk3, and the first clock signal Clk1 and the third clock signal Clk3 have the second delay TD2. The comparator 21 can receive the second clock signal Clk2 and the third clock signal Clk3 to determine which phase relationship is leading.

In this embodiment, the comparator 21 may be implemented, for example, by a D Flip Flop (DFF), wherein the second clock signal Clk2 is provided to the clock input terminal of the D flip flop, the third clock signal Clk3 is provided to the data input terminal of the D flip flop, and the comparison result CR may be generated at the inverting output terminal of the D flip flop.

In this way, the comparator 21 may capture and store the data value of the third clock signal Clk3 at the positive edge (positive clock edge) of the second clock signal Clk2, and output the inverted result of the stored third clock signal Clk3 as the comparison result CR. Therefore, when the second clock signal Clk2 leads the third clock signal Clk3, the comparator 21 may grasp and store the third clock signal Clk3 of a low voltage level and output the result of its inversion as the comparison result CR when the positive edge of the second clock signal Clk2 triggers. Conversely, when the second clock signal Clk2 lags behind the third clock signal Clk3, the comparator 21 may capture and store the third clock signal Clk3 of a high voltage level and output the result of the inversion thereof as the comparison result CR when the positive edge of the second clock signal Clk2 triggers. In other words, the comparator 21 may generate the comparison result CR of the high voltage level when the second clock signal Clk2 leads the third clock signal Clk3, and the comparator 21 may generate the comparison result CR of the low voltage level when the second clock signal Clk2 lags the third clock signal Clk3.

Of course, the comparators and phase comparators of other embodiments are also within the scope of the variation examples.

Finally, the comparison result CR may be provided to the adjustment circuit 22, so that the adjustment circuit 22 generates the control signal Vc for adjusting the delay line DL. In the present embodiment, the adjusting circuit 22 includes a successive approximation register 220 and a Digital-to-Analog Converter (DAC) 221. The successive approximation register 220 is coupled to the comparator 21 for receiving the comparison result CR and generating an approximation result AR comprising a plurality of bits in a binary (binary) approximation. In addition, the asymptotic register 220 may also receive the signal provided by the second inverter INV2 and inverted from the first clock signal Clk1 to be driven as a clock signal, in other words, the asymptotic register 220 may be triggered at the negative edge (negative edge) of the first clock signal Clk1 each time to capture the comparison result CR and perform an operation, and update the generated approximation result AR.

Then, the DAC 221 can generate the control signal Vc according to the multiple bits of the approximation result AR. In the present embodiment, the digital-to-analog converter 221 may convert the control signal Vc into an analog control signal Vc and provide the analog control signal Vc to the delay line DL to adjust the delay amount of each delay unit in the delay line DL.

In some embodiments, the circuit structure of the adjusting circuit 22 can be adaptively adjusted according to the aspects of the delay line DL and the delay unit. For example, when the delay cells in the delay line DL are in digital form, that is, the delay cells in the delay line DL receive digital control signals to adjust the delay amount, the dac 221 in the adjusting circuit 22 can be omitted correspondingly, so as to provide the approximation result AR generated by the successive approximation register 220 as the control signal Vc to the delay line DL to control the delay amount generated by the delay line DL.

FIG. 4A is a block diagram of a successive approximation register 220 according to an embodiment of the present invention. Next, please refer to fig. 2 and 4A together to understand the operation of the successive approximation register 220 in the following paragraphs.

In the upper half of FIG. 4A, the connection structure of the approximation circuits SAR 0-SARn-1 in the successive approximation register 220 is shown. In the bottom half of fig. 4A, a circuit block diagram of a single approximation circuit is shown.

First, as shown in the upper half of fig. 4A, the successive approximation register 220 includes a plurality of approximation circuits SAR 0-SARn-1 connected in series, wherein the number of approximation circuits corresponds to the number of bits included in the approximation result AR, and the approximation circuits SARn-1-SAR 0 can be used to generate bits Bn-1-B0 in the approximation result AR, respectively. Each approximation circuit has a comparison result input cmp, a shift input shift, a selection input sel, and an output out. In the approximation circuit, the comparison result input cmp may receive the comparison result CR, the shift input shift may be coupled to the output out of the preceding approximation circuit, and the selection input sel may receive all bits generated by the following approximation circuit, which are summed up by an OR gate (OR gate). In addition, the set end set of the approximation circuit SARn-1 of the most significant bit (most significant bit, MSB) Bn-1 receives the enable signal En, while the rest of the approximation circuits SARn-2-SAR 0 receive the enable signal En from the reset end rst. Finally, although not shown in the upper half of fig. 4A, each of the approximation circuits further has a clock input Clk for receiving the inverted first clock signal Clk1.

Next, as shown in the bottom half of fig. 4A, a multiplexer 43 and a D-type flip-flop 44 may be included in each approximation circuit. The multiplexer 43 may have three data inputs X-Z, two control signals A, B and an output. The data input end X is coupled with the comparison result input end cmp of the approximation circuit, the data input end Y is coupled with the displacement input end shift of the approximation circuit, and the data input end Z is coupled with the output end of the approximation circuit. The control signal terminal A is coupled to the selection input terminal sel of the approximation circuit, and the control signal terminal B is coupled to the output terminal out of the approximation circuit. Therefore, the approximation circuit selectively provides the data of one of the comparison result input cmp, the shift input shift and the output out of the approximation circuit to the output of the multiplexer 43 according to the signal received by the control signal terminal A, B.

With respect to multiplexer 43, its truth table is exemplarily shown in the lower right of fig. 4A. When the control signal terminal a receives a digital value, for example, a data value of 0, the multiplexer 43 can provide the data received by the data input terminal X, Y to the output terminal out of the multiplexer 43 according to the control signal terminal B. Specifically, when the control signal terminal A, B receives digital values, such as 0 and 0, respectively, the multiplexer 43 can provide the data approaching the shift input terminal shift of the circuit to the output terminal out of the multiplexer 43. When the control signal terminal A, B receives digital values, such as 0 and 1, respectively, the multiplexer 43 can provide the data of the comparison result input cmp of the approximation circuit to the output out of the multiplexer 43. In addition, when the control signal terminal a receives a digital value, for example, data 1, the multiplexer 43 can provide the data approaching the output terminal out of the circuit to the output terminal out of the multiplexer 43.

The D-type flip-flop 44 has a data input D, a clock input and a data output Q. The data input terminal D of the D-flip-flop 44 is coupled to the output terminal out of the multiplexer 43. The clock input terminal of the D-type flip-flop 44 is coupled to the clock input terminal Clk (not shown in the upper half of fig. 4A) of the approximating circuit to receive the inverted first clock signal Clk1 for control. The data output terminal Q of the D-type flip-flop 44 is coupled to the output terminal out of the approximation circuit. In this way, the D-type flip-flop 44 can capture and store the data of the data input terminal D at the negative edge of the first clock signal Clk1 and provide the data to the data output terminal Q of the D-type flip-flop 44.

Fig. 4B is a circuit diagram of a digital-to-analog converter 221 according to an embodiment of the invention. In the present embodiment, the digital-to-analog converter may be, for example, a series resistor string of R-2R to convert the received bits Bn-1-B0 of the approximation result AR into the control signal Vc in the form of an analog voltage. Of course, other types of digital-to-analog converters, such as current or capacitance types, are also within the scope of the alternative embodiments.

In the digital-to-analog converter 221, the analog voltage weight of each bit to the control signal Vc becomes twice as the bit order increases. That is, among the bits Bn-1 to B0 of the approximation result AR, from the least significant bit (least significant bit, LSB) B0 to the most significant bit Bn-1, which are weighted 2 for the analog voltage to the control signal Vc, respectively ⁰ ～2 ^n-1 . In this way, the DAC 221 can convert the digital approximation result AR into the control signal Vc in analog form by the series resistor string of R-2R. For example, when the analog voltage range of the control signal Vc received by the delay unit in the delay line DL is between 0 and the reference voltage Vref, the most significant bit Bn-1 corresponds to the analog voltage value of the reference voltage Vref/2, and the bit Bn-2 corresponds to the analog voltage value of the reference voltage Vref/4, and so on.

Fig. 4C is a waveform diagram of the control signal Vc generated by the adjusting circuit 22 according to an embodiment of the invention. Next, referring to fig. 4A-4C together, the following description will be made for the operation of the adjusting circuit 22.

In the upper half of FIG. 4C, bits B3-B0 of the approximation result AR output by the successive approximation register 220 during time intervals P1-P4 are shown. In the bottom half of fig. 4C, the analog voltage values of the control signals Vc generated by the digital-to-analog converter 221 during the time intervals P1-P4 are correspondingly shown.

In the example of fig. 4C, the precision or resolution of the successive approximation register 220 and the dac 221 is four bits, so the successive approximation register 220 in this embodiment has four approximation circuits SAR 3-SAR 0 for generating bits B3-B0 of the approximation result AR, respectively, wherein the bit B3 is the most significant bit and the bit B0 is the least significant bit.

First, before the time interval P1, the enable signal En is first provided to the approximation circuits SAR 3-SAR 0, so that the approximation circuits SAR 3-SAR 0 generate the approximation result AR with the bits B3-B0 of 1000 at the output terminal out after the signal of the clock input terminal clk is triggered to enter the time interval P1, thereby generating the approximation result AR as the first row in the upper half of fig. 4C.

Before the time interval P2, the multiplexer 43 of the approximating circuit SAR3 still outputs 0 to the following approximating circuits SAR2 to SAR0, so the control signal terminal a receives the digital value 0. However, since the output out of the approximation circuit SAR3 outputs a digital value of 1, the internal multiplexer 43 is switched to capture and store the comparison result CR3 for the bit B3 in the D-type flip-flop 44 for the time interval P1.

Therefore, in the time interval P2, the approximation circuit SAR3 can output the comparison result CR3 for the bit B3 as the bit B3 in the time interval P1 when the clock input clk is triggered. In addition, the approximation circuits SAR 2-0 are held in operation to shift the digital values to the right, and the bits B2-B0 are each 100, so that the approximation result AR of the second row in the upper half of fig. 4C is generated.

Then, in the time interval P3, for the multiplexer 43 of the approximating circuit SAR3, the control signal terminal B is enabled due to one of the approximating circuits SAR2 to SAR0 being non-zero, so that the approximating circuit SAR3 keeps storing and outputting the comparison result CR3 of the bit B3. In addition, the approximation circuit SAR2 captures the comparison result CR2 of the bit B2, and the approximation circuits SAR1 and SAR0 perform right shift operations to make the bits B1 and B0 respectively 10, so as to generate the approximation result AR as shown in the third row in the upper half of fig. 4C.

Finally, in the time interval P4, the approximation circuits SAR3 and SAR2 respectively store and output the comparison results CR3 and CR2 of the bits B3 and B2. The approximation circuit SAR1 grabs the comparison CR1 of bit B1. The approximation circuit SAR0 performs a right shift operation, thus producing an approximation result AR as in the fourth row in the upper half of fig. 4C.

Therefore, after the end of the time interval P4, the comparison result CR0 of the bit B0 can be generated, and the bits B3-B0 approximating the result AR can be obtained.

In the lower half of fig. 4C, the analog voltage values of the control signals Vc generated by the digital-to-analog converter 221 during the time periods P1 to P4 are correspondingly shown. In fig. 4C, the solid line shows the analog voltage level of the control signal Vc, and the dotted line shows the target voltage Vtar level to be approximated by the adjusting circuit 22.

In the time interval P1, when the bits B3-B0 are digital values 1000, the DAC 221 generates the Vref/2 control signal Vc. Since the control signal Vc in the time interval P1 is smaller than the target voltage Vtar, the comparator 21 can generate the comparison result CR3 with the digital value of 1 of the bit B3.

In the time interval P2, the bit B3 can be set to a digital value of 1 according to the comparison result CR3, and the bits B2-B0 are digital values of 100. Therefore, in the time interval P2, the control signal Vc may be set at the voltage level of Vref (3/4) and compared with the target voltage Vtar. Thus producing a comparison result CR2 with a digital value of 0 for bit B2.

In the time interval P3, the bit B3 may be kept as the comparison result CR3, the bit B2 may be set as the digital value 0 according to the comparison result CR2, and the bits B1, B0 are the digital value 10. Therefore, in the time interval P3, the control signal Vc may be set at the voltage level of Vref (5/8) and compared with the target voltage Vtar. Thus producing a comparison result CR1 with a digital value of 0 for bit B1.

Finally, in the time interval P4, bits B3-B1 may be respectively set and output according to the comparison results CR 3-CR 1, respectively, and bit B0 may be set to a digital value of 1. Therefore, in the time interval P4, the control signal Vc may be set at the voltage level of Vref (9/16) and compared with the target voltage Vtar. Thus, a comparison result CR0 (not shown in FIG. 4C) with a digital value of 0 for bit B0 is generated.

Therefore, in the present embodiment, after the end of the time intervals P1-P4, the approximation result AR with the bits B3-B0 of 1000 can be obtained to approximate the target voltage Vtar.

Fig. 5 is a waveform diagram illustrating an operation of the correction circuit 2 according to an embodiment of the invention. Next, please refer to fig. 2 and 5 together to understand the operation of the correction circuit 2 in the following description.

First, the correction circuit 2 may receive the external clock signal Clk and generate a first clock signal Clk1 and a second clock signal Clk2, wherein a first delay TD1 between the first clock signal Clk1 and the second clock signal Clk2 is a half period of the external clock signal Clk. Further, the second clock signal Clk1 may be further provided to the delay line DL to generate a third clock signal Clk3, wherein the second delay TD2 is generated between the first clock signal Clk1 and the third clock signal Clk3 according to the control signal Vc received by the delay unit in the delay line DL. In the case that the enable signal En is at the high level, the calibration circuit 2 can perform the built-in self-test according to the above, and align the third clock signal Clk3 generated by the delay line DL to the second clock signal Clk2 through the operations of the comparator 21 and the adjustment circuit 22, so that the third delay TD3 between the second clock signal Clk2 and the third clock signal Clk3 can be gradually reduced or approaches zero.

In detail, the adjusting circuit 22 can first generate the control signal Vc with the voltage level Vref/2 according to the enable signal En. The comparator 21 can compare the phases of the second clock signal Clk2 and the third clock signal Clk3 each time the positive edge of the second clock signal Clk2 triggers, and generate the comparison result CR. The progressive approximation register 220 adjusts the voltage level of the control signal Vc in a binary approximation manner according to the comparison result until all bits of the approximation result AR are obtained, and then the enable signal En is switched to a low level, so that the control signal Vc can be maintained in a predetermined delay range.

Specifically, the correction circuit 2 aims at aligning the third clock signal Clk3 generated by the delay line DL to the second clock signal Clk2, that is, setting the third delay TD3 set in the delay line DL to be the same as the first delay TD1 in the delay reference circuit 20. But limited by the resolution, the second delay TD2 between the second clock signal Clk2 and the third clock signal Clk3 cannot be zero. Taking fig. 4C as an example, in an ideal case, when the target voltage Vtar shown in fig. 4C is provided to the delay unit in the delay line DL, the delay unit in the delay line DL can provide a predetermined delay amount to align the third clock signal Clk3 with the second clock signal Clk2. The objective of the calibration circuit 2 is to adjust the control signal Vc such that the difference between the control signal Vc and the target voltage Vtar is smaller than the voltage value of the least significant bit, and further such that the time difference between the second clock signal Clk2 and the third clock signal Clk3 is controlled within the delay amount corresponding to the voltage value of the least significant bit, and such that the second delay TD2 generated by the delay line DL is controlled within the preset delay range.

On the other hand, since the first delay TD1 generated by the delay reference circuit 20 of the correction circuit 2 is related to the half period of the external clock signal clk, the period of the external clock signal clk provided to the correction circuit 2 can be adjusted during the built-in self-test, so as to adjust the second delay TD2 generated by the delay line DL. Therefore, although the first delay TD1 serving as the delay reference amount can be generated in the delay reference circuit 20, it can be adjusted by the external clock signal clk, so that the flexibility of system adjustment is maintained, and the compatibility of the correction circuit 2 is increased.

On the other hand, the delay line DL may receive the first clock signal Clk1 through the delay unit of the first stage, and in some embodiments, generate the third clock signal Clk3 through the delay unit of the last stage. Thus, when the delay line DL ends the built-in self-test, the total delay of the whole delay line DL can be corrected to be within the preset delay range, and the system can obtain the required clock signals from each stage of delay units in the delay line DL to drive according to the requirement. In some other embodiments, however, the delay line DL may generate the third clock signal Clk3 through a delay cell other than the last stage. For example, the delay line DL may be the third clock signal Clk3 by a clock signal generated by the delay unit of the first stage, the intermediate stage, or any stage, which are all within the scope of the variation embodiments.

Finally, since the correction circuit starts the overall correction operation only when the first bit of the successive approximation circuit 220 is activated, and since only a single comparator is required to output a high voltage level or a low voltage level, compared with the conventional method, harmonic lock (harmonic lock) and false lock (false lock) are less likely to occur, thereby effectively improving the reliability of the overall operation.

In summary, the calibration circuit of the present invention can perform built-in self-test, and can automatically calibrate the delay of the delay line in the circuit when only receiving the external clock signal Clke and the enable signal En, and perform accurate clock calibration without requiring additional pads, thereby effectively improving the accuracy of the clock signal provided to the circuit.

Claims (14)

1. A correction circuit for performing built-in self-test (BIST) on a delay line, the correction circuit comprising:

a delay reference circuit for generating a first clock signal and a second clock signal having a predetermined delay with the first clock signal according to an external clock signal, wherein the delay line generates a third clock signal according to the first clock signal, and the delay between the first clock signal and the third clock signal is controlled by a control signal received by the delay line;

the comparator is coupled with the delay reference circuit, compares the second clock signal with the third clock signal to judge whether the second clock signal leads or lags the third clock signal, and generates a comparison result; and

the adjusting circuit is coupled to the delay line and the comparator, and adjusts the control signal provided to the delay line according to the comparison result.

2. The correction circuit of claim 1, wherein the delay reference circuit comprises:

a first frequency divider dividing the external clock signal to generate the first clock signal;

an inverter inverting the external clock signal to generate an inverted clock signal; and

the second frequency divider is coupled to the inverter, and divides the inverted clock signal to generate the second clock signal.

3. The correction circuit of claim 2, wherein the first frequency divider and the second frequency divider are divide-by-two circuits.

4. The correction circuit of claim 1, wherein the predetermined delay between the first clock signal and the second clock signal generated by the delay reference circuit is one half of an operating period of the external clock signal.

5. The correction circuit of claim 1, wherein the adjustment circuit adjusts the control signal in a progressive approximation (Successive Approximation).

6. The correction circuit of claim 1, wherein the adjustment circuit comprises:

the progressive approximation register is coupled with the comparator and determines an approximation result comprising a plurality of bits according to the comparison result; and

a Digital-to-Analog Converter (DAC) coupled to the successive approximation register and the delay line, the DAC generating the Analog control signal according to the approximation result.

7. The correction circuit of claim 6, wherein the successive approximation register determines the bits of the approximation result according to a bit order based on the comparison result.

8. A calibration method for performing built-in self-test (BIST) on a delay line, the calibration method comprising:

generating a first clock signal and a second clock signal having a predetermined delay from the first clock signal according to an external clock signal by a delay reference circuit;

providing the first clock signal to the delay line to generate a third clock signal, wherein the delay between the first clock signal and the third clock signal is controlled by the control signal received by the delay line;

comparing the second clock signal with the third clock signal by a comparator to judge whether the second clock signal leads or lags the third clock signal and generate a comparison result; and

the control signal provided to the delay line is adjusted by an adjusting circuit according to the comparison result.

9. The method of claim 8, wherein generating the first clock signal and the second clock signal with the predetermined delay according to the external clock signal comprises:

dividing the external clock signal by a first frequency divider to generate the first clock signal;

inverting the external clock signal by an inverter to generate an inverted clock signal; and

the inverted clock signal is divided by a second divider to generate the second clock signal.

10. The calibration method of claim 9, wherein the first divider divides the frequency of the external clock signal by two and the second divider divides the frequency of the inverted clock signal by two.

11. The calibration method of claim 8, wherein the predetermined delay between the first clock signal and the second clock signal generated by the delay reference circuit is one half of an operation period of the external clock signal.

12. The correction method of claim 8, further comprising adjusting the control signal by the adjustment circuit in a progressive approximation (Successive Approximation).

13. The method of claim 8, wherein the step of adjusting the control signal provided to the delay line by the adjusting circuit according to the comparison result, further comprises:

determining an approximation result comprising a plurality of bits by a successive approximation register based on the comparison result; and

the Analog control signal is generated by a Digital-to-Analog Converter (DAC) according to the approximation result.

14. The correction method of claim 11, further comprising determining the bits of the approximation result in bit order according to the comparison result by the successive approximation register.