CN116666327A - Electronic packaging structure and manufacturing method thereof - Google Patents
Electronic packaging structure and manufacturing method thereof Download PDFInfo
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- CN116666327A CN116666327A CN202210880439.2A CN202210880439A CN116666327A CN 116666327 A CN116666327 A CN 116666327A CN 202210880439 A CN202210880439 A CN 202210880439A CN 116666327 A CN116666327 A CN 116666327A
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- 238000004100 electronic packaging Methods 0.000 title abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 205
- 239000004020 conductor Substances 0.000 claims abstract description 57
- 239000010410 layer Substances 0.000 claims description 150
- 239000000463 material Substances 0.000 claims description 77
- 229910000679 solder Inorganic materials 0.000 claims description 27
- 239000000853 adhesive Substances 0.000 claims description 18
- 230000001070 adhesive effect Effects 0.000 claims description 18
- 239000011810 insulating material Substances 0.000 claims description 15
- 239000012792 core layer Substances 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6616—Vertical connections, e.g. vias
- H01L2223/6622—Coaxial feed-throughs in active or passive substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Combinations Of Printed Boards (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The invention provides an electronic packaging structure and a manufacturing method thereof. The electronic package structure comprises an interposer, a circuit substrate, a chip and a circuit structure. The interposer includes an interposer substrate and a coaxial conductor. The interposer substrate includes a cavity. The coaxial conductive member is located in the interposer substrate. The coaxial conductive member comprises a first conductive structure, a second conductive structure and a first insulating structure. The second conductive structure surrounds the first conductive structure. The first insulating structure is arranged between the first conductive structure and the second conductive structure. The circuit substrate is arranged on the lower surface of the intermediate layer substrate and is electrically connected with the coaxial conductive piece. The chip is arranged in the cavity and is positioned on the circuit substrate so as to be electrically connected with the circuit substrate. The circuit structure is arranged on the upper surface of the medium layer substrate and is electrically connected with the coaxial conductive element.
Description
Technical Field
The present disclosure relates to packaging structures and methods for manufacturing the same, and particularly to an electronic packaging structure and a method for manufacturing the same.
Background
Along with technological progress, functions of electronic products are becoming more and more abundant, and integration of an antenna (antenna) structure and a chip packaging structure is beneficial to miniaturization and light weight requirements of the electronic products. Generally, for the current chip package structure with an antenna structure, a chip is usually disposed on a circuit substrate, and a film sealing material is covered on the chip to form the chip package structure. The antenna structure is arranged on the chip packaging structure and is electrically connected with the circuit substrate through the conductive posts or conductive balls penetrating through the film sealing material in the chip packaging structure. However, the above package structure cannot effectively prevent the radio frequency (radio frequency) signal from being scattered during transmission, and has a large volume.
Disclosure of Invention
The invention is directed to an electronic packaging structure and a manufacturing method thereof, which can reduce signal loss and contribute to miniaturization of the electronic packaging structure.
According to an embodiment of the invention, the electronic package structure comprises an interposer, a circuit substrate, a chip and a circuit structure. The interposer includes an interposer substrate and a coaxial conductor. The interposer substrate has an upper surface and a lower surface opposite the upper surface, wherein the interposer substrate includes a cavity. The coaxial conductive member is located in the interposer substrate. The coaxial conductive member comprises a first conductive structure, a second conductive structure and a first insulating structure. The second conductive structure surrounds the first conductive structure. The first insulating structure is arranged between the first conductive structure and the second conductive structure. The circuit substrate is arranged on the lower surface of the intermediate layer substrate and is electrically connected with the coaxial conductive piece. The chip is arranged in the cavity and is positioned on the circuit substrate so as to be electrically connected with the circuit substrate. The circuit structure is arranged on the upper surface of the medium layer substrate and is electrically connected with the coaxial conductive element.
In an electronic package structure according to an embodiment of the invention, a material of the interposer substrate includes a conductive material.
In an electronic package structure according to an embodiment of the present invention, the electronic package structure further includes a thermal interface material disposed on a back surface of the chip and in contact with the interposer substrate.
In an electronic package structure according to an embodiment of the invention, the circuit structure includes a first core layer, a first antenna layer, a second antenna layer, and a plurality of pads. The first core layer has a first surface and a second surface opposite to the first surface, wherein the second surface faces the interposer. The first antenna layer is disposed on the first surface. The second antenna layer is disposed on the second surface. The plurality of pads are disposed on the second surface and correspond to the coaxial conductive members.
In an electronic package structure according to an embodiment of the invention, the plurality of pads includes a first pad and a second pad. The first connecting pad corresponds to the first conductive structure of the coaxial conductive member. The second connecting pad corresponds to the second conductive structure of the coaxial conductive member, wherein the second connecting pad is annular.
In an electronic package structure according to an embodiment of the invention, the plurality of pads includes a first pad and a plurality of second pads. The first connecting pad corresponds to the first conductive structure of the coaxial conductive member. The plurality of second pads correspond to the second conductive structures of the coaxial conductive member, wherein the plurality of second pads encircle the first pads.
In an electronic package structure according to an embodiment of the invention, the electronic package structure further includes a first conductive connection member disposed between the plurality of pads of the circuit structure and the coaxial conductive member.
In an electronic package structure according to an embodiment of the invention, the electronic package structure further includes a first adhesive layer disposed between the interposer and the circuit structure.
In an electronic package structure according to an embodiment of the invention, the circuit substrate includes a plurality of pads corresponding to the coaxial conductive members. The electronic packaging structure also comprises a second conductive connecting piece which is arranged between the circuit substrate and the coaxial conductive piece.
In the electronic package according to an embodiment of the present invention, the first conductive structure of the coaxial conductive member is adapted to transmit signals, and the second conductive structure is adapted to be grounded or connected to a power source.
According to an embodiment of the present invention, the method for manufacturing the electronic package structure of the present invention includes the following steps. A circuit substrate is provided. The chip is arranged on the circuit substrate. An interposer is provided that includes an interposer substrate and coaxial conductors. The interposer substrate has an upper surface and a lower surface opposite the upper surface, wherein the interposer substrate includes a cavity. The coaxial conductive member is located in the interposer substrate. The coaxial conductive member comprises a first conductive structure, a second conductive structure and a first insulating structure. The second conductive structure surrounds the first conductive structure. The first insulating structure is arranged between the first conductive structure and the second conductive structure. Then, a circuit structure is provided and pressed on the upper surface of the medium layer substrate at a first temperature. A cavity is formed in the lower surface of the interposer substrate. At a second temperature, the circuit substrate is bonded on the lower surface of the interposer substrate, and the chip is disposed in the cavity.
In a manufacturing method according to an embodiment of the invention, the step of forming the interposer includes providing a core substrate having a first side and a second side opposite to the first side. A first through hole is formed in the core substrate. And filling the insulating material in the first through hole. A second through hole is formed in the insulating material to form a first insulating structure. A first conductive material layer is formed on the first side and the second side of the core substrate and in the second through hole. The first conductive material layer is patterned to expose a portion of the first insulating structure.
In the manufacturing method according to the embodiment of the present invention, the aperture of the first through hole is between 250 μm and 450 μm, and the aperture of the second through hole is between 50 μm and 100 μm.
In a manufacturing method according to an embodiment of the invention, the step of forming the interposer includes providing a core substrate having a first side and a second side opposite to the first side. An annular groove is formed on a first side of the core substrate, wherein the annular groove does not extend through a second side of the core substrate. And filling an insulating material in the annular groove to form a first insulating structure. A portion of the core substrate is removed from the second side of the core substrate until the first insulating structure is exposed. A first conductive material layer is formed on the first side and the second side of the core substrate. The first conductive material layer is patterned to expose a portion of the first insulating structure.
In the manufacturing method according to the embodiment of the invention, the manufacturing method further includes forming a first adhesive material layer on the upper surface of the interposer substrate, wherein the first adhesive material layer is in a semi-cured state. A plurality of through holes are formed in the first adhesive material layer to expose a portion of the coaxial conductive member. A first conductive connection material is formed in the plurality of vias.
In the manufacturing method according to the embodiment of the invention, the first conductive connection material includes copper paste, silver paste or transient liquid phase sintering paste.
In the manufacturing method according to the embodiment of the invention, the step of bonding the circuit structure on the upper surface of the interposer substrate includes bonding the circuit structure and the interposer substrate at a first temperature to correspondingly connect the plurality of pads of the circuit structure with the first conductive connecting material, and curing the first adhesive material layer.
In the manufacturing method according to the embodiment of the invention, the step of bonding the circuit substrate on the lower surface of the interposer substrate includes forming a solder mask on the lower surface of the interposer substrate, wherein the solder mask includes a plurality of through holes to expose a portion of the coaxial conductive members. A second conductive connecting material is formed in the plurality of vias. And correspondingly jointing the coaxial conductive piece and the plurality of connection pads of the circuit substrate through the second conductive connecting material.
In the manufacturing method according to the embodiment of the invention, the second conductive connection material includes solder paste or solder balls.
In the manufacturing method according to the embodiment of the present invention, the above-described first temperature is between 180 ℃ and 220 ℃, and the second temperature is between 250 ℃ and 270 ℃.
Based on the above, the electronic package structure of the present invention can integrate the circuit substrate, the interposer and the circuit structure in a package structure, and the chip is disposed in the cavity of the interposer, so that the space can be effectively utilized, thereby facilitating miniaturization of the electronic package structure, and facilitating improvement of heat dissipation capability of the chip due to the interposer being made of conductive material. In addition, because the intermediate layer comprises the coaxial conductive element for electrically connecting the circuit structure and the circuit substrate, the signal loss of the radio frequency signal received or sent by the circuit structure in the transmission process can be reduced, and the electromagnetic interference signal can be shielded, so that the signal integrity is improved.
Drawings
FIG. 1 is a schematic cross-sectional view of an electronic package according to an embodiment of the present invention;
FIG. 2 is a schematic top view of the electronic package of FIG. 1;
FIG. 3 is a schematic cross-sectional view of an electronic package according to another embodiment of the present invention;
Fig. 4A to 4C are schematic cross-sectional views illustrating a manufacturing process of a chip disposed on a circuit substrate according to an embodiment of the invention;
FIGS. 5A-5F are schematic cross-sectional views of a process flow of fabricating an interposer including coaxial conductors according to one embodiment of the present invention;
FIGS. 6A-6F are schematic cross-sectional views of a process flow of fabricating an interposer including coaxial conductors according to another embodiment of the present invention;
fig. 7A to 7D are schematic cross-sectional views illustrating a manufacturing process of a first conductive connector according to an embodiment of the present invention;
FIGS. 8A-8B are partial top views of the region R1 of FIG. 7B;
fig. 9A to 9C are schematic diagrams of a circuit structure according to an embodiment of the present invention;
fig. 10A to 10E are schematic cross-sectional views illustrating a manufacturing process of an electronic package structure according to an embodiment of the invention.
Description of the reference numerals
10,20 electronic packaging Structure
100 circuit board
100',200': structure
101 core substrate
102 insulating layer
110 line layer
112, 114. Contact pads
120 solder mask layer
130 chip
130a active surface
130b back side
132 contact point
140, primer
150 thermal interface material
200 interposer
201,201': core substrate
201a,201a' first side
201b,201b': second side
202,202': first conductive material layer
203,203' first conductive layer
205 interposer substrate
205a upper surface
205b lower surface
210 coaxial conductor
211 insulating material
212 first insulating structure
214 first conductive structure
214a first pad portion
214b first conductive post portion
216 second conductive structure
216a second pad portion
216b second conductive post portion
220 first adhesive layer
220' first adhesive material layer
222 release film
230,232 cavity
230a,230b,232a,232b sidewalls
230c bottom surface
240 first conductive connecting piece
240a intermediate conductive connector
240b peripheral conductive connector
240' first conductive connecting material
260 solder mask layer
270 second conductive connecting piece
270': second conductive connecting material
300 line structure
301 first core layer
301a first surface
301b second surface
302,303 insulating layer
305 conductive column
311,313 conductive layer
312 first antenna layer
314 second antenna layer
316 joint pad
316a first pad
316b,316b': second bond pad
320 solder mask layer
A1, R1, R2-region
CV1, CV2 via hole
OP1, OP2, OP3, openings
P part(s)
PR patterning a photoresist layer
T-ring groove
TH1 first through hole
TH2 second through hole
V1, V1a, V1b, V1a ', V1b', V2, V3: through holes
d1, d2 pore size
d3, d4 diameter
d5 distance
d6 external diameter
d7 width
Detailed Description
The following examples are set forth in detail in connection with the accompanying drawings, but are not intended to limit the scope of the invention. Moreover, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, like components in the following description will be described with like reference numerals.
Furthermore, the terms "comprising," including, "" having, "and the like, as used herein, are open-ended terms, meaning" including, but not limited to.
It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various components, elements, regions, layers and/or sections, these components, elements, regions, and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first component," "section," "region," "layer," or "portion" discussed below could be termed a second component, region, layer, or portion without departing from the teachings herein.
Directional terms mentioned herein, such as: "upper", "lower", "front", "rear", "left", "right", etc., are merely directions with reference to the drawings. Thus, the directional terminology is used for purposes of illustration and is not intended to be limiting of the invention.
In the drawings, the various figures illustrate the general features of methods, structures and/or materials used in certain embodiments. However, these drawings should not be construed as defining or limiting the scope or nature of what is covered by these embodiments. For example, the relative dimensions, thicknesses, and locations of various layers, regions, and/or structures may be reduced or exaggerated for clarity.
In the following embodiments, the same or similar components will be denoted by the same or similar reference numerals, and their detailed description will be omitted. In addition, features of the various embodiments may be combined with each other without conflict and simple equivalent variations and modifications may be made in accordance with the present specification or claims while remaining within the scope of the present patent coverage.
Fig. 1 is a schematic cross-sectional view of an electronic package according to an embodiment of the invention. Fig. 2 is a schematic top view of the electronic package of fig. 1. For clarity of illustration, fig. 2 shows only the chip 130, the first conductive connection 240, and the first adhesive layer 220 and other components are omitted, and the omitted parts may be understood with reference to fig. 1.
Referring to fig. 1 and 2, the electronic package structure 10 includes a circuit substrate 100, an interposer 200, a chip 130, and a circuit structure 300. Interposer 200 includes interposer substrate 205 and coaxial conductors 210. The interposer substrate 205 has an upper surface 205a and a lower surface 205b opposite the upper surface 205a, and the interposer substrate 205 includes a cavity 230. The coaxial conductor 210 is located in the interposer substrate 205. The coaxial conductor 210 includes a first conductive structure 214, a second conductive structure 216, and a first insulating structure 212. The second conductive structure 216 surrounds the first conductive structure 214. The first insulating structure 212 is disposed between the first conductive structure 214 and the second conductive structure 216. The circuit substrate 100 is disposed on the lower surface 205b of the interposer substrate 205 and electrically connected to the coaxial conductive element 210. The chip 130 is disposed in the cavity 230 and located on the circuit substrate 100 to be electrically connected to the circuit substrate 100. The circuit structure 300 is disposed on the upper surface 205a of the interposer substrate 205 and electrically connected to the coaxial conductive element 210.
Since the chip 130 can be disposed in the cavity 230 of the interposer 200, the space can be effectively utilized, and the volume of the electronic package structure 10 can be reduced. Because the interposer 200 includes the coaxial conductive element 210 to electrically connect the circuit structure 300 and the circuit substrate 100, signal loss of the radio frequency signal received or transmitted by the circuit structure 300 during transmission can be reduced, and electromagnetic interference signals can be shielded, so as to improve signal integrity.
In some embodiments, the interposer substrate 205 may be made of an electrically conductive material, preferably an electrically and thermally conductive material, such as copper, aluminum, or other suitable metal material or an alloy thereof. In this way, the coaxial conductive element 210 may be formed by a portion of the interposer substrate 205, and the interposer substrate 205 has heat dissipation capability.
In some embodiments, the cavity 230 is a recess recessed from the bottom surface 205b toward the top surface 205a, and the cavity 230 may be formed by sidewalls 230a, 230b and a bottom surface 230c of the interposer substrate 205. That is, the cavity 230 does not penetrate the interposer substrate 205, but the invention is not limited thereto. In other embodiments, the cavity 230 may extend through the interposer substrate 205.
In some embodiments, the dimensions (e.g., length, width, height) of cavity 230 are at least greater than the dimensions of chip 130 so that chip 130 may be received in cavity 230.
In some embodiments, the circuit structure 300 includes a first core layer 301, a first antenna layer 312, a second antenna layer 314, and a plurality of pads 316. The first core layer 301 has a first surface 301a and a second surface 301b opposite the first surface 301a, wherein the second surface 301b faces the interposer 200. The first antenna layer 312 is disposed on the first surface 301 a. The second antenna layer 314 and the plurality of pads 316 are disposed on the second surface 301 b. The plurality of pads 316 may include a first pad 316a and a second pad 316b. The first pads 316a correspond to the first conductive structures 214 of the coaxial conductive member 210, and the plurality of second pads 316b correspond to the second conductive structures 216 of the coaxial conductive member 210.
In some embodiments, the first conductive connection 240 may be disposed between the plurality of pads 316 of the circuit structure 300 and the coaxial conductive member 210, so that the pads 316 are electrically connected to the coaxial conductive member 210. In some embodiments, the material of the first conductive connection 240 may include copper, silver, copper alloy, copper-tin alloy, tin-bismuth alloy, or other suitable materials, which is not limited to the present invention.
In some embodiments, as shown in fig. 2, the arrangement pattern of the first conductive connection elements 240 corresponding to the coaxial conductive elements 210 may correspond to the arrangement of the plurality of pads 316 of the circuit structure 300 (refer to fig. 9B, 9C and related content). That is, the first conductive connection 240 may include an intermediate conductive connection 240a corresponding to the first pad 316a, and a peripheral conductive connection 240b corresponding to the second pad 316 b. In some embodiments, the second pads 316b are annular pads, so the peripheral conductive connection 240b may be correspondingly annular to surround the intermediate conductive connection 240a. In other embodiments, the second pad 316b includes a plurality of pads surrounding the first pad 316a, so the peripheral conductive connection 240b can be a plurality of peripheral conductive connection 240b' correspondingly, and surrounding the intermediate conductive connection 240a.
Although fig. 2 shows the electronic package structure 10 including two arrangements of the first conductive connectors 240 corresponding to the coaxial conductive elements 210, the invention is not limited thereto. The first conductive connection 240 of the electronic package 10 may include one or more arrangement patterns corresponding to the coaxial conductive elements 210.
In some embodiments, the coaxial conductive member 210 may be disposed around the chip 130, but the invention is not limited thereto. Although fig. 1 and fig. 2 show that the coaxial conductive elements 210 are symmetrically disposed on two sides of the chip 130, the invention is not limited thereto, and the positions and the number of the coaxial conductive elements 210 can be adjusted according to practical requirements.
In some embodiments, the electronic package structure 10 further includes a first adhesive layer 220. The first adhesive layer 220 is disposed between the interposer 200 and the circuit structure 300, so as to facilitate the bonding between the interposer 200 and the circuit structure 300.
In some embodiments, the circuit substrate 100 may be a Printed Circuit Board (PCB), a flexible printed circuit board (FPC), or other suitable circuit board. For example, the circuit substrate 100 includes a plurality of insulating layers and circuit layers (see fig. 4A for details). In some embodiments, the circuit substrate 100 includes pads 112 corresponding to the chips 130 and pads 114 corresponding to the coaxial conductors 210.
In some embodiments, chip 130 has an active surface 130a and a back surface 130b opposite active surface 130 a. The active surface 130a of the chip 130 faces the circuit substrate 100 and is electrically connected to the circuit substrate 100.
In some embodiments, electronic package 10 further includes thermal interface material 150 disposed on back side 130b of die 130 and in contact with bottom surface 230c of cavity 230. In this way, the chip 130 can dissipate heat through the thermal interface material 150 and further conduct the heat to the interposer substrate 205, so as to enhance the heat dissipation capability of the electronic package structure 10.
In some embodiments, the electronic package structure 10 further includes a second conductive connector 270, which may be disposed between the circuit substrate 100 and the coaxial conductive member 210. For example, the second conductive connection member 270 may be disposed between the pad 114 of the circuit substrate 100 and the coaxial conductive member 210, so that the pad 114 is electrically connected to the coaxial conductive member 210. In some embodiments, the material of the second conductive connector 270 may include tin, copper-tin alloy, lead-free alloy, or other suitable materials, which is not limited to the present invention.
In some embodiments, the first conductive structure 214 of the coaxial conductive member 210 is adapted to transmit signals and the second conductive structure 216 is adapted to be grounded or connected to a power source. That is, the pad 114 of the circuit substrate 100 corresponding to the first conductive structure 214 may be a signal pad, and the pad 114 of the circuit substrate 100 corresponding to the second conductive structure 216 may be a ground pad or a power pad.
Fig. 3 is a schematic cross-sectional view of an electronic package structure according to another embodiment of the invention. It should be noted that the embodiment of fig. 3 uses component reference numerals and partial contents of the embodiment of fig. 1, where the same or similar reference numerals are used to denote the same or similar components, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
Referring to fig. 3, the main differences between the electronic package structure 20 of fig. 3 and the electronic package structure 10 of fig. 1 are as follows: the interposer substrate 205 of the electronic package structure 20 includes a cavity 232, and the cavity 232 penetrates the interposer substrate 205. That is, the cavity 232 is formed by the sidewalls 232a, 232b of the interposer substrate 205, but has no bottom surface, so that the cavity 232 may expose the surface of the first adhesive layer 220.
In the present embodiment, the back surface 130b of the chip 130 is not provided with a thermal interface material, but is not limited to the present invention, and the thermal interface material may be provided according to practical requirements.
Fig. 4A to 4C are schematic cross-sectional views illustrating a manufacturing process of a chip disposed on a circuit substrate according to an embodiment of the invention. It should be noted that the embodiments of fig. 4A to 4C use component numbers and part of the contents of the embodiment of fig. 1, wherein the same or similar components are denoted by the same or similar numbers, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
Referring to fig. 4A, a circuit substrate 100 is provided. For example, the circuit substrate 100 may include a core substrate 101 and insulating layers 102 and circuit layers 110 alternately stacked on both sides of the core substrate 101. The topmost layer of the circuit layer 110 may include a plurality of pads 112, 114, the pad 112 may be a pad for subsequent corresponding connection with a contact of the chip 130, and the pad 114 may be a pad for subsequent corresponding connection with the coaxial conductive member 210.
It should be understood that fig. 4A only schematically illustrates two insulating layers 102 and four circuit layers 110 on the core layer 101, but is not limited to the present invention, and the number of insulating layers and circuit layers and the layout of the circuit layers can be adjusted according to practical requirements. In addition, although any via is not shown in the core layer of the present invention, the present invention is not limited thereto, and the via may be disposed in the core layer according to actual requirements.
Referring to fig. 4B, solder masks 120 are formed on both sides of the circuit substrate 100. The solder mask layer 120 has a plurality of openings OP1 to expose the outermost part of the circuit layer 110 of the circuit substrate 100. For example, the pads 112, 114 are exposed by the opening OP1 to facilitate subsequent connection with other components. The material of the solder mask layer 120 may be a solder mask material (e.g., green paint), a photosensitive dielectric material, or other suitable material.
Referring to fig. 4C, a chip 130 is disposed on the circuit substrate 100. For example, the active surface 130a of the chip 130 may include a plurality of contacts 132, and the contacts 132 correspond to the pads 112 of the circuit substrate 100, so that the chip 130 is disposed on the circuit substrate 100 and electrically connected.
In some embodiments, before the contacts 132 of the chip 130 are correspondingly connected to the pads 112 of the circuit substrate 100, an underfill 140 may be disposed in the openings OP1 exposing the pads 112, and then the subsequent bonding is performed to improve the bonding strength between the chip 130 and the circuit substrate 100, wherein the underfill 140 is made of, for example, an epoxy solder paste (epoxy solder paste) or other suitable materials. In other embodiments, the material of the underfill 140 may be epoxy flux (epoxy flux), epoxy glue (epoxy glue) or other suitable materials, and the underfill 140 may be disposed between the chip 130 and the circuit substrate 100 after the contacts 132 of the chip 130 are correspondingly connected to the pads 112 of the circuit substrate 100. In still other embodiments, the underfill 140 may not be provided, and the contacts 132 of the chip 130 may be directly bonded to the pads 112 of the circuit substrate 100.
In some embodiments, the underfill 140 may be disposed in a space between the chip 130 and the circuit substrate 100 to laterally cover a portion of the sidewalls of the contacts 132 or to entirely cover the sidewalls of the contacts 132.
In some embodiments, the thermal interface material 150 may be disposed on the back surface 130b of the crystal plane 130, but the invention is not limited thereto.
The fabrication of the structure 100' of the circuit substrate 100 including the chip 130 can be substantially completed after the above-mentioned processes.
Fig. 5A-5F are schematic cross-sectional views of a manufacturing process of an interposer substrate including coaxial conductors according to an embodiment of the invention. It should be noted that the embodiments of fig. 5A to 5F use component reference numerals and partial contents of the embodiment of fig. 1, wherein the same or similar reference numerals are used to denote the same or similar components, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
Referring to fig. 5A, a core substrate 201 is provided. For example, the core substrate 201 includes a first side 201a and a second side 201b opposite to the first side 201 a. The core substrate 201 may be, for example, a copper plate, an aluminum plate, an alloy plate, or other suitable conductive material. The thickness of the core substrate 201 may be between 150 μm and 250 μm.
Referring to fig. 5B, a first through hole TH1 is formed in the core substrate 201. For example, the first through holes TH1 penetrating the core substrate 201 may be formed in the core substrate 201 by mechanical drilling or etching. The aperture d1 of the first through hole TH1 may be between 250 μm and 450 μm.
Referring to fig. 5C, the insulating material 211 is filled in the first through holes TH 1. The insulating material 211 may be, for example, epoxy, polyester, polyimide, or other suitable insulating material.
Referring to fig. 5D, a second through hole TH2 is formed in the insulating material 211 to form a first insulating structure 212. For example, the second through holes TH2 may be formed at the center of the insulating material 211 by mechanical drilling or laser, etc. That is, the second through hole TH2 and the first through hole TH1 (shown in fig. 5B) have substantially the same axis. The aperture d2 of the second through holes TH2 may be between 50 μm and 100 μm. Due to the formation of the second through holes TH2, the insulating material 211 is partially removed to become the first insulating structure 212. The first insulating structure 212 is a hollow cylinder, that is, the first insulating structure 212 is annular in shape when viewed from above.
Referring to fig. 5E, a first conductive material layer 202 is formed on the first side 201a and the second side 201b of the core substrate 201 and in the second through holes TH2 (shown in fig. 5D). For example, a conductive material (e.g., copper, aluminum, or other suitable conductive material or an alloy thereof) may be formed on the first side 201a and the second side 201b of the core substrate 201 by electroplating or deposition process, and filled into the second through holes TH2 to form the first conductive material layer 202. In some embodiments, the first conductive material layer 202 may fill in the second through holes TH2.
In some embodiments, the material of the first conductive material layer 202 and the core substrate 201 are the same, so there may be no interface between the first conductive material layer 202 and the core substrate 201, but for clarity of the manufacturing process, fig. 5E and 5F distinguish the first conductive material layer 202 from the core substrate 201 by dotted lines.
Referring to fig. 5F, the first conductive material layer 202 is patterned to expose a portion of the first insulating structure 212. For example, the first conductive material layer 202 may be patterned by etching to remove a portion of the first conductive material layer 202 covering the first insulating structure 212, thereby forming an opening OP2 in the first conductive layer 203. That is, the opening OP2 may expose the first insulating structure 212, and the first conductive layer 203 covers the first side 201a and the second side 201b of the core substrate 201 and fills the second through hole TH2 (shown in fig. 5D). The first insulating structure 212, a portion of the first conductive layer 203, and a portion of the core substrate 201 may form a coaxial conductive element 210. In detail, the coaxial conductive member 210 may include a first conductive structure 214, a second conductive structure 216, and a first insulating structure 212. The first conductive structure 214 may include a first conductive pillar portion 214b and first pad portions 214a located at two ends of the first conductive pillar portion 214b. The first pad portion 214a is disposed on the first side 201a and the second side 201b and overlaps the second through hole TH2, and the first conductive pillar portion 214b is disposed in the second through hole TH2 to electrically connect the first pad portions 214a at two ends thereof. That is, a portion of the first conductive layer 203 may constitute the first pad portion 214a and the first conductive pillar portion 214b. In some embodiments, the diameter of the first pad portion 214a may be greater than the diameter of the first conductive post portion 214b, e.g., the diameter d3 of the first pad portion 214a may be between 75 μm and 175 μm and the diameter d4 of the first conductive post portion 214b may be between 50 μm and 100 μm.
The second conductive structure 216 surrounds the first conductive structure 214. The second conductive structure 216 may include a second conductive pillar portion 216b and second pad portions 216a located at both ends of the second conductive pillar portion 216 b. The second pad portion 216a is disposed on the first side 201a and the second side 201b and surrounds the first pad portion 214a, and the opening OP2 separates the first pad portion 214a from the second pad portion 216a, that is, the second pad portion 216a is not connected to the first pad portion 214 a. The second conductive post portion 216b is connected to the second pad portion 216a at both ends thereof and surrounds the first conductive post portion 214b. The first insulating structure 212 is disposed between the first conductive structure 214 and the second conductive structure 216 to electrically separate the first conductive structure 214 from the second conductive structure 216. In the present embodiment, the second pad portion 216a may be formed by a portion of the first conductive layer 203, and the second conductive pillar portion 216b may be formed by a portion of the core substrate 201.
In some embodiments, the core substrate 201 and the first conductive layer 203 may constitute an interposer substrate 205. In other words, a portion of the interposer substrate 205 may constitute the first conductive structure 214 and the second conductive structure 216 of the coaxial conductive element 210.
The interposer 200 including the coaxial conductive element 210 may be substantially completed after the above-described process.
Fig. 6A-6F are schematic cross-sectional views of a process flow of manufacturing an interposer substrate including coaxial conductors according to another embodiment of the present invention. It should be noted that the embodiments of fig. 6A to 6F use component numbers and part of the content of the embodiments of fig. 5A to 5F, wherein the same or similar components are denoted by the same or similar numbers, and the description of the same technical content is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
Referring to fig. 6A, a core substrate 201' is provided, wherein the core substrate 201' has a first side 201a ' and a second side 201b ' opposite to the first side 201a '. The core substrate 201' may be, for example, a copper plate, an aluminum plate, an alloy plate, or other suitable conductive material. The thickness of the core substrate 201' may be between 150 μm and 250 μm.
Referring to fig. 6B, an annular groove T is formed on the first side 201a 'of the core substrate 201', wherein the annular groove T does not penetrate through the second side 201B 'of the core substrate 201'. For example, the annular groove T may be etched on the first side 201a 'of the core substrate 201' by etching, as shown in the area A1 of fig. 6B, and the area A1 is a top view of the annular groove T. The portion P of the core substrate 201' surrounded by the annular groove T has substantially the same axis as the annular groove T.
In some embodiments, the distance d5 from the bottom surface of the annular groove T to the second side 201b' may be between 50 μm and 100 μm, but the invention is not limited thereto. In some embodiments, the outer diameter d6 of the annular groove T may be between 250 μm and 450 μm, but the invention is not limited thereto. In some embodiments, the width d7 of the annular groove T may be between 100 μm and 175 μm, but the invention is not limited thereto.
Referring to fig. 6C, an insulating material is filled in the annular groove T to form a first insulating structure 212.
Referring to fig. 6D, a portion of the core substrate 201' is removed from the second side 201b ' of the core substrate 201' until the first insulating structure 212 is exposed. For example, a portion of the core substrate 201' may be removed by etching, mechanical polishing, or the like, such that the second side 201b ' of the core substrate 201' is flush with the bottom surface of the first insulating structure 212.
Referring to fig. 6E, a first conductive material layer 202 'is formed on a first side 201a' and a second side 201b 'of a core substrate 201'. For example, a conductive material (e.g., copper, aluminum, or other suitable conductive material, or an alloy thereof) may be formed on the first side 201a 'and the second side 201b' of the core substrate 201 'and over the first insulating structure 212 by an electroplating or deposition process to form the first conductive material layer 202'. In some embodiments, the first conductive material layer 202 'and the core substrate 201' are made of the same material, so there may be no interface between the first conductive material layer 202 'and the core substrate 201', but the first conductive material layer 202 'is distinguished from the core substrate 201' by a dotted line in fig. 6E and 6F for clarity of the manufacturing process.
Referring to fig. 6F, the first conductive material layer 202' is patterned to expose a portion of the first insulating structure 212. For example, the first conductive material layer 202' may be patterned by etching to remove the first conductive material layer 202' partially covering the first insulating structure 212, thereby forming an opening OP3 in the first conductive layer 203 '. That is, the opening OP3 may expose the first insulating structure 212, and the first conductive layer 203 'covers the first side 201a' and the second side 201b 'of the core substrate 201'. The first insulating structure 212, a portion of the first conductive layer 203', and a portion of the core substrate 201' may form a coaxial conductive member 210. In detail, the coaxial conductive member 210 may include a first conductive structure 214, a second conductive structure 216, and a first insulating structure 212. The first conductive structure 214 may include a first conductive pillar portion 214b and first pad portions 214a located at two ends of the first conductive pillar portion 214b. The first pad portion 214a is disposed on the first side 201a 'and the second side 201B' and overlaps with a portion P (shown in fig. 6B) surrounded by the annular groove T (shown in fig. 6B), and the first conductive pillar portion 214B is formed by the portion P surrounded by the annular groove T (shown in fig. 6B) to electrically connect the first pad portions 214a at both ends thereof. That is, a portion of the first conductive layer 203 'may constitute the first pad portion 214a, and the core substrate 201' may constitute the first conductive pillar portion 214b.
The second conductive structure 216 surrounds the first conductive structure 214. The second conductive structure 216 may include a second conductive pillar portion 216b and second pad portions 216a located at both ends of the second conductive pillar portion 216 b. The second pad portion 216a is disposed on the first side 201a 'and the second side 201b' and surrounds the first pad portion 214a, and the opening OP3 separates the first pad portion 214a from the second pad portion 216a, that is, the second pad portion 216a is not connected to the first pad portion 214 a. The second conductive post portion 216b is connected to the second pad portion 216a at both ends thereof and surrounds the first conductive post portion 214b. The first insulating structure 212 is disposed between the first conductive structure 214 and the second conductive structure 216 to electrically separate the first conductive structure 214 from the second conductive structure 216. In the present embodiment, the second pad portion 216a may be formed by a portion of the first conductive layer 203', and the second conductive pillar portion 216b may be formed by a portion of the core substrate 201'.
In some embodiments, the core substrate 201 'and the first conductive layer 203' may constitute an interposer substrate 205. In other words, a portion of the interposer substrate 205 may constitute the first conductive structure 214 and the second conductive structure 216 of the coaxial conductive element 210.
The interposer 200 including the coaxial conductive element 210 may be substantially completed after the above-described process.
Fig. 7A to 7D are schematic cross-sectional views illustrating a manufacturing process of a first conductive connector according to an embodiment of the invention. Fig. 8A-8B are partial top views of the region R1 of fig. 7B. It should be noted that the embodiments of fig. 7A to 7D use component numbers and part of the contents of the embodiment of fig. 1, wherein the same or similar components are denoted by the same or similar numbers, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
Referring to fig. 7A, a first adhesive material layer 220' is formed on one side of the interposer 200. For example, the interposer 200 may be the interposer 200 including the coaxial conductive element 210 manufactured in fig. 5A to 5F or the interposer 200 including the coaxial conductive element 210 manufactured in fig. 6A to 6F, and the description is omitted herein for the sake of brevity. The first adhesive material layer 220 'may be formed on the upper surface 205a of the interposer substrate 205 of the interposer 200 by lamination (lamination) such that the first adhesive material layer 220' covers the first pad portion 214a and the second pad portion 216a on the upper surface 205a of the interposer substrate 205. The first adhesive material layer 220 'may be in a semi-cured state, for example, the first adhesive material layer 220' may include a resin in a semi-cured state, such as a B-stage (B-stage) epoxy glue/tape, a B-stage (B-stage) epoxy-containing fiberglass layer (prepreg), or other suitable materials. In some embodiments, the side of the first adhesive material layer 220 'not in contact with the interposer substrate 205 may include a release film 222, that is, the first adhesive material layer 220' is located between the interposer substrate 205 and the release film 222, but the invention is not limited thereto.
Referring to fig. 7B, a plurality of through holes V1 are formed in the first adhesive layer 220' to expose a portion of the coaxial conductive member 210. For example, a plurality of vias V1 may be formed in the first adhesive material layer 220' and the release film 222 (if any) by laser drilling. The plurality of through holes V1 may expose a portion of the first pad portion 214a and a portion of the second pad portion 216a of the coaxial conductive member 210.
In some embodiments, as shown in fig. 8A in a top view, the plurality of through holes V1 may include a through hole V1a and a plurality of through holes V1b surrounding the through hole V1 a. The through holes V1a correspond to the first pad portions 214a to expose a portion of the first pad portions 214a, and the plurality of through holes V1b correspond to the second pad portions 216a to expose a portion of the second pad portions 216a. In the present embodiment, only 6 through holes V1b surrounding the through hole V1a are schematically shown, but the present invention is not limited thereto, and the number of the through holes V1b can be adjusted according to practical requirements. For example, the shortest distance between adjacent through holes V1b may be designed to be less than or equal to 1/10 of the wavelength of the radio wave to be transmitted.
In other embodiments, as shown in fig. 8B, the plurality of vias V1 may include a via V1a ' and a single via V1B ' surrounding the via V1a ' in a top view. The through hole V1b' may be provided in a ring shape corresponding to the second pad portion 216a to expose a portion of the second pad portion 216a.
Referring to fig. 7C and 7D, a first conductive connection material 240' is formed in the plurality of vias V1, and then the release film 222 (if any) is removed. The first conductive connection material 240' may be, for example, silver paste, copper paste, transient liquid phase sintering (Transient Liquid Phase Sintering; TLPS) conductive paste, or other suitable material.
The fabrication of the interposer 200 'including the coaxial conductive element 210 and the first conductive connecting material 240' may be substantially completed after the above-described process.
Fig. 9A to 9C are schematic diagrams of a circuit structure according to an embodiment of the present invention. It should be noted that the embodiment of fig. 9A to 9C uses component reference numerals and partial contents of the embodiment of fig. 1, in which the same or similar reference numerals are used to denote the same or similar components, and the description of the same technical contents is omitted. Reference may be made to the foregoing embodiments for description of omitted parts, which are not repeated here.
Referring to fig. 9A to 9C, the circuit structure 300 includes a first core layer 301, a first antenna layer 312, a second antenna layer 314, and a plurality of pads 316. The first core layer 301 has a first surface 301a and a second surface 301b opposite to the first surface 301 a. The first antenna layer 312 is disposed on the first surface 301 a. The second antenna layer 314 and the plurality of pads 316 are disposed on the second surface 301b, that is, the second antenna layer 314 and the plurality of pads 316 are the same film layer. The plurality of pads 316 may correspond to the coaxial conductor 210 to facilitate subsequent connection to the coaxial conductor 210. For example, the plurality of pads 316 may include a first pad 316a and a second pad 316b. The first pad 316a corresponds to the first pad portion 214a of the coaxial conductor 210 and the second pad 316b corresponds to the second pad portion 216a of the coaxial conductor 210.
In some embodiments, as shown in fig. 9B, the second pads 316B may be a plurality of second pads 316B'. The plurality of second pads 316b 'corresponds to the second conductive structures 216 of the coaxial conductive member 210, wherein the plurality of second pads 316b' surround the first pads 316a. In other embodiments, as shown in fig. 9C, the second pad 316b may be a single second pad 316b. The second pad 316b is annular and surrounds the first pad 316a, and may correspond to the second conductive structure 216 of the coaxial conductive member 210.
In some embodiments, the wiring structure 300 further includes conductive layers 311, 313 and insulating layers 302, 303. The conductive layers 311 and 313 are disposed on the first surface 301a and the second surface 301b of the core layer 301, respectively. The insulating layer 302 is disposed between the conductive layer 311 and the first antenna layer 312, and has a via CV1 disposed in the insulating layer 302 to electrically connect the conductive layer 311 and the first antenna layer 312. The insulating layer 303 is disposed between the conductive layer 313 and the second antenna layer 314, and has a via CV2 disposed in the insulating layer 303 to electrically connect the conductive layer 313 and the second antenna layer 314 or the pad 316.
In some embodiments, the circuit structure 300 further includes a conductive pillar 305 penetrating the first core layer 301 to electrically connect the conductive layer 311 and the conductive layer 313. The conductive pillars 305 may be, for example, solid metal pillars or hollow metal pillars, and the hollow metal pillars are filled with an insulating material, which is not limited by the present invention. In other embodiments, the wiring structure 300 may not include conductive pillars that extend through the first core layer 301.
It should be understood that fig. 9A only schematically illustrates the insulating layers, the conductive layers and the antenna layers of the circuit structure 300, but is not limited to the present invention, and the number of the insulating layers, the conductive layers and the antenna layers and the wiring design can be adjusted according to practical requirements.
Fig. 10A to 10E are schematic cross-sectional views illustrating a manufacturing process of an electronic package structure according to an embodiment of the invention.
Referring to fig. 10A, a circuit structure 300 is provided. The circuit structure 300 is, for example, the circuit structure 300 shown in fig. 9A, and the related description is referred to above and is not repeated here. A solder mask 320 is formed on the surface of the insulating layers 302 and 303 to cover the first antenna layer 312 and the second antenna layer 314. The solder mask layer 320 has a plurality of through holes V2 to expose a portion of the pads 316. The material of the solder mask 320 may be a solder mask material (e.g., green paint), a photosensitive dielectric material, or other suitable material.
Referring to fig. 10A and 10B, a plurality of pads 316 of the circuit structure 300 are correspondingly connected to the first conductive connection material 240' disposed on the interposer 200. For example, the first conductive connection material 240 'may be disposed on the interposer 200, such as the structure 200' shown in fig. 7D, and the description is omitted herein for brevity. Then, the first conductive connection material 240 'disposed on the first pad portion 214a of the coaxial conductive member 210 corresponds to the pad 316a of the connection circuit structure 300, and the first conductive connection material 240' disposed on the second pad portion 216a of the coaxial conductive member 210 corresponds to the pad 316b of the connection circuit structure 300.
Then, the circuit structure 300 and the interposer 200 are pressed at a first temperature to cure the first adhesive material layer 220' to a C-stage (C-stage) to form the first adhesive layer 220. The first temperature is for example between 180 ℃ and 220 ℃.
In some embodiments, the first conductive connecting material 240' may be melted at the first temperature and then solidified to form the first conductive connecting member 240, so that the plurality of pads 316 of the circuit structure 300 and the corresponding coaxial conductive members 210 may be well bonded and electrically connected. In some embodiments, if the first conductive connection material 240' is a transient liquid phase sintering conductive paste, since the conductive paste includes metal solder particles (such as copper, tin-bismuth alloy, etc.), the combination of the metal particles that can generate liquid phase at the interface by heating, and then the intermetallic compound (intermetallic compound, IMC) is formed by solidification, so as to improve the bonding force of the interface and have good conductivity.
Referring to fig. 10C, a cavity 230 is formed in the lower surface 205b of the interposer substrate 205 to form the interposer 200. For example, a patterned photoresist layer PR may be formed on the lower surface 205b of the interposer substrate 205. The patterned photoresist layer PR covers the coaxial conductive member 210 and exposes a portion of the lower surface 205b of the interposer substrate 205. The interposer substrate 205 is then etched using the patterned photoresist layer PR as a mask to form the cavity 230. In the present embodiment, the cavity 230 does not etch through the interposer substrate 205, so the cavity 230 is formed by the sidewalls 230a, 230b and the bottom 230c of the interposer substrate 205, but the invention is not limited thereto. In other embodiments, the cavity 230 may etch through the interposer substrate 205, exposing the first adhesion layer 220.
Referring to fig. 10D, the patterned photoresist layer PR is removed. A solder mask layer 260 is formed on the lower surface 205b of the interposer substrate 205. The solder mask layer 260 includes a plurality of through holes V3 to expose a portion of the coaxial conductive member 210, such as a portion of the first pad portion 214a and a portion of the second pad portion 216a of the coaxial conductive member 210 on the lower surface 205 b. The material of the solder mask 260 may be a solder mask material (e.g., green paint), a photosensitive dielectric material, or other suitable material.
Referring to fig. 10E, a second conductive connecting material 270' is formed in the plurality of through holes V3 (shown in fig. 10D). The second conductive connection material 270' may be, for example, solder paste, solder balls, or other suitable material.
Then, referring to fig. 1, the circuit substrate 100 is bonded on the lower surface 205b of the interposer substrate 205 at the second temperature, and the chip 130 is disposed in the cavity 230. For example, the chip 130 may be disposed on the circuit substrate 100, such as the structure 100' shown in fig. 4C, and the description is omitted herein for brevity. Then, the chip 130 is corresponding to the cavity 230 of the interposer substrate 205, and the second conductive connecting material 270' is corresponding to the bonding pad 114 of the circuit substrate 100, so that the interposer 200 and the circuit substrate 100' can be bonded and electrically connected through the second conductive connecting material 270 '. In some embodiments, the second conductive connection material 270' may be subjected to a reflow process at a second temperature to form the second conductive connection 270, so as to enhance the bonding strength between the interposer 200 and the 100 circuit substrate. In some embodiments, the second temperature is between 250 ℃ and 270 ℃.
The fabrication of the electronic package 10 may be substantially completed after the above-described process.
In summary, the electronic package structure of the present invention can integrate the circuit substrate, the interposer and the circuit structure in a package structure, and the chip is disposed in the cavity of the interposer, so that the space is effectively utilized, which is beneficial to miniaturization of the electronic package structure, and the interposer is made of conductive material, which is beneficial to improving heat dissipation capability of the chip. In addition, because the intermediate layer comprises the coaxial conductive element for electrically connecting the circuit structure and the circuit substrate, the signal loss of the radio frequency signal received or sent by the circuit structure in the transmission process can be reduced, and the electromagnetic interference signal can be shielded, so that the signal integrity is improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (20)
1. An electronic package structure, comprising:
an interposer, comprising:
an interposer substrate having an upper surface and a lower surface opposite the upper surface, wherein the interposer substrate comprises a cavity; and
a coaxial conductor in the interposer substrate, the coaxial conductor comprising:
a first conductive structure;
a second conductive structure surrounding the first conductive structure; and
the first insulating structure is arranged between the first conductive structure and the second conductive structure;
the circuit substrate is arranged on the lower surface of the medium layer substrate and is electrically connected with the coaxial conductive piece;
the chip is arranged in the cavity and is positioned on the circuit substrate so as to be electrically connected with the circuit substrate; and
the circuit structure is arranged on the upper surface of the medium layer substrate and is electrically connected with the coaxial conductive piece.
2. The electronic package of claim 1, wherein the interposer substrate comprises a conductive material.
3. The electronic package of claim 1, further comprising:
and the thermal interface material is arranged on the back surface of the chip and is contacted with the medium layer substrate.
4. The electronic package of claim 1, wherein the wiring structure comprises:
a first core layer having a first surface and a second surface opposite the first surface, wherein the second surface faces the interposer;
a first antenna layer disposed on the first surface;
a second antenna layer disposed on the second surface; and
and the plurality of connecting pads are arranged on the second surface and correspond to the coaxial conductive piece.
5. The electronic package of claim 4, wherein the plurality of pads comprises:
a first pad corresponding to the first conductive structure of the coaxial conductive member; and
and the second connecting pad corresponds to the second conductive structure of the coaxial conductive piece, wherein the second connecting pad is annular.
6. The electronic package of claim 4, wherein the plurality of pads comprises:
a first pad corresponding to the first conductive structure of the coaxial conductive member; and
and a plurality of second connection pads corresponding to the second conductive structures of the coaxial conductive member, wherein the plurality of second connection pads encircle the first connection pads.
7. The electronic package of claim 4, further comprising:
the first conductive connecting piece is arranged between the plurality of connection pads of the circuit structure and the coaxial conductive piece.
8. The electronic package of claim 1, further comprising:
the first adhesion layer is arranged between the intermediate layer and the circuit structure.
9. The electronic package of claim 1, wherein the circuit substrate includes a plurality of pads corresponding to the coaxial conductors, the electronic package further comprising:
the second conductive connecting piece is arranged between the circuit substrate and the coaxial conductive piece.
10. The electronic package of claim 1, wherein the first conductive structure of the coaxial conductive member is adapted to transmit signals and the second conductive structure is adapted to be grounded or connected to a power source.
11. A method of manufacturing an electronic package, comprising:
providing a circuit substrate;
setting a chip on the circuit substrate;
providing an interposer, the interposer comprising:
An interposer substrate having an upper surface and a lower surface opposite to the upper surface; and
a coaxial conductive member is located in the interposer substrate, wherein the coaxial conductive member comprises:
a first conductive structure;
a second conductive structure surrounding the first conductive structure; and
the first insulating structure is arranged between the first conductive structure and the second conductive structure;
providing a circuit structure, and pressing the circuit structure on the upper surface of the interposer substrate at a first temperature;
forming a cavity in the lower surface of the interposer substrate; and
and at a second temperature, bonding the circuit substrate on the lower surface of the interposer substrate, and arranging the chip in the cavity.
12. The method of manufacturing according to claim 11, wherein the step of forming the interposer includes:
providing a core substrate having a first side and a second side opposite the first side;
forming a first through hole in the core substrate;
filling an insulating material in the first through hole;
forming a second through hole in the insulating material to form the first insulating structure;
Forming a first conductive material layer on the first side and the second side of the core substrate and in the second through hole; and
the first conductive material layer is patterned to expose a portion of the first insulating structure.
13. The method of manufacturing according to claim 12, wherein the first through-hole has a pore size of between 250 μm and 450 μm and the second through-hole has a pore size of between 50 μm and 100 μm.
14. The method of manufacturing according to claim 11, wherein the step of forming the interposer includes:
providing a core substrate having a first side and a second side opposite the first side;
forming an annular groove on the first side of the core substrate, wherein the annular groove does not extend through the second side of the core substrate;
filling an insulating material in the annular groove to form the first insulating structure;
removing a portion of the core substrate from the second side of the core substrate until the first insulating structure is exposed;
forming a first conductive material layer on the first side and the second side of the core substrate; and
the first conductive material layer is patterned to expose a portion of the first insulating structure.
15. The manufacturing method according to claim 11, characterized in that the manufacturing method further comprises:
forming a first adhesive material layer on the upper surface of the interposer substrate, wherein the first adhesive material layer is in a semi-cured state;
forming a plurality of through holes in the first adhesive material layer to expose a part of the coaxial conductive member;
a first conductive connection material is formed in the plurality of vias.
16. The method of manufacturing of claim 15, wherein the first conductive connection material comprises copper paste, silver paste, or transient liquid phase sintering paste.
17. The method of manufacturing of claim 15, wherein bonding the wiring structure to the upper surface of the interposer substrate comprises:
and pressing the circuit structure and the interposer substrate at the first temperature to correspondingly connect the plurality of connection pads of the circuit structure with the first conductive connecting material, and curing the first adhesive material layer.
18. The method of manufacturing of claim 11, wherein the step of bonding the circuit substrate to the lower surface of the interposer substrate comprises:
forming a solder mask layer on the lower surface of the interposer substrate, wherein the solder mask layer includes a plurality of through holes to expose a portion of the coaxial conductive members;
Forming a second conductive connection material in the plurality of vias; and
and correspondingly jointing the coaxial conductive piece and the plurality of connection pads of the circuit substrate through the second conductive connecting material.
19. The method of manufacturing of claim 18, wherein the second conductive connection material comprises solder paste or balls.
20. The method of manufacturing according to claim 11, wherein the first temperature is between 180 ℃ and 220 ℃ and the second temperature is between 250 ℃ and 270 ℃.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US202263312102P | 2022-02-21 | 2022-02-21 | |
| US63/312,102 | 2022-02-21 |
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| CN116666327A true CN116666327A (en) | 2023-08-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210880439.2A Pending CN116666327A (en) | 2022-02-21 | 2022-07-25 | Electronic packaging structure and manufacturing method thereof |
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| CN (1) | CN116666327A (en) |
| TW (1) | TWI825870B (en) |
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|---|---|---|---|---|
| KR102179166B1 (en) * | 2017-05-19 | 2020-11-16 | 삼성전자주식회사 | Antenna substrate and semiconductor combined module |
| TW202118026A (en) * | 2019-06-26 | 2021-05-01 | 日商索尼半導體解決方案公司 | Semiconductor device and method for producing same |
| KR20210044055A (en) * | 2019-10-14 | 2021-04-22 | 삼성전자주식회사 | Light emitting diode module and display apparatus including the same |
| KR20220021755A (en) * | 2020-08-14 | 2022-02-22 | 삼성전자주식회사 | Semiconductor package having a antenna |
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| TW202335558A (en) | 2023-09-01 |
| TWI825870B (en) | 2023-12-11 |
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