CN116666323A - Heat dissipation system for multi-chip interconnection structure - Google Patents

Heat dissipation system for multi-chip interconnection structure Download PDF

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Publication number
CN116666323A
CN116666323A CN202310363104.8A CN202310363104A CN116666323A CN 116666323 A CN116666323 A CN 116666323A CN 202310363104 A CN202310363104 A CN 202310363104A CN 116666323 A CN116666323 A CN 116666323A
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CN
China
Prior art keywords
heat dissipation
layer
heat
chip
interconnect structure
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Pending
Application number
CN202310363104.8A
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Chinese (zh)
Inventor
李霞
姜申飞
胡杨
王浩
潘岳
王立华
朱小云
王磊
郝培霖
韩慧明
莫志文
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Tsinghua University
Shanghai AI Innovation Center
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Tsinghua University
Shanghai AI Innovation Center
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Application filed by Tsinghua University, Shanghai AI Innovation Center filed Critical Tsinghua University
Priority to CN202310363104.8A priority Critical patent/CN116666323A/en
Publication of CN116666323A publication Critical patent/CN116666323A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The application relates to the technical field of chip heat dissipation, and provides a heat dissipation system for a multi-chip interconnection structure, which comprises: a chip interconnection layer including a plurality of dies; and a heat dissipation layer disposed on the chip interconnection layer, the heat dissipation layer comprising a plurality of heat dissipation elements, wherein at least one of the plurality of heat dissipation elements is disposed over one of the plurality of dies. The application can effectively improve the heat radiation capability of the heat radiation system, meet the heat radiation requirement of the wafer-level chips with the whole power reaching 25kW and the single-chip power reaching 500W, and better solve the heat radiation problem of the high heat source area of the chips. And the heat dissipation elements can be constructed into different structures so as to have different heat dissipation capacities, and the heat dissipation elements are arranged according to the gradient ordering of the heat dissipation capacities, so that the problem of the temperature uniformity of the chip can be solved.

Description

Heat dissipation system for multi-chip interconnection structure
Technical Field
The present application relates generally to the field of chip heat dissipation technology. In particular, the present application relates to a heat dissipation system for a multi-chip interconnect structure.
Background
As the scale of integration of chips increases, the power required per unit area of the chip increases. An increase in power per unit area of the chip will result in an increase in heat flux density (heat flux) on the chip, so that the heat generation amount of the chip increases, which in turn results in an increasing heat dissipation problem of the chip. Especially, in the case of wafer-level chips of multi-chip interconnection, since a plurality of chips are connected to each other, when the chips are heated seriously and the temperature distribution is not uniform, damage to devices and equipment is easily caused.
Disclosure of Invention
To at least partially solve the above-mentioned problems in the prior art, the present application proposes a heat dissipation system for a multi-chip interconnect structure, comprising:
a chip interconnection layer including a plurality of dies; and
a heat spreading layer disposed on the chip interconnection layer, the heat spreading layer comprising a plurality of heat spreading elements, wherein at least one of the plurality of heat spreading elements is disposed over one of the plurality of dies.
In one embodiment of the application, it is provided that each heat dissipating element is arranged on one of the plurality of dies.
In one embodiment of the present application, it is provided that the heat dissipation system for a multi-chip interconnection structure further includes:
and a cover plate layer disposed on the heat dissipation layer, wherein the heat dissipation layer is configured to conduct heat generated by the chip interconnection layer to the cover plate layer, and the cover plate layer is configured to exchange heat with the heat dissipation layer.
In one embodiment of the application, it is provided that the cover layer comprises:
a coolant inlet disposed on a first side of the cover sheet layer, wherein coolant flows into the cover sheet layer from the coolant inlet; and
a coolant outlet disposed on a second side of the cover sheet layer opposite the first side, wherein the coolant flows from the first side to the second side of the cover sheet layer while exchanging heat with the heat dissipation layer, and flows out of the coolant outlet.
In one embodiment of the application, it is provided that the heat dissipation layer further comprises:
a substrate, wherein a plurality of the heat dissipation elements are arranged on the substrate.
In one embodiment of the application, it is provided that the heat dissipation layer further comprises:
a thermally conductive layer disposed between the substrate and the chip interconnect layer, wherein the thermally conductive layer is configured to conduct heat generated by the die to the heat dissipating element.
In one embodiment of the application, it is provided that the cover plate layer is configured to adjust the heat dissipation capacity of the heat dissipation system for the multi-chip interconnect structure by adjusting the flow rate of the coolant.
In one embodiment of the application, it is provided that the flow rate of the coolant is configured to be 0.6m/s to 1.5m/s.
In one embodiment of the application, it is provided that the plurality of heat dissipation elements are configured in different configurations to have different heat dissipation capacities.
In one embodiment of the application, it is provided that the heat dissipation layer comprises a first side and a second side, the first side of the heat dissipation layer corresponding to the first side of the cover plate layer and the second side of the heat dissipation layer corresponding to the second side of the cover plate layer, wherein the heat dissipation capacity of the heat dissipation element arranged at a position close to the second side of the heat dissipation layer is higher than the heat dissipation capacity of the heat dissipation element at a position close to the first side of the heat dissipation layer.
The application has at least the following beneficial effects: the application provides a heat dissipation system for a multi-chip interconnection structure, wherein a heat dissipation layer comprises a plurality of heat dissipation elements, each heat dissipation element can be respectively arranged above one of a plurality of crystal grains of the chip interconnection layer, the heat dissipation capability of the heat dissipation system can be effectively improved, the heat dissipation requirement of a wafer-level chip with the whole power reaching 25kW and the single-crystal grain power reaching 500W can be met, and the heat dissipation problem of a chip high heat source area is better solved. In addition, the heat dissipation elements can be constructed into different structures so as to have different heat dissipation capacities, and the heat dissipation elements are arranged according to the gradient ordering of the heat dissipation capacities, so that the problem of the temperature uniformity of the chip can be solved.
Drawings
To further clarify the advantages and features present in various embodiments of the present application, a more particular description of various embodiments of the present application will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the application and are therefore not to be considered limiting of its scope. In the drawings, for clarity, the same or corresponding parts will be designated by the same or similar reference numerals.
Fig. 1 is a schematic diagram of a layered structure of a heat dissipation system for a multi-chip interconnect structure according to an embodiment of the present application.
Fig. 2A shows a schematic structural diagram of a heat dissipation layer according to an embodiment of the present application.
Fig. 2B shows a schematic plan view of a heat dissipation layer in an embodiment of the application.
Fig. 3A shows a schematic structural diagram of a heat dissipating component according to an embodiment of the present application.
Fig. 3B shows a schematic plan view of a heat dissipating component in an embodiment of the present application.
Fig. 4 shows a schematic view of a heat dissipating element of different structure in one embodiment of the present application.
Fig. 5A is a schematic diagram of a heat dissipation element with a different structure according to another embodiment of the present application.
Fig. 5B is a schematic plan view of a heat dissipating component with a different structure according to another embodiment of the present application.
Fig. 6 shows a schematic diagram of a heat dissipating component with a different structure according to another embodiment of the present application.
Detailed Description
It should be noted that the components in the figures may be shown exaggerated for illustrative purposes and are not necessarily to scale. In the drawings, identical or functionally identical components are provided with the same reference numerals.
In the present application, unless specifically indicated otherwise, "disposed on …", "disposed over …" and "disposed over …" do not preclude the presence of an intermediate therebetween. Furthermore, "disposed on or above" … merely indicates the relative positional relationship between the two components, but may also be converted to "disposed under or below" …, and vice versa, under certain circumstances, such as after reversing the product direction. In the present application, the term "disposed above …" encompasses both arrangements that are in contact with each other and arrangements that are not in contact with each other, i.e., that leave a gap.
In the present application, the embodiments are merely intended to illustrate the scheme of the present application, and should not be construed as limiting.
In the present application, the adjectives "a" and "an" do not exclude a scenario of a plurality of elements, unless specifically indicated.
It should also be noted herein that in embodiments of the present application, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that the components or assemblies may be added as needed for a particular scenario under the teachings of the present application. In addition, features of different embodiments of the application may be combined with each other, unless otherwise specified. For example, a feature of the second embodiment may be substituted for a corresponding feature of the first embodiment, or may have the same or similar function, and the resulting embodiment may fall within the scope of disclosure or description of the application.
It should also be noted herein that, within the scope of the present application, the terms "identical", "equal" and the like do not mean that the two values are absolutely equal, but rather allow for some reasonable error, that is, the terms also encompass "substantially identical", "substantially equal". By analogy, in the present application, the term "perpendicular", "parallel" and the like in the table direction also covers the meaning of "substantially perpendicular", "substantially parallel".
The numbers of the steps of the respective methods of the present application are not limited to the order of execution of the steps of the methods. The method steps may be performed in a different order unless otherwise indicated.
The application is further elucidated below in connection with the embodiments with reference to the drawings.
Fig. 1 is a schematic diagram of a layered structure of a heat dissipation system for a multi-chip interconnect structure according to an embodiment of the present application. As shown in fig. 1, the heat dissipation system includes a cover plate layer 101, a heat dissipation layer 102, and a chip interconnection layer 103.
The heat dissipation layer 102 is disposed on the chip interconnection layer 103, and the cover plate layer 101 is disposed on the heat dissipation layer 102, wherein the heat dissipation layer 102 conducts heat generated by the chip interconnection layer 103 to the cover plate layer 101, and exchanges heat at the cover plate layer 101. The chip interconnection layer 103 includes a plurality of dies 108, wherein the plurality of dies 108 are connected to each other.
The cover plate layer 101 and the heat dissipation layer 102 may be integrally formed by a welding process, so as to form a finished liquid cooling heat dissipation device. A coolant inlet 104 is provided on a first side of the cover plate layer 101 and a coolant outlet 105 is provided on a second side of the cover plate layer 101 opposite the first side, the coolant inlet 104 being connectable to a water inlet pipe and the coolant outlet 104 being connectable to a water outlet pipe, wherein coolant can flow from the first side to the second side of the cover plate layer 101 and carry away heat conducted to the cover plate layer 101.
Fig. 2A shows a schematic structural diagram of a heat dissipation layer according to an embodiment of the present application. Fig. 2B shows a schematic plan view of a heat dissipation layer in an embodiment of the application. As shown in fig. 2A and 2B, the heat dissipation layer 102 includes a substrate 106 and a plurality of heat dissipation elements 107, wherein the plurality of heat dissipation elements 107 are disposed on the substrate 106. At least one of the plurality of heat dissipation elements 107 is disposed above one of the plurality of dies 108, and preferably, as shown in fig. 1, the plurality of heat dissipation elements 107 are in one-to-one correspondence with the plurality of dies 108. The heat dissipation layer 102 is attached to the chip interconnection layer 103, and a heat conduction layer may be disposed between the substrate 106 and the chip interconnection layer 103 so as to conduct heat generated during operation of the die 108 to the heat dissipation element 107.
Fig. 3A shows a schematic structural diagram of a heat dissipating component according to an embodiment of the present application. Fig. 3B shows a schematic plan view of a heat dissipating component in an embodiment of the present application. As shown in fig. 3A and 3B, the heat dissipation element 107 is disposed on the substrate 106, and the heat dissipation element 107 may include a fin pin 301 and a fin 302, wherein the fin pin 301 may be disposed at a center of the heat dissipation element 107, the fin 302 may be disposed around the fin pin 301, and a flow path may be formed between a plurality of the fins 302.
The heat dissipation effect of the heat dissipation system provided by the present application may be determined by the flow rate of the coolant in the first aspect. Simulation experiments show that the faster the flow velocity of the coolant is, the better the heat dissipation effect of the heat dissipation system is, but after the flow velocity of the coolant reaches a critical value, even if the flow velocity of the coolant is continuously increased, the heat dissipation effect of the heat dissipation system is difficult to be continuously increased. The flow rate of the coolant may preferably be 0.6m/s to 1.5m/s according to the results of the simulation experiment.
Furthermore, according to the results of the simulation experiments, the heat dissipation system is at a lower temperature on a first side near the coolant inlet 104 and at a higher temperature on a second side near the coolant outlet 104, due to the gradual absorption of heat generated by the die 108 by the coolant during the flow. In the embodiment of the application, the temperature of the hot spot on the second side near the coolant outlet 104 is up to 70 degrees celsius, so that the heat dissipation requirement of the multi-chip interconnected wafer-level chip with the power density of 25kW can be well met, and the temperature of the hot spot does not exceed 70 degrees celsius.
According to the results of the simulation experiment, the temperature of the die 108 near the first side of the heat dissipation system is lower and the temperature of the die 108 near the second side of the heat dissipation system is higher. Therefore, in another embodiment of the present application, in order to improve the temperature uniformity of the chip, the heat dissipation elements 107 having different heat dissipation capacities may be disposed at different positions over the chip, specifically, the heat dissipation capacity of the heat dissipation elements 107 disposed at a position near the second side of the heat dissipation system is higher than the heat dissipation capacity of the heat dissipation elements 107 at a position near the first side of the heat dissipation system, and thus the temperature uniformity of the chip may be improved.
In the present application, the heat dissipation capacity of the heat dissipation element 107 is determined by the structure of the heat dissipation element 107. Fig. 4 shows a schematic view of a heat dissipating element of different structure in one embodiment of the present application. As shown in fig. 4, the heat dissipating element 107 may include only the fin 302, or the heat dissipating element 107 may include the fin pin 301 and the fin 302, or the heat dissipating element 107 may include only the fin pin 301, wherein the heat dissipating capacity of the heat dissipating element 107 including only the fin pin 301 is higher than the heat dissipating capacity of the heat dissipating element 107 including both the fin pin 301 and the fin 302, and the heat dissipating capacity of the heat dissipating element 107 including both the fin pin 301 and the fin 302 is higher than the heat dissipating capacity of the heat dissipating element 107 including only the fin 302.
Fig. 5A is a schematic diagram of a heat dissipation device with a different structure according to another embodiment of the present application. Fig. 5B is a schematic plan view of a heat dissipating component with a different structure according to another embodiment of the present application. As shown in fig. 5A-B, in the heat dissipating element 107 including only the fins 302, the fins 302 may be straight fins 501, wavy fins 502, or zigzag fins 503, wherein the heat dissipating capacity of the heat dissipating element 107 having the zigzag fins 503 is higher than the heat dissipating capacity of the heat dissipating element 107 having the wavy fins 502, and the heat dissipating capacity of the heat dissipating element 107 having the wavy fins 502 is higher than the heat dissipating capacity of the heat dissipating element 107 having the straight fins 501.
Fig. 6 shows a schematic diagram of a heat dissipating component with a different structure according to another embodiment of the present application. As shown in fig. 6, in the heat dissipating element 107 including only the fin pins 301, the fin pins 301 may be aligned or staggered, wherein the heat dissipating capacity of the heat dissipating element 107 in which the fin pins 301 are staggered is higher than the heat dissipating capacity of the heat dissipating element 107 in which the fin pins 301 are symmetrically arranged. Further, the fin pins 301 may be replaced with square columns or other structures, or the heat dissipation capability of the heat dissipation element may be adjusted by adjusting the diameter of the fin pins 301 and the spacing between the fin pins 301.
According to the simulation experiment, the variation of the hot spot temperature in the direction from the first side to the second side of the heat dissipation system has symmetrical periodicity, so that in the processing process, a plurality of rows of identical heat dissipation elements 107 can be processed first, and then combined in parallel to form an integral body with equivalent heat dissipation effect. Taking the heat dissipation system provided with the 7×7 heat dissipation element 107 shown in fig. 1 as an example, units of a size of 196mm×196mm×9mm, for example, can be split into 7 units of 196mm×28mm×9mm and recombined.
Furthermore, for chips with higher power densities, for example, 50W/cm 2 To 500W/cm 2 The heat dissipation element 107 may use a micro flow channel structure with a power density of 1000W/cm 2 In the above chip, the heat dissipation member 107 may use a multi-phase, air bubble convection structure.
While various embodiments of the present application have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be apparent to those skilled in the relevant art that various combinations, modifications, and variations can be made therein without departing from the spirit and scope of the application. Thus, the breadth and scope of the present application as disclosed herein should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (10)

1. A heat dissipation system for a multi-chip interconnect structure, comprising:
a chip interconnection layer including a plurality of dies; and
a heat spreading layer disposed on the chip interconnection layer, the heat spreading layer comprising a plurality of heat spreading elements, wherein at least one of the plurality of heat spreading elements is disposed over one of the plurality of dies.
2. The heat dissipation system for a multi-chip interconnect structure of claim 1, wherein each heat dissipation element is disposed over one of the plurality of dies.
3. The heat dissipation system for a multi-chip interconnect structure of claim 1, further comprising:
and a cover plate layer disposed on the heat dissipation layer, wherein the heat dissipation layer is configured to conduct heat generated by the chip interconnection layer to the cover plate layer, and the cover plate layer is configured to exchange heat with the heat dissipation layer.
4. The heat dissipation system for a multi-chip interconnect structure of claim 3, wherein the cover plate layer comprises:
a coolant inlet disposed on a first side of the cover sheet layer, wherein coolant flows into the cover sheet layer from the coolant inlet; and
a coolant outlet disposed on a second side of the cover sheet layer opposite the first side, wherein the coolant flows from the first side to the second side of the cover sheet layer while exchanging heat with the heat dissipation layer, and flows out of the coolant outlet.
5. The heat dissipation system for a multi-chip interconnect structure of claim 1, wherein the heat dissipation layer further comprises:
a substrate, wherein a plurality of the heat dissipation elements are arranged on the substrate.
6. The heat dissipation system for a multi-chip interconnect structure of claim 5, wherein the heat dissipation layer further comprises:
a thermally conductive layer disposed between the substrate and the chip interconnect layer, wherein the thermally conductive layer is configured to conduct heat generated by the die to the heat dissipating element.
7. The heat dissipation system for a multi-chip interconnect structure of claim 4, wherein the cover plate layer is configured to adjust a heat dissipation capability of the heat dissipation system for a multi-chip interconnect structure by adjusting a flow rate of the coolant.
8. The heat dissipation system for a multi-chip interconnect structure of claim 7, wherein a flow rate of the coolant is configured to be 0.6m/s to 1.5m/s.
9. The heat dissipating system for a multi-chip interconnect structure of claim 4 wherein said plurality of heat dissipating elements are configured in different configurations to have different heat dissipating capabilities.
10. The heat dissipation system for a multi-chip interconnect structure of claim 9, wherein the heat dissipation layer comprises a first side and a second side, the first side of the heat dissipation layer corresponding to the first side of the cap layer and the second side of the heat dissipation layer corresponding to the second side of the cap layer, wherein a heat dissipation capacity of the heat dissipation element disposed at a location proximate to the second side of the heat dissipation layer is higher than a heat dissipation capacity of the heat dissipation element at a location proximate to the first side of the heat dissipation layer.
CN202310363104.8A 2023-04-04 2023-04-04 Heat dissipation system for multi-chip interconnection structure Pending CN116666323A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310363104.8A CN116666323A (en) 2023-04-04 2023-04-04 Heat dissipation system for multi-chip interconnection structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310363104.8A CN116666323A (en) 2023-04-04 2023-04-04 Heat dissipation system for multi-chip interconnection structure

Publications (1)

Publication Number Publication Date
CN116666323A true CN116666323A (en) 2023-08-29

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Application Number Title Priority Date Filing Date
CN202310363104.8A Pending CN116666323A (en) 2023-04-04 2023-04-04 Heat dissipation system for multi-chip interconnection structure

Country Status (1)

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CN (1) CN116666323A (en)

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