CN116662231A - Rate matching method based on M-PHY interface and storage medium thereof - Google Patents
Rate matching method based on M-PHY interface and storage medium thereof Download PDFInfo
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Abstract
The application discloses a rate matching method based on an M-PHY interface and a storage medium thereof, wherein the method comprises the following steps: acquiring first data based on the M-PHY, wherein the first data comprises first clock information and first bit width information; frequency division processing is carried out on the first clock information to obtain second clock information; registering first bit width information in a period of first clock information to obtain registered information; and splicing the register information and the second clock information to obtain second data based on the unified protocol, wherein the rate of the second data is different from that of the first data. And the second data based on the unified protocol is obtained rapidly by carrying out rate matching on the first data based on the M-PHY, so that the compatibility and the communication efficiency between the M-PHY and the unified protocol are improved.
Description
Technical Field
The application relates to the technical field of rate matching, in particular to a rate matching method based on an M-PHY interface and a storage medium thereof.
Background
With the rapid development of smart phones, the phones have become a necessity in life. The requirements of people on smart phones are also increasing. The excellent mobile phone performance can bring the feeling of fingertip dancing to the user. In order to meet the requirement, various manufacturers have put into a great deal of research and development on a central processing unit (Central Processing Unit, CPU), a memory and a storage device of the mobile phone. The development of CPU and memory has now been fairly rapid, with a doubling of operating speed. But the traditional storage device operating speeds have far behind CPU and memory. The high-speed CPU and the memory are matched with the low-speed storage device, so that the performance advantages of the CPU and the memory cannot be exerted. The need for flash memory devices is particularly urgent, leading to the advent of universal flash memory (Universal Flash Storage, UFS). Among them, the Unified Protocol (UniPro) is an application for chip-to-chip (chip-to-chip) using high-speed serial links. UniPro is defined as a generic protocol that solves general interconnect problems such as error handling, flow control, routing, or arbitration. In addition, uniPro supports M-PHY links, which provide multiple transmission modes, i.e., low and high speed, each supporting a multi-speed transmission. In practical applications, because of the lack of protocol transfer between the M-PHY of the 20-bit remote monitoring and maintenance interface (Remote Monitor and Maintenance Interface, RMMI) and the UniPro of the 40-bit RMMI, the M-PHY at different rates cannot communicate with the UniPro normally.
Disclosure of Invention
In order to solve the above problems, the present application aims to provide a rate matching method based on an M-PHY interface and a storage medium thereof, which improves compatibility and communication efficiency between the M-PHY and UniPro through rate matching.
The application solves the problems by adopting the following technical scheme:
in a first aspect, an embodiment of the present application provides a rate matching method based on an M-PHY interface, where the method includes: acquiring first data based on an M-PHY (M-physical layer), wherein the first data comprises first clock information and first bit width information; performing frequency division processing on the first clock information to obtain second clock information; registering the first bit width information in the period of the first clock information to obtain registered information; and splicing the register information and the second clock information to obtain second data based on a unified protocol, wherein the rate of the second data is different from that of the first data.
In a second aspect, another embodiment of the present application provides a rate matching method based on an M-PHY interface, including: acquiring second data based on a unified protocol, wherein the second data comprises second clock information and second bit width information; frequency division processing is carried out on the first clock information to obtain third clock information consistent with the second clock information; cutting the second bit width information according to the third clock information and storing the second bit width information in sequence to obtain cutting information; and obtaining first data based on the M-PHY according to the cutting information and the first clock information, wherein the rate of the first data is different from the rate of the second data.
In a third aspect, an embodiment of the present application provides an electronic device, including: a memory, a processor and a computer program stored on the memory and executable on the processor, which when executed, implements a rate matching method based on an M-PHY interface as described above.
In a fourth aspect, an embodiment of the present application provides a computer readable storage medium storing a computer program which, when executed by a processor, implements a rate matching method based on an M-PHY interface as described above.
According to the embodiment of the application, the first clock information is subjected to frequency division processing by acquiring the first data based on the M-PHY to obtain the second clock information, and the first bit width information is registered in the period of the first clock information to obtain the register information; and splicing the register information and the second clock information to obtain second data based on the unified protocol. And by carrying out rate matching on the first data and the second data, the compatibility and the communication efficiency between the M-PHY and the UniPro are improved.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
Fig. 1 is a flowchart of a rate matching method based on an M-PHY interface according to an embodiment of the present application;
FIG. 2 is a flowchart of step S2000 in FIG. 1;
fig. 3 is a flowchart of step S3000 in fig. 1;
fig. 4 is a flowchart of step S4000 in fig. 1;
FIG. 5 is a block diagram of the second data of FIG. 1;
fig. 6 is a flowchart of a rate matching method based on an M-PHY interface according to another embodiment of the present application;
fig. 7 is a flowchart of step S6000 in fig. 6;
FIG. 8 is a flowchart of step S7000 in FIG. 6;
FIG. 9 is a flowchart of step S8000 in FIG. 6;
FIG. 10 is a block diagram of the first data of FIG. 6;
fig. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
In the description of the present application, it should be understood that references to orientation descriptions such as upper, lower, front, rear, left, right, etc. are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.
In the description of the present application, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present application, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present application can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
The rate matching method based on the M-PHY interface and the storage medium thereof related to the embodiment of the application are based on Physical (PHY) layer protocol. Electronic devices have proliferated throughout society to support a wide range of applications and uses. As the number and variety of devices increases, there is an increasing demand for electronic devices to communicate with each other. In response to this demand, various protocols have been proposed and employed. In many cases, the protocol defines the signal levels communicated between electronic devices, as well as the associated data representations and timing. UFS uses the M-PHY physical layer developed by the mobile industry processor interface (MobileIndustryProcessorInterface, MIPI) alliance, with speeds of 2.9Gbps per thread to 5.8Gbps per thread. The UFS realizes a full duplex Low voltage differential signaling (Low-Voltage Differential Signaling, LVDS) serial port, and has a wider bandwidth than the embedded multimedia card (Embedded Multi Media Card, eMMC) standard with 8 parallel threads.
Wherein MIPI M-PHY is the physical layer supporting all chip-to-chip applications, as well as high performance cameras and memory applications. The M-PHY may operate in a High Speed (HS) mode supporting ultra-High bandwidth up to 11.6Gb/s, or in a Low Power (LP) mode. Chip-to-chip application protocols supported in the M-PHY include DigRF, uniPro, and LLI, as well as CSI-3 for high performance camera applications. In practical application, because the RMMI speed based on the M-PHY is 20-bit and the RMMI speed is 40-bit and the UniPro based on the RMMI lacks protocol transfer, the M-PHY at different speeds cannot normally communicate with the UniPro, and the compatibility of an M-PHY interface is greatly influenced.
Based on the above, the embodiment of the application provides a rate matching method based on an M-PHY interface and a storage medium thereof, which improves the compatibility and communication efficiency between the M-PHY and UniPro by performing rate matching on first data and second data. Specifically, a protocol transfer function is played between the M-PHY of the 20-bit RMMI interface and the UniPro of the 40-bit RMMI interface, so that the effect of rate matching is achieved between the M-PHY and the UniPro of different rates, wherein the matching process involves the conversion of clock and bit width information.
Referring to fig. 1, fig. 1 shows a flow of a rate matching method based on an M-PHY interface according to an embodiment of the present application. As shown in fig. 1, the rate matching method based on the M-PHY interface according to the embodiment of the present application includes the following steps:
step S1000, first data based on the M-PHY is acquired, wherein the first data comprises first clock information and first bit width information.
It will be appreciated that in order to achieve rate matching between M-PHY and UniPro at different rates, conversion of clock information (Symbol) and bit width information (Symbol) during the matching process is required. Therefore, after the first data based on the M-PHY is acquired, the first clock information rx_symbol_20b and the first bit width information rx_symbol [15:0] in the first data need to be extracted.
It is understood that the acquiring the first clock information and the first bit width information in the first data based on the M-PHY by the BRIDGE module (rmmi_bridge) in RMMI is the prior art, and will not be described herein.
And step S2000, performing frequency division processing on the first clock information to obtain second clock information.
It will be appreciated that, since the rate of the first data based on the M-PHY is different from the rate of the second data based on the unified protocol, in order to match the rate between the first data and the second data, the first clock information needs to be subjected to frequency division processing, so as to obtain second clock information applicable to the second data.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a specific implementation procedure of another embodiment of the step S2000. As shown in fig. 2, step S2000 includes at least the following steps:
step S2100, obtain first clock information.
It will be appreciated that in order to perform the analysis processing on the first clock information, the first clock information needs to be acquired. In this embodiment, the first clock information rx_symbolclk_20b in the first data is obtained through rmmi_bridge, so as to process the rx_symbolclk_20b, so that the first data is converted into a data packet consistent with the UniPro data rate. It is understood that the acquisition of the first clock information through the RMMI interface belongs to the prior art, and is not described herein.
Step S2200, frequency division processing is performed on the first clock information according to the rate of the first data and the rate of the second data.
It will be appreciated that the first data has a rate of 20-bits, the second data has a rate of 40-bits, and the second data has a rate twice that of the first data, so that in order to ensure that the converted data matches the second data, the first clock information rx_symbol_20b needs to be subjected to a frequency division process to obtain rx_symbol_40b. In other embodiments, the first clock information can also be subjected to different frequency division processes, such as divide-by-four, divide-by-eight, etc., depending on the rate of the first data and the rate of the second data. It can be appreciated that the first clock information is subjected to frequency division processing through clk_ GENERATER in rmmi_bridge, which belongs to the prior art and is not described herein.
Step S2300, outputting the second clock information.
It will be appreciated that after the second clock information rx_symbolclk_40b is obtained, it needs to be output to the UniPro-based packet so that rmmi_bridge can generate second data that matches the UniPro packet rate.
Step S3000, registering the first bit width information in the period of the first clock information to obtain the registered information.
It can be understood that after the second clock information is acquired, information extraction and storage are further required to be performed on the first bit width information, so that the first bit width information corresponding to the period of the first clock information is accurately acquired, the synchronism of the first bit width information and the second clock information is ensured, the situation that data are not matched is avoided, and the rate matching of the first data and the second data is affected.
It will be appreciated that the registers are small memory areas within the CPU for storing data, for temporarily storing data and results of operations involved in the operations. In fact, a register is a common sequential logic circuit, but the sequential logic circuit only comprises a memory circuit. The storage circuit of the register is constituted by latches or flip-flops, and since one latch or flip-flop can store 1-bit binary numbers, an N-bit register can be constituted by N latches or flip-flops. Registers are high-speed memory components of limited memory capacity that are used to temporarily store instructions, data, and addresses.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a specific implementation procedure of another embodiment of the step S3000. As shown in fig. 3, step S3000 includes at least the following steps:
step S3100, capturing the first clock information by the D-type flip-flop, and outputting the first bit width information corresponding to the first clock information.
It is understood that the D-Flip-Flop (DFF) is a Flip-Flop that outputs a result that changes according to the state of D under the action of a clock signal. The DFF is an information storage device having a memory function and two stable states, and is the most basic logic unit constituting various timing circuits, and is also an important unit circuit in a digital logic circuit. DFF has therefore found wide application in digital systems and computers. It will be appreciated that the DFF has two stable states, namely 0 and 1, and can flip from one stable state to the other under the influence of an external signal, namely the first clock signal.
It is understood that the DFF has flip-flops that are integrated with flip-flops and gates. The triggering mode includes level triggering and edge triggering, the former can be triggered when Clock Pulse (CP) =1, and the latter is triggered at the front edge (positive transitions 0 to 1) of CP. The minor state of the DFF depends on the state of the D-side before triggering, i.e. the minor state = D. Thus, the DFF has two functions of 0 and 1.
It can be understood that the first clock information is captured by the D-type flip-flop, so that the first bit width information corresponding to the first clock information can be effectively obtained, that is, the first bit width information in one rx_symbolclk_20b clock period is registered by the DFF, and further, the first bit width information corresponding to the second clock information is accurately obtained.
Step S3200, register the first bit width information and output the register information.
It can be appreciated that the first bit width information corresponding to the first clock information acquired in step S3100 is stored in a register to acquire a set of the first bit width information in the first clock information. Referring to fig. 5, fig. 5 is a block diagram of the second data in the above steps. The registers register first bit width information { data1}, { data2}, { data3}, { data4}, { data5}, { data6}, etc. corresponding to the first clock information, respectively, and output as register information.
And S4000, splicing the register information and the second clock information to obtain second data based on a unified protocol, wherein the rate of the second data is different from that of the first data.
It can be understood that after the register information is acquired, in order to ensure the synchronism of the second data and the second clock information, the register information needs to be spliced to obtain the second data which is matched with the first data in speed.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a specific implementation procedure of another embodiment of the step S4000. As shown in fig. 4, step S4000 includes at least the following steps:
step S4100, concatenating the registration information and the second clock information.
It will be appreciated that in order to ensure the synchronism of the second data and the second clock information, the register information needs to be spliced to obtain the second data matched with the first data. As shown in fig. 5, due to the multiple relationship between the first clock information rx_symbolclk_20b and the second clock information rx_symbolclk_40b, the register information obtained in step S3200 needs to be spliced to obtain the second bit width information of the second data: { data2, data1}, { data4, data3}, { data6, data5}.
Step S4200, outputting second data, wherein a ratio of the rate of the second data to the rate of the first data is equal to a ratio of the second clock information to the first clock information.
It is understood that after the second bit width information is obtained, the second bit width information and the second clock information are synchronously output, that is, the second data is output. Wherein the ratio of the second data to the first data rate is equal to the ratio of the second clock information to the first clock information. As shown in fig. 5, since the second clock information is obtained by performing frequency division processing on the first clock information according to the rate of the first data and the rate of the second data, protocol transfer is completed between RMMI based on M-PHY with a rate of 20-bit and RMMI based on UniPro with a rate of 40-bit, so that normal communication between M-PHY and UniPro at different rates is realized. In practical application, the ratio of the second clock information to the first clock information is adjusted to adapt to the ratio of different second data to the first data rate, so that protocol switching between interfaces at different rates can be achieved.
Referring to fig. 6, fig. 6 shows a flow of a rate matching method based on an M-PHY interface according to another embodiment of the present application. As shown in fig. 6, the rate matching method based on the M-PHY interface according to the embodiment of the present application includes the following steps:
step S5000, second data based on a unified protocol is obtained, wherein the second data comprises second clock information and second bit width information.
It will be appreciated that in order to achieve rate matching between UniPro and M-PHY at different rates, conversion of clock information (Symbol) and bit width information (Symbol) during the matching process is required. Therefore, after acquiring the second data based on UniPro, the second clock information tx_symbol 40b and the second bit width information tx_symbol [31:0] in the second data need to be extracted.
It is understood that, consistent with the above step S1000, the obtaining the second clock information and the second bit width information in the second data based on UniPro through the BRIDGE module (rmmi_bridge) in RMMI is a prior art, and will not be described herein.
Step S6000, frequency division processing is carried out on the first clock information, and third clock information consistent with the second clock information is obtained.
It will be appreciated that, since the rate of the second data based on UniPro is different from the rate of the first data based on M-PHY, in order to match the rate between the first data and the second data, and also in order to ensure the consistency of the clock information, the frequency division processing is performed on the first clock information to obtain the third clock information applicable to the second data, in accordance with step S2000.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating a specific implementation procedure of another embodiment of the step S6000. As shown in fig. 7, step S6000 includes at least the following steps:
step S6100, obtain the first clock information.
It will be appreciated that in order to perform the analysis processing on the first clock information, the first clock information needs to be acquired. In this embodiment, the first clock information tx_symbol_20b in the first data is obtained through rmmi_bridge, so as to process the tx_symbol_20b, so that the second data is converted into a data packet consistent with the M-PHY data rate.
Step S6200, frequency dividing the first clock information according to the rate of the first data and the rate of the second data.
It will be appreciated that the first data has a rate of 20-bit, the second data has a rate of 40-bit, and the second data has a rate twice that of the first data, so that in order to ensure that the converted data matches the second data, the first clock information tx_symbol_20b needs to be subjected to a frequency division process to obtain the third clock information tx_symbol_40b. Likewise, in other embodiments, different frequency division processing, such as divide-by-four, divide-by-eight, etc., can be performed on the first clock information based on the rate of the first data and the rate of the second data.
Step S6300, outputting the third clock information.
It will be appreciated that after the third clock information tx_symbolclk_40b is obtained, it needs to be output to the M-PHY based packet so that rmmi_bridge can generate the first data rate matched to the M-PHY packet.
Step S7000, cutting the second bit width information according to the third clock information and storing the second bit width information in sequence to obtain the cutting information.
It can be understood that after the third clock information is acquired, information extraction and storage are further required to be performed on the second bit width information, so that the second bit width information corresponding to the period of the third clock information is accurately acquired, the synchronism of the second bit width information and the third clock information is ensured, the situation that data is not matched is avoided, and the rate matching of the first data and the second data is affected.
Referring to fig. 8, fig. 8 is a schematic diagram showing a specific implementation procedure of another embodiment of the step S7000. As shown in fig. 8, step S7000 includes at least the following steps:
and S7100, cutting the second bit width information according to the ratio of the third clock information to the first clock information to obtain the first bit width information.
It can be understood that, in order to ensure the synchronicity of the first bit width information and the third clock information, the second bit width information needs to be cut to obtain the first bit width information matched with the third clock information. Referring to fig. 10, fig. 10 shows a block diagram of the first data in the above step S6000, and the second bit width information { data2, data1}, { data4, data3}, { data6, data5} in the figure is cut. And because the ratio of the third clock information to the first clock information is 2, halving the second bit width information to obtain first bit width information { data2}, { data1}, { data4}, { data3}, { data6}, and { data5}.
And step 7200, sorting the first bit width information according to the weight value to obtain the cutting information.
It will be appreciated that the least significant bit (Least Significant Bit, LSB) means the least significant bit in the binary number, with the LSB being the rightmost side of the binary number. In practical applications, LSB has a weight of 2^0 and can be used to detect parity of numbers. The most significant bit (Most Significant Bit, MSB) belongs to the most significant bit in the binary number, which is located at the leftmost side of the binary number, and the MSB is the highest weighted bit, similar to the leftmost one bit in the decimal number. In practical applications, MSB represents n-1 bits in an n-bit binary number, with the highest weight 2 (n-1). For signed binary numbers, the negative number takes the form of an inverse or complement code, where the MSB is used to represent the sign, in particular, an MSB of 1 represents the negative number and 0 represents the positive number.
It can be understood that, in order to ensure the integrity of the first bit width information, the first bit width information needs to be sequenced according to the weight value, so as to obtain the cutting information { data1}, { data2}, { data3}, { data4}, { data5}, and { data6}. And the cutting information is sent out according to the sequence from the LSB to the MSB so as to ensure the effective sequence of the first bit width information and avoid the situation that the first data and the second data cannot be matched.
And step S8000, obtaining first data based on the M-PHY according to the cutting information and the first clock information, wherein the rate of the first data is different from that of the second data.
Referring to fig. 9, fig. 9 is a schematic diagram illustrating a specific implementation procedure of another embodiment of the step S8000. As shown in fig. 9, step S8000 includes at least the steps of:
step S8100, splice cut information and first clock information.
It will be appreciated that in order to ensure the synchronicity of the first data and the third clock information, a splicing operation needs to be performed on the cut information to obtain the first data matched with the second data. The splicing operation is identical to the above step S4100, and will not be described here again.
Step S8200, outputting first data, wherein a ratio of the first data to the second data rate is equal to a ratio of the first clock information to the second clock information.
It can be understood that after the first bit width information is acquired, the first bit width information and the third clock information are synchronously output, that is, the first data is output. Wherein the ratio of the first data to the second data rate is equal to the ratio of the first clock information to the second clock information. As shown in fig. 10, since the third clock information is obtained by performing the frequency division processing on the first clock information according to the rate of the first data and the rate of the second data, protocol transfer is completed between RMMI based on UniPro with a rate of 40-bit and RMMI based on M-PHY with a rate of 20-bit, so that normal communication between UniPro and M-PHY at different rates is realized.
Fig. 11 shows an electronic device 500 provided by an embodiment of the application. The electronic device 500 includes, but is not limited to:
a memory 501 for storing a program;
the processor 502 is configured to execute the program stored in the memory 501, and when the processor 502 executes the program stored in the memory 501, the processor 502 is configured to execute the rate matching method based on the M-PHY interface.
The processor 502 and the memory 501 may be connected by a bus or other means.
The memory 501 is used as a non-transitory computer readable storage medium for storing non-transitory software programs and non-transitory computer executable programs, such as the M-PHY interface-based rate matching method described in any embodiment of the present application. The processor 502 implements the rate matching method based on the M-PHY interface described above by running non-transitory software programs and instructions stored in the memory 501.
The memory 501 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for a function; the memory data area may store data for performing the rate matching method based on the M-PHY interface described above. In addition, memory 501 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some implementations, memory 501 may optionally include memory located remotely from processor 502, which may be connected to processor 502 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The non-transitory software programs and instructions required to implement the above-described M-PHY interface-based rate matching method are stored in memory 501 and when executed by one or more processors 502, perform the M-PHY interface-based rate matching method provided by any embodiment of the present application.
The embodiment of the application also provides a storage medium which stores computer executable instructions for executing the rate matching method based on the M-PHY interface.
In an embodiment, the storage medium stores computer-executable instructions that are executed by one or more control processors 502, for example, by one of the processors 502 in the electronic device 500, such that the one or more processors 502 perform the rate matching method based on the M-PHY interface provided by any embodiment of the present application.
The embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, i.e. may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically include computer readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave or other transport mechanism, and may include any information delivery media.
Claims (10)
1. A rate matching method based on an M-PHY interface, comprising the steps of:
acquiring first data based on an M-PHY (M-physical layer), wherein the first data comprises first clock information and first bit width information;
performing frequency division processing on the first clock information to obtain second clock information;
registering the first bit width information in the period of the first clock information to obtain registered information;
and splicing the register information and the second clock information to obtain second data based on a unified protocol, wherein the rate of the second data is different from that of the first data.
2. The rate matching method based on the M-PHY interface of claim 1, wherein the performing the frequency division on the first clock information to obtain second clock information includes:
acquiring the first clock information;
frequency division processing the first clock information according to the rate of the first data and the rate of the second data;
outputting the second clock information.
3. The method for rate matching based on the M-PHY interface of claim 2 wherein the registering the first bit width information in the period of the first clock information to obtain the registered information includes:
capturing the first clock information through a D-type trigger, and outputting the first bit width information corresponding to the first clock information;
and registering the first bit width information and outputting the registering information.
4. A method for rate matching based on an M-PHY interface according to claim 3, wherein the concatenating the register information and the second clock information to obtain second data based on a unified protocol includes:
splicing the register information and the second clock information;
and outputting the second data, wherein the ratio of the rate of the second data to the rate of the first data is equal to the ratio of the second clock information to the first clock information.
5. A rate matching method based on an M-PHY interface, comprising the steps of:
acquiring second data based on a unified protocol, wherein the second data comprises second clock information and second bit width information;
frequency division processing is carried out on the first clock information to obtain third clock information consistent with the second clock information;
cutting the second bit width information according to the third clock information and storing the second bit width information in sequence to obtain cutting information;
and obtaining first data based on the M-PHY according to the cutting information and the first clock information, wherein the rate of the first data is different from the rate of the second data.
6. The rate matching method based on an M-PHY interface of claim 5 wherein the frequency dividing the first clock information to obtain third clock information consistent with the second clock information, further comprises:
acquiring the first clock information;
frequency division processing the first clock information according to the rate of the first data and the rate of the second data;
and outputting the third clock information.
7. The method for rate matching based on an M-PHY interface of claim 6 wherein the step of slicing the second bit-width information according to the third clock information and storing it in order to obtain sliced information comprises:
cutting the second bit width information according to the ratio of the third clock information to the first clock information to obtain first bit width information;
and sequencing the first bit width information according to the weight value to obtain the cutting information.
8. The method for rate matching based on an M-PHY interface of claim 7 wherein the obtaining the first data based on the M-PHY based on the cut information and the first clock information comprises:
splicing the cutting information and the first clock information;
and outputting the first data, wherein the ratio of the first data to the second data rate is equal to the ratio of the first clock information to the second clock information.
9. An electronic device, comprising: a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method of any one of claims 1 to 4 when the computer program is executed; or a method as claimed in any one of claims 5 to 8.
10. A computer readable storage medium, characterized in that a computer program is stored, which computer program, when being executed by a processor, implements the method according to any of claims 1 to 4; or a method as claimed in any one of claims 5 to 8.
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