CN116660631A

CN116660631A - Line loss testing method, device, system, equipment and storage medium

Info

Publication number: CN116660631A
Application number: CN202310608804.9A
Authority: CN
Inventors: 靳爽
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2023-05-26
Filing date: 2023-05-26
Publication date: 2023-08-29

Abstract

The application provides a line loss testing method, a device, a system, equipment and a storage medium, wherein the method comprises the following steps: acquiring signals output by a first signal link under different loss parameters, wherein the first signal link comprises a main board, a signal leading-out board connected with the main board and a loss board connected with the signal leading-out board; the main board is provided with a processor, the signal output by the loss board is the signal output by the first signal link, and the loss value of the loss board is adjustable; determining critical loss parameters from different loss parameters by detecting the integrity of signals output by the first signal link under the different loss parameters; the critical loss parameter is a maximum loss parameter that enables the integrity of the signal output by the first signal link to meet a preset first integrity requirement. The method realizes the test of the maximum loss which can be borne by the motherboard wiring, thereby providing reference for the design wiring.

Description

Line loss testing method, device, system, equipment and storage medium

Technical Field

The present application relates to the field of computer technologies, and in particular, to a line loss testing method, device, system, equipment, and storage medium.

Background

The limit length of the signal trace is often related to the trace loss, and the influence of the trace loss becomes larger and larger along with the increase of the signal frequency. In general, the lengths of the wires that can be matched by different processors or different mainboards are different, which is caused by different wire loss corresponding to the processors or the mainboards. Therefore, when designing the processor or motherboard trace, the trace loss should be first determined, and then the limit trace length should be grasped based on the trace loss.

In some cases, the standard of the signal emitted by the motherboard or the processor in actual transmission is not clearly specified in the specification, which results in that the routing length of the signal line cannot be reasonably grasped when designing the motherboard or the processor.

Disclosure of Invention

Based on the state of the art, the application provides a line loss testing method, a device, a system, equipment and a storage medium, which can realize the testing of the maximum loss borne by the motherboard wiring, thereby providing reference for designing the motherboard wiring.

In order to achieve the technical purpose, the application provides the following technical scheme:

the first aspect of the present application provides a line loss testing method, including:

Acquiring signals output by a first signal link under different loss parameters, wherein the first signal link comprises a main board, a signal leading-out board connected with the main board and a loss board connected with the signal leading-out board; the main board is provided with a processor, the signal output by the loss board is the signal output by the first signal link, and the loss value of the loss board is adjustable;

determining critical loss parameters from different loss parameters by detecting the integrity of signals output by the first signal link under the different loss parameters; the critical loss parameter is a maximum loss parameter that enables the integrity of the signal output by the first signal link to meet a preset first integrity requirement.

In some implementations, the first signal link further includes a test instrument connected to the lossy plate;

determining critical loss parameters from different loss parameters by detecting the integrity of signals output by the first signal link under the different loss parameters, including:

detecting the integrity of signals output by the first signal link under different loss parameters by the test instrument;

And determining critical loss parameters from the different loss parameters according to the integrity of signals output by the first signal link under the different loss parameters.

In some implementations, the method further comprises:

acquiring a signal output by a second signal link, and detecting the integrity of the signal output by the second signal link; the second signal link comprises the main board and the signal leading-out board connected with the main board;

and under the condition that the integrity of the signal output by the second signal link meets the preset second integrity requirement, acquiring the signal output by the first signal link under different loss parameters.

In some implementations, the method further comprises:

detecting the integrity of output signals of the first signal link under the critical loss parameters in different working environments respectively;

and determining the critical loss parameter as a limit loss value of the first signal link under the condition that the integrity of output signals of the first signal link in different working environments respectively meet the first integrity requirement under the critical loss parameter.

In some implementations, if the integrity of the output signal of the first signal link in the different working environments respectively under the critical loss parameter does not meet the first integrity requirement, detecting the integrity of the output signal of the first signal link in the different working environments respectively under a candidate loss parameter, wherein the candidate loss parameter is smaller than the critical loss parameter;

And under the condition that the integrity of the output signals of the first signal link in different working environments respectively under the candidate loss parameters meets the first integrity requirement, determining the candidate loss parameters as limit loss values of the first signal link.

In some implementations, the method further comprises:

establishing a full-link simulation model taking the limit loss value as a loss parameter;

and determining loss parameters of the full-link simulation model by carrying out signal transmission simulation on the full-link simulation model.

In some implementations, detecting the integrity of the signal output by the first signal link at different loss parameters includes:

detecting the integrity of a signal output by the first signal link under a first loss parameter;

if the integrity of the signal output by the first signal link under the first loss parameter does not meet the first integrity requirement, detecting the integrity of the signal output by the first signal link under the second loss parameter, wherein the value of the second loss parameter is half of the value of the first loss parameter;

and if the integrity of the signal output by the first signal link under the first loss parameter meets the first integrity requirement, detecting the integrity of the signal output by the first signal link under the third loss parameter, wherein the value of the third loss parameter is the sum of the value of the first loss parameter and the value of the second loss parameter.

A second aspect of the present application proposes a line loss testing system, comprising:

the device comprises a main board, a signal extraction plate connected with the main board, a loss plate connected with the signal extraction plate and a testing instrument connected with the loss plate;

the main board is provided with a processor for outputting signals;

the signal extraction plate is used for extracting and sending signals in the main board to the loss plate;

the loss board is used for sending the received signals to the testing instrument under different loss parameters, and the loss value of the loss board is adjustable;

the testing instrument is used for acquiring signals output by the loss board, and determining critical loss parameters from different loss parameters by detecting the integrity of the signals acquired under the different loss parameters; the critical loss parameter is a maximum loss parameter that enables the integrity of the signal acquired by the test instrument to meet a preset first integrity requirement.

In some implementations, the wear plate is connected to the signal outlet plate and the test instrument by a test cable, respectively.

A third aspect of the present application provides a line loss testing apparatus, including:

The signal acquisition unit is used for acquiring signals output by a first signal link under different loss parameters, and the first signal link comprises a main board, a signal extraction plate connected with the main board and a loss plate connected with the signal extraction plate; the signal output by the loss board is the signal output by the first signal link, a processor is arranged on the main board, and the loss value of the loss board is adjustable;

the detection processing unit is used for determining critical loss parameters from different loss parameters by detecting the integrity of signals output by the first signal link under the different loss parameters; the critical loss parameter is a maximum loss parameter that enables the integrity of the signal output by the first signal link to meet a preset first integrity requirement.

A fourth aspect of the present application proposes a line loss testing apparatus comprising:

a memory and a processor;

the memory is connected with the processing and is used for storing programs;

the processor is configured to implement the line loss testing method by running the program in the memory.

A fifth aspect of the present application proposes a storage medium having stored thereon a computer program which, when executed by a processor, implements the line loss testing method described above.

According to the line loss testing method provided by the application, signals transmitted by signals sent by the main board under different loss parameters are acquired by means of the first signal link; and determining critical loss parameters from the different loss parameters by detecting the integrity of signals transmitted by signals sent by the main board under the different loss parameters. The method determines the maximum loss parameter which keeps the signal sent by the main board intact by testing the integrity of the signal sent by the main board after the signal is transmitted under different loss parameters, namely, the method realizes the test of the maximum loss which can be borne by the main board wiring, thereby providing reference for the design wiring.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a line loss test link according to an embodiment of the present application.

Fig. 2 is a flow chart of a circuit loss testing method according to an embodiment of the present application.

Fig. 3 is a schematic structural diagram of another line loss testing link according to an embodiment of the present application.

Fig. 4 is a schematic structural diagram of a circuit loss testing device according to an embodiment of the present application.

Fig. 5 is a schematic structural diagram of a line loss testing system according to an embodiment of the present application.

Fig. 6 is a schematic structural diagram of a line loss testing device according to an embodiment of the present application.

Detailed Description

The technical scheme of the embodiment of the application is suitable for application scenes of limiting loss of the signal transmission channel, and can test the limiting loss of the signal link to be constructed, which is passed by the signal sent by the processor, under the conditions of unknown specific link structure of the signal transmission channel and unknown performance of the processor, thereby providing reference for determining the routing length of the signal link to be constructed and being beneficial to improving the design efficiency of the signal link.

The ultimate trace length of a signal link is often related to trace loss, and as the signal frequency increases, the effect of trace loss on trace length becomes greater. For high-speed serial signals, the signal processing capability of different processors is also different, that is, the pre-emphasis and equalization capability of signal transmission are different, which leads to quite different transmission performance, loss and the like when signals are transmitted in a signal link, and this also brings difficulty to the design of the signal transmission link corresponding to the processor.

It is now common practice to take a model of the motherboard of the processor or of the loading processor for simulation evaluation, to determine the loss of the signal emitted by the processor in the actual transmission, and to design the signal routing according to the loss value.

However, in practical situations, simulation models of some processors or mainboards are difficult to obtain or the accuracy of the models cannot be estimated, and meanwhile, the design specifications do not clearly define the standard of wiring loss of signals sent by the mainboards or the processors in actual transmission. In this case, when designing a motherboard or a processor, the wiring length of the signal line cannot be reasonably grasped, which often results in problems of failure in development, repeated development, and resource waste.

In view of the above problems, the present application provides a line loss testing method, device, system, device and storage medium, which can determine the limit loss of a signal sent by a processor or a motherboard in actual signal link transmission through testing under the conditions of unknown processor or motherboard model and unknown wiring loss standard, so as to provide a reference for the signal transmission link design of the processor or the motherboard.

The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Exemplary implementation Environment

Fig. 1 shows an exemplary implementation environment of the technical solution of the embodiment of the present application. The technical scheme of the embodiment of the application is suitable for the line loss test link shown in fig. 1, and the link comprises a main board 001, a signal extraction plate 002 connected with the main board 001 and a loss plate 003 connected with the signal extraction plate 002.

The main board 001 is provided with a processor, and the main board 001 is used as a signal source for outputting signals, and the signals are sent out by the processor and transmitted through wiring inside the main board 001.

The signal extraction plate 002 is electrically connected with the motherboard 001, for example, the signal extraction plate 002 is connected through a signal port of the motherboard 001, a signal extraction terminal is provided on the signal extraction plate 002, and the signal extraction terminal can be connected with a signal line, thereby realizing extraction of signals from the motherboard to the signal line.

The lossy plate 003 is used to transmit signals and superimpose losses on the transmitted signals. The loss board 003 comprises a signal input end and a signal output end, wherein the signal input end is connected with a signal line led out by the signal leading-out board 002, so that the loss board 003 can receive a signal led out by the signal leading-out board 002 from the main board 001, the signal can be subjected to superposition loss during internal transmission of the loss board 003, and the signal after loss is output from the signal output end of the loss board 003. The transmission of signals in the loss board 003 is equivalent to the signal transmission loss generated in the signal transmission in the signal link, so that the loss condition of signals sent out by the main board 001 in the actual transmission process can be simulated through the loss board 003. The loss value of the loss board 003 is adjustable, so that different loss values can be superposed on the signals transmitted in the loss board 003, and the signals can be transmitted under different loss parameters.

The signal output end of the loss board 003 can be connected with a signal line, so that signal extraction is realized.

Based on the line loss test link, the line loss test method provided by the embodiment of the application can be applied to test equipment connected with the line loss test link. The test device is connected to a signal output end of the loss board 003, for example, through a signal line, and is used for receiving a signal transmitted through the loss board 003, and determining a limit line loss of a signal output by the main board 001 through signal analysis.

Exemplary method

The embodiment of the application provides a line loss testing method which can be applied to testing equipment, wherein the testing equipment is connected with the line loss testing link, and the signal transmission loss in the link is tested by executing the line loss testing method provided by the embodiment of the application.

Referring to fig. 2, the method includes:

s101, signals output by the first signal link under different loss parameters are obtained.

The first signal link is the line loss test link shown in fig. 1. As shown in fig. 1, the first signal link includes a main board 001, a signal outlet 002 connected to the main board 001, and a loss board 003 connected to the signal outlet 002.

The main board 001 is provided with a processor, and the main board 001 is used as a signal source for outputting signals, and the signals are sent out by the processor and transmitted through wiring inside the main board 001. The signal extraction board 002 extracts the signal in the main board 001 to the loss board 003, the signal output by the loss board 003 is the signal output by the first signal link, the loss value of the loss board 003 is adjustable, and when the loss board 003 is adjusted to different loss values, the first signal link is in different loss parameters.

The loss value of the loss board 003 is adjusted, and signals output by the loss board 003 under different loss values are obtained, so that signals output by the first signal link under different loss parameters are obtained.

Illustratively, the above-mentioned process of adjusting the loss parameter of the first signal link, such as the above-mentioned process of adjusting the loss value of the loss board 003, may be implemented by the control of the above-mentioned test apparatus.

S102, determining critical loss parameters from different loss parameters by detecting the integrity of signals output by the first signal link under the different loss parameters.

Specifically, for the signal output by the first signal link under each loss parameter, the signal integrity of the signal is detected, and the maximum loss parameter which enables the integrity of the signal output by the first signal link to meet the preset first integrity requirement is found out from the signal integrity of the signal, and is used as the critical loss parameter.

For example, the loss values of the loss board 003 may be sequentially increased from the minimum loss value by a set step size, and the integrity of the signal output by the loss board 003 at each loss value may be obtained. When the integrity of the signal output by the loss board at a certain loss value does not meet the set first integrity requirement, the loss value of the last step of the loss value is taken as a critical loss parameter.

As another alternative implementation manner, the embodiment of the present application uses a dichotomy to find the maximum loss parameter that enables the integrity of the signal output by the first signal link to meet the preset first integrity requirement.

Specifically, for a certain loss value interval, the integrity of the output signal of the middle loss value is detected first, the loss value interval is divided into two sections, if the integrity of the output signal of the middle loss value meets the first integrity requirement, the integrity of the output signal of the middle loss value of the larger section is detected, and if the integrity does not meet the first integrity requirement, the integrity of the output signal of the middle loss value of the smaller section is detected. The loss value interval is an adjustable interval of the loss parameter of the first signal link, that is, an adjustable interval of the loss value of the loss board.

For example, for a loss value interval of 1dB to 10dB, firstly testing whether the integrity of the output signal meets the first integrity requirement when the loss value is 5dB, and if so, detecting whether the integrity of the output signal meets the first integrity requirement when the loss value is 7.5 dB; if not, detecting whether the integrity of the output signal meets the first integrity requirement when the loss value is 2.5dB, and so on until the maximum loss value which enables the integrity of the signal output by the first signal link to meet the preset first integrity requirement is found out, namely the critical loss parameter.

In general, when the maximum loss parameter that enables the integrity of the signal output by the first signal link to meet the preset first integrity requirement is found by the above-mentioned dichotomy, the integrity of the signal output by the first signal link under the first loss parameter may be detected first, where the first loss parameter may be any loss parameter in the loss parameter adjustable interval of the first signal link.

And if the integrity of the signal output by the first signal link under the first loss parameter does not meet the first integrity requirement, detecting the integrity of the signal output by the first signal link under the second loss parameter, wherein the value of the second loss parameter is half of the value of the first loss parameter.

That is, when the integrity of the signal output by the first signal link under the first loss parameter does not meet the first integrity requirement, the loss parameter is reduced by 50%, the second loss parameter is obtained, and the integrity of the signal output by the first signal link under the second loss parameter is detected.

That is, when the integrity of the signal output by the first signal link under the first loss parameter meets the first integrity requirement, the loss parameter is increased by 50%, a third loss parameter is obtained, and the integrity of the signal output by the first signal link under the third loss parameter is detected.

According to the line loss testing method provided by the embodiment of the application, the signals transmitted by the signals sent by the main board under different loss parameters are acquired by means of the first signal link; and determining critical loss parameters from the different loss parameters by detecting the integrity of signals transmitted by signals sent by the main board under the different loss parameters. The method determines the maximum loss parameter which keeps the signal sent by the main board intact by testing the integrity of the signal sent by the main board after the signal is transmitted under different loss parameters, namely, the method realizes the test of the maximum loss which can be borne by the main board wiring, thereby providing reference for the design wiring.

As an alternative embodiment, the first signal link, that is, the line loss test link shown in fig. 1, may further include a test apparatus, where the test apparatus is connected to the signal output end of the loss board 003 through a signal line.

The above-mentioned test apparatus refers to an apparatus for testing the signal output by the loss board 003, and the test apparatus may be one or more according to the test items, for example, an oscilloscope for testing the integrity of the signal, an error code meter for testing the error rate of the signal, and so on.

The test apparatus described above may be used as a test device for executing the line loss test method according to the embodiment of the present application, and execute the line loss test methods described in steps S101 and S102.

Or, the test device for executing the line loss test method provided by the embodiment of the application is connected with the test instrument, and implementation of the line loss test method in the steps S101 and S102 is realized through the test device.

For example, the test device may detect the integrity of the signal output by the first signal link under different loss parameters by detecting the integrity of the signal output by the first signal link under different loss parameters, and when determining the critical loss parameter from the different loss parameters, may detect the integrity of the signal output by the first signal link under different loss parameters by using the test instrument described above.

For example, the testing device controls the testing instrument to perform signal integrity test on signals output by the loss board of the first signal link under different loss values, so as to obtain a signal integrity test result.

After the test equipment obtains the signal integrity test result, the critical loss parameter is determined from different loss parameters according to the signal integrity of the first signal link output under the different loss parameters.

For example, the test device records each loss parameter, and integrity information of the signal output by the first signal link under each loss parameter. And then, selecting the maximum loss parameter which enables the integrity of the signal output by the first signal link to meet the preset first integrity requirement from different loss parameters, and obtaining the critical loss parameter.

The test device detects the integrity of the signal output by the first signal link under different loss parameters through the test instrument, namely, after the test device adjusts the loss parameters of the first signal link, the test instrument detects the integrity of the signal output by the first signal link and then sends an integrity test result to the test device, so that the test device obtains the integrity of the signal output by the first signal link under the loss parameters. The test device may adjust the loss parameter of the first signal link according to the dichotomy, and in combination with the signal integrity test result output by the test instrument, the test device adjusts the loss parameter of the first signal link.

For example, the test equipment adjusts the loss parameter of the first signal link to a first loss parameter and then obtains the signal integrity of the first signal link under the first loss parameter determined by the test of the test instrument. If the signal integrity of the first signal link under the first loss parameter does not meet the first integrity requirement, reducing the loss parameter of the first signal link by 50% by the test equipment, adjusting the loss parameter to be a second loss parameter, and then acquiring the signal integrity of the first signal link under the second loss parameter, which is determined by the test of the test instrument; if the signal integrity of the first signal link under the first loss parameter meets the first integrity requirement, the testing device increases the loss parameter of the first signal link by 50%, adjusts the loss parameter to be a third loss parameter, and then acquires the signal integrity of the first signal link under the third loss parameter, which is determined by testing of the testing instrument, and the like.

In some embodiments, the above-mentioned line loss testing method constructs a second signal link before constructing the first signal link, and the second signal link is formed by connecting the main board 001 and the signal extraction board 002 shown in fig. 1, as shown in fig. 3.

The second signal link is a partial link of the first signal link.

Based on the second signal link, the line loss testing method provided by the embodiment of the application further includes:

and acquiring the signal output by the second signal link and detecting the integrity of the signal output by the second signal link.

Under the condition that the integrity of the signal output by the second signal link meets the preset second integrity requirement, the first signal link is constructed based on the first signal link, and the signal output by the first signal link under different loss parameters is obtained.

Specifically, the signal output end of the signal extraction plate can be connected through a testing instrument, and the integrity of the signal extracted from the main board by the signal extraction plate can be tested through the testing instrument.

If the integrity of the signal output by the second signal link meets the preset second integrity requirement, the signal transmitted by the main board and the signal extraction board can be determined to be satisfactory. The loss board is added on the basis of the second signal link to form the first signal link, so that the signal loss of the first signal link is ensured to be caused by the loss applied by the loss board, but not caused by the loss of the main board or the signal leading-out board. Therefore, the relation between the signal transmission performance of the first signal link and the line loss can be accurately determined by changing the loss value of the loss board in the first signal link to test the signal integrity of the first signal link under different loss parameters.

If the integrity of the signal output by the second signal link does not meet the preset second integrity requirement, the main board needs to be replaced, the wiring or the material of the main board needs to be adjusted, and the like until the signal output by the built second signal link meets the signal integrity requirement. And then building the first signal link based on the second signal link meeting the signal integrity requirement.

The line loss testing methods described in the foregoing embodiments are all implemented by testing the first signal link in a standard working environment at room temperature, but the signal transmission is affected by the working environment, for example, in an extreme environment, the signal loss may become large, so that the theoretical critical loss parameter in the standard working environment may not ensure that the signal link meets the requirements for signal transmission in an actual working scenario.

In order to ensure that the measured line loss better accords with the actual working scenario, in some embodiments, the line loss testing method further detects the integrity of the output signals of the first signal link in different working environments respectively under the critical loss parameter after determining the critical loss parameter.

The different working environments include, but are not limited to, temperature cycle environments, drop environments, smoke environments, three-proofing (mold proofing, moisture proofing, salt mist proofing) environments, stability fluctuation environments and the like. These different operating environments simulate the various possible operating environments that a signal link may encounter in actual conditions.

When the technical scheme of the embodiment of the application is actually implemented, the specific types of the different working environments can be determined according to the working environments which can be met by the signal link to be designed in the actual working condition.

The embodiment of the application detects the integrity of the output signals of the first signal link in the different working environments respectively under the critical loss parameter.

That is, if the integrity of the output signals of the first signal link in the different operating environments respectively satisfy the first integrity requirement under the critical loss parameter, the critical loss parameter is described as the maximum loss parameter that enables the output signals of the first signal link in the various operating environments to satisfy the signal integrity requirement, and thus the critical loss parameter can be regarded as the limit loss value of the first signal link.

And if the integrity of the output signals of the first signal link in different working environments respectively under the critical loss parameters does not meet the first integrity requirement, for example, the integrity of the output signals of the first signal link in one or more working environments under the critical loss parameters does not meet the first integrity requirement, detecting the integrity of the output signals of the first signal link in different working environments respectively under candidate loss parameters, wherein the candidate loss parameters are smaller than the critical loss parameters. That is, the loss parameter of the first signal link is reduced to a candidate loss parameter, and then the integrity of the output signal of the first signal link under the candidate loss parameter in different working environments is tested.

The loss parameter of the first signal link is reduced by a preset value, and the reduced loss parameter is used as the candidate loss parameter.

The preset value is a smaller value, such as 0.5dB, in the embodiment of the present application.

Specifically, if the integrity of the output signals of the first signal link in different working environments respectively under the candidate loss parameters meets the first integrity requirement, the candidate loss parameters are described as the maximum loss parameters capable of enabling the output signals of the first signal link in various working environments to meet the signal integrity requirement, so that the candidate loss parameters can be used as the limit loss values of the first signal link.

If the integrity of the output signals of the first signal link in the different working environments under the candidate loss parameters respectively does not meet the first integrity requirement, for example, the integrity of the output signals of the first signal link in one or more working environments under the candidate loss parameters does not meet the first integrity requirement, the loss parameters of the first signal link are reduced by a preset value again by referring to the processing, and then the integrity of the output signals of the first signal link in the different working environments under the reduced loss parameters is tested and whether the signal integrity meets the first integrity requirement is judged.

According to the scheme, the maximum loss parameter which enables the integrity of the output signal of the first signal link in various working environments to meet the preset first integrity requirement can be found, namely, the limit loss parameter of the first signal link is found.

The acquisition of the limit loss parameter is beneficial to accurately grasping the signal loss of the signal link to be designed in the actual working condition, and further provides a reference closer to the actual for the design of the signal link.

After the above processing, in some embodiments, a full-link simulation model using the above limiting loss value as a loss parameter is also established, and the loss parameter of the full-link simulation model is determined by performing signal transmission simulation on the full-link simulation model.

Specifically, the above-described test for the first signal link only tested signal loss on the signal link between the signal tap and the test instrument, but did not test signal loss on the motherboard and the signal tap.

In order to more comprehensively acquire the loss parameters of the first signal link, after the limit loss parameters of the first signal link are determined through the processing, the embodiment of the application builds a full-link simulation model which takes the limit loss values as the loss parameters, and determines the loss parameters of the full-link simulation model through carrying out signal transmission simulation on the full-link simulation model.

The loss parameters of the full-link simulation model comprise loss values, isolation and the like.

Through the processing, the loss parameters of the signal all-link can be more comprehensively determined, so that more comprehensive references are provided for signal link design.

As can be seen from the above description, the line loss testing method provided by the embodiment of the present application can test and determine the loss of the signal output by the processor or the motherboard when transmitting in the signal link under the conditions of unknown processor model and unknown line loss standard, thereby providing a reference for signal line design and development, and being beneficial to accurately grasping the signal link trace length.

Specifically, the line loss testing method provided by the embodiment of the application can provide reference in the pre-simulation stage of signal link design. After the signal link schematic diagram is drawn, information such as PCB lamination, signal topological structures such as types and numbers of through holes, connector types, signal wiring layers and layer replacement is determined, and then the simulation is carried out by setting up a full-link front simulation environment, taking the signal length as a variable, carrying out full-link simulation by taking the line limit loss determined by the line loss test method provided by the embodiment of the application as a standard, and simulating the limit wiring length corresponding to the limit loss, thereby providing guidance for PCB design and device layout.

On the other hand, the line loss testing method provided by the embodiment of the application can also provide reference in the post-simulation stage of the signal link design. Specifically, after the schematic diagram and the PCB are drawn, full-link post-simulation is performed according to the established lamination information of the PCB. And judging whether the PCB wiring is overlong or not by taking the line limit loss determined by the line loss testing method provided by the embodiment of the application as a standard, so as to optimize the signal wiring.

Exemplary apparatus

Correspondingly, the embodiment of the application also provides a circuit loss testing device, which is shown in fig. 4, and comprises:

a signal obtaining unit 100, configured to obtain signals output by a first signal link under different loss parameters, where the first signal link includes a main board, a signal extraction board connected to the main board, and a loss board connected to the signal extraction board; the signal output by the loss board is the signal output by the first signal link, a processor is arranged on the main board, and the loss value of the loss board is adjustable;

a detection processing unit 110, configured to determine a critical loss parameter from different loss parameters by detecting the integrity of a signal output by the first signal link under the different loss parameters; the critical loss parameter is a maximum loss parameter that enables the integrity of the signal output by the first signal link to meet a preset first integrity requirement.

Optionally, the first signal link further includes a test instrument connected to the lossy plate;

Optionally, the signal acquisition unit 100 is further configured to:

Optionally, the detection processing unit 110 is further configured to:

Optionally, if the integrity of the output signals of the first signal link in different working environments under the critical loss parameter does not meet the first integrity requirement, detecting the integrity of the output signals of the first signal link in different working environments under a candidate loss parameter, where the candidate loss parameter is smaller than the critical loss parameter;

Optionally, the apparatus further includes:

the simulation test unit is used for establishing a full-link simulation model taking the limit loss value as a loss parameter;

Optionally, detecting the integrity of the signal output by the first signal link under different loss parameters includes:

The circuit loss testing device provided by the embodiment belongs to the same application conception as the circuit loss testing method provided by the embodiment of the application, and can execute the circuit loss testing method provided by any embodiment of the application, and has the corresponding functional modules and beneficial effects of the execution method. Technical details not described in detail in this embodiment may be referred to the specific processing content of the line loss testing method provided in the foregoing embodiment of the present application, and will not be described herein.

The functions implemented by the above units may be implemented by the same or different processors, respectively, and embodiments of the present application are not limited.

It will be appreciated that the elements of the above apparatus may be implemented in the form of processor-invoked software. For example, the device includes a processor, where the processor is connected to a memory, and the memory stores instructions, and the processor invokes the instructions stored in the memory to implement any of the methods above or to implement functions of each unit of the device, where the processor may be a general-purpose processor, such as a CPU or a microprocessor, and the memory may be a memory within the device or a memory outside the device. Alternatively, the units in the apparatus may be implemented in the form of hardware circuits, and the functions of some or all of the units may be implemented by designing hardware circuits, which may be understood as one or more processors; for example, in one implementation, the hardware circuit is an ASIC, and the functions of some or all of the above units are implemented by designing the logic relationships of the elements in the circuit; for another example, in another implementation, the hardware circuit may be implemented by a PLD, for example, an FPGA may include a large number of logic gates, and the connection relationship between the logic gates is configured by a configuration file, so as to implement the functions of some or all of the above units. All units of the above device may be realized in the form of processor calling software, or in the form of hardware circuits, or in part in the form of processor calling software, and in the rest in the form of hardware circuits.

In an embodiment of the present application, the processor is a circuit with signal processing capability, and in an implementation, the processor may be a circuit with instruction reading and running capability, such as a CPU, a microprocessor, a GPU, or a DSP, etc.; in another implementation, the processor may implement a function through a logical relationship of hardware circuitry that is fixed or reconfigurable, e.g., a hardware circuit implemented by the processor as an ASIC or PLD, such as an FPGA, or the like. In the reconfigurable hardware circuit, the processor loads the configuration document, and the process of implementing the configuration of the hardware circuit may be understood as a process of loading instructions by the processor to implement the functions of some or all of the above units. Furthermore, a hardware circuit designed for artificial intelligence may be provided, which may be understood as an ASIC, such as NPU, TPU, DPU, etc.

It will be seen that each of the units in the above apparatus may be one or more processors (or processing circuits) configured to implement the above method, for example: CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

Furthermore, the units in the above apparatus may be integrated together in whole or in part, or may be implemented independently. In one implementation, these units are integrated together and implemented in the form of an SOC. The SOC may include at least one processor for implementing any of the methods above or for implementing the functions of the units of the apparatus, where the at least one processor may be of different types, including, for example, a CPU and an FPGA, a CPU and an artificial intelligence processor, a CPU and a GPU, and the like.

Exemplary System

Optionally, an embodiment of the present application further provides a line loss testing system, referring to fig. 5, the system includes:

a main board 010, a signal extraction board 011 connected to the main board 010, a loss board 012 connected to the signal extraction board 011, and a test device 013 connected to the loss board 012;

the main board 010 is provided with a processor for outputting signals;

the signal extraction board 011 is used for extracting and transmitting signals in the main board 010 to the loss board 012;

the loss board 012 is used for sending the received signals to the test instrument 013 under different loss parameters, and the loss value of the loss board 012 is adjustable;

the test instrument 013 is configured to obtain signals output by the loss board 012, and determine critical loss parameters from different loss parameters by detecting the integrity of signals obtained under the different loss parameters; the critical loss parameter is a maximum loss parameter that enables the integrity of the signal acquired by the test instrument 013 to meet a preset first integrity requirement.

Optionally, the lossy plate 012 is connected to the signal pigtail 011 and the test meter 013, respectively, by test cables.

The functions of the motherboard 010, the signal extraction board 011, and the loss board 012 in the system are respectively consistent with those of the motherboard 001, the signal extraction board 002, and the loss board 003 in the line loss test link shown in fig. 1, and the functions of the test instrument 013 in the system are consistent with those of the test device in the above-described method embodiment.

For the functions of the respective structures in the system, the processing procedure, the beneficial effects of the processing, etc., reference may be made to the description of the corresponding parts in the above method embodiments, and this will not be repeated here.

Exemplary electronic device

Another embodiment of the present application further provides a line loss testing apparatus, referring to fig. 6, which includes:

a memory 200 and a processor 210;

wherein the memory 200 is connected to the processor 210, and is used for storing a program;

the processor 210 is configured to implement the line loss testing method disclosed in any one of the foregoing embodiments by running a program stored in the memory 200.

Specifically, the line loss test apparatus may further include: a bus, a communication interface 220, an input device 230, and an output device 240.

The processor 210, the memory 200, the communication interface 220, the input device 230, and the output device 240 are interconnected by a bus. Wherein:

A bus may comprise a path that communicates information between components of a computer system.

Processor 210 may be a general-purpose processor such as a general-purpose Central Processing Unit (CPU), microprocessor, etc., or may be an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of programs in accordance with aspects of the present invention. But may also be a Digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components.

Processor 210 may include a main processor, and may also include a baseband chip, modem, and the like.

The memory 200 stores programs for implementing the technical scheme of the present invention, and may also store an operating system and other key services. In particular, the program may include program code including computer-operating instructions. More specifically, the memory 200 may include read-only memory (ROM), other types of static storage devices that may store static information and instructions, random access memory (random access memory, RAM), other types of dynamic storage devices that may store information and instructions, disk storage, flash, and the like.

The input device 230 may include means for receiving data and information entered by a user, such as a keyboard, mouse, camera, scanner, light pen, voice input device, touch screen, pedometer, or gravity sensor, among others.

Output device 240 may include means, such as a display screen, printer, speakers, etc., that allow information to be output to a user.

The communication interface 220 may include devices using any transceiver or the like for communicating with other devices or communication networks, such as ethernet, radio Access Network (RAN), wireless Local Area Network (WLAN), etc.

Processor 210 executes programs stored in memory 200 and invokes other devices that may be used to implement the various steps of any of the line loss testing methods provided by the above-described embodiments of the present application.

The embodiment of the application also provides a chip which comprises a processor and a data interface, wherein the processor reads and runs a program stored in a memory through the data interface so as to execute the line loss test method introduced in any embodiment, and the specific processing process and the beneficial effects thereof can be introduced by referring to the embodiment of the line loss test method.

Exemplary computer program product and storage Medium

In addition to the methods and apparatus described above, embodiments of the application may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform steps in a line loss test method described in the "exemplary methods" section of this specification.

The computer program product may write program code for performing operations of embodiments of the present application in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.

Furthermore, an embodiment of the present application may also be a storage medium having stored thereon a computer program that is executed by a processor to perform the steps in the line loss test method described in the "exemplary method" section of the present specification.

For the foregoing method embodiments, for simplicity of explanation, the methodologies are shown as a series of acts, but one of ordinary skill in the art will appreciate that the present application is not limited by the order of acts, as some steps may, in accordance with the present application, occur in other orders or concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present application.

It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other. For the apparatus class embodiments, the description is relatively simple as it is substantially similar to the method embodiments, and reference is made to the description of the method embodiments for relevant points.

The steps in the method of each embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs, and the technical features described in each embodiment can be replaced or combined.

The modules and the submodules in the device and the terminal of the embodiments of the application can be combined, divided and deleted according to actual needs.

In the embodiments provided in the present application, it should be understood that the disclosed terminal, apparatus and method may be implemented in other manners. For example, the above-described terminal embodiments are merely illustrative, and for example, the division of modules or sub-modules is merely a logical function division, and there may be other manners of division in actual implementation, for example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.

The modules or sub-modules illustrated as separate components may or may not be physically separate, and components that are modules or sub-modules may or may not be physical modules or sub-modules, i.e., may be located in one place, or may be distributed over multiple network modules or sub-modules. Some or all of the modules or sub-modules may be selected according to actual needs to achieve the purpose of the embodiment.

In addition, each functional module or sub-module in the embodiments of the present application may be integrated in one processing module, or each module or sub-module may exist alone physically, or two or more modules or sub-modules may be integrated in one module. The integrated modules or sub-modules may be implemented in hardware or in software functional modules or sub-modules.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software unit executed by a processor, or in a combination of the two. The software elements may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of line loss testing, comprising:

2. The method of claim 1, wherein the first signal link further comprises a test instrument coupled to the wear plate;

3. The method according to claim 1, wherein the method further comprises:

4. The method according to claim 1, wherein the method further comprises:

5. The method of claim 4, wherein if the integrity of the output signal of the first signal link in the different operating environments respectively under the critical loss parameter does not meet the first integrity requirement, detecting the integrity of the output signal of the first signal link in the different operating environments respectively under a candidate loss parameter, the candidate loss parameter being smaller than the critical loss parameter;

6. The method according to claim 4, wherein the method further comprises:

7. The method of claim 1, wherein detecting the integrity of the signal output by the first signal link at different loss parameters comprises:

8. A line loss testing system, comprising:

the main board is provided with a processor for outputting signals;

9. The signal line loss testing system according to claim 8, wherein the loss board is connected to the signal extraction board and the test instrument by test cables, respectively.

10. A line loss testing apparatus, comprising:

11. A line loss testing apparatus, comprising:

a memory and a processor;

the memory is connected with the processing and is used for storing programs;

the processor is configured to implement the line loss test method according to any one of claims 1 to 7 by running a program in the memory.

12. A storage medium having stored thereon a computer program which, when executed by a processor, implements the line loss testing method according to any of claims 1 to 7.