CN116648853A - Interactive online adaptation for digital predistortion and power amplifier system auto-tuning - Google Patents

Abstract

An auto-tuning controller for improving the power efficiency and linearity of a digital power amplifier DPA is provided. The controller includes: an interface including an input terminal and an output terminal connected to the DPA, the interface configured to acquire an input signal and an output signal; a digital predistortion DPD-DPA adaptive controller comprising a processor and memory that run and store DPD algorithms, efficiency enhancement methods and learn cost functions. The DPD adaptive controller is configured to perform the following steps: calculating DPD coefficients by using a data driven optimization method to define a learning cost function based on the DPD model, wherein the learning cost function includes both variables of DDA performance and variables of DPD performance; updating the learning cost function based on DPD performance; optimizing an updated learning cost function by solving the updated learning cost function for variables of the DDA performance; and providing optimal parameters for DPA and DPD through the interface.

Description

Interactive online adaptation for digital predistortion and power amplifier system auto-tuning

Technical Field

The present invention relates generally to a power amplifier system and more particularly to a digital doherty power amplifier (Doherty power amplifier) system and a Digital Predistortion (DPD) system and a learning based auto-tuning optimization method for a power amplifier system for enhancing the performance of a radio frequency power amplifier.

Background

The rapid increase in the amount and rate of wireless communication data has led to a significant increase in the power consumption of wireless transmitters, with Power Amplifiers (PA) being a critical component of energy consumption. Advanced techniques including Envelope Tracking (ET), doherty Power Amplifier (DPA), envelope Elimination and Restoration (EER) are proposed to improve the Power Added Efficiency (PAE) of the PA. Among these techniques, DPA is very promising due to its simple structure based on active load modulation that achieves high average efficiency.

Although DPA presents many advantages for efficiency enhancement, conventional analog DPA still suffers from drawbacks that result in performance degradation in terms of energy efficiency and operating bandwidth. Conventional DPA designs are based on a single input configuration including an analog power divider (which may be adjustable), a fixed phase alignment, a carrier PA operating on class AB and a peak PA operating on class C mode, and an output power combiner. In order to increase the efficiency of DPA, several approaches have been investigated, including gate bias adaptation, asymmetric DPA, multipath DPA, adjustable phase alignment and adaptive power splitting ratio.

To obtain optimal Digital Predistortion (DPD) and PA performance, the designer needs to manually tune the circuit operating parameters and the tuning process is only effective for fixed operating conditions such as input power, frequency and signal criteria. In a real scenario, the optimal control parameters vary with input and circuit state. The compensation circuit part is also complex and difficult to optimize, making the DPA design very cumbersome. These are just limitations of designs based on pure simulations.

A more flexible architecture, such as Digital DPA (DDPA), is needed to adaptively find optimal control parameters for the input signal for various circuit states and various bandwidths, modulation formats, power levels, and modulation formats. Furthermore, in the present invention we propose to make it possible to adapt not only the parameters of the PA but also the learning cost function of the PA as a function of DPD performance, so that both systems improve their performance simultaneously.

Disclosure of Invention

Some embodiments are based on the recognition that: digital Power Amplifiers (DPAs) are programmable so that they facilitate the circuit tuning process (auto-tuning) by designers and can take into account circuit imbalances such as phase delays and environmental variations including temperature for multiple paths. Thus, DPA is not only flexible but can provide enhanced performance compared to analog DPA.

Furthermore, some embodiments of the invention are based on the recognition that: an auto-tuning controller may be provided to improve the power efficiency and linearity of a Digital Power Amplifier (DPA). The auto-tuning controller may include: an interface including an input terminal and an output terminal connected to the DPA, the interface configured to acquire an input signal and an output signal; a Digital Predistortion (DPD) -DPA adaptive controller comprising a processor and memory to run and store DPD algorithms, efficiency enhancement methods and learn cost functions. The DPD adaptive controller may be configured to perform the steps of: calculating DPD coefficients by using a data driven optimization method to define a learning cost function based on the DPD model, wherein the learning cost function includes both variables of DDA performance and variables of DPD performance; updating the learning cost function based on the DPD performance; optimizing an updated learning cost function by solving the updated learning cost function for variables of the DDA performance; and providing optimal parameters of DPA and DPD through the interface. In some cases, the providing step may be to send the optimized updated variables of the learning cost function to the DPA via the interface.

According to an embodiment of the present invention, there is provided a DPA system, a Digital Doherty Power Amplifier (DDPA) system, a Digital Predistortion (DPD) and a learning-based auto-tuning method (optimization method) which improves the efficiency and gain of the DPD working with the PA system, in particular by adaptive control while satisfying linearity requirements. The DDPA system and optimization method can be used for a base station radio front end of a transmitter including 3G, 4G LTE, 5G and above.

In some cases, the DDPA system may include an auto-tune controller and a Doherty Power Amplifier (DPA) circuit having a control input and an output for generating an output signal. The auto-tuning controller may include: an interface including an input terminal and an output terminal connected to the DPA, the interface configured to acquire an input signal and an output signal; a Digital Predistortion (DPD) -DPA adaptive controller comprising a processor and memory to run and store DPD algorithms, efficiency enhancement methods and learn cost functions. The DPD adaptive controller may be configured to perform the steps of: calculating DPD coefficients by using a data driven optimization method to define a learning cost function based on the DPD model, wherein the learning cost function includes both variables of DDA performance and variables of DPD performance; updating the learning cost function based on the DPD performance; optimizing an updated learning cost function by solving the updated learning cost function for variables of the DDA performance; and providing optimal parameters of DPA and DPD through the interface. In some cases, the providing step may be to send the optimized updated variables of the learning cost function to the DPA via the interface.

Some embodiments of the present invention provide a DPD and Digital Doherty Amplifier (DDA) system that finds the optimal set of control parameters completely adaptively, regardless of device parameters, environmental changes, without complex engineering tuning, where the goal of optimal control is high efficiency with reasonable gain in, for example, a wideband radio transmitter.

One embodiment of the present invention is a model-free algorithm without assumptions or a priori knowledge about the DPA device, where the algorithm searches for an optimal configuration based on black box optimization, where the optimization learning cost function for the PA is a function of DPD performance.

Some embodiments not only optimize DPA efficiency, but also enhance gain and linearity in a flexible way, while the linearity term in the learning cost is proportional to DPD linearization performance. For example, in some embodiments, the system may balance gain and efficiency tradeoffs in different frequency bands or maximize efficiency under certain constraints. One example is to optimize efficiency while requiring the gain to be greater than a configured threshold. In the case of modulated signals, we optimize efficiency, gain, and Adjacent Channel Power Ratio (ACPR) under the same DDPA scenario. ACPR is an important factor in the modulated signal that limits the power of the primary channel transmission to the adjacent channels.

According to an embodiment of the present invention, a Digital Power Amplifier (DPA) system includes: a Power Amplifier (PA) circuit having a control input and an output for generating an output signal; and an adaptive control circuit comprising an input interface, an output interface, a memory storing an adaptive control algorithm, and a processor coupled to the memory that executes instructions based on the adaptive algorithm, wherein the input interface receives an input state signal and an output signal of the PA circuit, wherein the adaptive control algorithm determines control parameters of a control signal sent from the output interface to the control input for controlling operation of the PA circuit in response to the input state signal and the output signal.

The accompanying drawings are included to provide a further understanding of the invention, illustrate embodiments of the invention, and together with the description serve to explain the principle of the invention.

Drawings

[ FIG. 1]

Fig. 1 is a schematic diagram showing a Digital Power Amplifier (DPA) according to an embodiment of the invention;

[ FIG. 2]

Fig. 2 is a schematic diagram showing stages of improving linearity and efficiency of a power amplifier by DPD (digital predistortion) processing according to an embodiment of the present invention;

[ FIG. 3A ]

Fig. 3A is a schematic diagram illustrating an algorithm for PA auto-tuning according to an embodiment of the present invention;

[ FIG. 3B ]

Fig. 3B is a block diagram illustrating a Digital Power Amplifier (DPA) according to an embodiment of the invention;

[ FIG. 4]

FIG. 4 is a block diagram illustrating interactions between DPD, DPA and a learning cost update process according to an embodiment of the invention;

[ FIG. 5A ]

Fig. 5A is a flowchart of a DPD/DPA tuning algorithm according to an embodiment of the present invention;

[ FIG. 5B ]

FIG. 5B is a block diagram illustrating several data driven optimizations used in a DPD/DPA tuning algorithm in accordance with an embodiment of the present invention;

[ FIG. 5C ]

FIG. 5C is a block diagram illustrating several DPD model selections used in a DPD/DPA tuning algorithm in accordance with an embodiment of the invention;

[ FIG. 6]

FIG. 6 is a block diagram illustrating the effect of DPD and DPA performance on the learning cost function update process, according to an embodiment of the invention;

[ FIG. 7]

FIG. 7 shows steps of an algorithm for updating a learning cost function according to an embodiment of the present invention; and

[ FIG. 8]

Fig. 8 shows steps of an algorithm for a trimming process according to an embodiment of the present invention.

Detailed Description

Various embodiments of the present invention are described below with reference to the accompanying drawings. It should be noted that the figures are not drawn to scale and that elements having similar structures or functions are represented by like reference numerals throughout the figures. Furthermore, some components and process steps are indicated by numerals. It should also be noted that the drawings are only intended to facilitate the description of specific embodiments of the invention. They are not intended as an exhaustive description of the invention or as a limitation on the scope of the invention. In addition, aspects described in connection with particular embodiments of the invention are not necessarily limited to that embodiment and may be practiced in any other embodiments of the invention.

Some embodiments of the invention are based on the recognition that an auto-tuning controller can be provided to improve the power efficiency and linearity of a Digital Power Amplifier (DPA). The auto-tuning controller may include: an interface including an input terminal and an output terminal connected to the DPA, the interface configured to acquire an input signal and an output signal; a Digital Predistortion (DPD) -DPA adaptive controller comprising a processor and a memory running and storing a DPD algorithm, an efficiency enhancement method and a learning cost function. The DPD adaptive controller may be configured to perform the steps of: calculating DPD coefficients by using a data driven optimization method to define a learning cost function based on the DPD model, wherein the learning cost function includes both variables of DDA performance and variables of DPD performance; updating the learning cost function based on the DPD performance; optimizing an updated learning cost function by solving the updated learning cost function for variables of the DDA performance; and transmitting the optimized updated variables of the learning cost function to the DPA via the interface.

Fig. 1 is a block diagram of a Digital Power Amplifier (DPA) module (DDPA system) 100 in accordance with some embodiments of the invention. DPA module 100 may be a Digital Power Amplifier (DPA) module configured by a multi-input power amplifier 120 such as a doherty power amplifier, an outphasing power amplifier, a balanced power amplifier, and a push-pull power amplifier. As an example, a doherty power amplifier is used in the Digital Power Amplifier (DPA) module 100 to explain the function of the DPA module. The DPA module 100 may be referred to as a DDPA (digital doherty power amplifier) module 100. However, it should be noted that an out-of-phase power amplifier circuit, a balanced power amplifier circuit, or a push-pull power amplifier circuit may also be used, depending on variations in circuit design.

The DDPA module 100 may include a baseband processing module 101, a Digital Predistortion (DPD) and Digital Doherty Amplifier (DDA) adaptive control module 102, an amplitude ratio/phase control module (Amp-phase module) 103, a signal converter 110, a dual input DPA module (DPA module, but not limited to, dual input) 120, and a power supply 104, the power supply 104 for providing bias conditions (voltages and/or currents) to the DPA unit 120 according to optimal control parameters (or control parameters) 313 generated by the DDA adaptive control module 102. DPA module 120 includes a main PA (carrier PA) 121, a peak PA122, and an output combiner 123. The signal converter 110 includes digital-to-analog converters (DACs) 111 and 112 and up-converters 113 and 114. The PA output and input impedance matching networks are omitted from the figure.

The dual input DPA 120 includes a carrier Power Amplifier (PA) 121 for controlling a carrier signal and a peak Power Amplifier (PA) 122 for controlling a peak signal, and an output combiner 123 for combining signals from the carrier PA 121 and the peak PA 122. Obviously, the configuration of digital doherty can be extended to multi-way doherty, where more than two PAs are included in a similar topology as described in 100.

When power amplifiers other than doherty amplifiers (e.g., outphasing PA and balanced PA) are used in the module 100, the DPD & DDA adaptive control module 102 may be referred to as an auto-tuning controller or Digital Adaptive (DA) control module 102 for improving linearity and power efficiency of the Digital Power Amplifier (DPA). The DPD & DDA adaptive control module 102 includes a portion not shown in the drawing. For example, the DPD & DDA adaptive control module 102 includes an interface including an input terminal and an output terminal connected to the DPA. The interface is configured to acquire an input signal from the baseband processing module 101 and an output signal from the dual-input DPA 120, and to transmit optimal control parameters (optimal control parameter signals) 313 and 104. The auto-tune controller 102 also includes a Digital Predistortion (DPD) -DPA adaptive controller. A Digital Predistortion (DPD) -DPA adaptive controller includes a processor and memory that runs and stores a DPD algorithm, an efficiency enhancement method, and a learning cost function. In this case, the DPD adaptive controller is configured to perform the following steps: calculating DPD coefficients by using a data driven optimization method to define a learning cost function based on the DPD model, wherein the learning cost function includes both variables of DDA performance and variables of DPD performance; updating the learning cost function based on the DPD performance; optimizing an updated learning cost function by solving the updated learning cost function for variables of the DDA performance; and providing optimal parameters of DPA and DPD through the interface.

The input signal 301 is sent to the DA adaptive control module 102 via an interface. The DA adaptive control module 102 performs data driving optimization using the input signal 301 and the output signal 300 from the DPA module 120 and generates optimal control parameters 313 regarding the phase difference between the PAs 121 and 122 and the input power ratio of the PAs 121 and 122. In some cases, control parameters 313 may be referred to as updated DDPA parameters. The updated DDPA parameters 313 are provided to an amplifier phase (Amp-phase) module 103. Furthermore, the optimization discussed above may be referred to as a learning-based auto-tuning method of the power amplifier system.

In this case, the control parameters 313 include gate bias parameters of the PAs 121 (Vg 1) and 122 (Vg 2), an input signal phase difference between the PAs 121 and 122, and an input power distribution (ratio) of the PAs 121 and 122. Further, the power supply 104 receives the gate bias parameters from the DDA adaptive control module 102, and applies gate bias voltages to the PAs 121 and 122 according to the gate bias parameters (Vg 1, vg 2). When the amplifier phase (Amp-phase) module 103 receives the phase difference between the PAs 121 and 122 and the input power ratio of the PAs 121 and 122 from the DDA adaptive control module 102 as part of the control parameter 313, the amplifier phase (Amp-phase) module 103 generates signals S1 and S2 to apply to the PAs 121 and 122, respectively. In this case, the signals S1 and S2 are formed such that the amplitude ratio of the signals S1 and S2 and the phase difference between the signals S1 and S2 satisfy the value indicated by the optimal control parameter 313 calculated by the DDA adaptive control module 102.

In some cases, DDA adaptive control module 102 may include a power supply 104, and PAs 121 and 122 may be Field Effect Transistors (FETs) fabricated using gallium nitride (GaN) based materials or other different semiconductor device technologies. Further, the PAs 121 and 122 may be bipolar transistors (BPTs). In this case, the gate bias is replaced by the base current bias of the bipolar transistor. The BPT may be formed by GaN-based materials or other different semiconductor device technologies.

The output signal of the output combiner 123 (e.g., a quarter-wavelength transmission line may be used as the output combining network. Furthermore, other forms such as lumped element inductors, capacitors based on the same combining function may also be used) may be transmitted from an antenna (not shown) via a predetermined band pass filter (not shown). In some other cases, the output combining network may be spatial combining without any physical components or circuitry, such as in the case of massive MIMO phased arrays used in 5G (e.g., as defined in release 1515 of 3GPP standard specification 3GPP TS 38.104 release 15.2.0). Further, an input interface (not shown) of the DDA control module 102 receives (detects) an output signal of the output combiner 123 to calculate control parameters 313 that control the carrier PA 121 and the peak PA122, respectively. In some cases, the control parameters 313 may be referred to as tuning parameters.

Each of the carrier PA 121 and the peak PA122 may be controlled by control parameters 313 indicating gate bias, phase, and input signal power. The phase signal and the input power signal are applied to an amplifier phase (Amp-phase) module 103. The amplifier phase (Amp-phase) module 103 adjusts the amplitude ratio and phase of the signals of the carrier PA 121 and the peak PA122 according to the control parameters 313 generated by the DDA adaptive control module 102.

In this case, if necessary, the signal converter 110 generates and supplies appropriately phased signals and input power signals to the carrier PA 121 and the peak PA122 via a drive amplifier (not shown) that drives the carrier PA 121 and the peak PA 122.

The DPD & DDA adaptive control module 102 includes a processor (not shown) coupled to one or more memories (not shown) storing an adaptive control algorithm, wherein the processor executes instructions according to a predetermined adaptive algorithm. Furthermore, the adaptive control algorithm is based on model-free optimization, known as adaptive tuning control.

The control parameter 313 is generated by the DDA adaptive control module 102 that calculates the value of the control parameter 313 by adaptive optimization control. In some cases, control parameters 313 may be referred to as data-driven optimization parameters.

In addition, DDA adaptive control module 102 also includes an input interface (not shown) for receiving input signal 301 and output signal 300 of dual-input DPA module 120, and an output interface (not shown) for generating control parameters 313, control parameters 313 including phase control signals, power ratio control signals, and bias signals for controlling dual-input DPA 120 and carrier PA 104 and peak PA 105.

The DDA adaptive control module 102 receives the baseband signal from the baseband processing module 101 and detects the output signal 300 of the output combiner 106 via an input interface to generate control parameters 313 based on an adaptive control algorithm, the control parameters 313 may be referred to as data-driven optimization parameters 313. In this case, a portion of the data drive optimization parameters 313 are provided to an amplifier phase (Amp-phase) control module 103 via an output interface for controlling the phase and power ratio of PA 121 and PA 122. In addition, another portion of the data drive optimization parameters 313 are converted to gate biases that are provided to the PA 121 and PA122 via the power supply 104, respectively, for controlling the gate biases of the PA 121 and PA 122.

In fig. 1, DDPA module 100 is programmable so that it facilitates the circuit tuning process for the designer and allows for comprehensive consideration of multipath circuit imbalance and imperfections. Accordingly, the DDPA module 100 is not only flexible and low cost, but also provides better performance than analog DPA. Designs according to embodiments of the present invention benefit from software design principles such that control ports can be modified by algorithms to achieve optimal performance.

Making the RF power amplifier more efficient means driving it to a point close to its saturation point. In this case, the modulated waveform tends to be distorted (introduce nonlinearities characterized by ACPR (adjacent channel power ratio)). Thus, the design goal is to maximize Power Added Efficiency (PAE) while maintaining high gain and good linearity (ACPR). In some cases, digital linearity may be achieved by Digital Predistortion (DPD).

Fig. 2 shows the stages of improving linearity and efficiency of PAs 121 and 122 by DPD (digital predistortion) process 201 and efficiency enhancement process 202, respectively. In the process, digital predistortion of an input signal is performed in step 201, efficiency enhancement is performed in step 202, and an input signal obtained by the process by Digital Predistortion (DPD) and efficiency enhancement is supplied to the PAs 121 and 121 in step 203.

Fig. 3A shows a detailed block diagram of our algorithm for PA auto-tuning, where an input signal (input state signal) 301 is used as an input state, which includes different states indicating frequency and input power level, but is not limited to these two states, and may also include other states such as signal modulation formats. An input state signal 301 indicative of frequency and input signal power level is fed to DDA adaptive control module 102 to adaptively tune control parameters 313 of DDPA 120, such as gate bias 303, phase difference 304 between main and peak amplifiers, and input power profile 305, by using input signal 301 and output signal 330 of dual input DPA module 120. Finally, the tuned parameters are fed to a dual input DPA module 120.

Depending on circuit design variations, DPA module 120 may include three or more Power Amplifiers (PAs). See, for example, fig. 3B. In this case, DDA adaptive control module 102 provides control parameters 313 for each of the three or more power amplifiers.

Fig. 3B is a block diagram illustrating a multiple-input digital power amplifier module 350 that performs an auto-tuning process for a DPA module in accordance with an embodiment of the invention.

In this figure, when the functions of the components are similar to those in fig. 1, the same component numbers in fig. 1 are used for the components. In addition, descriptions of the same part numbers are omitted.

The multi-input digital power amplifier module 350 includes a baseband processing module 101, a DPD & DDA adaptive control module 102, an amplitude ratio/phase control module 103, a signal converter 110, and a multi-input PA module 120. In this case, the signal converter 110 includes digital-to-analog converters (DACs) 111, 112, and 112n and up-converters 113, 114, and 114n.

The multiple input PA module 120 includes a carrier Power Amplifier (PA) 121 for controlling a carrier signal and a peak power amplifier 122 for controlling a peak signal, a second peak Power Amplifier (PA) 122n for controlling a second peak signal, and an output combiner 123 for combining signals from the PA 121, the PA122, and the PA122 n. In this case, the signal converter 110 includes three or more DACs and three or more up-converters, and the multi-input PA module 120 includes three or more power amplifiers 121, 122, and 122n.

The DA adaptive control module 102 generates updated DPA parameters 313 using the input signal 301 and the output signal 300 of the multi-input PA module 120 and provides the updated DPA parameters to the amplifier phase (Amp-phase) module 103. Then, an amplifier phase (Amp-phase) module 103 provides a signal to the signal converter 110 such that the signal converter produces S1, S2, and S2n to be applied to PA 121, PA122, and PA122 n, respectively.

As described above, the DPD & DDA adaptive control module 102 is used to calculate the optimal control parameters 313. A detailed discussion of the optimal control parameters will be provided below.

As shown in fig. 4, the main embodiment of the present invention is the design of the interaction loop 450 between DPD adaptation and DDA adaptation performed in the DPD and DDA adaptation control module 102. Part of this interaction cycle 450 is based on the adaptation of the learning cost function 410 to the DPD performance 401. The learning cost function is adjusted based on DPD performance and then used to perform adaptive control 405 of DDA (DDA adaptation 405). The system is coupled and adaptation of DDA 405 also affects DPD performance 401. This interactive cycling makes this problem challenging.

As shown in fig. 5A, in some embodiments of the invention, we propose that the interaction loop 450 can be implemented as follows: the system optimization process begins with a pre-optimization stage 560 in which DDA is first modified separately. In this pre-optimization stage 560, the optimization variables of the DDA are defined 561, and then only the local learning cost function for the DDA is defined 562. The local DDA learning cost function is then optimized 563 using a data driven optimization method 566. As shown in fig. 5B, for example, an extremum searching method 576, a simulated annealing method 567, a bayesian optimizing method 577, a hill climbing method 579, or the like 597 may be used. After this pre-optimization phase 560, the algorithm checks if the user (input from the user interface) includes DPD tuning 564, if DPD tuning is not needed, the algorithm terminates, if DDP tuning is needed, the algorithm moves to the next phase, i.e. the interaction loop 450 between DPD tuning and DDA tuning, which constitutes the main embodiment of the present invention.

In this DPD-DDA interaction cycle, the 581DPD model is first selected. For example, in one embodiment, a polynomial model is selected; in another embodiment, a nonlinear triangle model is selected, and in yet another embodiment, a deep neural network model is selected as the DPD model. The DPD coefficients are then calculated at the stage of DPD iteration 582 using an optimization method. For example, 583 Least Squares (LS) optimization is used. In other embodiments, other non-linear optimization methods may be used at this stage 582. Then, a global learning Cost Function (CF) is measured 584. This global cost function differs from the local learning cost function 562 by the fact that it includes two elements from DDA performance 405 and DPD performance 401. Comparing 584 the learned cost function to a desired cost function threshold; if the value of the learning cost is high enough, the algorithm stops, otherwise the algorithm moves to the learning cost update stage 410.

In this stage, the coefficient of learning cost is updated 410 based on the performance of DPD 401. This stage will be described in detail later in fig. 6 as a main embodiment of the present invention.

Next, the updated learning cost function 410 is optimized 596. This optimization is achieved by solving to maximize the updated learning cost function 410 with respect to the DDA variable 313. These variables can be defined as:

Θ＝[A _CR,dB α φ Φ _Att V _GS,m V _GS,p ] (1)

wherein A is _CR,dB Is the threshold for PAPR reduction, α is the power ratio, φ is the phase difference, phi _Att Is the attenuation difference, V _GS,m Is the main bias voltage of the power amplifier, V _GS,p Is the peak bias voltage of the power amplifier.

However, we recognize that this optimization problem can be simplified by pruning DDA coefficients 580 that need to be optimized. The process 580 may result in a complete or partial optimization 596 based on the pruning 580 results. In effect, if pruning 580 selects the subset of DDA variables that are most sensitive in the optimization process, then the local optimization is solved for 596. On the other hand, if pruning process 580 finds that all DDA variables are equally important in optimization, then a full optimization is solved for 596.

In several embodiments of the present invention, we propose to start the pruning process at different stages of the algorithm. For example, in one embodiment, we propose to start the pruning process 580 after the pre-optimization phase 560, and if the user wants to include DPD tuning 564, then start 599 the pruning process 580 in parallel with defining the DPD model 581 and the subsequent phases of the algorithm. In another embodiment, we propose to start 591 the pruning process 580 only after the learning cost function has been updated 410. Details of the trimming process are given later in fig. 8.

Then, optimizing 596 the solution results in the value of the learned cost function being improved (i.e., higher than the cost function value in 584), or not being improved. If there is an improvement in the learning cost function value (i.e., higher), the algorithm loops back to the DPD optimization iteration 582. If not, then at 588 the algorithm tests whether the performance 401 of the DPD and the DDA performance 405 are within the desired threshold performance set by the user. If so, the algorithm terminates its learning of the optimal DPD coefficients and DDA coefficients. If not, the 587DPD model is modified to find a better DPD pattern that may lead to an improvement in the learning cost function 584.

DPD model modification 587 may be performed differently for different embodiments of the present invention. For example, we can only modify the size of DPD model 5871. This size modification, also known as DPD model resizing, may be accomplished using hill climbing or other optimization methods. We can also modify DPD model nonlinearities 5872. For example by implementing triangular nonlinearities rather than polynomial nonlinearities. We can also use deep neural network 5873 to model DPD, etc 5874.

As shown in fig. 6, in one embodiment of the present invention, we recognize that learning cost 410 may be defined as:

wherein ACPR is an _t ,EVM _t ,P _out,t And PAE (PAE) _t ACPR, EVM, output power, and efficiency targets, respectively. Similarly, ACPR, EVM, P _out And PAE are measured ACPR 610, EVM 640, output power 620, and efficiency 630, respectively. w (w) ₁ 631 is the weight associated with the first DPD performance ACPR 610, w ₂ 632 is the weight, w, associated with the second DPD performance EVM 640 ₃ 633 is a weight, w, associated with the first DPA power performance 620 ₄ 634 are weights associated with the second DPA efficiency performance 630.

The goal of our proposed approach is to maximize J410 to 1, which means that the user specification goal is met. The determination of the weighting coefficients is an important aspect in the design of the learning cost function.

For example, the equal weight method gives each objective function equal importance. This principle can be used to determine the weighting coefficients if no linearization process is used in the optimization process. However, DPD significantly improves linearity, which allows us to reduce the weight of the DPD performance 601 of linearity by assuming that DPD would improve DPA linearity performance. In this case we want to pay attention to the DPA performance 602 of power and efficiency. On the other hand, applying DPD introduces back-offs in terms of operating power levels, which significantly reduces output power and power efficiency. Therefore, it has an effect on the cost function, which becomes worse than the value before DPD is applied.

We therefore propose to design an adaptive cost function in which the weight coefficients are adjusted according to the evolution of the optimization process. The updating of the weighting coefficients is performed for how much the DPD improves the figures of merit ACPR 610 and EVM 640 compared to the previous iteration.

The coefficient w is described in algorithm 701 as shown in FIG. 7 _i I=1, 2,3, 4. In one embodiment of the invention, the weight w ₁ 631、w ₂ 632、w ₃ 633 and w ₄ 634 are adjusted as follows: the weights are initialized to a constant value 711 such that their sum equals 1. Run 721 optimizes to optimize the learning cost function using these constant weights, and then calculates 731 the resulting ACPR, EVM, and learning cost value J. The number of maximum learning iterations is set 731. Then, DPD is applied to the system and its performance is measured 601. Then, by evaluating DPD Performance ACPR 610 and Performance EVM 640 from the desired performance target ACPR _t And EVM _t How far to mainly aim at w ₁ ，w ₂ Performing weight adjustment; then, by the distance between two consecutive ACPR properties and the target ACPR _t Ratio of properties 771 gives w ₁ Is set in the above-described table. Similarly, w ₂ Is determined by the distance between two successive EVM performances and the target EVM _t The ratio 781 of the properties is given. These adjustment values are then used to adjust w ₁ 702 and w ₂ 703. The remaining weights are simply adjusted so that the sum of all weights remains equal to one 704, 706.

Optimization of the learning cost J is then performed again 707 using the updated weights, and the associated learning cost J is obtained 708. If the learning cost value is greater than the previous learning cost at the previous learning iteration 709, the weighted adaptive algorithm terminates. If not, the learning iteration counter i is incremented 755 and the weight adaptation loop is re-performed 705. The algorithm terminates when the learning costs have improved 710, 709, or when the learning iteration counter has reached its maximum number N.

In another embodiment, we propose to update the weights w as follows ₁ And w ₂ ：

w _1，i ＝w _1，i +||ACPR _1，i -ACPR _t ||

w _2，i ＝w _2，i +||EVM _i -EVM _t ||

The remaining weights may then be updated to maintain the sum of the total weights at 1, as in 704, 706.

In another embodiment we propose to update all weights as a general function of DPD performance 601. For example, we can write weights as:

w _1，i ＝w _1，i +f ₁ (ACPR _i ，ACPR _t ，EVM _i ，EVM _t )

w _2,i ＝w _2,i +f ₂ (ACPR _i ,ACPR _t ,EVM _i ,EVM _t )

w _3,i ＝w _3,i +f ₃ (ACPR _i ,ACPR _t ,EVM _i ,EVM _t )

w _4,i ＝w _4,i +f ₄ (ACPR _i ,ACPR _t ,EVM _i ,EVM _t ),

wherein f _i I=1, 2,3,4, defined as evaluating DPD performance ACPR 610, EVM 640 and desired performance ACPR _t ,EVM _t A function of the distance between them.

As shown in fig. 8, in some embodiments of the invention, we propose the following clipping process 580. The pruning process begins with coefficient values 599, 591 of the resulting DDA, and the coefficient of sensitivity index is initialized to i=1 5801. Then, the index coefficient i is left-right perturbed by adding and subtracting a small search value 5802. This exploration 5802 results in two new values of DDA coefficients for which the learning cost is estimated 5803. The obtained value of the learning cost is then saved in the memory 5804. Then, the DDA coefficient index increases by 1 5805. If the new index is less than the total number of DDA coefficients (which is equal to 6), the algorithm loops back to perturb the value of the DDA coefficient by adding a small explored value 5802 to the new index of DDA coefficient values. If the index is equal to the total number of DDA coefficients (which is equal to 6), the maximum value of all the saved learning cost function values is obtained, the corresponding value is the new value of the DDA coefficient, the corresponding coefficient index is one of the sensitivity coefficients, and then it is stored in the memory 5807. Then, the pruning process continues by using the new value of DDA coefficient and reinitializing the index to i=1. The pruning process continues until there is no improvement in learning costs. Finally, all the indexes found and stored in the memory are the sensitivity coefficients 5811 of the DDA coefficients.

The above-described embodiments of the invention may be implemented in any of a variety of ways. For example, embodiments may be implemented using hardware, software, or a combination thereof. When implemented in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers. Such a processor may be implemented as an integrated circuit with one or more processors in an integrated circuit component. However, the processor may be implemented using circuitry in any suitable format.

Furthermore, embodiments of the invention may be implemented as a method that has provided examples. Acts performed as part of the method may be ordered in any suitable manner. Thus, embodiments may be constructed in which acts are performed in a different order than shown, which may include performing some acts simultaneously, although shown as sequential acts in the illustrative embodiments.

Use of ordinal terms such as "first," "second," etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (except for the ordinal terms) to distinguish the claim elements.

While the invention has been described by way of examples of preferred embodiments, it is to be understood that various other adaptations and modifications may be made within the spirit and scope of the invention.

It is, therefore, intended in the appended claims to cover all such changes and modifications that fall within the true spirit and scope of the invention.

Claims (20)

1. An auto-tuning controller for improving power efficiency and linearity of a digital power amplifier, DPA, the auto-tuning controller comprising:

an interface including an input terminal and an output terminal connected to the DPA, the interface configured to acquire an input signal and an output signal;

a digital predistortion DPD-DPA adaptive controller comprising a processor and a memory running and storing a DPD algorithm, an efficiency enhancement method and a learning cost function, the DPD adaptive controller configured to perform the steps of:

calculating DPD coefficients by using a data driven optimization method to define a learning cost function based on the DPD model, wherein the learning cost function includes both variables of DDA performance and variables of DPD performance;

updating the learning cost function based on the DPD performance;

optimizing the updated learning cost function by solving the updated learning cost function for variables of the DDA performance; and

optimal parameters for DPA and DPD are provided through the interface.

2. The auto-tune controller of claim 1, wherein the learning cost function is defined based on sensitivity of the variable of DDA performance and the variable of DPD performance.

3. The auto-tuning controller of claim 1, wherein the learned cost function is defined by a PAPR reduction threshold, a power ratio, a phase difference, an attenuation difference, a main bias voltage of the power amplifier, and a peak bias voltage of the power amplifier.

4. The auto-tuning controller of claim 1, wherein the data-driven optimization method is an extremum searching method, a simulated annealing method, a bayesian optimization, genetic evolution, or a hill climbing method.

5. The auto-tune controller of claim 1, wherein the learning cost function is updated in real-time based on the DPD performance.

6. The auto-tuning controller of claim 1, wherein pruning of DPA coefficients is performed for fast learning in response to a request from a user.

7. The auto-tuning controller of claim 1, wherein if the value of the learned cost function is equal to or higher than the value of the desired cost function, then an update is avoided.

8. The auto-tuning controller of claim 1, wherein the learning cost function is adjusted in an interaction cycle comprising DPD adaptation and DDA adaptation.

9. The auto-tuning controller of claim 8, wherein the DDA is first adjusted individually to define a variable of the DDA.

10. The auto-tune controller of claim 1, wherein DPA adaptation and DPD adaptation are performed simultaneously in real time.

11. A digital doherty power amplifier DDPA system, the DDPA system comprising:

the auto-tuning controller of claim 1; and

a doherty power amplifier DPA circuit having a control input and an output for generating an output signal.

12. A DDPA system in accordance with claim 11 wherein offline training is performed from a previous optimal point.

13. The DDPA system of claim 11 wherein the optimization variables include a peak-to-average power ratio, PAPR reduced threshold, a power ratio, a phase difference, an attenuation difference, a main bias voltage of the PA, and a peak bias voltage of the PA.

14. A DDPA system according to claim 11, wherein the offline training is performed by Adam method, gradient descent or random gradient descent method.

15. A DDPA system according to claim 11, wherein the input signal conditions include at least a frequency of the PA, a signal power level, and a signal modulation format.

16. The DDPA system of claim 11 wherein the neural network is a convolutional neural network CNN, a deep neural network DNN, or a robust DNN.

17. The DDPA system of claim 11 wherein the trained DDA-DPD NN has been trained offline based on both input signal conditions and optimized DPD and DDA coefficients.

18. The DDPA system of claim 11 wherein the predetermined optimization method is extremum seeking optimization, simulated annealing, bayesian optimization, hill climbing, genetic evolution, or least squares.

19. A DDPA system according to claim 11, wherein a DDA-DPD NN obtained for one DDA unit can be transferred to a different DDA unit, wherein the transfer is done by limitedly tuning the DDA-DPD NN with sparse data from the new DDA unit.

20. A DDPA system in accordance with claim 11, wherein the interface is configured to connect to at least two power transistors.