CN116633271A - Method, circuit, phase-locked loop and chip for solving overvoltage of VCO capacitance switch - Google Patents

Method, circuit, phase-locked loop and chip for solving overvoltage of VCO capacitance switch Download PDF

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Publication number
CN116633271A
CN116633271A CN202310651421.XA CN202310651421A CN116633271A CN 116633271 A CN116633271 A CN 116633271A CN 202310651421 A CN202310651421 A CN 202310651421A CN 116633271 A CN116633271 A CN 116633271A
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capacitor
voltage
mos
mos tube
vco
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郭涛
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Chengdu Cetc Xingtuo Technology Co ltd
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Chengdu Cetc Xingtuo Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/02—Details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention discloses a method, a circuit, a phase-locked loop and a chip for solving overvoltage of a VCO (voltage controlled oscillator) capacitive switch, wherein the VCO is configured as an LC (inductance-capacitance) voltage controlled oscillator, the LC voltage controlled oscillator comprises a capacitive switch, the capacitive switch comprises a first MOS (metal oxide semiconductor) tube, a first capacitor and a second capacitor, a source electrode of the first MOS tube is connected with the first capacitor, a drain electrode of the first MOS tube is connected with the second capacitor, and a grid electrode of the first MOS tube is connected with a first control voltage P-Bank. The method comprises the steps of adding a second MOS tube between a first capacitor and a second capacitor, wherein the drain electrode of the second MOS tube is connected with the second capacitor, the grid electrode of the second MOS tube is connected with a first control voltage P-Bank, and the source electrode of the second MOS tube is connected with the drain electrode of the first MOS tube and a working voltage VDD, so that the voltage difference from the grid electrode to the source electrode of the first MOS tube and the drain electrode of the second MOS tube does not exceed the working voltage VDD, namely, overvoltage is avoided. The invention can effectively solve the problem of overvoltage of the device when the capacitance switch is turned off.

Description

Method, circuit, phase-locked loop and chip for solving overvoltage of VCO capacitance switch
Technical Field
The present invention relates to the field of clock chip design technologies, and in particular, to a method, a circuit, a phase-locked loop, and a chip for solving overvoltage of a VCO capacitor switch.
Background
LC oscillators with good noise performance are used in clock chip designs, particularly in high performance PLL (Phase Locked Loop ) designs. The noise performance of the LC oscillator affects the noise of the PLL, and the VAR (Volt Ampere Relation, volt-ampere characteristic) device of the LC oscillator is easily disturbed by the noise, so that the Voltage-controlled gain of the VCO (Voltage-controlled oscillator) cannot be too high, and the Voltage-controlled gain cannot cover the frequency variation range. In this case, a configurable capacitor switch array is required to widen the frequency coverage, and the overvoltage problem of the capacitor switch needs to be considered, especially when the VCO output swing reaches 2 times VDD, which may bring a great risk to the reliability of the device.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method, a circuit, a phase-locked loop and a chip for solving the overvoltage of a VCO capacitive switch, which can effectively solve the problem of overvoltage of a device when the capacitive switch is turned off.
The technical scheme adopted by the invention is as follows:
a method for solving overvoltage of a VCO capacitance switch, wherein the VCO, namely a voltage-controlled oscillator, is configured as an LC voltage-controlled oscillator, the LC voltage-controlled oscillator comprises a capacitance switch, the capacitance switch comprises a first MOS tube, a first capacitor and a second capacitor, the source electrode of the first MOS tube is connected with the first capacitor, the drain electrode is connected with the second capacitor, and the grid electrode is connected with a first control voltage P-Bank; the method for solving the overvoltage of the VCO capacitive switch comprises the following steps: and a second MOS tube is additionally arranged between the first capacitor and the second capacitor, the drain electrode of the second MOS tube is connected with the second capacitor, the grid electrode of the second MOS tube is connected with the first control voltage P-Bank, and the source electrode of the second MOS tube is connected with the drain electrode of the first MOS tube and the working voltage VDD, so that the voltage difference from the grid electrode to the source electrode of the first MOS tube and the drain electrode of the second MOS tube does not exceed the working voltage VDD, namely, no overvoltage is generated.
A circuit for solving overvoltage of a VCO capacitor switch, wherein the VCO, namely a voltage-controlled oscillator, is configured as an LC voltage-controlled oscillator, the LC voltage-controlled oscillator comprises a capacitor switch, the capacitor switch comprises a first MOS tube, a second MOS tube, a first capacitor and a second capacitor, a source electrode of the first MOS tube is connected with the first capacitor, a drain electrode of the second MOS tube is connected with the second capacitor, grid electrodes of the first MOS tube and the second MOS tube are connected with a first control voltage P-Bank, and drain electrodes of the first MOS tube and source electrodes of the second MOS tube are connected with a working voltage VDD, so that voltage difference from the grid electrodes of the first MOS tube and the second MOS tube to the source electrodes and the drain electrodes does not exceed the working voltage VDD, namely no overvoltage is caused.
Further, the LC voltage-controlled oscillator further includes an inductor, a third variable capacitor, a fourth variable capacitor, a third MOS transistor, a fourth MOS transistor, and a fifth MOS transistor, where a first end of the inductor is connected to the operating voltage VDD, a second end of the inductor is connected to the first end of the first capacitor, the first end of the third variable capacitor, a drain electrode of the third MOS transistor, and a gate electrode of the fourth MOS transistor, and a third end of the inductor is connected to the second end of the second capacitor, the second end of the fourth variable capacitor, a gate electrode of the third MOS transistor, and a drain electrode of the fourth MOS transistor; the second end of the third variable capacitor and the first end of the fourth variable capacitor are connected with a second control voltage V ctrl The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the fifth MOS tube is connected with the source electrodes of the third MOS tube and the fourth MOS tube, and the source electrode of the fifth MOS tube is grounded.
A high performance phase locked loop includes the circuit that addresses VCO capacitance switching overvoltage.
A clock chip includes the high performance phase locked loop.
A method for solving overvoltage of a VCO capacitance switch, wherein the VCO, namely a voltage-controlled oscillator, is configured as an LC voltage-controlled oscillator, the LC voltage-controlled oscillator comprises a capacitance switch, the capacitance switch comprises a first MOS tube, a first capacitor and a second capacitor, the source electrode of the first MOS tube is connected with the first capacitor, the drain electrode is connected with the second capacitor, and the grid electrode is connected with a first control voltage P-Bank; the method for solving the overvoltage of the VCO capacitive switch comprises the following steps: and replacing the first MOS tube with an I/O device, and boosting the first control voltage P-Bank to the working voltage of the I/O device through a level conversion module, so that the impedance is reduced and the voltage is not excessively exceeded.
A circuit for solving overvoltage of a VCO capacitor switch, wherein the VCO, namely a voltage-controlled oscillator, is configured as an LC voltage-controlled oscillator, the LC voltage-controlled oscillator comprises a capacitor switch, the capacitor switch comprises an I/O device, a first capacitor and a second capacitor, the first capacitor, the I/O device and the second capacitor are sequentially connected, and a first control voltage P-Bank is input into the I/O device after being boosted by a level conversion module, so that impedance is reduced and the voltage is not excessively increased.
Further, the LC voltage-controlled oscillator further comprises an inductor, a third variable capacitor and a fourth variable capacitorThe first end of the inductor is connected with the working voltage VDD, the second end of the inductor is connected with the first end of the first capacitor, the first end of the third variable capacitor, the drain electrode of the third MOS tube and the grid electrode of the fourth MOS tube, and the third end of the inductor is connected with the second end of the second capacitor, the second end of the fourth variable capacitor, the grid electrode of the third MOS tube and the drain electrode of the fourth MOS tube; the second end of the third variable capacitor and the first end of the fourth variable capacitor are connected with a second control voltage V ctrl The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the fifth MOS tube is connected with the source electrodes of the third MOS tube and the fourth MOS tube, and the source electrode of the fifth MOS tube is grounded.
A high performance phase locked loop includes the circuit that addresses VCO capacitance switching overvoltage.
A clock chip includes the high performance phase locked loop.
The invention has the beneficial effects that:
(1) The invention can effectively solve the problem of overvoltage of the device when the capacitor array is turned off by a method of giving the VDD common-mode voltage to the two switch intermediate points.
(2) The invention can effectively solve the problem of overvoltage of the device when the capacitor array is turned off by using the I/O device as the switch control of the capacitor array; the control signal is boosted by the level conversion module and then used as the control voltage of the capacitor array switch, so that the impedance of a capacitor passage is effectively reduced, and the influence on the Q value of the resonant cavity is avoided.
Drawings
Fig. 1 is a schematic diagram of a typical LC oscillator.
Fig. 2 is a schematic diagram of a current limited region and a voltage limited region.
Fig. 3 is a schematic diagram of an output swing equivalent to one end of the MOS transistor M1.
Fig. 4 is a schematic diagram of a capacitive switch according to embodiment 1 of the present invention.
Fig. 5 is a schematic diagram of an LC voltage controlled oscillator according to embodiment 1 of the present invention.
Detailed Description
Specific embodiments of the present invention will now be described in order to provide a clearer understanding of the technical features, objects and effects of the present invention. It should be understood that the particular embodiments described herein are illustrative only and are not intended to limit the invention, i.e., the embodiments described are merely some, but not all, of the embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
As shown in fig. 1, the waveforms at two ends of the capacitive switch are shown when the VCO oscillates, in which the swing at two ends of the VCO fluctuates up and down at the operating voltage VDD, and the swing can be up to 2 times the operating voltage VDD in order to pursue good performance because the noise performance of the LC oscillator is proportional to the swing of the output.
As shown in fig. 2, when the tail current increases gradually from zero, the resonance amplitude is mainly determined by the tail current and the equivalent transconductance, which is called the current-limited region. When the tail current increases to approach the resonance amplitude to 2 times the operating voltage VDD, the MOS transistor will operate most of the time in its linear region, which is called the voltage limited region. The VCO is typically operated between a current limited region and a voltage limited region.
In fig. 1, when the MOS transistor M1 serving as the switch is in the "ON" state, the quality factor of the whole switched capacitor array has the minimum value:
wherein omega 0 The angular frequency of the VCO is represented, C represents the equivalent capacitance of the switch array, n represents the n bits of the switch array, R on The linear resistance of the MOS transistor M1:
wherein L represents the gate length of the MOS tube, W represents the gate width of the MOS tube, mu n Representing the mobility of the MOS tube, C ox Representing the capacitance of the gate oxide layer per unit area, V gs Represents the gate-source voltage, V t Representing the threshold voltage of the MOS transistor.
At this time, the swing at two ends of the VCO is coupled to two ends of the MOS transistor M1 after passing through the capacitor, which is equivalent to high-pass filtering, as shown in fig. 3.
When the MOS tube M1 is turned on, the resistor R on The swing is basically attenuated after high-pass filtering, and the MOS tube M1 has no overvoltage condition; when the MOS tube M1 is disconnected, the ideal lower impedance is infinite, the swing amplitude is basically not attenuated after passing through the capacitor, and at the moment, overvoltage occurs from the grid electrode to the source electrode and from the drain electrode of the MOS tube M1.
Example 1
The embodiment provides a method for solving the overvoltage of a VCO capacitance switch, as shown in fig. 4, a second MOS transistor M2 is added between a first capacitor C1 and a second capacitor C2, a drain electrode of the second MOS transistor M2 is connected to the second capacitor C2, a gate electrode is connected to a first control voltage P-Bank, and a source electrode is connected to a drain electrode of the first MOS transistor M1 and a working voltage VDD, so that a voltage difference from the gate electrode to the source electrode and the drain electrode of the first MOS transistor M1 and the second MOS transistor M2 does not exceed the working voltage VDD, that is, no overvoltage occurs.
Meanwhile, the embodiment provides a circuit for solving the overvoltage of a VCO capacitive switch, wherein the VCO is configured as an LC voltage-controlled oscillator, the LC voltage-controlled oscillator comprises a capacitive switch, the capacitive switch comprises a first MOS tube M1, a second MOS tube M2, a first capacitor C1 and a second capacitor C2, a source electrode of the first MOS tube M1 is connected with the first capacitor C1, a drain electrode of the second MOS tube M2 is connected with the second capacitor C2, grid electrodes of the first MOS tube M1 and the second MOS tube M2 are both connected with a first control voltage P-Bank, and drain electrodes of the first MOS tube M1 and the second MOS tube M2 are both connected with a working voltage VDD, so that the voltage difference from the grid electrodes of the first MOS tube M1 and the second MOS tube M2 to the source electrode and the drain electrode does not exceed the working voltage VDD, namely the voltage does not exceed the working voltage VDD.
Preferably, as shown in fig. 5, the LC vco further includes an inductor L, a third variable capacitor C3, a fourth variable capacitor C4, a third MOS transistor M3, a fourth MOS transistor M4, and a fifth MOS transistor M5, wherein a first end of the inductor L is connected to the operating voltage VDD, a second end of the inductor L is connected to a first end of the first capacitor C1, a first end of the third variable capacitor C3, a drain electrode of the third MOS transistor M3, and a gate electrode of the fourth MOS transistor M4, and a third end of the inductor L is connected to a second end of the second capacitor C2, a second end of the fourth variable capacitor C4, a gate electrode of the third MOS transistor M3, and a third end of the inductor LA drain electrode of the fourth MOS tube M4; the second end of the third variable capacitor C3 and the first end of the fourth variable capacitor C4 are connected with the second control voltage V ctrl The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the fifth MOS tube M5 is connected with the source electrodes of the third MOS tube M3 and the fourth MOS tube M4, and the source electrode of the fifth MOS tube M5 is grounded.
Based on this, the present embodiment provides a high performance phase locked loop, including the above-mentioned circuit for solving the overvoltage of the VCO capacitance switch.
In addition, the embodiment also provides a clock chip which comprises the high-performance phase-locked loop.
Example 2
The embodiment provides a method for solving overvoltage of a VCO capacitive switch, which replaces a first MOS tube M1 with an I/O device. However, since the voltage range of the I/O device is generally greater than twice the internal operating voltage VDD, a simple replacement introduces another problem, the threshold voltage Vth of the I/O device is greater than the internal operating voltage VDD, resulting in an on-resistance R on Increase to affect the quality factor Q c,min 。
To solve the above problems, the present embodiment boosts the first control voltage P-Bank to the I/O device operating voltage through the level conversion module, thereby effectively reducing R on The problem of overvoltage is solved, and the influence on the Q value of the LC voltage-controlled oscillator is avoided.
Meanwhile, the embodiment provides a circuit for solving overvoltage of a VCO capacitive switch, the VCO is configured as an LC voltage-controlled oscillator, the LC voltage-controlled oscillator comprises a capacitive switch, the capacitive switch comprises an I/O device, a first capacitor C1 and a second capacitor C2, the first capacitor C1, the I/O device and the second capacitor C2 are sequentially connected, and a first control voltage P-Bank is input into the I/O device after being boosted by a level conversion module, so that impedance is reduced and the voltage is not excessively increased.
Preferably, the LC voltage-controlled oscillator further includes an inductor L, a third variable capacitor C3, a fourth variable capacitor C4, a third MOS transistor M3, a fourth MOS transistor M4, and a fifth MOS transistor M5, wherein a first end of the inductor L is connected to the operating voltage VDD, a second end of the inductor L is connected to a first end of the first capacitor C1, a first end of the third variable capacitor C3, a drain electrode of the third MOS transistor M3, and a gate electrode of the fourth MOS transistor M4, and a third end of the inductor L is connected to a first end of the second capacitor C2The second end of the second variable capacitor C4, the grid electrode of the third MOS tube M3 and the drain electrode of the fourth MOS tube M4; the second end of the third variable capacitor C3 and the first end of the fourth variable capacitor C4 are connected with the second control voltage V ctrl The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the fifth MOS tube M5 is connected with the source electrodes of the third MOS tube M3 and the fourth MOS tube M4, and the source electrode of the fifth MOS tube M5 is grounded.
Based on this, the present embodiment provides a high performance phase locked loop, including the above-mentioned circuit for solving the overvoltage of the VCO capacitance switch.
In addition, the embodiment also provides a clock chip which comprises the high-performance phase-locked loop.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.

Claims (10)

1. A method for solving overvoltage of a VCO capacitance switch, characterized in that the VCO, i.e. a voltage controlled oscillator, is configured as an LC voltage controlled oscillator, the LC voltage controlled oscillator comprises a capacitance switch, the capacitance switch comprises a first MOS transistor (M1), a first capacitor (C1) and a second capacitor (C2), a source electrode of the first MOS transistor (M1) is connected to the first capacitor (C1), a drain electrode is connected to the second capacitor (C2), and a gate electrode is connected to a first control voltage P-Bank;
the method for solving the overvoltage of the VCO capacitive switch comprises the following steps: a second MOS tube (M2) is additionally arranged between the first capacitor (C1) and the second capacitor (C2), the drain electrode of the second MOS tube (M2) is connected with the second capacitor (C2), the grid electrode is connected with the first control voltage P-Bank, and the source electrode is connected with the drain electrode of the first MOS tube (M1) and the working voltage VDD, so that the voltage difference from the grid electrode to the source electrode of the first MOS tube (M1) and the second MOS tube (M2) to the drain electrode does not exceed the working voltage VDD, namely no overvoltage.
2. The utility model provides a solve circuit of VCO capacitance switch excessive pressure, its characterized in that, VCO is configured as LC voltage-controlled oscillator, LC voltage-controlled oscillator includes capacitance switch, capacitance switch includes first MOS pipe (M1), second MOS pipe (M2), first electric capacity (C1) and second electric capacity (C2), first electric capacity (C1) is connected to the source of first MOS pipe (M1), second electric capacity (C2) is connected to the drain electrode of second MOS pipe (M2), first control voltage P-Bank is all connected to the grid of first MOS pipe (M1) and second MOS pipe (M2), operating voltage VDD is all connected to the source of drain electrode of first MOS pipe (M1) and second MOS pipe (M2), makes the voltage difference between grid to source and drain electrode of first MOS pipe (M1) and second MOS pipe (M2) do not exceed operating voltage VDD promptly.
3. The circuit for solving the overvoltage of the VCO capacitance switch according to claim 2, characterized in that the LC voltage controlled oscillator further comprises an inductor (L), a third variable capacitor (C3), a fourth variable capacitor (C4), a third MOS transistor (M3), a fourth MOS transistor (M4) and a fifth MOS transistor (M5), wherein a first end of the inductor (L) is connected to the operating voltage VDD, a second end of the inductor (L) is connected to a first end of the first capacitor (C1), a first end of the third variable capacitor (C3), a drain electrode of the third MOS transistor (M3) and a gate electrode of the fourth MOS transistor (M4), and a third end of the inductor (L) is connected to a second end of the second capacitor (C2), a second end of the fourth variable capacitor (C4), a gate electrode of the third MOS transistor (M3) and a drain electrode of the fourth MOS transistor (M4); the second end of the third variable capacitor (C3) and the first end of the fourth variable capacitor (C4) are connected with a second control voltage V ctrl The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the fifth MOS tube (M5) is connected with the source electrodes of the third MOS tube (M3) and the fourth MOS tube (M4), and the source electrode of the fifth MOS tube (M5) is grounded.
4. A high performance phase locked loop comprising a circuit to address VCO capacitance switching overvoltage as claimed in claim 2 or 3.
5. A clock chip comprising the high performance phase locked loop of claim 4.
6. A method for solving overvoltage of a VCO capacitance switch, characterized in that the VCO, i.e. a voltage controlled oscillator, is configured as an LC voltage controlled oscillator, the LC voltage controlled oscillator comprises a capacitance switch, the capacitance switch comprises a first MOS transistor (M1), a first capacitor (C1) and a second capacitor (C2), a source electrode of the first MOS transistor (M1) is connected to the first capacitor (C1), a drain electrode is connected to the second capacitor (C2), and a gate electrode is connected to a first control voltage P-Bank;
the method for solving the overvoltage of the VCO capacitive switch comprises the following steps: and replacing the first MOS tube (M1) with an I/O device, and boosting the first control voltage P-Bank to the working voltage of the I/O device through a level conversion module, so that the impedance is reduced and the voltage is not excessively high.
7. A circuit for solving overvoltage of a VCO capacitance switch is characterized in that the VCO, namely a voltage-controlled oscillator, is configured as an LC voltage-controlled oscillator, the LC voltage-controlled oscillator comprises a capacitance switch, the capacitance switch comprises an I/O device, a first capacitor (C1) and a second capacitor (C2), the first capacitor (C1), the I/O device and the second capacitor (C2) are sequentially connected, and a first control voltage P-Bank is input into the I/O device after being boosted by a level conversion module, so that impedance is reduced and the voltage is not excessively increased.
8. The circuit for solving the overvoltage of the VCO capacitance switch according to claim 7, wherein the LC voltage controlled oscillator further comprises an inductor (L), a third variable capacitor (C3), a fourth variable capacitor (C4), a third MOS transistor (M3), a fourth MOS transistor (M4) and a fifth MOS transistor (M5), a first end of the inductor (L) is connected to the operating voltage VDD, a second end of the inductor (L) is connected to a first end of the first capacitor (C1), a first end of the third variable capacitor (C3), a drain of the third MOS transistor (M3) and a gate of the fourth MOS transistor (M4), and a third end of the inductor (L) is connected to a second end of the second capacitor (C2), a second end of the fourth variable capacitor (C4), a gate of the third MOS transistor (M3) and a drain of the fourth MOS transistor (M4); the second end of the third variable capacitor (C3) and the first end of the fourth variable capacitor (C4) are connected with a second control voltage V ctrl The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the fifth MOS tube (M5) is connected with the third MOS tube (M)3) And the source electrode of the fourth MOS tube (M4), and the source electrode of the fifth MOS tube (M5) is grounded.
9. A high performance phase locked loop comprising a circuit to address VCO capacitance switching overvoltage as claimed in claim 7 or 8.
10. A clock chip comprising the high performance phase locked loop of claim 9.
CN202310651421.XA 2023-05-31 2023-05-31 Method, circuit, phase-locked loop and chip for solving overvoltage of VCO capacitance switch Pending CN116633271A (en)

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