CN116631328A - Pixel circuit, driving method thereof and display panel - Google Patents

Abstract

A pixel circuit, comprising: a data writing sub-circuit, a driving sub-circuit, a light emission control sub-circuit, a storage sub-circuit, and a compensation sub-circuit. The data writing sub-circuit is configured to supply a data signal transmitted by the data line to the first node under control of the first scan line. The storage subcircuit is configured to store the data signal. The light emission control sub-circuit is configured to supply the first power signal transmitted by the first power line to the second node under the control of the light emission control line during a display period of one frame. The second node is also electrically connected to a first signal line configured to supply a third power signal to the second node during an idle period of one frame. The drive sub-circuit is configured to provide a drive current to the third node under control of the first node using the first power signal or the third power signal provided by the second node. The compensation sub-circuit is configured to collect the driving current of the third node under the control of the second scan line to realize external compensation.

Description

Pixel circuit, driving method thereof and display panel

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display panel.

Background

In the display field, an Organic Light-Emitting Diode (OLED) has the characteristics of self-luminescence, high contrast, low energy consumption, wide viewing angle, high response speed, wide application range, wide application temperature range and the like, and has wide development prospect.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the disclosure provides a pixel circuit, a driving method thereof and a display panel.

In one aspect, embodiments of the present disclosure provide a pixel circuit for driving a light emitting element to emit light. The pixel circuit includes: a data writing sub-circuit, a driving sub-circuit, a light emission control sub-circuit, a storage sub-circuit, and a compensation sub-circuit. The data writing sub-circuit is electrically connected with the data line, the first scanning line and the first node and is configured to provide the data signal transmitted by the data line to the first node under the control of the first scanning line. The storage sub-circuit is electrically connected to the first node and the third node and configured to store the data signal. The light-emitting control sub-circuit is electrically connected with the first power line, the light-emitting control line and the second node and is configured to provide a first power signal transmitted by the first power line to the second node under the control of the light-emitting control line in a display period of one frame. The second node is also electrically connected to a first signal line configured to provide a third power signal to the second node during an idle period of one frame. The driving sub-circuit is electrically connected with the first node, the second node and the third node, and is configured to provide driving current for the third node by using the first power signal or the third power signal provided by the second node under the control of the first node. The third node is electrically connected to the light emitting element. The compensation sub-circuit is electrically connected with the sensing line, the second scanning line and the third node and is configured to collect the driving current of the third node under the control of the second scanning line so as to realize external compensation.

In some exemplary embodiments, the first signal line is configured to provide a third power signal to the second node during an idle period of a random one frame.

In some exemplary embodiments, the third power supply signal is the same as the first power supply signal.

In some exemplary embodiments, the light emission control line is configured to provide a pulse width modulation signal during a display period of one frame.

In some exemplary embodiments, the data writing sub-circuit includes: scanning the transistor. The control electrode of the scanning transistor is electrically connected with the first scanning line, the first electrode of the scanning transistor is electrically connected with the data line, and the second electrode of the scanning transistor is electrically connected with the first node.

In some exemplary embodiments, the driving sub-circuit includes: and a driving transistor. The control electrode of the driving transistor is electrically connected with the first node, the first electrode of the driving transistor is electrically connected with the second node, and the second electrode of the driving transistor is electrically connected with the third node.

In some exemplary embodiments, the memory sub-circuit includes: and a storage capacitor. The first polar plate of the storage capacitor is electrically connected with the first node, and the second polar plate of the storage capacitor is electrically connected with the third node.

In some exemplary embodiments, the compensation sub-circuit includes: a sense transistor. The control electrode of the sensing transistor is electrically connected with the second scanning line, the first electrode of the sensing transistor is electrically connected with the sensing line, and the second electrode of the sensing transistor is electrically connected with the third node.

In some exemplary embodiments, the light emission control sub-circuit includes: a light emission control transistor. The control electrode of the light-emitting control transistor is electrically connected with the light-emitting control line, the first electrode of the light-emitting control transistor is electrically connected with the first power line, and the second electrode of the light-emitting control transistor is electrically connected with the second node.

In another aspect, an embodiment of the present disclosure provides a driving method of a pixel circuit, which is applied to the pixel circuit as described above, the driving method including: in the display stage of each frame, a data writing sub-circuit provides data signals transmitted by a data line to a first node under the control of a first scanning line, a storage sub-circuit stores the data signals, a light-emitting control sub-circuit provides a first power supply signal to a second node under the control of a light-emitting control line, and a driving sub-circuit provides driving current to a third node under the control of the first node; in the idle stage of one frame, the first signal line provides a third power supply signal to the second node, and the compensation sub-circuit collects the driving current of the third node under the control of the second scanning line so as to realize external compensation.

In another aspect, embodiments of the present disclosure provide a display panel including: a plurality of pixel circuits, a plurality of compensation control circuits, and a plurality of first signal lines as described above; at least one first signal line is electrically connected to the plurality of pixel circuits. The compensation control circuit is electrically connected with the first control line, the third power line and the first signal line and is configured to provide the third power signal transmitted by the third power line to the first signal line under the control of the first control line.

In some exemplary embodiments, one first signal line is electrically connected to one row of pixel circuits, and a plurality of compensation control circuits are electrically connected to a plurality of first signal lines in one-to-one correspondence.

In some exemplary embodiments, the compensation control circuit includes: a first control transistor. The control electrode of the first control transistor is electrically connected with the first control line, the first electrode of the first control transistor is electrically connected with the third power line, and the second electrode of the first control transistor is electrically connected with the first signal line.

In some exemplary embodiments, a first control line electrically connected to the compensation control circuit electrically connected to one first signal line is electrically connected to a first scan line or a second scan line electrically connected to the pixel circuit electrically connected to the first signal line.

In some exemplary embodiments, the display panel further includes: a plurality of cascaded scan driving circuits; and a scanning driving circuit of any stage configured to supply a scanning driving signal to one row of pixel circuits through the first scanning line in a display period of each frame, and to supply a sensing driving signal to the one row of pixel circuits through the second scanning line in an idle period of a random one frame.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, and not constitute a limitation to the technical aspects of the present disclosure. The shape and size of one or more of the components in the drawings do not reflect true proportions, and are intended to illustrate the disclosure only.

FIG. 1 is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure;

FIG. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

FIG. 3 is a schematic structural diagram of a display panel according to at least one embodiment of the present disclosure;

FIG. 4 is a schematic diagram illustrating connection of a scan driving circuit, a compensation control circuit and a pixel circuit of a display panel according to at least one embodiment of the present disclosure;

FIG. 5 is an equivalent circuit diagram of a compensation control circuit according to at least one embodiment of the present disclosure;

FIG. 6 is a timing diagram illustrating operation of a pixel circuit according to at least one embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a scan driving circuit of a display panel according to at least one embodiment of the present disclosure;

fig. 8 is an equivalent circuit diagram of a scan driving circuit of a display panel according to at least one embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Embodiments may be implemented in a number of different forms. One of ordinary skill in the art will readily recognize the fact that the patterns and matters may be changed into one or more forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict.

In the drawings, the size of one or more constituent elements, thicknesses of layers or regions may be exaggerated for clarity. Accordingly, one aspect of the present disclosure is not necessarily limited to this dimension, and the shapes and sizes of the various components in the drawings do not reflect actual proportions. Further, the drawings schematically show ideal examples, and one mode of the present disclosure is not limited to the shapes or numerical values shown in the drawings, and the like.

The ordinal terms such as "first," "second," "third," and the like in the present disclosure are provided to avoid intermixing of constituent elements, and are not intended to be limiting in number. The term "plurality" in this disclosure means two or more in number.

In the present disclosure, for convenience, terms such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe positional relationships of the constituent elements with reference to the drawings, only for convenience in describing the present specification and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this disclosure, the terms "mounted," "connected," and "connected" are to be construed broadly, unless otherwise specifically indicated and defined. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The meaning of the above terms in the present disclosure can be understood by one of ordinary skill in the art as appropriate. Wherein "electrically connected" includes the case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit an electric signal between the connected constituent elements. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having one or more functions, and the like.

In this disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and a current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region through which current mainly flows.

In this disclosure, to distinguish between two electrodes of a transistor except a gate electrode, one of the electrodes is referred to as a first electrode, the other electrode is referred to as a second electrode, the first electrode may be a source electrode or a drain electrode, the second electrode may be a drain electrode or a source electrode, and in addition, the gate electrode of the transistor is referred to as a control electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Thus, in this disclosure, the "source electrode" and the "drain electrode" may be interchanged.

In the present disclosure, "parallel" refers to a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and thus, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus includes a state in which the angle is 85 ° or more and 95 ° or less.

In this disclosure, "film" and "layer" may be interchanged. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The terms "about" and "approximately" in this disclosure refer to situations where the limits are not strictly defined, allowing for process and measurement error ranges.

Fig. 1 is a schematic diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some exemplary implementations, as shown in fig. 1, the pixel circuit of the present embodiment may include: a driving sub-circuit 101, a data writing sub-circuit 102, a memory sub-circuit 103, a compensation sub-circuit 104, and a light emission control sub-circuit 105. The data writing sub-circuit 102 may be electrically connected to the data line DL, the first scan line GL1, and the first node N1, and configured to provide the data signal transmitted by the data line DL to the first node N1 under the control of the first scan line GL 1. The storage sub-circuit 103 may be electrically connected to the first node N1 and the third node N3, and configured to store a data signal. The light emission control sub-circuit 105 may be electrically connected to the first power line VDD, the light emission control line EML, and the second node N2, and configured to supply the first power signal transmitted by the first power line VDD to the second node N2 under the control of the light emission control line EML during a display period of one frame. The second node N2 may also be electrically connected to the first signal line L1. The first signal line L1 is configured to supply the third power signal to the second node N2 during an idle period of one frame. The driving sub-circuit 101 may be electrically connected to the first node N1, the second node N2, and the third node N3, and configured to supply the driving current to the third node N3 using the first power signal or the third power signal supplied from the second node N2 under the control of the first node N1. The compensation sub-circuit 104 may be electrically connected to the sensing line SEL, the second scanning line GL2, and the third node N3, and configured to collect a driving current of the third node N3 under the control of the second scanning line GL2 to implement external compensation. The first electrode of the light emitting element EL is electrically connected to the third node N3, and the second electrode is electrically connected to the second power supply line VSS. In some examples, the first electrode of the light emitting element EL may be an anode and the second electrode may be a cathode. However, the present embodiment is not limited thereto.

In the embodiments of the present disclosure, a "frame" may include a display period and an idle (Blanking) period that sequentially occur, for example, in the display period, the gate driving circuit outputs a display driving signal that may drive the display panel to complete scanning display of a complete one image from a first line to a last line, and in the idle period, the gate driving circuit outputs an idle output signal that may be used to drive a sensing transistor in a certain line of subpixels in the display panel to complete external compensation of the line of subpixels.

In some example embodiments, the first signal line may be configured to provide the third power signal to the second node during an idle period of a random one frame. In other words, the present embodiment may employ a random compensation method. However, the present embodiment is not limited thereto. In other examples, this embodiment may employ a line-by-line sequential compensation approach.

In the present exemplary embodiment, external compensation is performed by setting a compensation sub-circuit to collect a driving current when compensating for a sub-pixel in an OLED display panel. In some examples, the gate driving circuit, which may be constituted by the shift register unit, supplies a scan driving signal for the scan transistor and a sense driving signal for the sense transistor to the sub-pixels in the display panel, respectively, when external compensation is performed, wherein the sense driving signals supplied by the gate driving circuit may be scanned sequentially row by row or may be scanned randomly. For example, the progressive sequential scanning may be to output a sensing driving signal for a first row of subpixels of the display panel during an idle period of a first frame, output a sensing driving signal for a second row of subpixels of the display panel during an idle period of a second frame, and so on to complete progressive sequential compensation of the display panel. However, the external compensation scheme of the row-by-row sequence may cause a problem of poor display, for example, there is one scan line moving row by row in the process of performing the scanning display of a plurality of frames, or the difference of time points of external compensation may cause a large difference in brightness of different regions of the display panel, thereby causing uneven brightness of different regions of the display panel. In this example, the random compensation refers to an external compensation method different from the progressive sequential compensation, and the sensing driving signal corresponding to the sub-pixels of any one row in the display panel may be randomly output in an idle period of a certain frame. Random compensation may improve display failures that may occur with progressive sequential scanning. In some examples, the scan drive signal may be transmitted by a first scan line and the sense drive signal may be transmitted by a second scan line.

The pixel circuit provided by the present exemplary embodiment can realize random compensation. When the compensation sub-circuit performs random sensing in an idle period, the first signal line can provide a third power supply signal to the second node so as to support the compensation sub-circuit to collect driving current and realize random external compensation.

In some exemplary embodiments, the third power supply signal may be the same as the first power supply signal. For example, the first power supply signal and the third power supply signal may be high level signals having the same voltage value. However, the present embodiment is not limited thereto. For example, the voltage value of the first power supply signal and the voltage value of the third power supply signal may be different.

In some exemplary embodiments, the light emission control line is configured to provide a pulse width modulation signal (PWM, pulse Width Modulation) during a display phase of one frame. In this example, pulse dimming can be achieved by providing a pulse width modulation signal through the light emission control line, thereby realizing a pixel circuit compensating for compatible pulse dimming.

In some exemplary embodiments, the first power line VDD may continuously supply the first power signal of a high level, and the second power line VSS may continuously supply the second power signal of a low level.

Fig. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 2, the data writing sub-circuit 102 may include: the transistor T1 is scanned. The compensation subcircuit 104 may include a sense transistor T2. The driving sub-circuit 101 may include: and a driving transistor T3. The emission control sub-circuit 105 may include an emission control transistor T4. The memory sub-circuit 103 may include: and a storage capacitor Cst.

As shown in fig. 2, the control electrode of the driving transistor T3 is electrically connected to the first node N1, the first electrode of the driving transistor T3 is electrically connected to the second node N2, and the second electrode of the driving transistor T3 is electrically connected to the third node N3. The control electrode of the scan transistor T1 is electrically connected to the first scan line GL1, the first electrode of the scan transistor T1 is electrically connected to the data line DL, and the second electrode of the scan transistor T1 is electrically connected to the first node N1. The first electrode plate of the storage capacitor Cst is electrically connected with the first node N1, and the second electrode plate of the storage capacitor Cst is electrically connected with the third node N3. The control electrode of the sensing transistor T2 is electrically connected to the second scan line GL2, the first electrode of the sensing transistor T2 is electrically connected to the sensing line SEL, and the second electrode of the sensing transistor T2 is electrically connected to the third node N3. The control electrode of the emission control transistor T4 is electrically connected to the emission control line EML, the first electrode of the emission control transistor T4 is electrically connected to the first power line VDD, and the second electrode of the emission control transistor T4 is electrically connected to the second node N2. The first electrode of the light emitting element EL is electrically connected to the third node N3, and the second electrode of the light emitting element EL is electrically connected to the second power supply line VSS. The first signal line L1 is electrically connected to the second node N2.

In this example, the first node N1 is a connection point of the scan transistor T1, the storage capacitor Cst, and the driving transistor T3. The second node N2 is a connection point of the driving transistor T3, the light emission control transistor T4, and the first signal line L1. The third node N3 is a connection point of the driving transistor T3, the storage capacitor Cst, the sensing transistor T2, and the light emitting element EL.

In some exemplary embodiments, the plurality of transistors of the pixel circuit may be N-type transistors or may be P-type transistors. The same type of transistor is adopted in the pixel circuit, so that the process flow can be simplified, the process difficulty of the display substrate is reduced, and the yield of products is improved. In some possible implementations, the plurality of transistors in the pixel circuit may include a P-type transistor and an N-type transistor. The present embodiment is not limited thereto.

In some exemplary embodiments, the transistors T1 to T4 in the pixel circuit may employ low temperature polysilicon thin film transistors, or may employ oxide thin film transistors, or may employ low temperature polysilicon thin film transistors and oxide thin film transistors. The active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (LTPS, low Temperature Poly-Silicon), and the active layer of the Oxide thin film transistor adopts Oxide semiconductor (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charge and the like, the oxide thin film transistor has the advantages of low leakage current and the like, the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor are integrated on one display substrate to form a low-temperature polycrystalline oxide (LTPO, low Temperature Polycrystalline Oxide) display substrate, the advantages of the low-temperature polycrystalline silicon thin film transistor and the oxide thin film transistor can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

Fig. 3 is a schematic diagram of a display panel according to at least one embodiment of the disclosure. In some exemplary embodiments, as shown in fig. 3, the display panel may include: a timing controller 11, a data driver 12, a gate driving circuit, and a sub-pixel array 15. The gate driving circuit may include, for example, a first driving circuit 13 and a second driving circuit 14. The sub-pixel array 15 is located in the display area and may include a plurality of sub-pixels PX arranged in a regular arrangement. Each sub-pixel PX may include a pixel circuit and a light emitting element connected to the pixel circuit. The gate driving circuit may be located at a peripheral region of the periphery of the display region. The first driving circuit 13 may include a plurality of scan driving circuits and a plurality of compensation control circuits in cascade. The scan driving circuit may be configured to supply the scan driving signal to the sub-pixels PX along the first scan line or to supply the sensing driving signal to the sub-pixels PX along the second scan line. The compensation control circuit is electrically connected with the scanning driving circuit and the first signal line. The compensation control circuit is configured to supply a first power supply signal to the first signal line under control of an output signal of the scan drive circuit. The plurality of first signal lines L11 to L1e may be electrically connected to pixel circuits of the plurality of rows of sub-pixels PX in one-to-one correspondence. I.e., one first signal line is electrically connected to the pixel circuits of one row of sub-pixels PX. The second driving circuit 14 may include a plurality of cascaded light emitting driving circuits configured to supply light emitting control signals to the sub-pixels PX along the light emitting control lines. The data driver 12 is configured to supply data signals to the sub-pixels PX along the data lines. The timing controller 11 is configured to control the first driving circuit 13, the second driving circuit 14, and the data driver 12.

In some exemplary embodiments, the timing controller 11 may provide gray values and control signals suitable for the specification of the data driver 12 to the data driver 12; the timing controller 11 may supply a clock signal, a start signal, etc. suitable for the specification of the first driving circuit 13 to the first driving circuit 13; the timing controller 11 may supply a clock signal, a start signal, etc. suitable for the specification of the second driving circuit 14 to the second driving circuit 14. The data driver 12 may generate data voltages to be supplied to the plurality of data lines DL1 to DLr using the gray values and the control signals received from the timing controller 11. For example, the data driver 12 may sample the gray value with a clock signal and apply the data signal corresponding to the gray value to the data lines DL1 to DLr in units of sub-pixel rows. The first driving circuit 13 may generate scan driving signals to be supplied to the plurality of first scan lines GL11 to GL1m by a clock signal, a start signal, or the like received from the timing controller 11. For example, the first driving circuit 13 may sequentially supply the scan driving signal having the on-level pulse to the first scan line. In some examples, the first driving circuit 13 may include a plurality of scan driving circuits in cascade, and the scan driving signals may be generated in such a manner that the scan initiation signals provided in the form of the on-level pulses are sequentially transferred to the next stage circuit under the control of the clock signal. The second driving circuit 14 may generate the light emission control signals to be supplied to the light emission control lines EML1 to EMLo by a clock signal, a start signal, or the like received from the timing controller 11. For example, the second driving circuit 14 may sequentially supply the light emission control signal having the off-level pulse to the light emission control lines. The second driving circuit 14 may include a plurality of cascaded light-emitting driving circuits to generate the light-emission control signal in such a manner that the light-emission initial signal provided in the form of the off-level pulse is sequentially transmitted to the next stage circuit under the control of the clock signal. Wherein e, r, m and o are natural numbers.

In some exemplary embodiments, the data driver 12 may be provided on a separate chip or a printed circuit board to be connected to the sub-pixels through signal access pins provided at bonding regions of the substrate base. For example, the data driver 12 may be formed on a substrate using a chip on glass, a chip on plastic, a chip on film, or the like. The timing controller 11 may be provided separately from the data driver 12 or integrally with the data driver 12. However, the present embodiment is not limited thereto.

In some exemplary embodiments, the first driving circuit 13 and the second driving circuit 14 may be directly disposed on the substrate base. The first driving circuit 13 and the second driving circuit 14 may be formed together with the sub-pixels in a process of forming the pixel circuits of the sub-pixels. However, the present embodiment is not limited thereto.

Fig. 4 is a schematic connection diagram of a scan driving circuit, a compensation control circuit and a pixel circuit of a display panel according to at least one embodiment of the present disclosure. In fig. 4, a one-stage scanning driving circuit 23, a compensation control circuit 22, and a pixel circuit 21 are illustrated as an example.

In some exemplary embodiments, as shown in fig. 4, the compensation control circuit 22 may be electrically connected to the scan driving circuit 23, the third power line V3, and the first signal line L1, and configured to supply the third power signal transmitted by the third power line V3 to the first signal line L1 under the control of the output signal of the scan driving circuit 23. The first signal line L1 may extend in the sub-pixel row direction and be electrically connected to the second node N2 of the one row of pixel circuits 21. The scan driving circuit 23 may be electrically connected to the first scan line GL1 and the second scan line GL2, and configured to supply a scan driving signal to the scan transistor T1 through the first scan line GL1 and a sense driving signal to the sense transistor T2 through the second scan line GL 2. In some examples, the third power line V3 is electrically connected to the first power line VDD, providing the same signal. However, the present embodiment is not limited thereto. For example, the third power supply signal supplied from the third power supply line V3 is different from the first power supply signal supplied from the first power supply line VDD.

Fig. 5 is an equivalent circuit diagram of a compensation control circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 5, the compensation control circuit 22 may include: a first control transistor T5. The control electrode of the first control transistor T5 is electrically connected to the first control line CNL, the first electrode of the first control transistor T5 is electrically connected to the third power line V3, and the second electrode of the first control transistor T5 is electrically connected to the first signal line L1. In some examples, the first scan line GL1, the second scan line GL2, and the first control line CNL may be electrically connected, i.e., receive the same signal. However, the present embodiment is not limited thereto.

Fig. 5 shows an exemplary structure of the compensation control circuit, and those skilled in the art will readily understand that the implementation of the compensation control circuit is not limited thereto, as long as the functions thereof can be implemented.

Fig. 6 is a timing diagram illustrating operation of a pixel circuit according to at least one embodiment of the present disclosure. The transistors of the pixel circuit and the compensation control circuit provided in fig. 5 are each an N-type thin film transistor. In this example, the sub-pixel random compensation is described as an example. As shown in fig. 5, the pixel circuit 21 according to the present example may include: 4 transistors (i.e., transistors T1 to T4) and 1 capacitor unit (i.e., storage capacitor Cst). The pixel circuit of this example is electrically connected to 6 input terminals (i.e., the data line DL, the first scan line GL1, the second scan line GL2, the emission control line EML, the sensing line SEL, the first signal line L1) and 3 power supply terminals (i.e., the first power supply line VDD, the second power supply line VSS, and the third power supply line V3). The compensation control circuit 22 to which the present example relates may include: 1 transistor (i.e., transistor T5). The first power line VDD and the third power line V3 may continuously supply a high level signal, and the second power line VSS may continuously supply a low level signal.

In some examples, as shown in fig. 6, the compensation operation for one row of sub-pixels may be completed in an idle period between every two frame display periods, for example, detection of the threshold voltage Vth and mobility of the driving transistor of one row of sub-pixels is completed to obtain a compensation data signal using the detected data in the display period to complete the display. As shown in fig. 6, the i+1 th row of sub-pixels are randomly compensated for an idle period B (k) between the k-th frame display period D (k) and the k+1-th frame display period D (k+1), and the i-th row of sub-pixels are randomly compensated for an idle period B (k+1). Wherein i is a positive integer.

The operation of the pixel circuit of the i-th row of sub-pixels will be described below as an example. As shown in fig. 6, the display period D (k) at the ith row of subpixels may include: a data writing stage and a light emitting stage.

In the data writing stage, the first and second scan lines GL1 (i) and GL2 (i) supply high-level signals, and the scan and sense transistors T1 and T2 are turned on. The scan transistor T1 is turned on, writes a data signal supplied from the data line DL into the control electrode (i.e., the first node N1) of the driving transistor T3, and charges the storage capacitor Cst such that the storage capacitor Cst stores the written data signal. The sensing transistor T2 is turned on, and the reset voltage supplied from the sensing line SEL may be supplied to the first electrode of the light emitting element EL to reset the first electrode of the light emitting element EL. The emission control line EML (i) supplies a low level signal, and the emission control transistor T4 is turned off. The first control line CNL (i) supplies a high level signal, and the first control transistor T5 of the compensation control circuit connected to the pixel circuit of the i-th row is turned on to supply a third power supply signal to the first signal line L (i). At this stage, the light emitting element EL does not emit light.

In the light emitting period, the first and second scan lines GL1 (i) and GL2 (i) supply low-level signals, and the scan and sense transistors T1 and T2 are turned off. The emission control line EML (i) supplies a high level signal, and the emission control transistor T4 is turned on. The high-level first power signal supplied from the first power line VDD is transmitted to the first electrode of the driving transistor T3, and the driving transistor T3 supplies a driving current to the light emitting element EL to drive the light emitting element EL to emit light. In this example, the emission control line EML (i) supplies a pulse width modulation signal, and the on state of the emission control transistor T4 may be adjusted according to the duty ratio of the pulse width modulation signal, thereby controlling the emission period of the light emitting element EL in the emission phase. For example, in the light emitting stage, the light emitting element EL may be controlled to emit light when the pulse width modulation signal is at a high level, and the light emitting element EL may be controlled not to emit light when the pulse width modulation signal is at a low level, thereby realizing pulse dimming. In some examples, during the gray scale adjustment of the light emitting element EL, the duty cycle of the pulse width modulation signal may correspond to a gray scale, for example, the highest gray scale corresponds to a duty cycle of 100% and the lowest gray scale corresponds to a duty cycle of 0. The duty cycle is the proportion of the high level duration in the total duration of the pulse cycle in one pulse cycle. In this stage, the first control line CNL (i) supplies a low level signal, and the first control transistor T5 is turned off. Since the first signal line L1 (i) is electrically connected to the second node N2 of the i-th row pixel circuit, the voltage of the first signal line L1 (i) may be changed according to the control of the emission control line EML (i). In this stage, the first signal line L1 (i) may output a pulse width modulation signal under the control of the emission control line EML (i).

In some examples, as shown in fig. 6, in the idle period B (k+1), the first control line CNL (i), the first scan line GL1 (i), and the second scan line GL2 (i) provide high level signals, and the scan transistor T1, the sense transistor T2, and the first control transistor T5 are turned on. The scan transistor T1 is turned on, and the test data voltage supplied from the data line DL is written into the control electrode (i.e., the first node N1) of the driving transistor T3. The first control transistor T5 is turned on, and supplies the third power supply signal to the first signal line L1 (i). The driving transistor T3 may supply a driving current to the light emitting element EL using the third power supply signal. The sensing transistor T2 is turned on, and an electrical signal at the second pole (i.e., the third node N3) of the driving transistor T3 is read through the sensing transistor T2 and output through the sensing line SEL. For example, the mobility of the driving transistor T3 may be compensated by an output electric signal by an external circuit.

In this example, during an idle period of a random frame, under the control of the first scan line and the second scan line, when the sense transistor collects the driving current of the third node, the first signal line may provide the third power signal to the second node to ensure the generation of the driving current, supporting the implementation of random compensation. In the display period of one frame, the second node may provide a pulse width modulation signal under the control of the light emission control line, thereby realizing pulse dimming. Therefore, the pixel circuit provided by the embodiment can realize external random compensation and is compatible with pulse dimming, and is simple and reliable.

In some exemplary embodiments, the scan driving circuit may be utilized to provide output signals to the first scan line, the second scan line, and the first control line to ensure random compensation is achieved.

Fig. 7 is a schematic diagram of a scan driving circuit of a display panel according to at least one embodiment of the disclosure. In some exemplary implementations, as shown in fig. 7, the scan driving circuit of the present embodiment may include: a sense input sub-circuit 231, a display input sub-circuit 232, a reset sub-circuit 233, a control sub-circuit 234, and an output sub-circuit 235. The sensing input sub-circuit 231 is configured to control the potential of the first control node Q under the control of the selection control signal terminal OE, the second input signal terminal STU2, and the first clock signal terminal CLKA. The display input sub-circuit 232 is configured to supply the third voltage signal transferred by the third voltage line VGH1 to the first control node Q under the control of the first input signal terminal STU 1. The reset sub-circuit 233 is configured to reset the first control node Q under the control of the global reset signal terminal TRST or the display reset signal terminal STD, and is also configured to reset the fifth control node N under the control of the second control node QA or the third control node QB. The control sub-circuit 234 is configured to control the potentials of the first control node Q, the second control node QA, and the third control node QB. The output sub-circuit 235 is configured to output a shift signal from the shift output terminal CR, a first output signal from the first output terminal OUTA, and a second output signal from the second output terminal OUTB under the control of the first control node Q, the second control node QA, and the third control node QB.

In the display period of one frame, the shift signal output from the output sub-circuit 235 through the shift output terminal CR may be supplied to the next stage scan driving circuit as the first input signal supplied to the first input terminal, thereby completing the line-by-line shift of the display scan. The first output signal output through the first output terminal OUTA and the second output signal output through the second output terminal OUTB may be configured to drive a certain row of subpixels in the display panel. In some examples, the second output terminal OUTB of the scan driving circuit may be electrically connected to the first scan line, the second scan line, and the first control line. However, the present embodiment is not limited thereto.

Fig. 8 is an equivalent circuit diagram of a scan driving circuit of a display panel according to at least one embodiment of the present disclosure. In some exemplary embodiments, as shown in fig. 8, the sense input subcircuit 231 may include: a first transistor M1, a second transistor M2, a third transistor M3, and a first capacitor C1. The display input subcircuit 232 may include: and a fourth transistor M4. The reset sub-circuit 233 may include: a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The control subcircuit 234 may include: the ninth transistor M9 to the fifteenth transistor M15. The output subcircuit 235 may include: the sixteenth transistor M16 to the twenty-fourth transistor M24, the second capacitor C2, and the third capacitor C3.

In some examples, as shown in fig. 8, the control electrode of the first transistor M1 is electrically connected to the selection control signal terminal OE, the first electrode of the first transistor M1 is electrically connected to the second input signal terminal STU2, and the second electrode of the first transistor M1 is electrically connected to the fourth control node H. The level (e.g., high level) of the fourth control node H may be maintained from the display period of one frame to the idle period of the frame. The control electrode of the second transistor M2 is electrically connected to the fourth control node H, the first electrode of the second transistor M2 is electrically connected to the first clock signal line CLKA, and the second electrode of the second transistor M2 is electrically connected to the fifth control node N. For example, in an idle period of one frame, when the first clock signal supplied from the first clock signal line CLKA is at a high level, the second transistor M2 may transmit a high level signal to the fifth control node N, thereby causing the fifth control node N to become at a high level. The control electrode of the third transistor M3 is electrically connected to the fifth control node N, the first electrode of the third transistor M3 is electrically connected to the first voltage line VGL1, and the second electrode of the third transistor M3 is electrically connected to the first control node Q. The first polar plate of the first capacitor C1 is electrically connected with the fourth control node H, and the second polar plate is electrically connected with the fifth control node N. The control electrode of the fourth transistor M4 is electrically connected to the first input signal terminal STU1, the first electrode of the fourth transistor M4 is electrically connected to the third voltage line VGH1, and the second electrode of the fourth transistor M4 is electrically connected to the first control node Q.

In some examples, as shown in fig. 8, the control electrode of the fifth transistor M5 is electrically connected to the second control node QA, the first electrode of the fifth transistor M5 is electrically connected to the fifth control node N, and the second electrode of the fifth transistor M5 is electrically connected to the first voltage line VGL 1. The fifth transistor M5 is configured to reset the fifth control node N under the control of the second control node QA. The control electrode of the sixth transistor M6 is electrically connected to the third control node QB, the first electrode of the sixth transistor M6 is electrically connected to the fifth control node N, and the second electrode of the sixth transistor M6 is electrically connected to the first voltage line VGL 1. The sixth transistor M6 is configured to reset the fifth control node N under the control of the third control node QB. The control electrode of the seventh transistor M7 is electrically connected to the global reset signal terminal TRST, the first electrode of the seventh transistor M7 is electrically connected to the first control node Q, and the second electrode of the seventh transistor M7 is electrically connected to the first voltage line VGL 1. The seventh transistor M7 is configured to reset the first control node Q under the control of the global reset signal terminal TRST. The control electrode of the eighth transistor M8 is electrically connected to the display reset signal terminal STD, the first electrode of the eighth transistor M8 is electrically connected to the first control node Q, and the second electrode of the eighth transistor M8 is electrically connected to the first voltage line VGL 1. The eighth transistor M8 is configured to reset the first control node Q under control of the display reset signal terminal STD.

In some examples, as shown in fig. 8, the control electrode and the first electrode of the ninth transistor M9 are electrically connected to the fourth voltage line VGH2, and the second electrode of the ninth transistor M9 is electrically connected to the second control node QA. The ninth transistor M9 is configured to control the potential of the second control node QA under the control of the fourth voltage line VGH 2. The control electrode of the tenth transistor M10 is electrically connected to the first control node Q, the first electrode of the tenth transistor M10 is electrically connected to the second control node QA, and the second electrode of the tenth transistor M10 is electrically connected to the first voltage line VGL 1. The tenth transistor M10 is configured to supply the first voltage signal to the second control node QA under the control of the first control node Q. The control electrode of the eleventh transistor M11 is electrically connected to the second control node QA, the first electrode of the eleventh transistor M11 is electrically connected to the first voltage line VGL1, and the second electrode of the eleventh transistor M11 is electrically connected to the first control node Q. The eleventh transistor M11 is configured to supply the first voltage signal to the first control node Q under the control of the second control node QA. The control electrode of the twelfth transistor M12 is electrically connected to the third control node QB, the first electrode of the twelfth transistor M12 is electrically connected to the first voltage line VGL1, and the second electrode of the twelfth transistor M12 is electrically connected to the first control node Q. The twelfth transistor M12 is configured to supply the first voltage signal to the first control node QA under the control of the third control node QB. The control electrode of the thirteenth transistor M13 is electrically connected to the first clock signal terminal CLKA, the first electrode of the thirteenth transistor M13 is electrically connected to the second control node QA, and the second electrode of the thirteenth transistor M13 is electrically connected to the second electrode of the fourteenth transistor M14. The control electrode of the fourteenth transistor M14 is electrically connected to the fourth control node H, and the first electrode of the fourteenth transistor M14 is electrically connected to the first voltage line VGL 1. The control electrode of the fifteenth transistor M15 is electrically connected to the first input signal terminal STU1, the first electrode of the fifteenth transistor M15 is electrically connected to the first voltage line VGL1, and the second electrode of the fifteenth transistor M15 is electrically connected to the second control node QA.

In some examples, as shown in fig. 8, the control electrode of the sixteenth transistor M16 is electrically connected to the first control node Q, the first electrode of the sixteenth transistor M16 is electrically connected to the second clock signal terminal CLKB, and the second electrode of the sixteenth transistor M16 is electrically connected to the shift output terminal CR. The control electrode of the seventeenth transistor M17 is electrically connected to the first control node Q, the first electrode of the seventeenth transistor M17 is electrically connected to the third clock signal terminal CLKC, and the second electrode of the seventeenth transistor M17 is electrically connected to the first output terminal OUTA. The gate of the eighteenth transistor M18 is electrically connected to the first control node Q, the first gate of the eighteenth transistor M18 is electrically connected to the fourth clock signal terminal CLKD, and the second gate of the eighteenth transistor M18 is electrically connected to the second output terminal OUTB. The control electrode of the nineteenth transistor M19 is electrically connected to the second control node QA, the first electrode of the nineteenth transistor M19 is electrically connected to the first voltage line VGL1, and the second electrode of the nineteenth transistor M19 is electrically connected to the shift output terminal CR. The control electrode of the twentieth transistor M20 is electrically connected to the second control node QA, the first electrode of the twentieth transistor M20 is electrically connected to the second voltage line VGL2, and the second electrode of the twentieth transistor M20 is electrically connected to the first output terminal OUTA. The control electrode of the twenty-first transistor M21 is electrically connected to the second control node QA, the first electrode of the twenty-first transistor M21 is electrically connected to the second voltage line VGL2, and the second electrode of the twenty-first transistor M21 is electrically connected to the second output terminal OUTB. The control electrode of the twenty-second transistor M22 is electrically connected to the third control node QB, the first electrode of the twenty-second transistor M22 is electrically connected to the first voltage line VGL1, and the second electrode of the twenty-second transistor M22 is electrically connected to the shift output terminal CR. The control electrode of the twenty-third transistor M23 is electrically connected to the third control node QB, the first electrode of the twenty-third transistor M23 is electrically connected to the second voltage line VGL2, and the second electrode of the twenty-third transistor M23 is electrically connected to the first output terminal OUTA. The control electrode of the twenty-fourth transistor M24 is electrically connected to the third control node QB, the first electrode of the twenty-fourth transistor M24 is electrically connected to the second voltage line VGL2, and the second electrode of the twenty-fourth transistor M24 is electrically connected to the second output terminal OUTB. The first electrode plate of the second capacitor C2 is electrically connected to the first control node Q, and the second electrode plate of the second capacitor C2 is electrically connected to the first output terminal OUTA. The first plate of the third capacitor C3 is electrically connected to the first control node Q, and the second plate of the third capacitor C3 is electrically connected to the second output terminal OUTB.

When the sensing driving signal of the ith row sub-pixel of the corresponding display panel needs to be outputted in the idle period of a certain frame, the corresponding fourth control node H needs to be pulled up to a high level in the display period of the frame, and meanwhile, in the idle period of the frame, the first clock signal of the high level is provided by the first clock signal terminal CLKA to pull up the potential of the fifth control node N, thereby further pulling up the potential of the first control node Q, and then when the scan driving signal of the high level needs to be outputted, the third clock signal of the high level is provided by the third clock signal terminal CLKC, or the fourth clock signal of the high level is provided by the fourth clock signal terminal CLKD.

The scan driving circuit provided in this example can provide the scan driving signal in the display period and the sense driving signal (the signals transmitted by the first scan line and the second scan line as shown in fig. 6) in the idle period, so that random compensation can be realized, and display defects such as uneven display brightness and the like and scan lines caused by sequential compensation line by line can be avoided.

Fig. 8 shows an exemplary structure of the scan driving circuit. However, the present embodiment is not limited to the implementation of the scan driving circuit as long as the functions thereof can be realized.

The drawings in the present disclosure relate only to the structures to which the present disclosure relates, and other structures may be referred to in general. The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

It will be understood by those skilled in the art that various modifications and equivalent substitutions may be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments, which are intended to be encompassed within the scope of the appended claims.

Claims (15)

1. A pixel circuit for driving a light emitting element to emit light, comprising: a data writing sub-circuit, a driving sub-circuit, a light emission control sub-circuit, a storage sub-circuit, and a compensation sub-circuit;

the data writing sub-circuit is electrically connected with the data line, the first scanning line and the first node and is configured to provide a data signal transmitted by the data line for the first node under the control of the first scanning line;

the storage sub-circuit is electrically connected with the first node and the third node and is configured to store the data signal;

the light-emitting control sub-circuit is electrically connected with a first power line, a light-emitting control line and a second node and is configured to provide a first power signal transmitted by the first power line to the second node under the control of the light-emitting control line in a display period of one frame;

The second node is further electrically connected to a first signal line configured to supply a third power signal to the second node during an idle period of one frame;

the driving sub-circuit is electrically connected with the first node, the second node and the third node and is configured to provide driving current for the third node by using a first power signal or a third power signal provided by the second node under the control of the first node; the third node is electrically connected with the light-emitting element;

the compensation sub-circuit is electrically connected with the sensing line, the second scanning line and the third node and is configured to collect the driving current of the third node under the control of the second scanning line so as to realize external compensation.

2. The pixel circuit of claim 1, wherein the first signal line is configured to provide a third power supply signal to the second node during an idle period of a random frame.

3. The pixel circuit of claim 1, wherein the third power supply signal is the same as the first power supply signal.

4. The pixel circuit according to claim 1, wherein the light emission control line is configured to supply the pulse width modulation signal during a display period of one frame.

5. The pixel circuit of claim 1, wherein the data writing sub-circuit comprises: a scanning transistor; the control electrode of the scanning transistor is electrically connected with the first scanning line, the first electrode of the scanning transistor is electrically connected with the data line, and the second electrode of the scanning transistor is electrically connected with the first node.

6. The pixel circuit of claim 1, wherein the drive sub-circuit comprises: a driving transistor; the control electrode of the driving transistor is electrically connected with the first node, the first electrode of the driving transistor is electrically connected with the second node, and the second electrode of the driving transistor is electrically connected with the third node.

7. The pixel circuit of claim 1, wherein the storage sub-circuit comprises: a storage capacitor; the first polar plate of the storage capacitor is electrically connected with the first node, and the second polar plate of the storage capacitor is electrically connected with the third node.

8. The pixel circuit of claim 1, wherein the compensation sub-circuit comprises: a sense transistor; the control electrode of the sensing transistor is electrically connected with the second scanning line, the first electrode of the sensing transistor is electrically connected with the sensing line, and the second electrode of the sensing transistor is electrically connected with the third node.

9. The pixel circuit of claim 1, wherein the light emission control sub-circuit comprises: a light emission control transistor; the control electrode of the light-emitting control transistor is electrically connected with the light-emitting control line, the first electrode of the light-emitting control transistor is electrically connected with the first power line, and the second electrode of the light-emitting control transistor is electrically connected with the second node.

10. A driving method of a pixel circuit, characterized in that it is applied to the pixel circuit according to any one of claims 1 to 9, the driving method comprising:

in the display stage of each frame, a data writing sub-circuit provides data signals transmitted by a data line to a first node under the control of a first scanning line, a storage sub-circuit stores the data signals, a light-emitting control sub-circuit provides a first power supply signal to a second node under the control of a light-emitting control line, and a driving sub-circuit provides driving current to a third node under the control of the first node;

in the idle stage of one frame, the first signal line provides a third power supply signal to the second node, and the compensation sub-circuit collects the driving current of the third node under the control of the second scanning line so as to realize external compensation.

11. A display panel, comprising: a plurality of pixel circuits according to any one of claims 1 to 9, a plurality of compensation control circuits, and a plurality of first signal lines; at least one first signal line is electrically connected to the plurality of pixel circuits;

the compensation control circuit is electrically connected with the first control line, the third power line and the first signal line and is configured to provide the third power signal transmitted by the third power line to the first signal line under the control of the first control line.

12. The display panel according to claim 11, wherein one first signal line is electrically connected to one row of pixel circuits, and a plurality of compensation control circuits are electrically connected to the plurality of first signal lines in one-to-one correspondence.

13. The display panel of claim 11, wherein the compensation control circuit comprises: a first control transistor; the control electrode of the first control transistor is electrically connected with the first control line, the first electrode of the first control transistor is electrically connected with the third power line, and the second electrode of the first control transistor is electrically connected with the first signal line.

14. The display panel according to claim 11, wherein a first control line to which a compensation control circuit electrically connected to one first signal line is electrically connected to a first scan line or a second scan line electrically connected to a pixel circuit electrically connected to the first signal line.

15. The display panel of claim 11, further comprising: a plurality of cascaded scan driving circuits; and a scanning driving circuit of any stage configured to supply a scanning driving signal to one row of pixel circuits through the first scanning line in a display period of each frame, and to supply a sensing driving signal to the one row of pixel circuits through the second scanning line in an idle period of a random one frame.