CN116615027A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN116615027A CN116615027A CN202310713143.6A CN202310713143A CN116615027A CN 116615027 A CN116615027 A CN 116615027A CN 202310713143 A CN202310713143 A CN 202310713143A CN 116615027 A CN116615027 A CN 116615027A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 169
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000463 material Substances 0.000 claims description 18
- 230000010354 integration Effects 0.000 abstract description 17
- -1 nitrogen ions Chemical class 0.000 description 16
- 239000003990 capacitor Substances 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 230000002349 favourable effect Effects 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000013021 overheating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
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- Semiconductor Memories (AREA)
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Abstract
Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a method for manufacturing the same, the semiconductor structure including: the memory unit comprises a first transistor and a second transistor which are arranged along the third direction, wherein the first end of the first transistor is electrically connected with the control end of the second transistor; a first word line extending in the second direction and a first bit line extending in the first direction, the first word line being electrically connected to the control terminal of the first transistor, the first bit line being electrically connected to the second terminal of the first transistor; a second word line extending in the first direction and a second bit line extending in the second direction, the second word line being electrically connected to the first terminal of the second transistor, the second bit line being electrically connected to the second terminal of the second transistor. At least the integration density of the memory cell array structure can be improved.
Description
Technical Field
Embodiments of the present disclosure relate to the field of semiconductors, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
A common dynamic random access memory (DRAM, dynamic Random Access Memory) is of the 1T1C type, i.e. a transistor source or drain is electrically connected to a capacitor to form a memory cell structure. The structure stores data by using the capacitor, but the capacitor consumes electric quantity during reading and leaks electricity, so that the electric charge in the capacitor needs to be continuously refreshed, the power consumption of the DRAM is larger, and the electrical property is unstable. Meanwhile, the technology for manufacturing the capacitor occupies a large area, and the size shrinkage is also a difficult problem.
To overcome the difficulties presented by capacitance, a 2T0C type memory cell structure is used, i.e., a transistor source or drain is electrically connected to the gate of another transistor to form a memory cell structure, wherein the gate of one transistor may form a natural capacitor and allow charge to be stored and flow through. However, the integration density of the semiconductor structure using the 2T0C type memory cell in the prior art still remains to be improved.
Disclosure of Invention
Embodiments of the present disclosure provide a semiconductor structure and a method of manufacturing the same, which are at least advantageous for improving the integration density of memory cells.
According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a semiconductor structure, including: the memory cells are arranged at intervals along a first direction and a second direction and are arranged in an array, the first direction and the second direction are perpendicular to a third direction, an included angle between the first direction and the second direction is smaller than 90 degrees, the memory cells comprise a first transistor and a second transistor which are arranged along the third direction, and a first end of the first transistor is electrically connected with a control end of the second transistor; a first word line extending in the second direction, a first bit line extending in the first direction and electrically connected to the control terminal of the first transistor, and a first bit line electrically connected to the second terminal of the first transistor; the second word line extends along the first direction, the second bit line extends along the second direction, the second word line is electrically connected with the first end of the second transistor, and the second bit line is electrically connected with the second end of the second transistor.
In some embodiments, the first direction is at an angle of 60 ° to the second direction.
In some embodiments, the distance between the first transistors in any adjacent memory cell is the same; the distance between the second transistors in any adjacent memory cell is the same.
In some embodiments, the first transistor is a write transistor and the second transistor is a read transistor.
In some embodiments, the first transistor comprises: a semiconductor pillar; the first word line is opposite to at least part of the side face of the semiconductor column; and the first source-drain doped regions are positioned in the semiconductor columns at two opposite sides of the first word line, wherein one first source-drain doped region is used as a first end of the first transistor and is electrically connected with the control end of the second transistor, and the other first source-drain doped region is used as a second end of the first transistor and is electrically connected with the first bit line.
In some embodiments, the material of the semiconductor pillars comprises IGZO.
In some embodiments, the second transistor includes: a semiconductor layer; a second gate electrode, the second gate electrode being opposite to at least part of the semiconductor layer, and the second gate electrode being electrically connected to the first end of the first transistor; and the second source-drain doped regions are respectively positioned at two opposite ends of the semiconductor layer along the third direction, wherein one second source-drain doped region is used as a first end of the second transistor to be electrically connected with the second word line, and the other second source-drain doped region is used as a second end of the second transistor to be electrically connected with the second bit line.
In some embodiments, the second gate is columnar; the semiconductor layer is opposite to the side face and the bottom face of the second grid electrode, and the top face of the second grid electrode is electrically connected with the first end of the first transistor; one of the second source-drain doped regions is adjacent to the top surface of the second gate, and the other second source-drain doped region is adjacent to the bottom surface of the second gate.
In some embodiments, the second transistor further comprises: a first electrical connection layer in electrical contact with the second source drain doped region adjacent to the top surface of the second gate; a second electrical connection layer in electrical contact with the second source drain doped region adjacent to a bottom surface of the second gate; wherein the first electrical connection layer is in electrical contact with one of the second bit line or the second word line, and the second electrical connection layer is in electrical contact with the other of the second bit line or the second word line.
In some embodiments, the material of the semiconductor layer includes IGZO.
According to some embodiments of the present disclosure, another aspect of embodiments of the present disclosure further provides a method for manufacturing a semiconductor structure, including: forming a plurality of memory cells, wherein the memory cells are arranged at intervals along a first direction and a second direction and are arranged in an array, the first direction and the second direction are perpendicular to a third direction, an included angle between the first direction and the second direction is smaller than 90 degrees, the memory cells comprise a first transistor and a second transistor which are arranged along the third direction, and a first end of the first transistor is electrically connected with a control end of the second transistor; forming a first word line and a first bit line, wherein the first word line extends along the second direction, the first bit line extends along the first direction, the first word line is electrically connected with a control end of the first transistor, and the first bit line is electrically connected with a second end of the first transistor; and forming a second word line and a second bit line, wherein the second word line extends along the first direction, the second bit line extends along the second direction, the second word line is electrically connected with the first end of the second transistor, and the second bit line is electrically connected with the second end of the second transistor.
In some embodiments, forming the second transistor includes forming a semiconductor layer and a second gate, where the second gate is in a column shape, the semiconductor layer is opposite to a side surface and a bottom surface of the second gate, a top surface of the second gate is electrically connected to a first end of the first transistor, two opposite ends of the semiconductor layer along the third direction have second source-drain doped regions, one of the second source-drain doped regions is electrically connected to the second word line as a first end of the second transistor, the other of the second source-drain doped regions is electrically connected to the second bit line as a second end of the second transistor, one of the second source-drain doped regions is adjacent to the top surface of the second gate, and the other of the second source-drain doped regions is adjacent to the bottom surface of the second gate.
The technical scheme provided by the embodiment of the disclosure has at least the following advantages:
the embodiment of the disclosure provides a semiconductor structure, which comprises: the memory unit comprises a first transistor and a second transistor which are arranged along the third direction, wherein the first end of the first transistor is electrically connected with the control end of the second transistor; a first word line extending in the second direction and a first bit line extending in the first direction, the first word line being electrically connected to the control terminal of the first transistor, the first bit line being electrically connected to the second terminal of the first transistor; a second word line extending in the first direction and a second bit line extending in the second direction, the second word line being electrically connected to the first terminal of the second transistor, the second bit line being electrically connected to the second terminal of the second transistor. In an embodiment of the disclosure, an included angle between a first direction of an extending direction of the first bit line and the second word line and a second direction of the extending direction of the second bit line and the first word line is smaller than 90 °. Compared with the prior art that the first direction is perpendicular to the second direction, the integration density of the memory cells can be improved under the condition that the interval distance between two adjacent memory cells is not changed, the size of the semiconductor structure is reduced, the area of an area surrounded by four adjacent memory cells is reduced, namely the area occupied by each memory cell in the memory cell array structure is reduced, and the miniaturization degree of the semiconductor structure can be improved. In addition, the first transistor and the second transistor form a memory cell together, and a capacitor device is not needed, so that the size of the memory cell structure is reduced, and the integration density of the memory cell structure is improved.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a schematic top view of a semiconductor structure;
FIG. 2 is a schematic diagram of a partial top view of a semiconductor structure according to an embodiment of the present disclosure;
fig. 3 is a schematic perspective view of a semiconductor structure according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of a semiconductor structure according to one embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of a semiconductor structure according to another embodiment of the present disclosure;
Fig. 7 is a schematic perspective view of another partial region in a semiconductor structure according to an embodiment of the disclosure;
fig. 8 is a schematic cross-sectional view illustrating a step of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
fig. 9 is a schematic cross-sectional view illustrating a step of a method for manufacturing a semiconductor structure according to another embodiment of the disclosure;
fig. 10 is a schematic perspective view illustrating another step in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.
Detailed Description
As known from the background art, the current semiconductor structure has a problem of low integration density of memory cells.
Referring to fig. 1, fig. 1 is a schematic top view of a semiconductor structure. The semiconductor structure includes a plurality of memory cells 10 arranged in an array at intervals along a first direction X and a second direction Y, and the first direction X is perpendicular to the second direction Y. The memory cell 10 includes a first transistor and a second transistor. The semiconductor structure further includes a first word line, a first bit line, a second word line, and a second bit line, which are not shown. The first word line extends along a second direction Y, the first bit line extends along a first direction X, the second word line extends along the first direction X, the second bit line extends along a second direction Y, the first word line is electrically connected with the first bit line and the first transistor, and the second word line is electrically connected with the second bit line and the second transistor.
It is found by analysis that, in the above semiconductor structure, the array structure of the plurality of memory cells 10 in the semiconductor structure is arranged in a square shape, and if the distance between two adjacent memory cells 10 is a, in the array structure of the memory cells 10 in the semiconductor structure, the area of the area surrounded by the adjacent four memory cells 10 should be a 2 . Because of the large area of the area enclosed by the adjacent four memory cells 10 in the memory cell 10 structure, the integration density of memory cells in the semiconductor structure is low. If a semiconductor structure can be provided, the area of the area surrounded by the adjacent four memory cells can be reduced without changing the distance between the adjacent two memory cells, so that the above problems can be solved, and the integration density of the memory cell structure can be improved.
Embodiments of the present disclosure provide a semiconductor structure, comprising: the memory cells are arranged in an array at intervals along a first direction and a second direction, the included angle between the first direction and the second direction is smaller than 90 degrees, and the memory cells comprise a first transistor and a second transistor. The first word line extends along the second direction, the first bit line extends along the first direction, the second word line extends along the first direction, and the second bit line extends along the first direction Extending in two directions. In this way, the array structure of the plurality of memory cells in the semiconductor structure is arranged in a hexagonal shape, and if the distance between two adjacent memory cells is a, in the memory cell array in the semiconductor structure, the area of the area surrounded by the four adjacent memory cells is smaller than a 2 . By changing the integrated array form of the memory cells, the area of the area surrounded by the adjacent four memory cells can be reduced under the condition that the interval distance between the adjacent two memory cells is not changed, namely, the area occupied by each memory cell in the memory cell array structure is reduced, so that the miniaturization degree of the semiconductor structure is improved, and the integration density of the memory cells is improved.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.
Fig. 2 is a schematic diagram of a partial top view of a semiconductor structure according to an embodiment of the disclosure, and fig. 3 is a schematic diagram of a three-dimensional structure of a semiconductor according to an embodiment of the disclosure.
Referring to fig. 2 to 3, the semiconductor structure includes: the plurality of memory cells 100 are arranged at intervals along a first direction X and a second direction Y in an array manner, the first direction X and the second direction Y are perpendicular to a third direction Z, an included angle between the first direction X and the second direction Y is smaller than 90 degrees, the memory cells 100 comprise a first transistor 110 and a second transistor 120 which are arranged along the third direction Z, and a first end of the first transistor 110 is electrically connected with a control end of the second transistor 120; a first word line 130 and a first bit line 140, the first word line 130 extending along a second direction Y, the first bit line 140 extending along a first direction X, the first word line 130 being electrically connected to the control terminal of the first transistor 110, the first bit line 140 being electrically connected to the second terminal of the first transistor 110; the second word line 150 and the second bit line 160, the second word line 150 extends along the first direction X, the second bit line 160 extends along the second direction Y, and the second word line 150 is electrically connected to the first terminal of the second transistor 120, and the second bit line 160 is electrically connected to the second terminal of the second transistor 120.
Referring to fig. 2, it can be seen from fig. 2 that the array structure of the plurality of memory cells 100 in the semiconductor structure is arranged in a hexagonal shape, and if the distance between two adjacent memory cells 100 is a, the area of the area surrounded by the four adjacent memory cells 100 in the semiconductor structure should be smaller than a 2 . Since the area of the area surrounded by the adjacent four memory cells 100 is smaller in the memory cell 100 structure, the size occupied by each memory cell 100 is smaller, and the integration density of the memory cell 100 structure in the semiconductor structure can be improved.
Referring to fig. 3, in the semiconductor structure, each memory cell 100 includes a first transistor 110 and a second transistor 120 arranged along a third direction Z. Further, a first bit line 140, a first word line 130, a second bit line 160, and a second word line 150 are sequentially provided in a direction from the first transistor 110 to the second transistor 120. The first bit line 140 and the second word line 150 extend along a first direction X, and the first word line 130 and the second bit line 160 extend along a second direction Y.
Referring to fig. 3 to 4, fig. 4 is a schematic circuit diagram corresponding to a semiconductor structure according to an embodiment of the disclosure. In some embodiments, the first transistor 110 may be a write transistor and the second transistor 120 may be a read transistor. In operation of the semiconductor structure, charge is stored in the gate capacitance of the second transistor 120, i.e. in the control terminal of the second transistor 120, where the charge is stored is commonly referred to as a storage node SN. The 2T0C memory cell is controlled by the first transistor 110 for writing operation of the memory cell, the second transistor 120 for reading operation of the memory cell, and the gate capacitance of the transistor is used for storing charges, which has been shown that the transistor prepared by using the metal oxide semiconductor has a smaller off-current, so that charges stored in the gate capacitance can be kept for a longer time.
For the sake of brevity and clarity of illustration, the entire structure of the first transistor 110, the entire structure of the second transistor 120, and the connection structure between the components are not explicitly shown in fig. 3.
Illustratively, the thin film transistor (Thin Film Transistor, TFT) prepared based on IGZO has a capacitance of less than 10 22 The extremely low off-current of A/mu m can reduce the leakage current of the 2T0C memory cell prepared by the method. Illustratively, a 2T0C memory cell prepared based on two IGZO-TFTs, having a retention time of greater than 400 seconds, and having a retention time of about 3X 10 -19 The extremely low off-current of a/μm can improve the data retention capability of the 2T0C memory cell.
The memory cell structure is of the 2T0C type, has no capacitor device, is favorable for reducing the size of the memory cell structure, and in addition, in the third direction Z, the first transistor 110 and the second transistor 120 are stacked up and down, which is favorable for reducing the layout space of the memory cell structure in the first direction X and the second direction Y, thereby being favorable for improving the integration density of the memory cell 100 structure.
Referring to fig. 2, in some embodiments, the first direction X may be at an angle of 60 ° to the second direction Y. The array structure of the memory cells 100 thus arranged may be arranged in a regular hexagon, and if the distance between two adjacent memory cells 100 is a, the area of the area surrounded by the adjacent four memory cells 100 in the array structure of the memory cells 100 in the semiconductor structure should be It can be seen that, compared with the area a of the area surrounded by the adjacent four memory cells in the memory cell array perpendicular to the first direction X and the second direction Y 2 The area of the area surrounded by the adjacent four memory cells 100 in the array structure of the memory cells 100 is small. That is, the size of each memory cell 100 in the semiconductor structure in the first direction X or the second direction Y is small, the degree of miniaturization of the semiconductor structure can be improved, and the integration density of the memory cells can be improved.
With continued reference to fig. 2, in some embodiments, the distance between the first transistors 110 in any adjacent memory cells 100 may be the same; the distance between the second transistors 120 in any adjacent memory cell 100 may be the same. That is, the distance between any adjacent memory cells 100 may be the same. If the included angle between the first direction X and the second direction Y is 60 °, the array structure of the memory cells 100 may be arranged in a regular hexagon, and the distances between any two adjacent memory cells 100 may be the same. The distance between any adjacent memory cells 100 may be the smallest distance that the adjacent transistors in the semiconductor structure may select, so that the distance between the adjacent memory cells 100 may be further reduced, the size occupied by each memory cell 100 in the semiconductor structure in the first direction X or the second direction Y may be reduced, the degree of miniaturization of the semiconductor structure may be further improved, and the integration density of the memory cells 100 may be further improved.
Fig. 5 is a schematic cross-sectional structure of a first transistor 110 (refer to fig. 3) in a semiconductor structure according to an embodiment of the disclosure, and fig. 6 is a schematic cross-sectional structure of the first transistor 110 in a semiconductor structure according to another embodiment of the disclosure.
Referring to fig. 5, in some embodiments, the first transistor 110 may be a Gate-All-Around FET (GAA). In a fully-around gate transistor, the gate may surround the periphery of the channel. The first transistor 110 may include: a semiconductor pillar 111; the first word line 130 is directly opposite at least a portion of the side of the semiconductor pillar 111; the first source-drain doped regions 112 are located in the semiconductor pillars 111 on opposite sides of the first word line 130, wherein one first source-drain doped region 112 serves as a first terminal of the first transistor 110 and is electrically connected to the control terminal of the second transistor 120, and the other first source-drain doped region 112 serves as a second terminal of the first transistor 110 and is electrically connected to the first bit line 140. The region of the semiconductor pillar 111 opposite to the first word line 130 may be a channel region of the first transistor 110, and the first word line 130 may be a gate of the first transistor 110. Doping treatment may be performed in the first source/drain doped regions 112 in the semiconductor pillars 111 on opposite sides of the first word line 130, wherein N-type ions, such as nitrogen ions, phosphorus ions, etc., may be implanted if N-type doping is required. If P-type doping is required, P-type ions, such as boron ions, aluminum ions, etc., may be implanted.
Referring to fig. 4 and fig. 5, the first end and the second end of the first transistor 110 may be the source/drain of the first transistor 110, and the control end of the first transistor 110 is the gate of the first transistor 110. The first terminal of the first transistor 110 may be a source of the first transistor 110, the first terminal of the first transistor 110 is connected to a control terminal of the second transistor 120 and forms a storage node SN of the semiconductor structure, the second terminal of the first transistor 110 may be a drain of the first transistor 110, the second terminal of the first transistor 110 is electrically connected to the first bit line 140, and a control terminal of the first transistor 110, i.e., a gate of the first transistor 110 is electrically connected to the first word line 130.
It should be noted that the semiconductor structure may further have a connection structure, which is not fully shown in fig. 3 for brevity and clarity of illustration, and may electrically connect the second end of the first transistor and the first bit line.
In some embodiments, the material of the semiconductor pillars 111 may include IGZO (indium gallium zinc oxide ). The IGZO contains indium, gallium and zinc, and is a novel semiconductor material. The use of IGZO material in the semiconductor pillars 111 in the semiconductor structure as channels of the semiconductor structure may improve the performance of the semiconductor structure. Compared with the channel layer made of amorphous silicon, the carrier mobility of the channel layer made of IGZO is 20-30 times that of amorphous silicon, and the charge and discharge rate of the semiconductor structure can be improved by the IGZO, so that the energy efficiency of the semiconductor structure is improved.
In other embodiments, the semiconductor pillars 111 may also include other materials, for example, the material of the semiconductor pillars 111 may also include ITO (Indium Tin Oxide).
With continued reference to fig. 5, in some embodiments, a first gate dielectric layer 113 may also be included in the first transistor 110, and the first gate dielectric layer 113 may be located at least between the first word line 130 and the semiconductor pillar 111. The material of the first gate dielectric layer 113 may include silicon oxide or aluminum oxide, etc. The arrangement of the first gate dielectric layer 113 can improve the electron conduction performance of the first transistor 110, so that the electron conduction in the semiconductor structure is smoother, the first gate dielectric layer 113 can also control current, prevent overheating or short circuit of a device caused by overlarge current, form a charge channel, be used for controlling the flow of electrons in the device, improve the stability of the device, improve the efficiency of the device, and protect the device from environmental factors to a certain extent. In addition, the first gate dielectric layer 113 has a certain surface activity, and can be used as a surface active layer in the semiconductor structure to receive or place other substances.
Referring to fig. 6, in some embodiments, the first transistor 110 may further include a first gate 114, where the first gate 114 may face at least a portion of a side surface of the semiconductor pillar 111, and the semiconductor pillar 111 located on opposite sides of the first gate 114 may have a first source-drain doped region 112 therein, and a portion of the semiconductor pillar 111 facing the first gate 114 may be a channel of the first transistor 110. The first word line 130 may cover a surface of the first gate 114 remote from the semiconductor pillar 111 and electrically connected to the first gate 114. The first gate dielectric layer 113 may be located between the first gate 114 and the semiconductor pillar 111.
Fig. 7 is a schematic cross-sectional view of a second transistor 120 (refer to fig. 3) in a semiconductor structure according to an embodiment of the disclosure.
Referring to fig. 7, in some embodiments, the second transistor 120 may be a vertical ring-Channel-structure transistor (CAA). In a vertical ring channel structure transistor, the channel may surround the periphery of the gate. The second transistor 120 may include: a semiconductor layer 121; a second gate electrode 122, the second gate electrode 122 being opposite to at least part of the semiconductor layer 121, and the second gate electrode 122 being electrically connected to the first terminal of the first transistor 110; the second source-drain doped regions 123 are respectively located at two opposite ends of the semiconductor layer 121 along the third direction Z, wherein one second source-drain doped region 123 is electrically connected to the second word line 150 as a first end of the second transistor 120, and the other second source-drain doped region 123 is electrically connected to the second bit line 160 as a second end of the second transistor 120. The semiconductor layer 121 partially facing the second gate electrode 122 may serve as a channel of the second transistor 120, and the second source-drain doped regions 123 respectively located at two opposite ends of the first transistor 110 along the third direction Z may also be facing the second gate electrode 122. The second source/drain doped region 123 may be doped, wherein N-type ions, such as nitrogen ions, phosphorus ions, etc., may be implanted if N-type doping is required. If P-type doping is required, P-type ions, such as boron ions, aluminum ions, etc., may be implanted.
Referring to fig. 4 and 7, the control terminal of the second transistor 120 is electrically connected to the first terminal of the first transistor 110, i.e., the second gate 122 of the second transistor 120 may be electrically connected to the source of the first transistor 110 to form the storage node SN. The first and second ends of the second transistor 120 may be the source/drain of the second transistor 120. The first terminal of the second transistor 120 may be a source of the second transistor 120, the first terminal of the second transistor 120 is electrically connected to the second word line 130, the second terminal of the second transistor 120 may be a drain of the second transistor 120, and the second terminal of the second transistor 120 is electrically connected to the second bit line 160.
With continued reference to fig. 7, in some embodiments, the second gate 122 may be columnar; the semiconductor layer 121 is opposite to the side surface and the bottom surface of the second gate electrode 122, and the top surface of the second gate electrode 122 is electrically connected to the first end of the first transistor 110; one of the second source/drain doped regions 123 is adjacent to the top surface of the second gate 122, and the other second source/drain doped region 123 is adjacent to the bottom surface of the second gate 122. The semiconductor layer 121 surrounds the side surface of the second gate electrode 122, and the semiconductor layer 121 is also opposite to the bottom surface of the second gate electrode 122, that is, the semiconductor layer 121 may enclose a semi-enclosed space, the space extends into the columnar second gate electrode 122, and the top surface of the second gate electrode 122 extends out of the top of the space enclosed by the semiconductor layer 121 and is electrically connected to the first end of the first transistor 110. The second gate electrode 122 is opposite to the channel in the semiconductor layer 121 and the two second source-drain doped regions 123, but only the semiconductor layer 121 located between the two second source-drain doped regions 123 along the third direction Z is the channel of the second transistor 120. In the third direction Z, the first transistor 110 is located on the top surface of the second transistor 120, and the first end of the first transistor 110 may be in contact with the top surface of the second gate 122 in the second transistor 120.
In some embodiments, a second gate dielectric layer 124 may also be included in the second transistor 120. The second gate dielectric layer 124 may be at least between the second gate electrode 122 and the semiconductor layer 121. The material of the second gate dielectric layer 124 may include silicon oxide or aluminum oxide, etc. The arrangement of the second gate dielectric layer 124 can improve the electron conduction performance of the second transistor 120, so that electrons can be conducted more smoothly in the semiconductor structure, the second gate dielectric layer 124 can also control current, prevent overheating or short circuit caused by overlarge current, and can form a charge channel for controlling the flow of electrons in the device, and can also improve the stability of the device, improve the efficiency of the device, and protect the device from environmental factors to a certain extent. In addition, the second gate dielectric layer 124 has a certain surface activity, and can be used as a surface active layer in the semiconductor structure to receive or place other substances.
With continued reference to fig. 7, in some embodiments, the second transistor 120 further includes: a first electrical connection layer 125 in electrical contact with the second source drain doped region 123 adjacent to the top surface of the second gate 122; a second electrical connection layer 126 in electrical contact with the second source-drain doped region 123 adjacent to the bottom surface of the second gate 122; wherein the first electrical connection layer 125 is in electrical contact with one of the second bit line 160 or the second word line 150, and the second electrical connection layer 126 is in electrical contact with the other of the second bit line 160 or the second word line 150. The first electrical connection layer 125 and the second electrical connection layer 126 are source and drain electrodes of the second transistor 120, wherein the first electrical connection layer 125 may be electrically connected to the second bit line 160, the first electrical connection layer 125 may be a drain electrode of the second transistor 120, the second electrical connection layer 126 may be electrically connected to the second word line 150, and the second electrical connection layer 126 may be a source electrode of the second transistor 120. It should be noted that, for simplicity and clarity of illustration, the first electrical connection layer 125 and the second electrical connection layer 126 are not shown in fig. 3, and all structures of the first electrical connection layer 125 and the second electrical connection layer 126 are not shown in fig. 7, so long as the first electrical connection layer 125 and the second electrical connection layer 126 can perform their connection functions in the semiconductor structure, the first electrical connection layer 125 electrically connects one second source-drain doped region 123 in the second transistor 120 with one of the second word line 150 or the second bit line 160, and the second electrical connection layer 126 electrically connects the other second source-drain doped region 123 in the second transistor 120 with the other of the second word line 150 or the second bit line 160.
In some embodiments, the material of the semiconductor layer 121 may include IGZO (indium gallium zinc oxide ). The IGZO contains indium, gallium and zinc, and is a novel semiconductor material. The use of IGZO material in the semiconductor layer 121 in the semiconductor structure as a channel of the semiconductor structure may improve the performance of the semiconductor structure. Compared with the channel layer made of amorphous silicon, the carrier mobility of the channel layer made of IGZO is 20-30 times that of amorphous silicon, and the charge and discharge rate of the semiconductor structure can be improved by the IGZO, so that the energy efficiency of the semiconductor structure is improved.
In other embodiments, the semiconductor layer 121 may further include other materials, for example, the material of the semiconductor layer 121 may further include ITO (Indium Tin Oxide).
In the semiconductor structure provided by the embodiment of the disclosure, the semiconductor structure comprises a plurality of memory cells which are arranged in an array at intervals along a first direction and a second direction, wherein an included angle between the first direction and the second direction is smaller than 90 degrees, the memory cells comprise a first transistor and a second transistor, a first word line extends along the second direction, a first bit line extends along the first direction, a second word line extends along the first direction, and a second bit line extends along the second direction. Therefore, by changing the integrated array form of the memory cells, the area of the area surrounded by the adjacent four memory cells can be reduced under the condition that the interval distance between the adjacent two memory cells is not changed, namely, the area occupied by each memory cell in the memory cell array structure is reduced, so that the miniaturization degree of the semiconductor structure is improved, and the integration density of the memory cells is improved.
Accordingly, another embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure, which may be used to form the semiconductor structure. The semiconductor structure provided in another embodiment of the present disclosure will be described in detail with reference to the accompanying drawings, and the same or corresponding parts as those of the previous embodiment may be referred to for the corresponding description of the previous embodiment, which will not be repeated in detail.
Fig. 8 is a schematic cross-sectional view of a memory cell in a step of forming the memory cell in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.
Referring to fig. 8, a plurality of memory cells 100 (refer to fig. 2) are formed, the plurality of memory cells 100 are arranged at intervals along a first direction X and a second direction Y and are arranged in an array, the first direction X and the second direction Y are perpendicular to a third direction Z, the memory cells 100 include a first transistor 110 and a second transistor 120 arranged along the third direction Z, and a first end of the first transistor 110 is electrically connected to a control end of the second transistor 120. In the third direction Z, the first transistor 110 is located on the top surface of the second transistor 120, and the first segment of the first transistor 110 is in contact with and electrically connected to the top surface of the control terminal of the second transistor 120.
In some embodiments, forming the memory cell 100 includes forming the second transistor 120, forming the first transistor 110, and arranging the second transistor 120 and the first transistor 110 in a memory cell 100 along the third direction Z, where the second transistor 120 is located on the bottom surface of the first transistor 110.
With continued reference to fig. 8, in some embodiments, forming the second transistor 120 may include forming the semiconductor layer 121 and the second gate 122, wherein the second gate 122 is pillar-shaped, the semiconductor layer 121 faces a side surface and a bottom surface of the second gate 122, a top surface of the second gate 122 is electrically connected to the first end of the first transistor 110, opposite ends of the semiconductor layer 121 along the third direction Z have second source/drain doped regions 123, wherein one second source/drain doped region 123 is electrically connected to the second word line 150 as a first end of the second transistor 120, the other second source/drain doped region 123 is electrically connected to the second bit line 160 as a second end of the second transistor 120, one second source/drain doped region 123 is adjacent to the top surface of the second gate 122, and the other second source/drain doped region 123 is adjacent to the bottom surface of the second gate 122. The second transistor formed may be a vertical ring Channel structure transistor (CAA). In a vertical ring channel structure transistor, the channel may surround the periphery of the gate. The second source-drain doped region 123 in the second transistor 120 is formed by performing a doping process, wherein N-type ions, such as nitrogen ions, phosphorus ions, etc., may be implanted if N-type doping is required. If P-type doping is required, P-type ions, such as boron ions, aluminum ions, etc., may be implanted.
In some embodiments, the second gate 122 in the second transistor 120 may be formed in a column shape, where the semiconductor layer 121 faces the side surface and the bottom surface of the second gate 122, and the top surface of the second gate 122 is exposed, and one second source-drain doped region 123 is adjacent to the top surface of the second gate 122, and the other second source-drain doped region 123 is adjacent to the bottom surface of the second gate 122.
In some embodiments, the second transistor 120 may further have a second gate dielectric layer 124 formed therein, and the second gate dielectric layer 124 may be at least located between the second gate electrode 122 and the semiconductor layer 121. The material of the second gate dielectric layer 124 may include silicon oxide or aluminum oxide, etc.
In some embodiments, forming the second transistor 120 may further include: a first electrical connection layer 125 and a second electrical connection layer 126 are formed, wherein the first electrical connection layer 125 is in electrical contact with the second source-drain doped region 123 adjacent to the top surface of the second gate electrode 122, and the second electrical connection layer 126 is in electrical contact with the second source-drain doped region 123 adjacent to the bottom surface of the second gate electrode 122. The first and second electrical connection layers 125 and 126 may be used to electrically connect the second bit line 160 and the second word line 150, respectively.
In some embodiments, the first transistor 110 may be a Gate-All-Around FET (GAA). In a fully-around gate transistor, the gate may surround the periphery of the channel. Forming the first transistor 110 may include: the semiconductor column 111 is formed, and two first source-drain doped regions 112 are formed on two sides of the semiconductor column 111 along the third direction Z. One of the first source/drain doped regions 112 is used as a first end of the first transistor 110 to cover the top surface of the second gate 122 of the second transistor 120, and the first end of the first transistor 110 is electrically connected to the second gate 122 of the second transistor 120, and the other first source/drain doped region 112 is used as a second end of the first transistor 110. The first source/drain doped regions 112 on opposite sides of the semiconductor pillar 111 need to be doped, wherein N-type ions, such as nitrogen ions, phosphorus ions, etc., may be implanted if N-type doping is required. If P-type doping is required, P-type ions, such as boron ions, aluminum ions, etc., may be implanted.
In some embodiments, forming the first transistor 110 may further include forming a first gate dielectric layer 113, and the first gate dielectric layer 113 may be located at least between the first word line 130 and the semiconductor pillar 111. The material of the first gate dielectric layer 113 may include silicon oxide or aluminum oxide, etc.
Fig. 9 is a schematic cross-sectional view of a memory cell region after forming a first word line, a first bit line, a second word line, and a second bit line in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, and fig. 10 is a schematic perspective view of a semiconductor structure after forming a first word line, a first bit line, a second word line, and a second bit line in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.
Referring to fig. 9 and 10, a first word line 130 and a first bit line 140 are formed, the first word line 130 extends along a second direction Y, the first bit line 140 extends along a first direction Z, wherein an included angle between the first direction X and the second direction Y is smaller than 90 °, the first word line 130 is electrically connected to a control terminal of the first transistor 110, and the first bit line 140 is electrically connected to a second terminal of the first transistor 110. A plurality of first word lines 130 and a plurality of first bit lines 140 may be formed in the semiconductor structure, each of the first word lines 130 may be located on the same horizontal plane, and each of the first bit lines 140 may be located on the same horizontal plane along the third direction Z. The arrangement of the first word lines 130 and the first bit lines 140 may determine the array arrangement of the first transistors 110 in the semiconductor structure to a certain extent, and since the included angle between the extending directions of the first word lines 130 and the first bit lines 140 is smaller than 90 °, the area of the area surrounded by the adjacent four first transistors 110 is smaller than the area of the area surrounded by the adjacent four first transistors 110 when the extending directions of the first word lines 130 and the first bit lines 140 are perpendicular to each other without changing the distance between the adjacent first transistors 110. Therefore, the first word lines 130 and the first bit lines 140 arranged in this way can make the array arrangement of the first transistors 110 in the semiconductor structure denser, and each first transistor 110 occupies a smaller size in the first direction X and the second direction Y, so that the integration density of the memory array can be improved.
Referring to fig. 9 and 10, a second word line 150 and a second bit line 160 are formed, the second word line 150 extends along a first direction X, the second bit line 160 extends along a second direction Y, an included angle between the first direction X and the second direction Y is smaller than 90 °, and the second word line 150 is electrically connected to a first terminal of the second transistor 120, and the second bit line 160 is electrically connected to a second terminal of the second transistor 120. A plurality of second word lines 150 and a plurality of second bit lines 160 may be formed in the semiconductor structure, and each of the second word lines 150 may be located on the same horizontal plane and each of the second bit lines 160 may be located on the same horizontal plane along the third direction Z. The arrangement of the second word lines 150 and the second bit lines 160 may determine the array arrangement of the second transistors 120 in the semiconductor structure to a certain extent, and the arrangement structure may reduce the area of the area surrounded by the adjacent four second transistors 120 without changing the distance between the adjacent second transistors 120 because the included angle between the extending directions of the second word lines 150 and the second bit lines 160 is smaller than 90 °. Therefore, the second word lines 150 and the second bit lines 160 arranged in this way can make the array arrangement of the second transistors 120 in the semiconductor structure denser, and each second transistor 120 occupies a smaller size in the first direction X and the second direction Y, so that the integration density of the memory array can be improved.
The first transistor 110 and the second transistor 120 form the memory cell 100, and according to the above, the arrangement of the first word line 130 and the first bit line 140 can make the array structure of the first transistor 110 denser, and the arrangement of the second word line 150 and the second bit line 160 can make the array structure of the second transistor 120 denser. Therefore, the included angle between the first direction X and the second direction Y is smaller than 90 ° so that the array structure of the memory cell 100 is denser, and the integration density of the memory array in the semiconductor structure can be improved.
The manufacturing method of the semiconductor structure provided by the embodiment of the disclosure comprises the following steps: forming a plurality of memory cells which are arranged in an array at intervals along a first direction and a second direction, wherein an included angle between the first direction and the second direction is smaller than 90 degrees, and the memory cells comprise first transistors and second transistors which are arranged along a third direction; and forming a first word line, a first bit line, a second word line and a second bit line, wherein the first word line extends along a second direction, the first bit line extends along a first direction, the second word line extends along the first direction, and the second bit line extends along the second direction. Therefore, by changing the included angle between the first direction and the second direction and changing the integrated array form of the memory cells, the area of the area surrounded by the adjacent four memory cells can be reduced under the condition that the interval distance between the adjacent two memory cells is not changed, namely, the occupied area of each memory cell in the memory cell array structure is reduced, so that the miniaturization degree of the semiconductor structure is improved, and the integrated density of the memory cells is improved.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should be assessed accordingly to that of the appended claims.
Claims (12)
1. A semiconductor structure, comprising:
the memory cells are arranged at intervals along a first direction and a second direction and are arranged in an array, the first direction and the second direction are perpendicular to a third direction, an included angle between the first direction and the second direction is smaller than 90 degrees, the memory cells comprise a first transistor and a second transistor which are arranged along the third direction, and a first end of the first transistor is electrically connected with a control end of the second transistor;
a first word line extending in the second direction, a first bit line extending in the first direction and electrically connected to the control terminal of the first transistor, and a first bit line electrically connected to the second terminal of the first transistor;
The second word line extends along the first direction, the second bit line extends along the second direction, the second word line is electrically connected with the first end of the second transistor, and the second bit line is electrically connected with the second end of the second transistor.
2. The semiconductor structure of claim 1, wherein the first direction is at an angle of 60 ° to the second direction.
3. The semiconductor structure of claim 1, wherein a distance between the first transistors in any adjacent memory cell is the same; the distance between the second transistors in any adjacent memory cell is the same.
4. The semiconductor structure of claim 1, wherein the first transistor is a write transistor and the second transistor is a read transistor.
5. The semiconductor structure of any one of claims 1-4, wherein the first transistor comprises:
a semiconductor pillar;
the first word line is opposite to at least part of the side face of the semiconductor column;
and the first source-drain doped regions are positioned in the semiconductor columns at two opposite sides of the first word line, wherein one first source-drain doped region is used as a first end of the first transistor and is electrically connected with the control end of the second transistor, and the other first source-drain doped region is used as a second end of the first transistor and is electrically connected with the first bit line.
6. The semiconductor structure of claim 5, wherein the material of the semiconductor pillars comprises IGZO.
7. The semiconductor structure of any one of claims 1-4, wherein the second transistor comprises:
a semiconductor layer;
a second gate electrode, the second gate electrode being opposite to at least part of the semiconductor layer, and the second gate electrode being electrically connected to the first end of the first transistor;
and the second source-drain doped regions are respectively positioned at two opposite ends of the semiconductor layer along the third direction, wherein one second source-drain doped region is used as a first end of the second transistor to be electrically connected with the second word line, and the other second source-drain doped region is used as a second end of the second transistor to be electrically connected with the second bit line.
8. The semiconductor structure of claim 7, wherein the second gate is pillar-shaped; the semiconductor layer is opposite to the side face and the bottom face of the second grid electrode, and the top face of the second grid electrode is electrically connected with the first end of the first transistor; one of the second source-drain doped regions is adjacent to the top surface of the second gate, and the other second source-drain doped region is adjacent to the bottom surface of the second gate.
9. The semiconductor structure of claim 8, wherein the second transistor further comprises:
a first electrical connection layer in electrical contact with the second source drain doped region adjacent to the top surface of the second gate;
a second electrical connection layer in electrical contact with the second source drain doped region adjacent to a bottom surface of the second gate;
wherein the first electrical connection layer is in electrical contact with one of the second bit line or the second word line, and the second electrical connection layer is in electrical contact with the other of the second bit line or the second word line.
10. The semiconductor structure of claim 7, wherein the material of the semiconductor layer comprises IGZO.
11. A method of fabricating a semiconductor structure, comprising:
forming a plurality of memory cells, wherein the memory cells are arranged at intervals along a first direction and a second direction and are arranged in an array, the first direction and the second direction are perpendicular to a third direction, an included angle between the first direction and the second direction is smaller than 90 degrees, the memory cells comprise a first transistor and a second transistor which are arranged along the third direction, and a first end of the first transistor is electrically connected with a control end of the second transistor;
Forming a first word line and a first bit line, wherein the first word line extends along the second direction, the first bit line extends along the first direction, the first word line is electrically connected with a control end of the first transistor, and the first bit line is electrically connected with a second end of the first transistor;
and forming a second word line and a second bit line, wherein the second word line extends along the first direction, the second bit line extends along the second direction, the second word line is electrically connected with the first end of the second transistor, and the second bit line is electrically connected with the second end of the second transistor.
12. The method of manufacturing according to claim 11, wherein forming the second transistor comprises:
the method comprises the steps of forming a semiconductor layer and a second grid, wherein the second grid is columnar, the semiconductor layer is opposite to the side face and the bottom face of the second grid, the top face of the second grid is electrically connected with the first end of the first transistor, second source-drain doped regions are arranged at two opposite ends of the semiconductor layer along the third direction, one second source-drain doped region serves as the first end of the second transistor and is electrically connected with a second word line, the other second source-drain doped region serves as the second end of the second transistor and is electrically connected with a second bit line, one second source-drain doped region is adjacent to the top face of the second grid, and the other second source-drain doped region is adjacent to the bottom face of the second grid.
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