CN116613956A - Low-inductance high-power semiconductor module - Google Patents
Low-inductance high-power semiconductor module Download PDFInfo
- Publication number
- CN116613956A CN116613956A CN202310482195.7A CN202310482195A CN116613956A CN 116613956 A CN116613956 A CN 116613956A CN 202310482195 A CN202310482195 A CN 202310482195A CN 116613956 A CN116613956 A CN 116613956A
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- Prior art keywords
- bridge
- insulating substrate
- power semiconductor
- semiconductor module
- lower half
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 94
- 238000009413 insulation Methods 0.000 claims abstract description 9
- 230000007423 decrease Effects 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 2
- 238000010248 power generation Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005674 electromagnetic induction Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
Abstract
A low-inductance high-power semiconductor module relates to the technical field of semiconductors. The power chip comprises a shell, an insulating substrate, a power chip, a bonding wire, a positive electrode, a negative electrode and an output electrode; the insulation substrate is fixedly arranged on the bottom plate and comprises an upper half-bridge insulation substrate and a lower half-bridge insulation substrate which are arranged at intervals; the power chip is bonded on the top of the insulating substrate; the top of the insulating substrate is provided with a flat connecting bridge electrically connected with the insulating substrate. The scheme utilizes the flat connecting bridge of the power loop, and the flow direction of the flat connecting bridge is opposite to the flow direction of the current below, and utilizes the electromagnetic principle and the magnetic circuit cancellation principle to reduce the parasitic inductance of the module.
Description
Technical Field
The invention relates to the technical field of power semiconductors, in particular to a low-inductance high-power semiconductor module.
Background
The power semiconductor technology plays a very important role in the current rapidly-developed industrial field, and the power module is used as a representative of the power semiconductor technology and is widely applied to industries such as electric automobiles, photovoltaic power generation, wind power generation, industrial frequency conversion and the like. With the rise of the industry in China, the power semiconductor module has wider market prospect.
In order to improve the working efficiency of a power electronic system, the power module is required to have higher switching frequency, but the parasitic inductance of the traditional packaging structure is larger, so that larger voltage overshoot is caused when the power semiconductor device is switched, the risk of overvoltage breakdown of the power device is increased, and the further improvement of the switching frequency of the power module is limited. Parasitic inductance has been a major challenge to overcome in power electronics applications, particularly high frequency, high power applications.
The existing mainstream power module comprises an outer frame, a bottom plate, an insulating substrate, a power chip, bonding wires, power terminals and the like. The three insulating substrates are arranged above the bottom plate through welding, a plurality of power chips are welded above each insulating substrate, and a copper layer of each insulating substrate is electrically connected with the corresponding chip; the front side of the chip is electrically connected with the copper layer form of the insulating substrate through bonding wires. The power loops depend on the copper layer on the upper surface of the insulating substrate, so that the power density of the power semiconductor is difficult to further improve; meanwhile, the parasitic inductance of the power loop is large, the fast switching action cannot be met, and the power loop is not suitable for high-frequency application occasions.
Disclosure of Invention
The invention aims at the problems and provides a low-inductance high-power semiconductor module which reduces parasitic inductance of the module and improves power density.
The technical scheme of the invention is as follows:
a low-inductance high-power semiconductor module comprises a shell, an insulating substrate, a power chip, a bonding wire, a positive electrode, a negative electrode and an output electrode; the insulation substrate is fixedly arranged on the bottom plate and comprises an upper half-bridge insulation substrate and a lower half-bridge insulation substrate which are arranged at intervals; the power chip is bonded on the top of the insulating substrate; the top of the insulating substrate is provided with a flat connecting bridge electrically connected with the insulating substrate.
Specifically, the flat connection bridge is arranged on the top of the lower half-bridge insulating substrate;
the left side pin of flat connecting bridge is connected with the upper half bridge insulating substrate, and the right side pin is electrically connected with the positive electrode.
Specifically, the flat connection bridge is arranged on the top of the upper half-bridge insulating substrate;
the left side pin of the flat connecting bridge is connected with the lower half-bridge insulating substrate, and the right side pin is electrically connected with the negative electrode.
Specifically, the flat connecting bridge comprises a left pin, a connecting bridge body and a right pin which are connected in sequence;
the number of the left pins is not less than one, and the left pins are connected with the upper half-bridge insulating substrate or the lower half-bridge insulating substrate;
the connecting bridge body is provided with a distance from the top of the bonding wire;
the number of the right-side pins is not less than one, and the right-side pins are connected with the lower half-bridge insulating substrate or the upper half-bridge insulating substrate.
Specifically, a plurality of rectangular holes extending from the direction of the lower half-bridge insulating substrate to the direction of the upper half-bridge insulating substrate are formed in the flat connecting bridge.
Specifically, a plurality of rectangular holes are uniformly distributed at intervals.
Specifically, a plurality of round holes I are arranged on the rectangular hole at intervals.
Specifically, the flat connection bridge is provided with a plurality of circular holes II extending from the direction of the lower half-bridge insulating substrate to the direction of the upper half-bridge insulating substrate.
Specifically, the intervals among the rectangular holes gradually increase from the middle to the two sides.
Specifically, the widths of the rectangular holes are gradually decreased from the middle to two sides.
The invention has the beneficial effects that:
1) The invention utilizes the flat connection bridge of the power loop, and the current flow direction at the lower part is opposite, and utilizes the electromagnetic principle and the magnetic circuit cancellation principle to reduce the parasitic inductance of the module.
2) The power circuit is not completely dependent on the copper layer on the upper surface of the insulating substrate, so that more power semiconductor chips can be arranged, thereby realizing larger current specification and increasing power density.
Drawings
Figure 1 is a schematic view of the external perspective structure of the present invention,
figure 2 is a schematic view of the internal perspective structure of the present invention,
figure 3 is a schematic perspective view of the connection state of the flat connection bridge,
figure 4 is a schematic view showing a connection state of a flat connection bridge in a three-dimensional structure,
figure 5 is a schematic three-dimensional structure of a connection state of the flat connection bridge,
figure 6 is a schematic perspective view showing the arrangement state of the upper half-bridge insulating substrate and the lower half-bridge insulating substrate,
figure 7 is a schematic perspective view of a flat bridge design,
figure 8 is a schematic perspective view of a second design of flat bridge structure,
figure 9 is a schematic perspective view of a third structural design of the flat connection bridge,
figure 10 is a schematic perspective view of a fourth structural design of the flat connection bridge,
figure 11 is a schematic perspective view of a fifth structural design of the flat connection bridge,
FIG. 12 is a schematic diagram of power semiconductor module power loop current flow;
in the drawing 100 is a base plate,
200 is an insulating substrate and is provided with a plurality of insulating layers,
210 is an upper half-bridge insulating substrate, 211 is a first metal layer one,
220, 221 is the second metal layer one,
300 is a power chip that is configured to be coupled to a power supply,
310 is the upper half-bridge power semiconductor chip, 311 is the IGBT chip one, 312 is the FRD chip one,
320 is the lower half-bridge power semiconductor chip, 321 is the IGBT chip two, 322 is the FRD chip two,
400 is a bond wire and,
500 is a flat connection bridge, 510 is a rectangular hole, 511 is a circular hole one, 520 is a circular hole two, 530 is a left side pin, 540 is a right side pin,
610 is the positive electrode, 620 is the negative electrode, 630 is the output electrode.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. In the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The invention is shown in fig. 1-12; a low inductance high power semiconductor module includes a case (the case includes an outer frame, a bottom plate 100 and a top cover), an insulating substrate 200, a power chip 300, a bonding wire 400, a positive electrode, a negative electrode and an output electrode; the insulating substrate 200 is fixedly disposed on the base plate 100, and includes an upper half-bridge insulating substrate 210 and a lower half-bridge insulating substrate 220 that are disposed at intervals; the power chip 300 is bonded on top of the insulating substrate; the top of the insulating substrate is provided with a flat connection bridge 500 electrically connected with the insulating substrate.
Further defined, the flat connection bridge 500 is disposed on top of the lower half-bridge insulating substrate 220;
the left side pin 530 of the flat connection bridge 500 is connected to the upper half-bridge insulating substrate 210, and the right side pin 540 is electrically connected to the positive electrode.
Referring to fig. 6, the power semiconductor module has two insulating substrates, wherein an upper half-bridge insulating substrate 210 is provided on the left side and a lower half-bridge insulating substrate 220 is provided on the right side, and a flat connection bridge 500 is disposed above the lower half-bridge insulating substrate 220. A lower half-bridge power semiconductor chip 320 and bonding wires 400 are disposed between the lower half-bridge insulating substrate 220 and the flat connection bridge 500, wherein the lower half-bridge power semiconductor chip 320 is soldered on the corresponding copper layer of the right-side insulating substrate, and the bonding wires 400 are bonded on the upper surface of the lower half-bridge power semiconductor chip 320.
Further expansion, may be disposed on the upper half-bridge insulating substrate 210 in addition to being disposed on the lower half-bridge insulating substrate 220;
the flat connection bridge 500 is disposed on top of the upper half-bridge insulating substrate 210;
the left side pin 530 of the flat connection bridge 500 is connected to the lower half-bridge insulating substrate 220, and the right side pin 540 is electrically connected to the negative electrode.
Further defined, the flat connection bridge 500 includes a left side pin 530, a connection bridge body and a right side pin 540 connected in sequence;
the number of the left pins 530 is not less than one, and the left pins are connected with the upper half-bridge insulating substrate 210 (the first metal layer 211) or the lower half-bridge insulating substrate 220;
a space is arranged between the connecting bridge body and the top of the bonding wire 400;
the number of the right pins 540 is not less than one, and the right pins are connected to the lower half-bridge insulating substrate 220 (the second metal layer 221) or the upper half-bridge insulating substrate 210.
Further defined, the power chip 300 includes an upper half-bridge power semiconductor chip 310 disposed on an upper half-bridge insulating substrate 210;
the upper half-bridge power semiconductor chip 310 includes a number of IGBT chips one 311 and a number of FRD chips one 312.
Besides the IGBT chip 311, a MOSFET chip 311 can be adopted;
in addition to FRD chip one 312, SBD chip one may be employed; in the present case, four IGBT chips 311 and four FRD chips 312 are respectively used to form four paths.
Further defined, the power chip 300 includes a lower half-bridge power semiconductor chip 320 disposed on a lower half-bridge insulating substrate 220;
the lower half-bridge power semiconductor chip 320 includes four IGBT chips two 321 and four FRD chips two 322.
Besides the IGBT chip II 321, a MOSFET chip II can be adopted;
in addition to FRD chip two 322, SBD chip two may be used; in the scheme, four IGBT chips 311, 312, 321 and 322 are respectively adopted to form four paths. The metal layer in the upper half-bridge insulating substrate 210 or the lower half-bridge insulating substrate 220 is copper or aluminum.
Referring to fig. 12, when the upper half-bridge power semiconductor chip 310 is operated, a current (shown by a solid line in fig. 3) flowing into the positive electrode is applied to the corresponding copper layer of the right insulating substrate via the bonding wire 400, the pins of the flat connection bridge 500 are welded on the copper layer, the current flows through the flat connection bridge 500 and reaches the left insulating substrate, and then reaches the output electrode via the copper layer of the left insulating substrate, the upper half-bridge power semiconductor chip and the bonding wire 400.
When the lower half-bridge power semiconductor chip 320 is operated, current flows in through the output electrode, reaches the right insulating substrate through the bonding wire 400, flows through the lower half-bridge power semiconductor chip 320 and the bonding wire 400, and flows out through the negative electrode (shown by a dotted line in fig. 3).
As can be seen from fig. 3, the current flow of the flat connection bridge 500 is from the positive electrode to the output electrode, the current flow of the insulating substrate below the flat connection bridge 500 is from the output electrode to the negative electrode, and as can be seen from the electromagnetic induction principle and the magnetic circuit cancellation principle, the flat connection bridge 500 can significantly reduce the parasitic inductance of the module.
The flat connection bridge 500 structure is further expanded as follows:
example 1
Referring to fig. 7; the connection bridge body of the flat connection bridge 500 is provided with a plurality of rectangular holes 510 extending from the direction of the lower half-bridge insulating substrate 220 to the direction of the upper half-bridge insulating substrate 210.
The rectangular holes 510 are uniformly distributed at intervals.
Example 2
Referring to fig. 8; the rectangular hole 510 is provided with a plurality of circular holes 511 arranged at intervals.
Example 3
Referring to fig. 9, the connection bridge body of the flat connection bridge 500 is provided with a plurality of groups of second circular holes 520 extending from the lower half-bridge insulating substrate 220 to the upper half-bridge insulating substrate 210.
In the middle of the flat connection bridge 500, a plurality of rectangular holes 510 or a circular hole two 520 are provided, the pattern is arranged to divide the current into a plurality of paths (in this case, as can be seen from fig. 6, the number of the chips on the insulating substrate is 4, the current basically flows through the chips are the same), the number of the divided parts is generally equal to the number of the IGBT chips two 321 of the lower half-bridge insulating substrate 220 below, and each current path of the flat connection bridge 500 corresponds to the current path of the chip below.
Example 4
Referring to fig. 10, the intervals between the rectangular holes 510 are increased from the middle to the both sides.
Example 5
Referring to fig. 11, the widths of the rectangular holes 510 decrease from the middle to the two sides.
In embodiment 4 and embodiment 5, considering that the current is not uniformly distributed on the flat connection bridge 500, the more concentrated the current is generally along the center line, which affects the magnetic circuit cancellation effect. In order to achieve a sufficient reduction in parasitic inductance, unbalanced slits are provided in the flat connection bridge 500, thereby achieving as uniform a current flow direction as possible.
For the purposes of this disclosure, the following points are also described:
(1) The drawings of the embodiments disclosed in the present application relate only to the structures related to the embodiments disclosed in the present application, and other structures can refer to common designs;
(2) The embodiments disclosed herein and features of the embodiments may be combined with each other to arrive at new embodiments without conflict;
the above is only a specific embodiment disclosed in the present application, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. The low-inductance high-power semiconductor module is characterized by comprising a shell, an insulating substrate, a power chip, a bonding wire, a positive electrode, a negative electrode and an output electrode; the insulation substrate is fixedly arranged on the bottom plate and comprises an upper half-bridge insulation substrate and a lower half-bridge insulation substrate which are arranged at intervals; the power chip is welded on the top of the insulating substrate; the top of the insulating substrate is provided with a flat connecting bridge electrically connected with the insulating substrate.
2. The low inductance high power semiconductor module of claim 1, wherein said flat connection bridge is disposed on top of said lower half bridge insulating substrate;
the left side pin of flat connecting bridge is connected with the upper half bridge insulating substrate, and the right side pin is electrically connected with the positive electrode.
3. The low inductance high power semiconductor module of claim 1, wherein said flat connection bridge is disposed on top of said upper half bridge insulating substrate;
the left side pin of the flat connecting bridge is connected with the lower half-bridge insulating substrate, and the right side pin is electrically connected with the negative electrode.
4. The low-inductance high-power semiconductor module according to claim 1, wherein the flat connection bridge comprises a left side pin, a connection bridge body and a right side pin which are connected in sequence;
the number of the left pins is not less than one, and the left pins are connected with the upper half-bridge insulating substrate or the lower half-bridge insulating substrate;
the connecting bridge body is provided with a distance from the top of the bonding wire;
the number of the right-side pins is not less than one, and the right-side pins are connected with the lower half-bridge insulating substrate or the upper half-bridge insulating substrate.
5. The low-inductance high-power semiconductor module according to claim 1, wherein the flat connection bridge is provided with a plurality of rectangular holes extending from the lower half-bridge insulating substrate direction to the upper half-bridge insulating substrate direction.
6. The low-inductance high-power semiconductor module of claim 5, wherein a plurality of said rectangular holes are uniformly spaced.
7. The low-inductance high-power semiconductor module according to claim 6, wherein the rectangular holes are provided with a plurality of circular holes I arranged at intervals.
8. The low-inductance high-power semiconductor module according to claim 5, wherein the flat connection bridge is provided with a plurality of circular holes extending from the lower half-bridge insulating substrate direction to the upper half-bridge insulating substrate direction.
9. The low inductance, high power semiconductor module of claim 5, wherein the spacing between the rectangular holes increases from the middle to the sides.
10. A low inductance high power semiconductor module according to claim 5 or 9, wherein the width of a plurality of said rectangular holes decreases from the middle to the sides in sequence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310482195.7A CN116613956A (en) | 2023-04-29 | 2023-04-29 | Low-inductance high-power semiconductor module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310482195.7A CN116613956A (en) | 2023-04-29 | 2023-04-29 | Low-inductance high-power semiconductor module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116613956A true CN116613956A (en) | 2023-08-18 |
Family
ID=87673832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310482195.7A Pending CN116613956A (en) | 2023-04-29 | 2023-04-29 | Low-inductance high-power semiconductor module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116613956A (en) |
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2023
- 2023-04-29 CN CN202310482195.7A patent/CN116613956A/en active Pending
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