CN116613177A - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

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Publication number
CN116613177A
CN116613177A CN202310769452.5A CN202310769452A CN116613177A CN 116613177 A CN116613177 A CN 116613177A CN 202310769452 A CN202310769452 A CN 202310769452A CN 116613177 A CN116613177 A CN 116613177A
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China
Prior art keywords
module
layer
conductive layer
insulating layer
substrate
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CN202310769452.5A
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Chinese (zh)
Inventor
靳笑阳
盖翠丽
郭恩卿
潘康观
郭双
鲁建军
程芸
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Yungu Guan Technology Co Ltd
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Yungu Guan Technology Co Ltd
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Priority to CN202310769452.5A priority Critical patent/CN116613177A/en
Publication of CN116613177A publication Critical patent/CN116613177A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The embodiment of the invention discloses an array substrate and a display panel. The array substrate includes: the first conductive layer is arranged on one side of the substrate; the active layer is arranged on one side of the first conductive layer, which is far away from the substrate; the second conductive layer is arranged on one side of the active layer, which is far away from the substrate; the first insulating layer is arranged between the first conductive layer and the active layer; the second insulating layer is arranged between the active layer and the second conductive layer; the array substrate further comprises at least one first transistor and at least one second transistor, wherein the first transistor comprises an active layer, a second insulating layer and a second conductive layer; the second transistor includes a first conductive layer, a first insulating layer, and an active layer; the thickness of the first insulating layer is greater than the thickness of the second insulating layer. The technical scheme provided by the embodiment of the invention improves the display effect of the display panel and solves the problem of poor brightness uniformity of the display panel.

Description

Array substrate and display panel
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate and a display panel.
Background
With the development of display technology, the requirements of people on the display panel are increasing. The gate voltage of the driving transistor in the pixel circuit of the conventional display panel has a narrowed driving range, resulting in a problem of poor luminance uniformity of the display panel.
Disclosure of Invention
The embodiment of the invention provides an array substrate and a display panel, which are used for solving the problem of poor brightness uniformity of the display panel.
In order to realize the technical problems, the invention adopts the following technical scheme:
the embodiment of the invention provides an array substrate, which comprises:
a substrate;
the first conductive layer is arranged on one side of the substrate;
the active layer is arranged on one side of the first conductive layer, which is far away from the substrate;
the second conductive layer is arranged on one side of the active layer, which is far away from the substrate;
the first insulating layer is arranged between the first conductive layer and the active layer;
the second insulating layer is arranged between the active layer and the second conductive layer;
the array substrate further comprises at least one first transistor and at least one second transistor, wherein the first transistor comprises an active layer, a second insulating layer and a second conductive layer; the second transistor includes a first conductive layer, a first insulating layer, and an active layer;
the thickness of the first insulating layer is different from the thickness of the second insulating layer.
Optionally, the second transistor further comprises a second insulating layer and a second conductive layer.
Optionally, the array substrate further includes:
a pixel circuit including a driving module including the second transistor and a switching module including the first transistor;
preferably, the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
Optionally, the array substrate further includes:
the shading layer is arranged on one side, close to the substrate, of the first conductive layer of the second transistor;
the pixel circuit further includes: the first capacitor is formed by the shading layer and the first conductive layer;
the orthographic projection of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the second transistor on the substrate.
Optionally, the array substrate further includes:
the third conductive layer is arranged on one side of the second conductive layer away from the substrate;
the pixel circuit further includes: the second capacitor is formed by the third conductive layer and the second conductive layer, or the second capacitor is formed by the first conductive layer and the light shielding layer;
the orthographic projection of the second capacitor on the substrate overlaps with the orthographic projection of the second transistor on the substrate.
Optionally, the array substrate further includes:
the third insulating layer is arranged between the shading layer and the first conductive layer;
preferably, the first insulating layer includes an organic layer, the second insulating layer includes an inorganic layer, and the third insulating layer includes an organic layer or an inorganic layer.
Optionally, the switch module includes:
a data writing module and a compensation module;
the first pole of the driving module is connected with the first power end, the second pole of the driving module is connected with the first end of the light-emitting module and the first end of the data writing module, the second end of the light-emitting module is connected with the second power end, the grid electrode of the driving module is connected with the first end of the compensation module, and the second end of the compensation module is connected with the first pole of the driving module; the control end of the compensation module is connected with the second scanning line;
the second end of the data writing module is connected with the data line, and the control end of the data writing module is connected with the first scanning line;
the first capacitor is connected between the first end of the data writing module and the grid electrode of the driving module.
Optionally, the switch module further includes:
the first end of the first initialization module is connected with the first end of the data writing module, and the second end of the first initialization module is connected with the second pole of the driving module; the control end of the first initialization module is connected with the third scanning line;
the first end of the second initialization module is connected with the first end of the light-emitting module, the second end of the second initialization module is connected with the initialization line, and the control end of the second initialization module is connected with the second scanning line; the second capacitor is connected between the first pole of the driving module and the first power supply end;
optionally, the switch module further includes: the first end of the first light-emitting control module is connected with the first power end, the second end of the first light-emitting control module is connected with the first pole of the driving module, and the control end of the first light-emitting control module is connected with the light-emitting control line; the first end of the second light-emitting control module is connected with the first end of the data writing module, the second end of the second light-emitting control module is connected with the first end of the light-emitting module, and the control end of the second light-emitting control module is connected with the third scanning line.
According to another aspect of the present invention, there is provided a display panel including the array substrate set forth in any of the first aspect.
The array substrate provided by the embodiment of the invention comprises at least one first transistor and at least one second transistor by arranging the array substrate, wherein the first transistor comprises an active layer, a second insulating layer and a second conductive layer. The second transistor includes a first conductive layer, a first insulating layer, and an active layer. The first conductive layer and the second conductive layer serve as gates of the driving module and the switching module, respectively. The first insulating layer and the second insulating layer are respectively used as gate insulating layers of the driving module and the switching module, and the thickness of the first insulating layer is different from that of the second insulating layer. The arrangement can ensure that the gate insulating layer of the driving module on the array substrate is thicker, so that the driving voltage range of the driving module is larger, and further the display gray scale is ensured to be unfolded. On the other hand, the grid insulating layer of the switch module on the array substrate is thinner, so that the on-off efficiency and the on-off efficiency of the switch module are improved, the uniformity of the luminous brightness of the display panel is improved, and the display effect of the display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings needed in the description of the embodiments of the present invention, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the contents of the embodiments of the present invention and these drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another array substrate according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another pixel circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a layout structure of a pixel circuit according to an embodiment of the present invention;
FIG. 6 is a timing diagram of a pixel circuit according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Based on the above technical problems, the present embodiment proposes the following solutions:
fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. Referring to fig. 1, an array substrate 100 according to an embodiment of the present invention includes a substrate 10, and a first conductive layer M1 disposed on one side of the substrate 10; the active layer 20 is disposed on a side of the first conductive layer M1 away from the substrate 10; the second conductive layer M2 is disposed on a side of the active layer 20 away from the substrate 10; the first insulating layer 30 is disposed between the first conductive layer M1 and the active layer 20; the second insulating layer 40 is disposed between the active layer 20 and the second conductive layer M2; the array substrate 100 further includes at least one first transistor including an active layer 20, a second insulating layer 40, and a second conductive layer M2; the second transistor includes a first conductive layer M1, a first insulating layer 30, and an active layer 20. The thickness of the first insulating layer 30 is different from the thickness of the second insulating layer 40.
Specifically, the substrate 10 may be a flexible substrate 10 or a rigid substrate 10. The materials of the first and second conductive layers M1 and M2 may include metal or other non-metal conductive materials. The material of the active layer 20 may include silicon oxide, polysilicon, and the like. The materials of the first insulating layer 30 and the second insulating layer 40 are insulating materials, including silicon oxide or silicon nitride, for example.
A first insulating layer 30 is disposed between the first conductive layer M1 and the active layer 20. A second insulating layer 40 is disposed between the second conductive layer M2 and the active layer 20. The first and second conductive layers M1 and M2 may serve as gate layers of a driving module or a switching module. The active layer 20 may serve as a source and a drain of the driving module and the switching module. The first insulating layer 30 and the second insulating layer 40 may serve as gate insulating layers of the driving module or the switching module.
For example, a switching module may be provided including the first conductive layer M1, the first insulating layer 30, and the active layer 20, and a driving module includes the second conductive layer M2, the second insulating layer 40, and the active layer 20. Further, the thickness of the first insulating layer 30 is set smaller than the thickness of the second insulating layer 40. Alternatively, a driving module may be provided including the first conductive layer M1, the first insulating layer 30, and the active layer 20, and a switching module may include the second conductive layer M2, the second insulating layer 40, and the active layer 20. Further, the thickness of the first insulating layer 30 is set to be larger than the thickness of the second insulating layer 40.
The first transistor includes an active layer 20, a second insulating layer 40, and a second conductive layer M2. The second transistor includes a first conductive layer M1, a first insulating layer 30, and an active layer 20. By providing the first insulating layer 30 and the second insulating layer 40 to be different in thickness, the thickness of the gate insulating layer of the first transistor is made different from the thickness of the gate insulating layer of the second transistor. A first transistor may be provided as a driving module and a second transistor as a switching module. Alternatively, a first transistor is provided as the switching module and a second transistor is provided as the driving module. The arrangement is such that the thickness of the gate insulation layer of the drive module is different from the thickness of the gate insulation layer of the switch module. Because the switching response of the switching module is faster and better, the gate insulating layer of the transistor serving as the switching module can be thinner, so that the on and off speeds of the switching module are improved, the response speed of the pixel circuit is improved, and the display effect of the display panel is improved.
Since the driving module is used for driving, a wide gate voltage driving range is required. Since the thicker the gate insulating layer of the driving module is, the larger the range of the gate voltage of the driving module is. The gate insulating layer between the conductive layer and the active layer 20 of the driving module may be set thicker to increase the range of the driving voltage of the driving module, thereby ensuring gray scale spreading.
The array substrate 100 provided in this embodiment includes the first conductive layer M1 and the second conductive layer M2 as the gate electrodes of the driving module and the switching module, and the first insulating layer 30 and the second insulating layer 40 as the gate insulating layers of the driving module and the switching module, respectively, and includes the active layer 20, the second insulating layer 40 and the second conductive layer M2 by providing the first transistor. The second transistor includes a first conductive layer M1, a first insulating layer 30, and an active layer 20, and the thickness of the first insulating layer 30 is different from the thickness of the second insulating layer 40. By the arrangement, the thicker gate insulation layer of the driving module on the array substrate 100 can be ensured, so that the driving voltage range of the driving module is larger, and further the development of the display gray scale is ensured. On the other hand, the gate insulating layer of the switch module on the array substrate 100 is thinner, so that the on-efficiency and the off-efficiency of the switch module are improved, the uniformity of the light-emitting brightness of the display panel is further improved, and the display effect of the display panel is improved.
Optionally, fig. 2 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 2, the second transistor may further include a second insulating layer and a second conductive layer.
Specifically, the second transistor includes a first conductive layer M1, a first insulating layer 30, an active layer 20, a second insulating layer 40, and a second conductive layer M2. By the arrangement, the second transistors are of double-gate structures, the number of the gates of the second transistors is conveniently set according to the requirement, and therefore the display effect of the display panel is improved.
Optionally, fig. 3 is a schematic structural diagram of another array substrate according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 2 and 3, the array substrate 100 provided in the embodiment of the present invention may further include a pixel circuit 200, where the pixel circuit 200 includes a driving module 1 and a switching module 2, the driving module 1 includes a second transistor, and the switching module 2 includes a first transistor. Preferably, the thickness of the first insulating layer 30 is greater than the thickness of the second insulating layer 40.
For example, the second conductive layer M2 may be disposed to form the switching module 2 with the active layer 20; referring to fig. 2, the first conductive layer M1 and the active layer 20 form the driving module 1, or, referring to fig. 3, the first conductive layer M1 and the active layer 20 and the second conductive layer M2 form the driving module 1.
Specifically, referring to fig. 2 and 3, the second conductive layer M2 and the active layer 20 form the switch module 2, and the second insulating layer 40 between the active layer 20 and the second conductive layer M2 has a relatively thin thickness, so that the on and off speeds of the switch module 2 can be increased, the response speed of the pixel circuit 200 can be increased, and the display effect of the display panel can be improved.
With continued reference to fig. 2, the first conductive layer M1 and the active layer 20 form the driving module 1, and the thickness of the first insulating layer 30 between the first conductive layer M1 and the active layer 20 is thicker, so that the driving voltage range of the driving module 1 can be increased, and gray scale development is further ensured. Fig. 2 exemplarily shows that the driving module 1 is a bottom gate structure, and the first conductive layer M1 serves as a gate electrode.
In another alternative embodiment, with continued reference to fig. 3, the first conductive layer M1, the active layer 20 and the second conductive layer M2 may be configured to form the driving module 1, where the driving module 1 has a dual gate structure. Wherein the first conductive layer M1 is used as a bottom gate, and the second conductive layer M2 is used as a top gate. Since the thickness of the first insulating layer 30 between the first conductive layer M1 and the active layer 20 is greater than that of the second insulating layer 40, the range of the gate voltage of the driving module 1 is increased, which is advantageous for gray scale development, and further improves the brightness uniformity of the display panel.
Alternatively, the first insulating layer 30 may include an organic layer, and the second insulating layer 40 may include an inorganic layer. The arrangement can ensure the stability of the driving performance of the driving module 1 and the performance of the switch module 2, and can also reduce the process cost better.
Optionally, with continued reference to fig. 2, based on the foregoing embodiment, the array substrate 100 further includes: a light shielding layer M0, wherein the light shielding layer M0 is disposed on one side of the first conductive layer M1 of the second transistor, which is close to the substrate 10; the pixel circuit 200 further includes: the first capacitor Cst1, the first capacitor Cst1 is formed by the light shielding layer M0 and the first conductive layer M1; the front projection of the first capacitor Cst1 on the substrate 10 at least partially overlaps the front projection of the second transistor on the substrate 10.
Specifically, since the active layer 20 includes Indium Gallium Zinc Oxide (IGZO), its stability is easily affected by light, and by providing the light shielding layer M0, the stability of the driving module 1 is better improved. On the other hand, the light shielding layer M0 and the first conductive layer M1 form a first capacitor Cst1, and the front projection of the first capacitor Cst1 on the substrate 10 and the front projection of the second transistor on the substrate 10 at least partially overlap, so that the first capacitor Cst1 can be made larger, and the routing length of the connecting line between the gate of the driving module 1 and the first capacitor Cst1 can be saved.
It should be noted that fig. 2 exemplarily illustrates that the second conductive layer M2 is disposed on a side of the driving module 1 away from the substrate 10, where the second conductive layer M2 is used as a shielding layer, and is connected to a voltage signal of the source S of the driving module 1, so as to improve the light shielding capability of the side of the active layer 20 away from the substrate 10, and further improve the stability of the driving module 1.
Fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Fig. 5 is a schematic diagram of a layout structure of a pixel circuit according to an embodiment of the present invention. With reference to fig. 3, fig. 4, and fig. 5 in combination with the foregoing embodiment, optionally, with continued reference to fig. 3 in accordance with the foregoing embodiment, the array substrate 100 provided in this embodiment may further include: a third conductive layer M3, where the third conductive layer M3 is disposed on a side of the second conductive layer M2 away from the substrate 10; the pixel circuit 200 further includes: the second capacitor Cst2 is formed by the third conductive layer M3 and the second conductive layer M2. Alternatively, referring to fig. 5, the second capacitor Cst2 is formed by the first conductive layer M1 and the light shielding layer M0; the orthographic projection of the second capacitor Cst2 on the substrate 10 overlaps the orthographic projection of the second transistor on the substrate 10.
Specifically, the arrangement is convenient for forming the second capacitor Cst2 according to layout requirements, the orthographic projection of the second capacitor Cst2 on the substrate 10 overlaps with the orthographic projection of the second transistor on the substrate 10, the second capacitor Cst2 is convenient to be arranged larger, and the wiring space of the pixel circuit 200 is not additionally increased.
With continued reference to fig. 3, the array substrate 100 may further include: the third insulating layer 50, the third insulating layer 50 is disposed between the light shielding layer M0 and the first conductive layer M1. Alternatively, the third insulating layer 50 may include an organic layer or an inorganic layer, and is not limited herein, and may include silicon oxide or silicon nitride, for example.
Still another alternative implementation, with continued reference to fig. 4 on the basis of the above embodiment, the switch module 2 may optionally include: a data writing module 21 and a compensation module 22; the first pole D of the driving module 1 is connected with the first power supply end VDD, the second pole S of the driving module 1 is connected with the first end of the light emitting module D1 and the first end of the data writing module 21, the second end of the light emitting module D1 is connected with the second power supply end VSS, the grid G of the driving module 1 is connected with the first end of the compensation module 22, and the second end of the compensation module 22 is connected with the first pole D of the driving module 1; the control end of the compensation module 22 is connected with the second scanning line EMB; the second end of the data writing module 21 is connected with the data line Vdata, and the control end of the data writing module 21 is connected with the first scanning line Sn; the first capacitor Cst1 is connected between the first terminal of the data writing module 21 and the gate electrode G of the driving module 1.
Specifically, during the data writing phase, the compensation module 22 is turned on, so that the first pole D of the driving module 1 and the gate G of the driving module 1 are shorted. The data writing module 21 is turned on, and the data voltage is written into the gate G of the driving module 1 through the turned-on data writing module 21, the driving module 1, and the compensation module 22.
It should be noted that fig. 4 exemplarily illustrates a case where the driving module 1 includes the driving transistor T1, the data writing module 21 includes the first transistor T2, and the compensating module 22 includes the second transistor T3.
On the basis of the above embodiment, with continued reference to fig. 4 and 5, the switch module 2 may optionally further include a first initialization module 23, a first end of the first initialization module 23 is connected to the first end of the data writing module 21, and a second end of the first initialization module 23 is connected to the second pole S of the driving module 1; the control end of the first initialization module 23 is connected with a third scanning line SnB; the first end of the second initialization module 24 is connected with the first end of the light emitting module D1, the second end of the second initialization module 24 is connected with the initialization line Vref, and the control end of the second initialization module 24 is connected with the second scan line EMB; the second capacitor Cst2 is connected between the first electrode D of the driving module 1 and the first power terminal VDD.
Specifically, fig. 6 is a timing chart of a pixel circuit according to an embodiment of the present invention. Referring to fig. 4 and 6, in the initial state t0, the driving module 1 is turned on, the first initializing module 23 is turned on, and the light emitting module D1 emits light.
In the initialization stage t1, the second scan line EMB and the third scan line SnB are turned on by the on-level signal, the compensation module 22 is turned on, and the first initialization module 23 and the second initialization module 24 are turned on. The initialization line Vref transmits an initialization voltage to the first terminal of the light emitting module D1 through the turned-on second initialization module 24. The initialization line Vref transmits an initialization voltage to the gate of the driving module 1 through the turned-on first initialization module 23, second initialization module 24, and compensation module 22. And initializes the first and second capacitances Cst1 and Cst 2.
In the data writing stage t2, the third scan line SnB transmits a turn-off level signal, and the first initializing module 23 is turned off. The second scan line EMB transmits a turn-on level signal, and the compensation module 22 is turned on, so that the first electrode D of the driving module 1 and the gate G of the driving module 1 are shorted. The first scan line Sn is a turn-on level signal, and the data writing module 21 is turned on, and the data voltage forms a loop through the turned-on data writing module 21, the first capacitor Cst1, the turned-on compensation module 22, the second capacitor Cst2, and the first power supply terminal VDD, so that the data voltage is written into the gate G of the driving module 1.
Due to the existence of the first capacitor Cst1 and the second capacitor Cst2, the voltage difference of the first capacitor Cst1 is (C st2 ) (Vref-Vdata)/(Cs1+Cs2+Cgs) +Vth, wherein C in the formula st2 The capacitance value of the second capacitor is represented by Vref in the formula, the initialization voltage value is represented by Vdata in the formula, the capacitance value of the first capacitor is represented by Cst1 in the formula, the capacitance value between the gate G and the second pole S of the driving module is represented by Cgs in the formula, and the threshold voltage of the driving module 1 is represented by Vth in the formula.
It should be noted that, as exemplarily shown in fig. 4 and 5, the first initialization module 23 includes the third transistor T4, and the second initialization module 24 includes the fourth transistor T6.
With continued reference to fig. 4 and 6, the switch module 2 may further include: a first light emitting control module 25 and a second light emitting control module 26, wherein a first end of the first light emitting control module 25 is connected with a first power end VDD, a second end of the first light emitting control module 25 is connected with a first pole D of the driving module 1, and a control end of the first light emitting control module 25 is connected with a light emitting control line EM; the first end of the second light emitting control module 26 is connected to the first end of the data writing module 21, the second end of the second light emitting control module 26 is connected to the first end of the light emitting module D1, and the control end of the second light emitting control module 26 is connected to the third scan line SnB.
Specifically, in the initial state t0, the driving module 1 is turned on, the first initializing module 23 is turned on, both the first light emitting control module 25 and the second light emitting control module 26 are turned on, and the light emitting module D1 emits light.
In the initialization phase t1, the emission control line EM transmits a signal of the off level, and the first emission control module 25 is turned off. The third scan line SnB is an on-level signal, and the second light-emitting control module 26 and the first initialization module 23 are both turned on. The second scan line EMB is a turn-on level signal, and the compensation module 22 and the second initialization module 24 are both turned on, and the initialization line Vref transmits an initialization voltage to the first terminal of the light emitting module D1 through the turned-on second initialization module 24. The initialization line Vref transmits an initialization voltage to the gate of the driving module 1 through the turned-on second initialization module 24, second light emission control module 26, first initialization module 23, and compensation module 22. And initializes the first and second capacitances Cst1 and Cst 2.
In the data writing stage t2, the light emission control line EM transmits a signal of an off level, and the first light emission control module 25 is turned off. The third scan line SnB transmits a turn-off level signal, and both the second light-emitting control module 26 and the first initialization module 23 are turned off. The second scan line EMB transmits a turn-on level signal, and the compensation module 22 is turned on, so that the first electrode D of the driving module 1 and the gate G of the driving module 1 are shorted. The first scan line Sn is a turn-on level signal, and the data writing module 21 is turned on, and the data voltage forms a loop through the turned-on data writing module 21, the first capacitor Cst1, the turned-on compensation module 22, the second capacitor Cst2, and the first power voltage, so that the data voltage is written into the gate G of the driving module 1. Due to the existence of the first capacitor Cst1 and the second capacitor Cst2, makeThe voltage difference of the capacitor Cst1 is (C st2 )*(Vref-Vdata)/(Cst1+Cst2+Cgs)+Vth。
In the light emitting phase t3, the second scan line EMB transmits a turn-off level signal, and the compensation module 22 is turned off. The first scan line Sn transmits a turn-off level signal, and the data writing module 21 is turned off. When the light emission control line EM transmits the on level signal and the third scanning line SnB transmits the on level signal, the driving module 1, the first light emission control module 25, the second light emission control module 26 and the first initialization module 23 are all turned on, and the light emitting module D1 emits light.
In the light emitting stage t3, the lighting current of the light emitting module D1 is controlled by the difference between the gate-source voltage Vgs of the driving module 1 and the threshold voltage Vth of the driving module, and the lighting current of the light emitting module D1 is (C st2 ) The function of (Vref-Vdata)/(Cs1+Cs2+Cgs) +Vth is not included, since the first power voltage, the second power voltage and the threshold voltage Vth of the driving module 1 are not included in the function. Therefore, the pixel circuit has better compensation effect on the voltage drop of the first power voltage and the second power voltage and the threshold voltage Vth of the driving module 1.
It should be noted that, as exemplarily shown in fig. 4 and 5, the first light emitting control module 25 includes the fifth transistor T7, the second light emitting control module 26 includes the sixth transistor T5, and the light emitting module D1 includes a light emitting diode, and the first terminal of the light emitting module D1 may be an anode of the light emitting diode, and the active layer 20 includes IGZO, which is not limited herein.
Optionally, with continued reference to fig. 3 and 5, the array substrate may further include a fourth metal layer M4, where the fourth metal layer M4 is disposed on a side of the third metal layer M3 away from the substrate 10. For example, the data line Vdata and the first power terminal VDD may be disposed on the fourth metal layer M4, which is not limited herein.
Fig. 7 is a schematic structural diagram of a display panel according to an embodiment of the invention. Referring to fig. 7, the display panel 300 provided in this embodiment, including the array substrate 100 provided in any of the foregoing embodiments, has the beneficial effects of the array substrate 100 provided in any of the foregoing embodiments, and will not be described herein again.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.

Claims (10)

1. An array substrate, characterized by comprising:
the substrate is provided with a plurality of holes,
the first conductive layer is arranged on one side of the substrate;
an active layer arranged on one side of the first conductive layer away from the substrate;
the second conductive layer is arranged on one side of the active layer, which is far away from the substrate;
a first insulating layer disposed between the first conductive layer and the active layer;
a second insulating layer disposed between the active layer and the second conductive layer;
the array substrate further comprises at least one first transistor and at least one second transistor, wherein the first transistor comprises an active layer, a second insulating layer and a second conductive layer; the second transistor includes a first conductive layer, a first insulating layer, and an active layer;
the thickness of the first insulating layer is different from the thickness of the second insulating layer.
2. The array substrate of claim 1, wherein,
the second transistor further includes a second insulating layer and a second conductive layer.
3. The array substrate according to claim 1 or 2, further comprising:
a pixel circuit including a driving module including the second transistor and a switching module including the first transistor;
preferably, the thickness of the first insulating layer is greater than the thickness of the second insulating layer.
4. The array substrate of claim 3, further comprising:
a light shielding layer disposed on a side of the first conductive layer of the second transistor near the substrate;
the pixel circuit further includes: a first capacitor formed by the light shielding layer and the first conductive layer;
the orthographic projection of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the second transistor on the substrate.
5. The array substrate of claim 4, further comprising:
the third conductive layer is arranged on one side, far away from the substrate, of the second conductive layer;
the pixel circuit further includes: a second capacitor formed by the third conductive layer and the second conductive layer, or formed by the first conductive layer and the light shielding layer;
the orthographic projection of the second capacitor on the substrate overlaps with the orthographic projection of the second transistor on the substrate.
6. The array substrate of claim 4, further comprising:
a third insulating layer disposed between the light shielding layer and the first conductive layer;
preferably, the first insulating layer includes an organic layer, the second insulating layer includes an inorganic layer, and the third insulating layer includes an organic layer or an inorganic layer.
7. The array substrate of claim 5, wherein the switch module comprises:
a data writing module and a compensation module;
the first pole of the driving module is connected with a first power end, the second pole of the driving module is connected with the first end of the light emitting module and the first end of the data writing module, the second end of the light emitting module is connected with a second power end, the grid electrode of the driving module is connected with the first end of the compensation module, and the second end of the compensation module is connected with the first pole of the driving module; the control end of the compensation module is connected with the second scanning line;
the second end of the data writing module is connected with the data line, and the control end of the data writing module is connected with the first scanning line;
the first capacitor is connected between the first end of the data writing module and the grid electrode of the driving module.
8. The array substrate of claim 7, wherein the switch module further comprises:
the first end of the first initialization module is connected with the first end of the data writing module, and the second end of the first initialization module is connected with the second pole of the driving module; the control end of the first initialization module is connected with a third scanning line;
the first end of the second initialization module is connected with the first end of the light-emitting module, the second end of the second initialization module is connected with an initialization line, and the control end of the second initialization module is connected with a second scanning line; the second capacitor is connected between the first pole of the driving module and the first power supply end.
9. The array substrate of claim 7, wherein the switch module further comprises: the first end of the first light-emitting control module is connected with a first power end, the second end of the first light-emitting control module is connected with a first pole of the driving module, and the control end of the first light-emitting control module is connected with a light-emitting control line; the first end of the second light-emitting control module is connected with the first end of the data writing module, the second end of the second light-emitting control module is connected with the first end of the light-emitting module, and the control end of the second light-emitting control module is connected with a third scanning line.
10. A display panel comprising the array substrate of claims 1 to 8.
CN202310769452.5A 2023-06-27 2023-06-27 Array substrate and display panel Pending CN116613177A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310769452.5A CN116613177A (en) 2023-06-27 2023-06-27 Array substrate and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310769452.5A CN116613177A (en) 2023-06-27 2023-06-27 Array substrate and display panel

Publications (1)

Publication Number Publication Date
CN116613177A true CN116613177A (en) 2023-08-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310769452.5A Pending CN116613177A (en) 2023-06-27 2023-06-27 Array substrate and display panel

Country Status (1)

Country Link
CN (1) CN116613177A (en)

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